1 /* Definitions of target machine for GNU compiler, for IBM RS/6000.
2 Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002 Free Software Foundation, Inc.
4 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
6 This file is part of GNU CC.
8 GNU CC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GNU CC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GNU CC; see the file COPYING. If not, write to
20 the Free Software Foundation, 59 Temple Place - Suite 330,
21 Boston, MA 02111-1307, USA. */
24 /* Note that some other tm.h files include this one and then override
25 many of the definitions. */
27 /* Definitions for the object file format. These are set at
30 #define OBJECT_XCOFF 1
33 #define OBJECT_MACHO 4
35 #define TARGET_ELF (TARGET_OBJECT_FORMAT == OBJECT_ELF)
36 #define TARGET_XCOFF (TARGET_OBJECT_FORMAT == OBJECT_XCOFF)
37 #define TARGET_MACOS (TARGET_OBJECT_FORMAT == OBJECT_PEF)
38 #define TARGET_MACHO (TARGET_OBJECT_FORMAT == OBJECT_MACHO)
44 /* Default string to use for cpu if not specified. */
45 #ifndef TARGET_CPU_DEFAULT
46 #define TARGET_CPU_DEFAULT ((char *)0)
49 /* Common ASM definitions used by ASM_SPEC among the various targets
50 for handling -mcpu=xxx switches. */
51 #define ASM_CPU_SPEC \
53 %{mpower: %{!mpower2: -mpwr}} \
56 %{mno-power: %{!mpowerpc*: -mcom}} \
57 %{!mno-power: %{!mpower2: %(asm_default)}}} \
58 %{mcpu=common: -mcom} \
59 %{mcpu=power: -mpwr} \
60 %{mcpu=power2: -mpwrx} \
61 %{mcpu=power3: -m604} \
62 %{mcpu=power4: -mpower4} \
63 %{mcpu=powerpc: -mppc} \
65 %{mcpu=rios1: -mpwr} \
66 %{mcpu=rios2: -mpwrx} \
77 %{mcpu=ec603e: -mppc} \
90 %{mcpu=8540: -me500} \
91 %{maltivec: -maltivec}"
93 #define CPP_DEFAULT_SPEC ""
95 #define ASM_DEFAULT_SPEC ""
97 /* This macro defines names of additional specifications to put in the specs
98 that can be used in various specifications like CC1_SPEC. Its definition
99 is an initializer with a subgrouping for each command option.
101 Each subgrouping contains a string constant, that defines the
102 specification name, and a string constant that used by the GNU CC driver
105 Do not define this macro if it does not need to do anything. */
107 #define SUBTARGET_EXTRA_SPECS
109 #define EXTRA_SPECS \
110 { "cpp_default", CPP_DEFAULT_SPEC }, \
111 { "asm_cpu", ASM_CPU_SPEC }, \
112 { "asm_default", ASM_DEFAULT_SPEC }, \
113 SUBTARGET_EXTRA_SPECS
115 /* Architecture type. */
117 extern int target_flags;
119 /* Use POWER architecture instructions and MQ register. */
120 #define MASK_POWER 0x00000001
122 /* Use POWER2 extensions to POWER architecture. */
123 #define MASK_POWER2 0x00000002
125 /* Use PowerPC architecture instructions. */
126 #define MASK_POWERPC 0x00000004
128 /* Use PowerPC General Purpose group optional instructions, e.g. fsqrt. */
129 #define MASK_PPC_GPOPT 0x00000008
131 /* Use PowerPC Graphics group optional instructions, e.g. fsel. */
132 #define MASK_PPC_GFXOPT 0x00000010
134 /* Use PowerPC-64 architecture instructions. */
135 #define MASK_POWERPC64 0x00000020
137 /* Use revised mnemonic names defined for PowerPC architecture. */
138 #define MASK_NEW_MNEMONICS 0x00000040
140 /* Disable placing fp constants in the TOC; can be turned on when the
142 #define MASK_NO_FP_IN_TOC 0x00000080
144 /* Disable placing symbol+offset constants in the TOC; can be turned on when
145 the TOC overflows. */
146 #define MASK_NO_SUM_IN_TOC 0x00000100
148 /* Output only one TOC entry per module. Normally linking fails if
149 there are more than 16K unique variables/constants in an executable. With
150 this option, linking fails only if there are more than 16K modules, or
151 if there are more than 16K unique variables/constant in a single module.
153 This is at the cost of having 2 extra loads and one extra store per
154 function, and one less allocable register. */
155 #define MASK_MINIMAL_TOC 0x00000200
157 /* Nonzero for the 64bit model: longs and pointers are 64 bits. */
158 #define MASK_64BIT 0x00000400
160 /* Disable use of FPRs. */
161 #define MASK_SOFT_FLOAT 0x00000800
163 /* Enable load/store multiple, even on powerpc */
164 #define MASK_MULTIPLE 0x00001000
165 #define MASK_MULTIPLE_SET 0x00002000
167 /* Use string instructions for block moves */
168 #define MASK_STRING 0x00004000
169 #define MASK_STRING_SET 0x00008000
171 /* Disable update form of load/store */
172 #define MASK_NO_UPDATE 0x00010000
174 /* Disable fused multiply/add operations */
175 #define MASK_NO_FUSED_MADD 0x00020000
177 /* Nonzero if we need to schedule the prolog and epilog. */
178 #define MASK_SCHED_PROLOG 0x00040000
180 /* Use AltiVec instructions. */
181 #define MASK_ALTIVEC 0x00080000
183 /* Return small structures in memory (as the AIX ABI requires). */
184 #define MASK_AIX_STRUCT_RET 0x00100000
185 #define MASK_AIX_STRUCT_RET_SET 0x00200000
187 /* The only remaining free bit is 0x00400000. sysv4.h uses
188 0x00800000 -> 0x40000000, and 0x80000000 is not available
189 because target_flags is signed. */
191 #define TARGET_POWER (target_flags & MASK_POWER)
192 #define TARGET_POWER2 (target_flags & MASK_POWER2)
193 #define TARGET_POWERPC (target_flags & MASK_POWERPC)
194 #define TARGET_PPC_GPOPT (target_flags & MASK_PPC_GPOPT)
195 #define TARGET_PPC_GFXOPT (target_flags & MASK_PPC_GFXOPT)
196 #define TARGET_NEW_MNEMONICS (target_flags & MASK_NEW_MNEMONICS)
197 #define TARGET_NO_FP_IN_TOC (target_flags & MASK_NO_FP_IN_TOC)
198 #define TARGET_NO_SUM_IN_TOC (target_flags & MASK_NO_SUM_IN_TOC)
199 #define TARGET_MINIMAL_TOC (target_flags & MASK_MINIMAL_TOC)
200 #define TARGET_64BIT (target_flags & MASK_64BIT)
201 #define TARGET_SOFT_FLOAT (target_flags & MASK_SOFT_FLOAT)
202 #define TARGET_MULTIPLE (target_flags & MASK_MULTIPLE)
203 #define TARGET_MULTIPLE_SET (target_flags & MASK_MULTIPLE_SET)
204 #define TARGET_STRING (target_flags & MASK_STRING)
205 #define TARGET_STRING_SET (target_flags & MASK_STRING_SET)
206 #define TARGET_NO_UPDATE (target_flags & MASK_NO_UPDATE)
207 #define TARGET_NO_FUSED_MADD (target_flags & MASK_NO_FUSED_MADD)
208 #define TARGET_SCHED_PROLOG (target_flags & MASK_SCHED_PROLOG)
209 #define TARGET_ALTIVEC (target_flags & MASK_ALTIVEC)
210 #define TARGET_AIX_STRUCT_RET (target_flags & MASK_AIX_STRUCT_RET)
212 #define TARGET_32BIT (! TARGET_64BIT)
213 #define TARGET_HARD_FLOAT (! TARGET_SOFT_FLOAT)
214 #define TARGET_UPDATE (! TARGET_NO_UPDATE)
215 #define TARGET_FUSED_MADD (! TARGET_NO_FUSED_MADD)
218 /* For libgcc2 we make sure this is a compile time constant */
219 #if defined (__64BIT__) || defined (__powerpc64__)
220 #define TARGET_POWERPC64 1
222 #define TARGET_POWERPC64 0
225 #define TARGET_POWERPC64 (target_flags & MASK_POWERPC64)
228 #define TARGET_XL_CALL 0
230 /* Run-time compilation parameters selecting different hardware subsets.
232 Macro to define tables used to set the flags.
233 This is a list in braces of pairs in braces,
234 each pair being { "NAME", VALUE }
235 where VALUE is the bits to set or minus the bits to clear.
236 An empty string NAME is used to identify the default VALUE. */
238 #define TARGET_SWITCHES \
239 {{"power", MASK_POWER | MASK_MULTIPLE | MASK_STRING, \
240 N_("Use POWER instruction set")}, \
241 {"power2", (MASK_POWER | MASK_MULTIPLE | MASK_STRING \
243 N_("Use POWER2 instruction set")}, \
244 {"no-power2", - MASK_POWER2, \
245 N_("Do not use POWER2 instruction set")}, \
246 {"no-power", - (MASK_POWER | MASK_POWER2 | MASK_MULTIPLE \
248 N_("Do not use POWER instruction set")}, \
249 {"powerpc", MASK_POWERPC, \
250 N_("Use PowerPC instruction set")}, \
251 {"no-powerpc", - (MASK_POWERPC | MASK_PPC_GPOPT \
252 | MASK_PPC_GFXOPT | MASK_POWERPC64), \
253 N_("Do not use PowerPC instruction set")}, \
254 {"powerpc-gpopt", MASK_POWERPC | MASK_PPC_GPOPT, \
255 N_("Use PowerPC General Purpose group optional instructions")},\
256 {"no-powerpc-gpopt", - MASK_PPC_GPOPT, \
257 N_("Don't use PowerPC General Purpose group optional instructions")},\
258 {"powerpc-gfxopt", MASK_POWERPC | MASK_PPC_GFXOPT, \
259 N_("Use PowerPC Graphics group optional instructions")},\
260 {"no-powerpc-gfxopt", - MASK_PPC_GFXOPT, \
261 N_("Don't use PowerPC Graphics group optional instructions")},\
262 {"powerpc64", MASK_POWERPC64, \
263 N_("Use PowerPC-64 instruction set")}, \
264 {"no-powerpc64", - MASK_POWERPC64, \
265 N_("Don't use PowerPC-64 instruction set")}, \
266 {"altivec", MASK_ALTIVEC , \
267 N_("Use AltiVec instructions")}, \
268 {"no-altivec", - MASK_ALTIVEC , \
269 N_("Don't use AltiVec instructions")}, \
270 {"new-mnemonics", MASK_NEW_MNEMONICS, \
271 N_("Use new mnemonics for PowerPC architecture")},\
272 {"old-mnemonics", -MASK_NEW_MNEMONICS, \
273 N_("Use old mnemonics for PowerPC architecture")},\
274 {"full-toc", - (MASK_NO_FP_IN_TOC | MASK_NO_SUM_IN_TOC \
275 | MASK_MINIMAL_TOC), \
276 N_("Put everything in the regular TOC")}, \
277 {"fp-in-toc", - MASK_NO_FP_IN_TOC, \
278 N_("Place floating point constants in TOC")}, \
279 {"no-fp-in-toc", MASK_NO_FP_IN_TOC, \
280 N_("Don't place floating point constants in TOC")},\
281 {"sum-in-toc", - MASK_NO_SUM_IN_TOC, \
282 N_("Place symbol+offset constants in TOC")}, \
283 {"no-sum-in-toc", MASK_NO_SUM_IN_TOC, \
284 N_("Don't place symbol+offset constants in TOC")},\
285 {"minimal-toc", MASK_MINIMAL_TOC, \
286 "Use only one TOC entry per procedure"}, \
287 {"minimal-toc", - (MASK_NO_FP_IN_TOC | MASK_NO_SUM_IN_TOC), \
289 {"no-minimal-toc", - MASK_MINIMAL_TOC, \
290 N_("Place variable addresses in the regular TOC")},\
291 {"hard-float", - MASK_SOFT_FLOAT, \
292 N_("Use hardware fp")}, \
293 {"soft-float", MASK_SOFT_FLOAT, \
294 N_("Do not use hardware fp")}, \
295 {"multiple", MASK_MULTIPLE | MASK_MULTIPLE_SET, \
296 N_("Generate load/store multiple instructions")}, \
297 {"no-multiple", - MASK_MULTIPLE, \
298 N_("Do not generate load/store multiple instructions")},\
299 {"no-multiple", MASK_MULTIPLE_SET, \
301 {"string", MASK_STRING | MASK_STRING_SET, \
302 N_("Generate string instructions for block moves")},\
303 {"no-string", - MASK_STRING, \
304 N_("Do not generate string instructions for block moves")},\
305 {"no-string", MASK_STRING_SET, \
307 {"update", - MASK_NO_UPDATE, \
308 N_("Generate load/store with update instructions")},\
309 {"no-update", MASK_NO_UPDATE, \
310 N_("Do not generate load/store with update instructions")},\
311 {"fused-madd", - MASK_NO_FUSED_MADD, \
312 N_("Generate fused multiply/add instructions")},\
313 {"no-fused-madd", MASK_NO_FUSED_MADD, \
314 N_("Don't generate fused multiply/add instructions")},\
315 {"sched-prolog", MASK_SCHED_PROLOG, \
317 {"no-sched-prolog", -MASK_SCHED_PROLOG, \
318 N_("Don't schedule the start and end of the procedure")},\
319 {"sched-epilog", MASK_SCHED_PROLOG, \
321 {"no-sched-epilog", -MASK_SCHED_PROLOG, \
323 {"aix-struct-return", MASK_AIX_STRUCT_RET | MASK_AIX_STRUCT_RET_SET, \
324 N_("Return all structures in memory (AIX default)")},\
325 {"svr4-struct-return", - MASK_AIX_STRUCT_RET,\
326 N_("Return small structures in registers (SVR4 default)")},\
327 {"svr4-struct-return",MASK_AIX_STRUCT_RET_SET,\
329 {"no-aix-struct-return", - MASK_AIX_STRUCT_RET,\
331 {"no-aix-struct-return", MASK_AIX_STRUCT_RET_SET,\
333 {"no-svr4-struct-return", MASK_AIX_STRUCT_RET | MASK_AIX_STRUCT_RET_SET,\
336 {"", TARGET_DEFAULT | MASK_SCHED_PROLOG, \
339 #define TARGET_DEFAULT (MASK_POWER | MASK_MULTIPLE | MASK_STRING)
341 /* This is meant to be redefined in the host dependent files */
342 #define SUBTARGET_SWITCHES
344 /* Processor type. Order must match cpu attribute in MD file. */
366 extern enum processor_type rs6000_cpu;
368 /* Recast the processor type to the cpu attribute. */
369 #define rs6000_cpu_attr ((enum attr_cpu)rs6000_cpu)
371 /* Define generic processor types based upon current deployment. */
372 #define PROCESSOR_COMMON PROCESSOR_PPC601
373 #define PROCESSOR_POWER PROCESSOR_RIOS1
374 #define PROCESSOR_POWERPC PROCESSOR_PPC604
375 #define PROCESSOR_POWERPC64 PROCESSOR_RS64A
377 /* Define the default processor. This is overridden by other tm.h files. */
378 #define PROCESSOR_DEFAULT PROCESSOR_RIOS1
379 #define PROCESSOR_DEFAULT64 PROCESSOR_RS64A
381 /* Specify the dialect of assembler to use. New mnemonics is dialect one
382 and the old mnemonics are dialect zero. */
383 #define ASSEMBLER_DIALECT (TARGET_NEW_MNEMONICS ? 1 : 0)
385 /* This is meant to be overridden in target specific files. */
386 #define SUBTARGET_OPTIONS
388 #define TARGET_OPTIONS \
390 {"cpu=", &rs6000_select[1].string, \
391 N_("Use features of and schedule code for given CPU") }, \
392 {"tune=", &rs6000_select[2].string, \
393 N_("Schedule code for given CPU") }, \
394 {"debug=", &rs6000_debug_name, N_("Enable debug output") }, \
395 {"traceback=", &rs6000_traceback_name, \
396 N_("Select full, part, or no traceback table") }, \
397 {"abi=", &rs6000_abi_string, N_("Specify ABI to use") }, \
398 {"long-double-", &rs6000_long_double_size_string, \
399 N_("Specify size of long double (64 or 128 bits)") }, \
400 {"isel=", &rs6000_isel_string, \
401 N_("Specify yes/no if isel instructions should be generated") }, \
402 {"vrsave=", &rs6000_altivec_vrsave_string, \
403 N_("Specify yes/no if VRSAVE instructions should be generated for AltiVec") }, \
404 {"longcall", &rs6000_longcall_switch, \
405 N_("Avoid all range limits on call instructions") }, \
406 {"no-longcall", &rs6000_longcall_switch, "" }, \
410 /* rs6000_select[0] is reserved for the default cpu defined via --with-cpu */
411 struct rs6000_cpu_select
419 extern struct rs6000_cpu_select rs6000_select[];
422 extern const char *rs6000_debug_name; /* Name for -mdebug-xxxx option */
423 extern const char *rs6000_abi_string; /* for -mabi={sysv,darwin,eabi,aix,altivec} */
424 extern int rs6000_debug_stack; /* debug stack applications */
425 extern int rs6000_debug_arg; /* debug argument handling */
427 #define TARGET_DEBUG_STACK rs6000_debug_stack
428 #define TARGET_DEBUG_ARG rs6000_debug_arg
430 extern const char *rs6000_traceback_name; /* Type of traceback table. */
432 /* These are separate from target_flags because we've run out of bits
434 extern const char *rs6000_long_double_size_string;
435 extern int rs6000_long_double_type_size;
436 extern int rs6000_altivec_abi;
437 extern int rs6000_spe_abi;
438 extern int rs6000_isel;
439 extern int rs6000_fprs;
440 extern const char *rs6000_isel_string;
441 extern const char *rs6000_altivec_vrsave_string;
442 extern int rs6000_altivec_vrsave;
443 extern const char *rs6000_longcall_switch;
444 extern int rs6000_default_long_calls;
446 #define TARGET_LONG_DOUBLE_128 (rs6000_long_double_type_size == 128)
447 #define TARGET_ALTIVEC_ABI rs6000_altivec_abi
448 #define TARGET_ALTIVEC_VRSAVE rs6000_altivec_vrsave
450 #define TARGET_SPE_ABI 0
452 #define TARGET_ISEL 0
453 #define TARGET_FPRS 1
455 /* Sometimes certain combinations of command options do not make sense
456 on a particular target machine. You can define a macro
457 `OVERRIDE_OPTIONS' to take account of this. This macro, if
458 defined, is executed once just after all the command options have
461 Don't use this macro to turn on various extra optimizations for
462 `-O'. That is what `OPTIMIZATION_OPTIONS' is for.
464 On the RS/6000 this is used to define the target cpu type. */
466 #define OVERRIDE_OPTIONS rs6000_override_options (TARGET_CPU_DEFAULT)
468 /* Define this to change the optimizations performed by default. */
469 #define OPTIMIZATION_OPTIONS(LEVEL,SIZE) optimization_options(LEVEL,SIZE)
471 /* Show we can debug even without a frame pointer. */
472 #define CAN_DEBUG_WITHOUT_FP
475 #define REGISTER_TARGET_PRAGMAS(PFILE) do { \
476 cpp_register_pragma (PFILE, 0, "longcall", rs6000_pragma_longcall); \
479 /* Target #defines. */
480 #define TARGET_CPU_CPP_BUILTINS() \
481 rs6000_cpu_cpp_builtins (pfile)
483 /* Target machine storage layout. */
485 /* Define this macro if it is advisable to hold scalars in registers
486 in a wider mode than that declared by the program. In such cases,
487 the value is constrained to be within the bounds of the declared
488 type, but kept valid in the wider mode. The signedness of the
489 extension may differ from that of the type. */
491 #define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \
492 if (GET_MODE_CLASS (MODE) == MODE_INT \
493 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
496 /* Define this if function arguments should also be promoted using the above
499 #define PROMOTE_FUNCTION_ARGS
501 /* Likewise, if the function return value is promoted. */
503 #define PROMOTE_FUNCTION_RETURN
505 /* Define this if most significant bit is lowest numbered
506 in instructions that operate on numbered bit-fields. */
507 /* That is true on RS/6000. */
508 #define BITS_BIG_ENDIAN 1
510 /* Define this if most significant byte of a word is the lowest numbered. */
511 /* That is true on RS/6000. */
512 #define BYTES_BIG_ENDIAN 1
514 /* Define this if most significant word of a multiword number is lowest
517 For RS/6000 we can decide arbitrarily since there are no machine
518 instructions for them. Might as well be consistent with bits and bytes. */
519 #define WORDS_BIG_ENDIAN 1
521 #define MAX_BITS_PER_WORD 64
523 /* Width of a word, in units (bytes). */
524 #define UNITS_PER_WORD (! TARGET_POWERPC64 ? 4 : 8)
526 #define MIN_UNITS_PER_WORD UNITS_PER_WORD
528 #define MIN_UNITS_PER_WORD 4
530 #define UNITS_PER_FP_WORD 8
531 #define UNITS_PER_ALTIVEC_WORD 16
532 #define UNITS_PER_SPE_WORD 8
534 /* Type used for ptrdiff_t, as a string used in a declaration. */
535 #define PTRDIFF_TYPE "int"
537 /* Type used for size_t, as a string used in a declaration. */
538 #define SIZE_TYPE "long unsigned int"
540 /* Type used for wchar_t, as a string used in a declaration. */
541 #define WCHAR_TYPE "short unsigned int"
543 /* Width of wchar_t in bits. */
544 #define WCHAR_TYPE_SIZE 16
546 /* A C expression for the size in bits of the type `short' on the
547 target machine. If you don't define this, the default is half a
548 word. (If this would be less than one storage unit, it is
549 rounded up to one unit.) */
550 #define SHORT_TYPE_SIZE 16
552 /* A C expression for the size in bits of the type `int' on the
553 target machine. If you don't define this, the default is one
555 #define INT_TYPE_SIZE 32
557 /* A C expression for the size in bits of the type `long' on the
558 target machine. If you don't define this, the default is one
560 #define LONG_TYPE_SIZE (TARGET_32BIT ? 32 : 64)
561 #define MAX_LONG_TYPE_SIZE 64
563 /* A C expression for the size in bits of the type `long long' on the
564 target machine. If you don't define this, the default is two
566 #define LONG_LONG_TYPE_SIZE 64
568 /* A C expression for the size in bits of the type `float' on the
569 target machine. If you don't define this, the default is one
571 #define FLOAT_TYPE_SIZE 32
573 /* A C expression for the size in bits of the type `double' on the
574 target machine. If you don't define this, the default is two
576 #define DOUBLE_TYPE_SIZE 64
578 /* A C expression for the size in bits of the type `long double' on
579 the target machine. If you don't define this, the default is two
581 #define LONG_DOUBLE_TYPE_SIZE rs6000_long_double_type_size
583 /* Constant which presents upper bound of the above value. */
584 #define MAX_LONG_DOUBLE_TYPE_SIZE 128
586 /* Define this to set long double type size to use in libgcc2.c, which can
587 not depend on target_flags. */
588 #ifdef __LONG_DOUBLE_128__
589 #define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 128
591 #define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 64
594 /* Width in bits of a pointer.
595 See also the macro `Pmode' defined below. */
596 #define POINTER_SIZE (TARGET_32BIT ? 32 : 64)
598 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
599 #define PARM_BOUNDARY (TARGET_32BIT ? 32 : 64)
601 /* Boundary (in *bits*) on which stack pointer should be aligned. */
602 #define STACK_BOUNDARY ((TARGET_32BIT && !TARGET_ALTIVEC_ABI) ? 64 : 128)
604 /* Allocation boundary (in *bits*) for the code of a function. */
605 #define FUNCTION_BOUNDARY 32
607 /* No data type wants to be aligned rounder than this. */
608 #define BIGGEST_ALIGNMENT 128
610 /* A C expression to compute the alignment for a variables in the
611 local store. TYPE is the data type, and ALIGN is the alignment
612 that the object would ordinarily have. */
613 #define LOCAL_ALIGNMENT(TYPE, ALIGN) \
614 ((TARGET_ALTIVEC && TREE_CODE (TYPE) == VECTOR_TYPE) ? 128 : \
615 (TARGET_SPE && TREE_CODE (TYPE) == VECTOR_TYPE) ? 64 : ALIGN)
617 /* Alignment of field after `int : 0' in a structure. */
618 #define EMPTY_FIELD_BOUNDARY 32
620 /* Every structure's size must be a multiple of this. */
621 #define STRUCTURE_SIZE_BOUNDARY 8
623 /* Return 1 if a structure or array containing FIELD should be
624 accessed using `BLKMODE'.
626 For the SPE, simd types are V2SI, and gcc can be tempted to put the
627 entire thing in a DI and use subregs to access the internals.
628 store_bit_field() will force (subreg:DI (reg:V2SI x))'s to the
629 back-end. Because a single GPR can hold a V2SI, but not a DI, the
630 best thing to do is set structs to BLKmode and avoid Severe Tire
632 #define MEMBER_TYPE_FORCES_BLK(FIELD, MODE) \
633 (TARGET_SPE && TREE_CODE (TREE_TYPE (FIELD)) == VECTOR_TYPE)
635 /* A bitfield declared as `int' forces `int' alignment for the struct. */
636 #define PCC_BITFIELD_TYPE_MATTERS 1
638 /* Make strings word-aligned so strcpy from constants will be faster.
639 Make vector constants quadword aligned. */
640 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
641 (TREE_CODE (EXP) == STRING_CST \
642 && (ALIGN) < BITS_PER_WORD \
646 /* Make arrays of chars word-aligned for the same reasons.
647 Align vectors to 128 bits. */
648 #define DATA_ALIGNMENT(TYPE, ALIGN) \
649 (TREE_CODE (TYPE) == VECTOR_TYPE ? (TARGET_SPE_ABI ? 64 : 128) \
650 : TREE_CODE (TYPE) == ARRAY_TYPE \
651 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
652 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
654 /* Non-zero if move instructions will actually fail to work
655 when given unaligned data. */
656 #define STRICT_ALIGNMENT 0
658 /* Define this macro to be the value 1 if unaligned accesses have a cost
659 many times greater than aligned accesses, for example if they are
660 emulated in a trap handler. */
661 #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) \
663 || (((MODE) == SFmode || (MODE) == DFmode || (MODE) == DImode) \
666 /* Standard register usage. */
668 /* Number of actual hardware registers.
669 The hardware registers are assigned numbers for the compiler
670 from 0 to just below FIRST_PSEUDO_REGISTER.
671 All registers that the compiler knows about must be given numbers,
672 even those that are not normally considered general registers.
674 RS/6000 has 32 fixed-point registers, 32 floating-point registers,
675 an MQ register, a count register, a link register, and 8 condition
676 register fields, which we view here as separate registers.
678 In addition, the difference between the frame and argument pointers is
679 a function of the number of registers saved, so we need to have a
680 register for AP that will later be eliminated in favor of SP or FP.
681 This is a normal register, but it is fixed.
683 We also create a pseudo register for float/int conversions, that will
684 really represent the memory location used. It is represented here as
685 a register, in order to work around problems in allocating stack storage
686 in inline functions. */
688 #define FIRST_PSEUDO_REGISTER 113
690 /* This must be included for pre gcc 3.0 glibc compatibility. */
691 #define PRE_GCC3_DWARF_FRAME_REGISTERS 77
693 /* 1 for registers that have pervasive standard uses
694 and are not available for the register allocator.
696 On RS/6000, r1 is used for the stack. On Darwin, r2 is available
697 as a local register; for all other OS's r2 is the TOC pointer.
699 cr5 is not supposed to be used.
701 On System V implementations, r13 is fixed and not available for use. */
703 #define FIXED_REGISTERS \
704 {0, 1, FIXED_R2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, FIXED_R13, 0, 0, \
705 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
706 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
707 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
708 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, 1, \
709 /* AltiVec registers. */ \
710 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
711 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
716 /* 1 for registers not available across function calls.
717 These must include the FIXED_REGISTERS and also any
718 registers that can be used without being saved.
719 The latter must include the registers where values are returned
720 and the register where structure-value addresses are passed.
721 Aside from that, you can include as many other registers as you like. */
723 #define CALL_USED_REGISTERS \
724 {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, FIXED_R13, 0, 0, \
725 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
726 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, \
727 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
728 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, \
729 /* AltiVec registers. */ \
730 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
731 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
736 /* Like `CALL_USED_REGISTERS' except this macro doesn't require that
737 the entire set of `FIXED_REGISTERS' be included.
738 (`CALL_USED_REGISTERS' must be a superset of `FIXED_REGISTERS').
739 This macro is optional. If not specified, it defaults to the value
740 of `CALL_USED_REGISTERS'. */
742 #define CALL_REALLY_USED_REGISTERS \
743 {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, FIXED_R13, 0, 0, \
744 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
745 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, \
746 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
747 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, \
748 /* AltiVec registers. */ \
749 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
750 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
761 #define MAX_CR_REGNO 75
763 #define FIRST_ALTIVEC_REGNO 77
764 #define LAST_ALTIVEC_REGNO 108
765 #define TOTAL_ALTIVEC_REGS (LAST_ALTIVEC_REGNO - FIRST_ALTIVEC_REGNO + 1)
766 #define VRSAVE_REGNO 109
767 #define VSCR_REGNO 110
768 #define SPE_ACC_REGNO 111
769 #define SPEFSCR_REGNO 112
771 /* List the order in which to allocate registers. Each register must be
772 listed once, even those in FIXED_REGISTERS.
774 We allocate in the following order:
775 fp0 (not saved or used for anything)
776 fp13 - fp2 (not saved; incoming fp arg registers)
777 fp1 (not saved; return value)
778 fp31 - fp14 (saved; order given to save least number)
779 cr7, cr6 (not saved or special)
780 cr1 (not saved, but used for FP operations)
781 cr0 (not saved, but used for arithmetic operations)
782 cr4, cr3, cr2 (saved)
783 r0 (not saved; cannot be base reg)
784 r9 (not saved; best for TImode)
785 r11, r10, r8-r4 (not saved; highest used first to make less conflict)
786 r3 (not saved; return value register)
787 r31 - r13 (saved; order given to save least number)
788 r12 (not saved; if used for DImode or DFmode would use r13)
789 mq (not saved; best to use it if we can)
790 ctr (not saved; when we have the choice ctr is better)
792 cr5, r1, r2, ap, xer, vrsave, vscr (fixed)
793 spe_acc, spefscr (fixed)
796 v0 - v1 (not saved or used for anything)
797 v13 - v3 (not saved; incoming vector arg registers)
798 v2 (not saved; incoming vector arg reg; return value)
799 v19 - v14 (not saved or used for anything)
800 v31 - v20 (saved; order given to save least number)
804 #define REG_ALLOC_ORDER \
806 45, 44, 43, 42, 41, 40, 39, 38, 37, 36, 35, 34, \
808 63, 62, 61, 60, 59, 58, 57, 56, 55, 54, 53, 52, 51, \
809 50, 49, 48, 47, 46, \
810 75, 74, 69, 68, 72, 71, 70, \
812 9, 11, 10, 8, 7, 6, 5, 4, \
814 31, 30, 29, 28, 27, 26, 25, 24, 23, 22, 21, 20, 19, \
815 18, 17, 16, 15, 14, 13, 12, \
818 /* AltiVec registers. */ \
820 90, 89, 88, 87, 86, 85, 84, 83, 82, 81, 80, \
822 96, 95, 94, 93, 92, 91, \
823 108, 107, 106, 105, 104, 103, 102, 101, 100, 99, 98, \
828 /* True if register is floating-point. */
829 #define FP_REGNO_P(N) ((N) >= 32 && (N) <= 63)
831 /* True if register is a condition register. */
832 #define CR_REGNO_P(N) ((N) >= 68 && (N) <= 75)
834 /* True if register is a condition register, but not cr0. */
835 #define CR_REGNO_NOT_CR0_P(N) ((N) >= 69 && (N) <= 75)
837 /* True if register is an integer register. */
838 #define INT_REGNO_P(N) ((N) <= 31 || (N) == ARG_POINTER_REGNUM)
840 /* SPE SIMD registers are just the GPRs. */
841 #define SPE_SIMD_REGNO_P(N) ((N) <= 31)
843 /* True if register is the XER register. */
844 #define XER_REGNO_P(N) ((N) == XER_REGNO)
846 /* True if register is an AltiVec register. */
847 #define ALTIVEC_REGNO_P(N) ((N) >= FIRST_ALTIVEC_REGNO && (N) <= LAST_ALTIVEC_REGNO)
849 /* Return number of consecutive hard regs needed starting at reg REGNO
850 to hold something of mode MODE.
851 This is ordinarily the length in words of a value of mode MODE
852 but can be less for certain modes in special long registers.
854 For the SPE, GPRs are 64 bits but only 32 bits are visible in
855 scalar instructions. The upper 32 bits are only available to the
858 POWER and PowerPC GPRs hold 32 bits worth;
859 PowerPC64 GPRs and FPRs point register holds 64 bits worth. */
861 #define HARD_REGNO_NREGS(REGNO, MODE) \
862 (FP_REGNO_P (REGNO) \
863 ? ((GET_MODE_SIZE (MODE) + UNITS_PER_FP_WORD - 1) / UNITS_PER_FP_WORD) \
864 : (SPE_SIMD_REGNO_P (REGNO) && TARGET_SPE && SPE_VECTOR_MODE (MODE)) \
865 ? ((GET_MODE_SIZE (MODE) + UNITS_PER_SPE_WORD - 1) / UNITS_PER_SPE_WORD) \
866 : ALTIVEC_REGNO_P (REGNO) \
867 ? ((GET_MODE_SIZE (MODE) + UNITS_PER_ALTIVEC_WORD - 1) / UNITS_PER_ALTIVEC_WORD) \
868 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
870 #define ALTIVEC_VECTOR_MODE(MODE) \
871 ((MODE) == V16QImode \
872 || (MODE) == V8HImode \
873 || (MODE) == V4SFmode \
874 || (MODE) == V4SImode)
876 #define SPE_VECTOR_MODE(MODE) \
877 ((MODE) == V4HImode \
878 || (MODE) == V2SFmode \
879 || (MODE) == V2SImode)
881 /* Define this macro to be nonzero if the port is prepared to handle
882 insns involving vector mode MODE. At the very least, it must have
883 move patterns for this mode. */
885 #define VECTOR_MODE_SUPPORTED_P(MODE) \
886 ((TARGET_SPE && SPE_VECTOR_MODE (MODE)) \
887 || (TARGET_ALTIVEC && ALTIVEC_VECTOR_MODE (MODE)))
889 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
890 For POWER and PowerPC, the GPRs can hold any mode, but the float
891 registers only can hold floating modes and DImode, and CR register only
892 can hold CC modes. We cannot put TImode anywhere except general
893 register and it must be able to fit within the register set. */
895 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
896 (FP_REGNO_P (REGNO) ? \
897 (GET_MODE_CLASS (MODE) == MODE_FLOAT \
898 || (GET_MODE_CLASS (MODE) == MODE_INT \
899 && GET_MODE_SIZE (MODE) == UNITS_PER_FP_WORD)) \
900 : ALTIVEC_REGNO_P (REGNO) ? ALTIVEC_VECTOR_MODE (MODE) \
901 : SPE_SIMD_REGNO_P (REGNO) && TARGET_SPE && SPE_VECTOR_MODE (MODE) ? 1 \
902 : CR_REGNO_P (REGNO) ? GET_MODE_CLASS (MODE) == MODE_CC \
903 : XER_REGNO_P (REGNO) ? (MODE) == PSImode \
904 : ! INT_REGNO_P (REGNO) ? (GET_MODE_CLASS (MODE) == MODE_INT \
905 && GET_MODE_SIZE (MODE) <= UNITS_PER_WORD) \
908 /* Value is 1 if it is a good idea to tie two pseudo registers
909 when one has mode MODE1 and one has mode MODE2.
910 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
911 for any hard reg, then this must be 0 for correct output. */
912 #define MODES_TIEABLE_P(MODE1, MODE2) \
913 (GET_MODE_CLASS (MODE1) == MODE_FLOAT \
914 ? GET_MODE_CLASS (MODE2) == MODE_FLOAT \
915 : GET_MODE_CLASS (MODE2) == MODE_FLOAT \
916 ? GET_MODE_CLASS (MODE1) == MODE_FLOAT \
917 : GET_MODE_CLASS (MODE1) == MODE_CC \
918 ? GET_MODE_CLASS (MODE2) == MODE_CC \
919 : GET_MODE_CLASS (MODE2) == MODE_CC \
920 ? GET_MODE_CLASS (MODE1) == MODE_CC \
921 : ALTIVEC_VECTOR_MODE (MODE1) \
922 ? ALTIVEC_VECTOR_MODE (MODE2) \
923 : ALTIVEC_VECTOR_MODE (MODE2) \
924 ? ALTIVEC_VECTOR_MODE (MODE1) \
927 /* A C expression returning the cost of moving data from a register of class
928 CLASS1 to one of CLASS2.
930 On the RS/6000, copying between floating-point and fixed-point
931 registers is expensive. */
933 #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \
934 ((CLASS1) == FLOAT_REGS && (CLASS2) == FLOAT_REGS ? 2 \
935 : (CLASS1) == FLOAT_REGS && (CLASS2) != FLOAT_REGS ? 10 \
936 : (CLASS1) != FLOAT_REGS && (CLASS2) == FLOAT_REGS ? 10 \
937 : (CLASS1) == ALTIVEC_REGS && (CLASS2) != ALTIVEC_REGS ? 20 \
938 : (CLASS1) != ALTIVEC_REGS && (CLASS2) == ALTIVEC_REGS ? 20 \
939 : (((CLASS1) == SPECIAL_REGS || (CLASS1) == MQ_REGS \
940 || (CLASS1) == LINK_REGS || (CLASS1) == CTR_REGS \
941 || (CLASS1) == LINK_OR_CTR_REGS) \
942 && ((CLASS2) == SPECIAL_REGS || (CLASS2) == MQ_REGS \
943 || (CLASS2) == LINK_REGS || (CLASS2) == CTR_REGS \
944 || (CLASS2) == LINK_OR_CTR_REGS)) ? 10 \
947 /* A C expressions returning the cost of moving data of MODE from a register to
950 On the RS/6000, bump this up a bit. */
952 #define MEMORY_MOVE_COST(MODE, CLASS, IN) \
953 ((GET_MODE_CLASS (MODE) == MODE_FLOAT \
954 && (rs6000_cpu == PROCESSOR_RIOS1 || rs6000_cpu == PROCESSOR_PPC601) \
958 /* Specify the cost of a branch insn; roughly the number of extra insns that
959 should be added to avoid a branch.
961 Set this to 3 on the RS/6000 since that is roughly the average cost of an
962 unscheduled conditional branch. */
964 #define BRANCH_COST 3
967 /* A fixed register used at prologue and epilogue generation to fix
968 addressing modes. The SPE needs heavy addressing fixes at the last
969 minute, and it's best to save a register for it.
971 AltiVec also needs fixes, but we've gotten around using r11, which
972 is actually wrong because when use_backchain_to_restore_sp is true,
973 we end up clobbering r11.
975 The AltiVec case needs to be fixed. Dunno if we should break ABI
976 compatability and reserve a register for it as well.. */
978 #define FIXED_SCRATCH (TARGET_SPE ? 14 : 11)
980 /* Define this macro to change register usage conditional on target flags.
981 Set MQ register fixed (already call_used) if not POWER architecture
982 (RIOS1, RIOS2, RSC, and PPC601) so that it will not be allocated.
983 64-bit AIX reserves GPR13 for thread-private data.
984 Conditionally disable FPRs. */
986 #define CONDITIONAL_REGISTER_USAGE \
989 if (! TARGET_POWER) \
990 fixed_regs[64] = 1; \
992 fixed_regs[13] = call_used_regs[13] \
993 = call_really_used_regs[13] = 1; \
994 if (TARGET_SOFT_FLOAT || !TARGET_FPRS) \
995 for (i = 32; i < 64; i++) \
996 fixed_regs[i] = call_used_regs[i] \
997 = call_really_used_regs[i] = 1; \
998 if (DEFAULT_ABI == ABI_V4 \
999 && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM \
1001 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] \
1002 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] \
1003 = call_really_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1; \
1004 if (DEFAULT_ABI == ABI_DARWIN \
1005 && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM) \
1006 global_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] \
1007 = fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] \
1008 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] \
1009 = call_really_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1; \
1010 if (TARGET_ALTIVEC) \
1011 global_regs[VSCR_REGNO] = 1; \
1014 global_regs[SPEFSCR_REGNO] = 1; \
1015 fixed_regs[FIXED_SCRATCH] \
1016 = call_used_regs[FIXED_SCRATCH] \
1017 = call_really_used_regs[FIXED_SCRATCH] = 1; \
1019 if (! TARGET_ALTIVEC) \
1021 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i) \
1022 fixed_regs[i] = call_used_regs[i] = call_really_used_regs[i] = 1; \
1023 call_really_used_regs[VRSAVE_REGNO] = 1; \
1025 if (TARGET_ALTIVEC_ABI) \
1026 for (i = FIRST_ALTIVEC_REGNO; i < FIRST_ALTIVEC_REGNO + 20; ++i) \
1027 call_used_regs[i] = call_really_used_regs[i] = 1; \
1030 /* Specify the registers used for certain standard purposes.
1031 The values of these macros are register numbers. */
1033 /* RS/6000 pc isn't overloaded on a register that the compiler knows about. */
1034 /* #define PC_REGNUM */
1036 /* Register to use for pushing function arguments. */
1037 #define STACK_POINTER_REGNUM 1
1039 /* Base register for access to local variables of the function. */
1040 #define FRAME_POINTER_REGNUM 31
1042 /* Value should be nonzero if functions must have frame pointers.
1043 Zero means the frame pointer need not be set up (and parms
1044 may be accessed via the stack pointer) in functions that seem suitable.
1045 This is computed in `reload', in reload1.c. */
1046 #define FRAME_POINTER_REQUIRED 0
1048 /* Base register for access to arguments of the function. */
1049 #define ARG_POINTER_REGNUM 67
1051 /* Place to put static chain when calling a function that requires it. */
1052 #define STATIC_CHAIN_REGNUM 11
1054 /* Link register number. */
1055 #define LINK_REGISTER_REGNUM 65
1057 /* Count register number. */
1058 #define COUNT_REGISTER_REGNUM 66
1060 /* Place that structure value return address is placed.
1062 On the RS/6000, it is passed as an extra parameter. */
1063 #define STRUCT_VALUE 0
1065 /* Define the classes of registers for register constraints in the
1066 machine description. Also define ranges of constants.
1068 One of the classes must always be named ALL_REGS and include all hard regs.
1069 If there is more than one class, another class must be named NO_REGS
1070 and contain no registers.
1072 The name GENERAL_REGS must be the name of a class (or an alias for
1073 another name such as ALL_REGS). This is the class of registers
1074 that is allowed by "g" or "r" in a register constraint.
1075 Also, registers outside this class are allocated only when
1076 instructions express preferences for them.
1078 The classes must be numbered in nondecreasing order; that is,
1079 a larger-numbered class must never be contained completely
1080 in a smaller-numbered class.
1082 For any two classes, it is very desirable that there be another
1083 class that represents their union. */
1085 /* The RS/6000 has three types of registers, fixed-point, floating-point,
1086 and condition registers, plus three special registers, MQ, CTR, and the
1089 However, r0 is special in that it cannot be used as a base register.
1090 So make a class for registers valid as base registers.
1092 Also, cr0 is the only condition code register that can be used in
1093 arithmetic insns, so make a separate class for it. */
1121 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1123 /* Give names of register classes as strings for dump file. */
1125 #define REG_CLASS_NAMES \
1136 "NON_SPECIAL_REGS", \
1140 "LINK_OR_CTR_REGS", \
1142 "SPEC_OR_GEN_REGS", \
1150 /* Define which registers fit in which classes.
1151 This is an initializer for a vector of HARD_REG_SET
1152 of length N_REG_CLASSES. */
1154 #define REG_CLASS_CONTENTS \
1156 { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \
1157 { 0xfffffffe, 0x00000000, 0x00000008, 0x00000000 }, /* BASE_REGS */ \
1158 { 0xffffffff, 0x00000000, 0x00000008, 0x00000000 }, /* GENERAL_REGS */ \
1159 { 0x00000000, 0xffffffff, 0x00000000, 0x00000000 }, /* FLOAT_REGS */ \
1160 { 0x00000000, 0x00000000, 0xffffe000, 0x00001fff }, /* ALTIVEC_REGS */ \
1161 { 0x00000000, 0x00000000, 0x00000000, 0x00002000 }, /* VRSAVE_REGS */ \
1162 { 0x00000000, 0x00000000, 0x00000000, 0x00004000 }, /* VSCR_REGS */ \
1163 { 0x00000000, 0x00000000, 0x00000000, 0x00008000 }, /* SPE_ACC_REGS */ \
1164 { 0x00000000, 0x00000000, 0x00000000, 0x00010000 }, /* SPEFSCR_REGS */ \
1165 { 0xffffffff, 0xffffffff, 0x00000008, 0x00000000 }, /* NON_SPECIAL_REGS */ \
1166 { 0x00000000, 0x00000000, 0x00000001, 0x00000000 }, /* MQ_REGS */ \
1167 { 0x00000000, 0x00000000, 0x00000002, 0x00000000 }, /* LINK_REGS */ \
1168 { 0x00000000, 0x00000000, 0x00000004, 0x00000000 }, /* CTR_REGS */ \
1169 { 0x00000000, 0x00000000, 0x00000006, 0x00000000 }, /* LINK_OR_CTR_REGS */ \
1170 { 0x00000000, 0x00000000, 0x00000007, 0x00002000 }, /* SPECIAL_REGS */ \
1171 { 0xffffffff, 0x00000000, 0x0000000f, 0x00000000 }, /* SPEC_OR_GEN_REGS */ \
1172 { 0x00000000, 0x00000000, 0x00000010, 0x00000000 }, /* CR0_REGS */ \
1173 { 0x00000000, 0x00000000, 0x00000ff0, 0x00000000 }, /* CR_REGS */ \
1174 { 0xffffffff, 0x00000000, 0x0000efff, 0x00000000 }, /* NON_FLOAT_REGS */ \
1175 { 0x00000000, 0x00000000, 0x00001000, 0x00000000 }, /* XER_REGS */ \
1176 { 0xffffffff, 0xffffffff, 0xffffffff, 0x00003fff } /* ALL_REGS */ \
1179 /* The same information, inverted:
1180 Return the class number of the smallest class containing
1181 reg number REGNO. This could be a conditional expression
1182 or could index an array. */
1184 #define REGNO_REG_CLASS(REGNO) \
1185 ((REGNO) == 0 ? GENERAL_REGS \
1186 : (REGNO) < 32 ? BASE_REGS \
1187 : FP_REGNO_P (REGNO) ? FLOAT_REGS \
1188 : ALTIVEC_REGNO_P (REGNO) ? ALTIVEC_REGS \
1189 : (REGNO) == CR0_REGNO ? CR0_REGS \
1190 : CR_REGNO_P (REGNO) ? CR_REGS \
1191 : (REGNO) == MQ_REGNO ? MQ_REGS \
1192 : (REGNO) == LINK_REGISTER_REGNUM ? LINK_REGS \
1193 : (REGNO) == COUNT_REGISTER_REGNUM ? CTR_REGS \
1194 : (REGNO) == ARG_POINTER_REGNUM ? BASE_REGS \
1195 : (REGNO) == XER_REGNO ? XER_REGS \
1196 : (REGNO) == VRSAVE_REGNO ? VRSAVE_REGS \
1197 : (REGNO) == VSCR_REGNO ? VRSAVE_REGS \
1198 : (REGNO) == SPE_ACC_REGNO ? SPE_ACC_REGS \
1199 : (REGNO) == SPEFSCR_REGNO ? SPEFSCR_REGS \
1202 /* The class value for index registers, and the one for base regs. */
1203 #define INDEX_REG_CLASS GENERAL_REGS
1204 #define BASE_REG_CLASS BASE_REGS
1206 /* Get reg_class from a letter such as appears in the machine description. */
1208 #define REG_CLASS_FROM_LETTER(C) \
1209 ((C) == 'f' ? FLOAT_REGS \
1210 : (C) == 'b' ? BASE_REGS \
1211 : (C) == 'h' ? SPECIAL_REGS \
1212 : (C) == 'q' ? MQ_REGS \
1213 : (C) == 'c' ? CTR_REGS \
1214 : (C) == 'l' ? LINK_REGS \
1215 : (C) == 'v' ? ALTIVEC_REGS \
1216 : (C) == 'x' ? CR0_REGS \
1217 : (C) == 'y' ? CR_REGS \
1218 : (C) == 'z' ? XER_REGS \
1221 /* The letters I, J, K, L, M, N, and P in a register constraint string
1222 can be used to stand for particular ranges of immediate operands.
1223 This macro defines what the ranges are.
1224 C is the letter, and VALUE is a constant value.
1225 Return 1 if VALUE is in the range specified by C.
1227 `I' is a signed 16-bit constant
1228 `J' is a constant with only the high-order 16 bits non-zero
1229 `K' is a constant with only the low-order 16 bits non-zero
1230 `L' is a signed 16-bit constant shifted left 16 bits
1231 `M' is a constant that is greater than 31
1232 `N' is a positive constant that is an exact power of two
1233 `O' is the constant zero
1234 `P' is a constant whose negation is a signed 16-bit constant */
1236 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
1237 ( (C) == 'I' ? (unsigned HOST_WIDE_INT) ((VALUE) + 0x8000) < 0x10000 \
1238 : (C) == 'J' ? ((VALUE) & (~ (unsigned HOST_WIDE_INT) 0xffff0000)) == 0 \
1239 : (C) == 'K' ? ((VALUE) & (~ (HOST_WIDE_INT) 0xffff)) == 0 \
1240 : (C) == 'L' ? (((VALUE) & 0xffff) == 0 \
1241 && ((VALUE) >> 31 == -1 || (VALUE) >> 31 == 0)) \
1242 : (C) == 'M' ? (VALUE) > 31 \
1243 : (C) == 'N' ? (VALUE) > 0 && exact_log2 (VALUE) >= 0 \
1244 : (C) == 'O' ? (VALUE) == 0 \
1245 : (C) == 'P' ? (unsigned HOST_WIDE_INT) ((- (VALUE)) + 0x8000) < 0x10000 \
1248 /* Similar, but for floating constants, and defining letters G and H.
1249 Here VALUE is the CONST_DOUBLE rtx itself.
1251 We flag for special constants when we can copy the constant into
1252 a general register in two insns for DF/DI and one insn for SF.
1254 'H' is used for DI/DF constants that take 3 insns. */
1256 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
1257 ( (C) == 'G' ? (num_insns_constant (VALUE, GET_MODE (VALUE)) \
1258 == ((GET_MODE (VALUE) == SFmode) ? 1 : 2)) \
1259 : (C) == 'H' ? (num_insns_constant (VALUE, GET_MODE (VALUE)) == 3) \
1262 /* Optional extra constraints for this machine.
1264 'Q' means that is a memory operand that is just an offset from a reg.
1265 'R' is for AIX TOC entries.
1266 'S' is a constant that can be placed into a 64-bit mask operand
1267 'T' is a constant that can be placed into a 32-bit mask operand
1268 'U' is for V.4 small data references.
1269 't' is for AND masks that can be performed by two rldic{l,r} insns. */
1271 #define EXTRA_CONSTRAINT(OP, C) \
1272 ((C) == 'Q' ? GET_CODE (OP) == MEM && GET_CODE (XEXP (OP, 0)) == REG \
1273 : (C) == 'R' ? LEGITIMATE_CONSTANT_POOL_ADDRESS_P (OP) \
1274 : (C) == 'S' ? mask64_operand (OP, DImode) \
1275 : (C) == 'T' ? mask_operand (OP, SImode) \
1276 : (C) == 'U' ? (DEFAULT_ABI == ABI_V4 \
1277 && small_data_operand (OP, GET_MODE (OP))) \
1278 : (C) == 't' ? (mask64_2_operand (OP, DImode) \
1279 && (fixed_regs[CR0_REGNO] \
1280 || !logical_operand (OP, DImode)) \
1281 && !mask64_operand (OP, DImode)) \
1284 /* Given an rtx X being reloaded into a reg required to be
1285 in class CLASS, return the class of reg to actually use.
1286 In general this is just CLASS; but on some machines
1287 in some cases it is preferable to use a more restrictive class.
1289 On the RS/6000, we have to return NO_REGS when we want to reload a
1290 floating-point CONST_DOUBLE to force it to be copied to memory.
1292 We also don't want to reload integer values into floating-point
1293 registers if we can at all help it. In fact, this can
1294 cause reload to abort, if it tries to generate a reload of CTR
1295 into a FP register and discovers it doesn't have the memory location
1298 ??? Would it be a good idea to have reload do the converse, that is
1299 try to reload floating modes into FP registers if possible?
1302 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
1303 (((GET_CODE (X) == CONST_DOUBLE \
1304 && GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT) \
1306 : (GET_MODE_CLASS (GET_MODE (X)) == MODE_INT \
1307 && (CLASS) == NON_SPECIAL_REGS) \
1311 /* Return the register class of a scratch register needed to copy IN into
1312 or out of a register in CLASS in MODE. If it can be done directly,
1313 NO_REGS is returned. */
1315 #define SECONDARY_RELOAD_CLASS(CLASS,MODE,IN) \
1316 secondary_reload_class (CLASS, MODE, IN)
1318 /* If we are copying between FP or AltiVec registers and anything
1319 else, we need a memory location. */
1321 #define SECONDARY_MEMORY_NEEDED(CLASS1,CLASS2,MODE) \
1322 ((CLASS1) != (CLASS2) && ((CLASS1) == FLOAT_REGS \
1323 || (CLASS2) == FLOAT_REGS \
1324 || (CLASS1) == ALTIVEC_REGS \
1325 || (CLASS2) == ALTIVEC_REGS))
1327 /* Return the maximum number of consecutive registers
1328 needed to represent mode MODE in a register of class CLASS.
1330 On RS/6000, this is the size of MODE in words,
1331 except in the FP regs, where a single reg is enough for two words. */
1332 #define CLASS_MAX_NREGS(CLASS, MODE) \
1333 (((CLASS) == FLOAT_REGS) \
1334 ? ((GET_MODE_SIZE (MODE) + UNITS_PER_FP_WORD - 1) / UNITS_PER_FP_WORD) \
1335 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
1337 /* If defined, gives a class of registers that cannot be used as the
1338 operand of a SUBREG that changes the mode of the object illegally. */
1340 #define CLASS_CANNOT_CHANGE_MODE FLOAT_REGS
1342 /* Defines illegal mode changes for CLASS_CANNOT_CHANGE_MODE. */
1344 #define CLASS_CANNOT_CHANGE_MODE_P(FROM,TO) \
1345 (GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO))
1347 /* Stack layout; function entry, exit and calling. */
1349 /* Enumeration to give which calling sequence to use. */
1352 ABI_AIX, /* IBM's AIX */
1353 ABI_AIX_NODESC, /* AIX calling sequence minus
1354 function descriptors */
1355 ABI_V4, /* System V.4/eabi */
1356 ABI_DARWIN /* Apple's Darwin (OS X kernel) */
1359 extern enum rs6000_abi rs6000_current_abi; /* available for use by subtarget */
1361 /* Structure used to define the rs6000 stack */
1362 typedef struct rs6000_stack {
1363 int first_gp_reg_save; /* first callee saved GP register used */
1364 int first_fp_reg_save; /* first callee saved FP register used */
1365 int first_altivec_reg_save; /* first callee saved AltiVec register used */
1366 int lr_save_p; /* true if the link reg needs to be saved */
1367 int cr_save_p; /* true if the CR reg needs to be saved */
1368 unsigned int vrsave_mask; /* mask of vec registers to save */
1369 int toc_save_p; /* true if the TOC needs to be saved */
1370 int push_p; /* true if we need to allocate stack space */
1371 int calls_p; /* true if the function makes any calls */
1372 enum rs6000_abi abi; /* which ABI to use */
1373 int gp_save_offset; /* offset to save GP regs from initial SP */
1374 int fp_save_offset; /* offset to save FP regs from initial SP */
1375 int altivec_save_offset; /* offset to save AltiVec regs from inital SP */
1376 int lr_save_offset; /* offset to save LR from initial SP */
1377 int cr_save_offset; /* offset to save CR from initial SP */
1378 int vrsave_save_offset; /* offset to save VRSAVE from initial SP */
1379 int spe_gp_save_offset; /* offset to save spe 64-bit gprs */
1380 int toc_save_offset; /* offset to save the TOC pointer */
1381 int varargs_save_offset; /* offset to save the varargs registers */
1382 int ehrd_offset; /* offset to EH return data */
1383 int reg_size; /* register size (4 or 8) */
1384 int varargs_size; /* size to hold V.4 args passed in regs */
1385 int vars_size; /* variable save area size */
1386 int parm_size; /* outgoing parameter size */
1387 int save_size; /* save area size */
1388 int fixed_size; /* fixed size of stack frame */
1389 int gp_size; /* size of saved GP registers */
1390 int fp_size; /* size of saved FP registers */
1391 int altivec_size; /* size of saved AltiVec registers */
1392 int cr_size; /* size to hold CR if not in save_size */
1393 int lr_size; /* size to hold LR if not in save_size */
1394 int vrsave_size; /* size to hold VRSAVE if not in save_size */
1395 int altivec_padding_size; /* size of altivec alignment padding if
1397 int spe_gp_size; /* size of 64-bit GPR save size for SPE */
1398 int spe_padding_size;
1399 int toc_size; /* size to hold TOC if not in save_size */
1400 int total_size; /* total bytes allocated for stack */
1403 /* Define this if pushing a word on the stack
1404 makes the stack pointer a smaller address. */
1405 #define STACK_GROWS_DOWNWARD
1407 /* Define this if the nominal address of the stack frame
1408 is at the high-address end of the local variables;
1409 that is, each additional local variable allocated
1410 goes at a more negative offset in the frame.
1412 On the RS/6000, we grow upwards, from the area after the outgoing
1414 /* #define FRAME_GROWS_DOWNWARD */
1416 /* Size of the outgoing register save area */
1417 #define RS6000_REG_SAVE ((DEFAULT_ABI == ABI_AIX \
1418 || DEFAULT_ABI == ABI_AIX_NODESC \
1419 || DEFAULT_ABI == ABI_DARWIN) \
1420 ? (TARGET_64BIT ? 64 : 32) \
1423 /* Size of the fixed area on the stack */
1424 #define RS6000_SAVE_AREA \
1425 (((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_AIX_NODESC || DEFAULT_ABI == ABI_DARWIN) ? 24 : 8) \
1426 << (TARGET_64BIT ? 1 : 0))
1428 /* MEM representing address to save the TOC register */
1429 #define RS6000_SAVE_TOC gen_rtx_MEM (Pmode, \
1430 plus_constant (stack_pointer_rtx, \
1431 (TARGET_32BIT ? 20 : 40)))
1433 /* Size of the V.4 varargs area if needed */
1434 #define RS6000_VARARGS_AREA 0
1436 /* Align an address */
1437 #define RS6000_ALIGN(n,a) (((n) + (a) - 1) & ~((a) - 1))
1439 /* Size of V.4 varargs area in bytes */
1440 #define RS6000_VARARGS_SIZE \
1441 ((GP_ARG_NUM_REG * (TARGET_32BIT ? 4 : 8)) + (FP_ARG_NUM_REG * 8) + 8)
1443 /* Offset within stack frame to start allocating local variables at.
1444 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
1445 first local allocated. Otherwise, it is the offset to the BEGINNING
1446 of the first local allocated.
1448 On the RS/6000, the frame pointer is the same as the stack pointer,
1449 except for dynamic allocations. So we start after the fixed area and
1450 outgoing parameter area. */
1452 #define STARTING_FRAME_OFFSET \
1453 (RS6000_ALIGN (current_function_outgoing_args_size, \
1454 TARGET_ALTIVEC ? 16 : 8) \
1455 + RS6000_VARARGS_AREA \
1458 /* Offset from the stack pointer register to an item dynamically
1459 allocated on the stack, e.g., by `alloca'.
1461 The default value for this macro is `STACK_POINTER_OFFSET' plus the
1462 length of the outgoing arguments. The default is correct for most
1463 machines. See `function.c' for details. */
1464 #define STACK_DYNAMIC_OFFSET(FUNDECL) \
1465 (RS6000_ALIGN (current_function_outgoing_args_size, \
1466 TARGET_ALTIVEC ? 16 : 8) \
1467 + (STACK_POINTER_OFFSET))
1469 /* If we generate an insn to push BYTES bytes,
1470 this says how many the stack pointer really advances by.
1471 On RS/6000, don't define this because there are no push insns. */
1472 /* #define PUSH_ROUNDING(BYTES) */
1474 /* Offset of first parameter from the argument pointer register value.
1475 On the RS/6000, we define the argument pointer to the start of the fixed
1477 #define FIRST_PARM_OFFSET(FNDECL) RS6000_SAVE_AREA
1479 /* Offset from the argument pointer register value to the top of
1480 stack. This is different from FIRST_PARM_OFFSET because of the
1481 register save area. */
1482 #define ARG_POINTER_CFA_OFFSET(FNDECL) 0
1484 /* Define this if stack space is still allocated for a parameter passed
1485 in a register. The value is the number of bytes allocated to this
1487 #define REG_PARM_STACK_SPACE(FNDECL) RS6000_REG_SAVE
1489 /* Define this if the above stack space is to be considered part of the
1490 space allocated by the caller. */
1491 #define OUTGOING_REG_PARM_STACK_SPACE
1493 /* This is the difference between the logical top of stack and the actual sp.
1495 For the RS/6000, sp points past the fixed area. */
1496 #define STACK_POINTER_OFFSET RS6000_SAVE_AREA
1498 /* Define this if the maximum size of all the outgoing args is to be
1499 accumulated and pushed during the prologue. The amount can be
1500 found in the variable current_function_outgoing_args_size. */
1501 #define ACCUMULATE_OUTGOING_ARGS 1
1503 /* Value is the number of bytes of arguments automatically
1504 popped when returning from a subroutine call.
1505 FUNDECL is the declaration node of the function (as a tree),
1506 FUNTYPE is the data type of the function (as a tree),
1507 or for a library call it is an identifier node for the subroutine name.
1508 SIZE is the number of bytes of arguments passed on the stack. */
1510 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
1512 /* Define how to find the value returned by a function.
1513 VALTYPE is the data type of the value (as a tree).
1514 If the precise function being called is known, FUNC is its FUNCTION_DECL;
1515 otherwise, FUNC is 0.
1517 On the SPE, both FPs and vectors are returned in r3.
1519 On RS/6000 an integer value is in r3 and a floating-point value is in
1520 fp1, unless -msoft-float. */
1522 #define FUNCTION_VALUE(VALTYPE, FUNC) \
1523 gen_rtx_REG ((INTEGRAL_TYPE_P (VALTYPE) \
1524 && TYPE_PRECISION (VALTYPE) < BITS_PER_WORD) \
1525 || POINTER_TYPE_P (VALTYPE) \
1526 ? word_mode : TYPE_MODE (VALTYPE), \
1527 TREE_CODE (VALTYPE) == VECTOR_TYPE \
1528 && TARGET_ALTIVEC ? ALTIVEC_ARG_RETURN \
1529 : TREE_CODE (VALTYPE) == REAL_TYPE \
1530 && TARGET_SPE_ABI && !TARGET_FPRS \
1532 : TREE_CODE (VALTYPE) == REAL_TYPE \
1533 && TARGET_HARD_FLOAT && TARGET_FPRS \
1534 ? FP_ARG_RETURN : GP_ARG_RETURN)
1536 /* Define how to find the value returned by a library function
1537 assuming the value has mode MODE. */
1539 #define LIBCALL_VALUE(MODE) \
1540 gen_rtx_REG (MODE, ALTIVEC_VECTOR_MODE (MODE) ? ALTIVEC_ARG_RETURN \
1541 : GET_MODE_CLASS (MODE) == MODE_FLOAT \
1542 && TARGET_HARD_FLOAT && TARGET_FPRS \
1543 ? FP_ARG_RETURN : GP_ARG_RETURN)
1545 /* The AIX ABI for the RS/6000 specifies that all structures are
1546 returned in memory. The Darwin ABI does the same. The SVR4 ABI
1547 specifies that structures <= 8 bytes are returned in r3/r4, but a
1548 draft put them in memory, and GCC used to implement the draft
1549 instead of the final standard. Therefore, TARGET_AIX_STRUCT_RET
1550 controls this instead of DEFAULT_ABI; V.4 targets needing backward
1551 compatibility can change DRAFT_V4_STRUCT_RET to override the
1552 default, and -m switches get the final word. See
1553 rs6000_override_options for more details.
1555 int_size_in_bytes returns -1 for variable size objects, which go in
1556 memory always. The cast to unsigned makes -1 > 8. */
1558 #define RETURN_IN_MEMORY(TYPE) \
1559 (AGGREGATE_TYPE_P (TYPE) && \
1560 (TARGET_AIX_STRUCT_RET || \
1561 (unsigned HOST_WIDE_INT) int_size_in_bytes (TYPE) > 8))
1563 /* DRAFT_V4_STRUCT_RET defaults off. */
1564 #define DRAFT_V4_STRUCT_RET 0
1566 /* Let RETURN_IN_MEMORY control what happens. */
1567 #define DEFAULT_PCC_STRUCT_RETURN 0
1569 /* Mode of stack savearea.
1570 FUNCTION is VOIDmode because calling convention maintains SP.
1571 BLOCK needs Pmode for SP.
1572 NONLOCAL needs twice Pmode to maintain both backchain and SP. */
1573 #define STACK_SAVEAREA_MODE(LEVEL) \
1574 (LEVEL == SAVE_FUNCTION ? VOIDmode \
1575 : LEVEL == SAVE_NONLOCAL ? (TARGET_32BIT ? DImode : TImode) : Pmode)
1577 /* Minimum and maximum general purpose registers used to hold arguments. */
1578 #define GP_ARG_MIN_REG 3
1579 #define GP_ARG_MAX_REG 10
1580 #define GP_ARG_NUM_REG (GP_ARG_MAX_REG - GP_ARG_MIN_REG + 1)
1582 /* Minimum and maximum floating point registers used to hold arguments. */
1583 #define FP_ARG_MIN_REG 33
1584 #define FP_ARG_AIX_MAX_REG 45
1585 #define FP_ARG_V4_MAX_REG 40
1586 #define FP_ARG_MAX_REG ((DEFAULT_ABI == ABI_AIX \
1587 || DEFAULT_ABI == ABI_AIX_NODESC \
1588 || DEFAULT_ABI == ABI_DARWIN) \
1589 ? FP_ARG_AIX_MAX_REG : FP_ARG_V4_MAX_REG)
1590 #define FP_ARG_NUM_REG (FP_ARG_MAX_REG - FP_ARG_MIN_REG + 1)
1592 /* Minimum and maximum AltiVec registers used to hold arguments. */
1593 #define ALTIVEC_ARG_MIN_REG (FIRST_ALTIVEC_REGNO + 2)
1594 #define ALTIVEC_ARG_MAX_REG (ALTIVEC_ARG_MIN_REG + 11)
1595 #define ALTIVEC_ARG_NUM_REG (ALTIVEC_ARG_MAX_REG - ALTIVEC_ARG_MIN_REG + 1)
1597 /* Return registers */
1598 #define GP_ARG_RETURN GP_ARG_MIN_REG
1599 #define FP_ARG_RETURN FP_ARG_MIN_REG
1600 #define ALTIVEC_ARG_RETURN (FIRST_ALTIVEC_REGNO + 2)
1602 /* Flags for the call/call_value rtl operations set up by function_arg */
1603 #define CALL_NORMAL 0x00000000 /* no special processing */
1604 /* Bits in 0x00000001 are unused. */
1605 #define CALL_V4_CLEAR_FP_ARGS 0x00000002 /* V.4, no FP args passed */
1606 #define CALL_V4_SET_FP_ARGS 0x00000004 /* V.4, FP args were passed */
1607 #define CALL_LONG 0x00000008 /* always call indirect */
1609 /* 1 if N is a possible register number for a function value
1610 as seen by the caller.
1612 On RS/6000, this is r3, fp1, and v2 (for AltiVec). */
1613 #define FUNCTION_VALUE_REGNO_P(N) ((N) == GP_ARG_RETURN \
1614 || ((N) == FP_ARG_RETURN) \
1615 || (TARGET_ALTIVEC && \
1616 (N) == ALTIVEC_ARG_RETURN))
1618 /* 1 if N is a possible register number for function argument passing.
1619 On RS/6000, these are r3-r10 and fp1-fp13.
1620 On AltiVec, v2 - v13 are used for passing vectors. */
1621 #define FUNCTION_ARG_REGNO_P(N) \
1622 (((unsigned)((N) - GP_ARG_MIN_REG) < (unsigned)(GP_ARG_NUM_REG)) \
1623 || (TARGET_ALTIVEC && \
1624 (unsigned)((N) - ALTIVEC_ARG_MIN_REG) < (unsigned)(ALTIVEC_ARG_NUM_REG)) \
1625 || ((unsigned)((N) - FP_ARG_MIN_REG) < (unsigned)(FP_ARG_NUM_REG)))
1628 /* A C structure for machine-specific, per-function data.
1629 This is added to the cfun structure. */
1630 typedef struct machine_function GTY(())
1632 /* Whether a System V.4 varargs area was created. */
1634 /* Flags if __builtin_return_address (n) with n >= 1 was used. */
1635 int ra_needs_full_frame;
1638 /* Define a data type for recording info about an argument list
1639 during the scan of that argument list. This data type should
1640 hold all necessary information about the function itself
1641 and about the args processed so far, enough to enable macros
1642 such as FUNCTION_ARG to determine where the next arg should go.
1644 On the RS/6000, this is a structure. The first element is the number of
1645 total argument words, the second is used to store the next
1646 floating-point register number, and the third says how many more args we
1647 have prototype types for.
1649 For ABI_V4, we treat these slightly differently -- `sysv_gregno' is
1650 the next availible GP register, `fregno' is the next available FP
1651 register, and `words' is the number of words used on the stack.
1653 The varargs/stdarg support requires that this structure's size
1654 be a multiple of sizeof(int). */
1656 typedef struct rs6000_args
1658 int words; /* # words used for passing GP registers */
1659 int fregno; /* next available FP register */
1660 int vregno; /* next available AltiVec register */
1661 int nargs_prototype; /* # args left in the current prototype */
1662 int orig_nargs; /* Original value of nargs_prototype */
1663 int prototype; /* Whether a prototype was defined */
1664 int call_cookie; /* Do special things for this call */
1665 int sysv_gregno; /* next available GP register */
1668 /* Define intermediate macro to compute the size (in registers) of an argument
1671 #define RS6000_ARG_SIZE(MODE, TYPE) \
1672 ((MODE) != BLKmode \
1673 ? (GET_MODE_SIZE (MODE) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD \
1674 : (int_size_in_bytes (TYPE) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
1676 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1677 for a call to a function whose data type is FNTYPE.
1678 For a library call, FNTYPE is 0. */
1680 #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT) \
1681 init_cumulative_args (&CUM, FNTYPE, LIBNAME, FALSE)
1683 /* Similar, but when scanning the definition of a procedure. We always
1684 set NARGS_PROTOTYPE large so we never return an EXPR_LIST. */
1686 #define INIT_CUMULATIVE_INCOMING_ARGS(CUM,FNTYPE,LIBNAME) \
1687 init_cumulative_args (&CUM, FNTYPE, LIBNAME, TRUE)
1689 /* Update the data in CUM to advance over an argument
1690 of mode MODE and data type TYPE.
1691 (TYPE is null for libcalls where that information may not be available.) */
1693 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1694 function_arg_advance (&CUM, MODE, TYPE, NAMED)
1696 /* Non-zero if we can use a floating-point register to pass this arg. */
1697 #define USE_FP_FOR_ARG_P(CUM,MODE,TYPE) \
1698 (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1699 && (CUM).fregno <= FP_ARG_MAX_REG \
1700 && TARGET_HARD_FLOAT && TARGET_FPRS)
1702 /* Non-zero if we can use an AltiVec register to pass this arg. */
1703 #define USE_ALTIVEC_FOR_ARG_P(CUM,MODE,TYPE) \
1704 (ALTIVEC_VECTOR_MODE (MODE) \
1705 && (CUM).vregno <= ALTIVEC_ARG_MAX_REG \
1706 && TARGET_ALTIVEC_ABI)
1708 /* Determine where to put an argument to a function.
1709 Value is zero to push the argument on the stack,
1710 or a hard register in which to store the argument.
1712 MODE is the argument's machine mode.
1713 TYPE is the data type of the argument (as a tree).
1714 This is null for libcalls where that information may
1716 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1717 the preceding args and about the function being called.
1718 NAMED is nonzero if this argument is a named parameter
1719 (otherwise it is an extra parameter matching an ellipsis).
1721 On RS/6000 the first eight words of non-FP are normally in registers
1722 and the rest are pushed. The first 13 FP args are in registers.
1724 If this is floating-point and no prototype is specified, we use
1725 both an FP and integer register (or possibly FP reg and stack). Library
1726 functions (when TYPE is zero) always have the proper types for args,
1727 so we can pass the FP value just in one register. emit_library_function
1728 doesn't support EXPR_LIST anyway. */
1730 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1731 function_arg (&CUM, MODE, TYPE, NAMED)
1733 /* For an arg passed partly in registers and partly in memory,
1734 this is the number of registers used.
1735 For args passed entirely in registers or entirely in memory, zero. */
1737 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
1738 function_arg_partial_nregs (&CUM, MODE, TYPE, NAMED)
1740 /* A C expression that indicates when an argument must be passed by
1741 reference. If nonzero for an argument, a copy of that argument is
1742 made in memory and a pointer to the argument is passed instead of
1743 the argument itself. The pointer is passed in whatever way is
1744 appropriate for passing a pointer to that type. */
1746 #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \
1747 function_arg_pass_by_reference(&CUM, MODE, TYPE, NAMED)
1749 /* If defined, a C expression which determines whether, and in which
1750 direction, to pad out an argument with extra space. The value
1751 should be of type `enum direction': either `upward' to pad above
1752 the argument, `downward' to pad below, or `none' to inhibit
1755 #define FUNCTION_ARG_PADDING(MODE, TYPE) function_arg_padding (MODE, TYPE)
1757 /* If defined, a C expression that gives the alignment boundary, in bits,
1758 of an argument with the specified mode and type. If it is not defined,
1759 PARM_BOUNDARY is used for all arguments. */
1761 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
1762 function_arg_boundary (MODE, TYPE)
1764 /* Perform any needed actions needed for a function that is receiving a
1765 variable number of arguments.
1769 MODE and TYPE are the mode and type of the current parameter.
1771 PRETEND_SIZE is a variable that should be set to the amount of stack
1772 that must be pushed by the prolog to pretend that our caller pushed
1775 Normally, this macro will push all remaining incoming registers on the
1776 stack and set PRETEND_SIZE to the length of the registers pushed. */
1778 #define SETUP_INCOMING_VARARGS(CUM,MODE,TYPE,PRETEND_SIZE,NO_RTL) \
1779 setup_incoming_varargs (&CUM, MODE, TYPE, &PRETEND_SIZE, NO_RTL)
1781 /* Define the `__builtin_va_list' type for the ABI. */
1782 #define BUILD_VA_LIST_TYPE(VALIST) \
1783 (VALIST) = rs6000_build_va_list ()
1785 /* Implement `va_start' for varargs and stdarg. */
1786 #define EXPAND_BUILTIN_VA_START(valist, nextarg) \
1787 rs6000_va_start (valist, nextarg)
1789 /* Implement `va_arg'. */
1790 #define EXPAND_BUILTIN_VA_ARG(valist, type) \
1791 rs6000_va_arg (valist, type)
1793 /* For AIX, the rule is that structures are passed left-aligned in
1794 their stack slot. However, GCC does not presently do this:
1795 structures which are the same size as integer types are passed
1796 right-aligned, as if they were in fact integers. This only
1797 matters for structures of size 1 or 2, or 4 when TARGET_64BIT.
1798 ABI_V4 does not use std_expand_builtin_va_arg. */
1799 #define PAD_VARARGS_DOWN (TYPE_MODE (type) != BLKmode)
1801 /* Define this macro to be a nonzero value if the location where a function
1802 argument is passed depends on whether or not it is a named argument. */
1803 #define STRICT_ARGUMENT_NAMING 1
1805 /* We do not allow indirect calls to be optimized into sibling calls, nor
1806 do we allow calls with vector parameters. */
1807 #define FUNCTION_OK_FOR_SIBCALL(DECL) function_ok_for_sibcall ((DECL))
1809 /* Output assembler code to FILE to increment profiler label # LABELNO
1810 for profiling a function entry. */
1812 #define FUNCTION_PROFILER(FILE, LABELNO) \
1813 output_function_profiler ((FILE), (LABELNO));
1815 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1816 the stack pointer does not matter. No definition is equivalent to
1819 On the RS/6000, this is non-zero because we can restore the stack from
1820 its backpointer, which we maintain. */
1821 #define EXIT_IGNORE_STACK 1
1823 /* Define this macro as a C expression that is nonzero for registers
1824 that are used by the epilogue or the return' pattern. The stack
1825 and frame pointer registers are already be assumed to be used as
1828 #define EPILOGUE_USES(REGNO) \
1829 ((reload_completed && (REGNO) == LINK_REGISTER_REGNUM) \
1830 || (TARGET_ALTIVEC && (REGNO) == VRSAVE_REGNO) \
1831 || (current_function_calls_eh_return \
1833 && (REGNO) == TOC_REGISTER))
1836 /* TRAMPOLINE_TEMPLATE deleted */
1838 /* Length in units of the trampoline for entering a nested function. */
1840 #define TRAMPOLINE_SIZE rs6000_trampoline_size ()
1842 /* Emit RTL insns to initialize the variable parts of a trampoline.
1843 FNADDR is an RTX for the address of the function's pure code.
1844 CXT is an RTX for the static chain value for the function. */
1846 #define INITIALIZE_TRAMPOLINE(ADDR, FNADDR, CXT) \
1847 rs6000_initialize_trampoline (ADDR, FNADDR, CXT)
1849 /* Definitions for __builtin_return_address and __builtin_frame_address.
1850 __builtin_return_address (0) should give link register (65), enable
1852 /* This should be uncommented, so that the link register is used, but
1853 currently this would result in unmatched insns and spilling fixed
1854 registers so we'll leave it for another day. When these problems are
1855 taken care of one additional fetch will be necessary in RETURN_ADDR_RTX.
1857 /* #define RETURN_ADDR_IN_PREVIOUS_FRAME */
1859 /* Number of bytes into the frame return addresses can be found. See
1860 rs6000_stack_info in rs6000.c for more information on how the different
1861 abi's store the return address. */
1862 #define RETURN_ADDRESS_OFFSET \
1863 ((DEFAULT_ABI == ABI_AIX \
1864 || DEFAULT_ABI == ABI_DARWIN \
1865 || DEFAULT_ABI == ABI_AIX_NODESC) ? (TARGET_32BIT ? 8 : 16) : \
1866 (DEFAULT_ABI == ABI_V4) ? 4 : \
1867 (internal_error ("RETURN_ADDRESS_OFFSET not supported"), 0))
1869 /* The current return address is in link register (65). The return address
1870 of anything farther back is accessed normally at an offset of 8 from the
1872 #define RETURN_ADDR_RTX(COUNT, FRAME) \
1873 (rs6000_return_addr (COUNT, FRAME))
1876 /* Definitions for register eliminations.
1878 We have two registers that can be eliminated on the RS/6000. First, the
1879 frame pointer register can often be eliminated in favor of the stack
1880 pointer register. Secondly, the argument pointer register can always be
1881 eliminated; it is replaced with either the stack or frame pointer.
1883 In addition, we use the elimination mechanism to see if r30 is needed
1884 Initially we assume that it isn't. If it is, we spill it. This is done
1885 by making it an eliminable register. We replace it with itself so that
1886 if it isn't needed, then existing uses won't be modified. */
1888 /* This is an array of structures. Each structure initializes one pair
1889 of eliminable registers. The "from" register number is given first,
1890 followed by "to". Eliminations of the same "from" register are listed
1891 in order of preference. */
1892 #define ELIMINABLE_REGS \
1893 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1894 { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1895 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \
1898 /* Given FROM and TO register numbers, say whether this elimination is allowed.
1899 Frame pointer elimination is automatically handled.
1901 For the RS/6000, if frame pointer elimination is being done, we would like
1902 to convert ap into fp, not sp.
1904 We need r30 if -mminimal-toc was specified, and there are constant pool
1907 #define CAN_ELIMINATE(FROM, TO) \
1908 ((FROM) == ARG_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM \
1909 ? ! frame_pointer_needed \
1910 : (FROM) == 30 ? ! TARGET_MINIMAL_TOC || TARGET_NO_TOC || get_pool_size () == 0 \
1913 /* Define the offset between two registers, one to be eliminated, and the other
1914 its replacement, at the start of a routine. */
1915 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1917 rs6000_stack_t *info = rs6000_stack_info (); \
1919 if ((FROM) == FRAME_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM) \
1920 (OFFSET) = (info->push_p) ? 0 : - info->total_size; \
1921 else if ((FROM) == ARG_POINTER_REGNUM && (TO) == FRAME_POINTER_REGNUM) \
1922 (OFFSET) = info->total_size; \
1923 else if ((FROM) == ARG_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM) \
1924 (OFFSET) = (info->push_p) ? info->total_size : 0; \
1925 else if ((FROM) == 30) \
1931 /* Addressing modes, and classification of registers for them. */
1933 /* #define HAVE_POST_INCREMENT 0 */
1934 /* #define HAVE_POST_DECREMENT 0 */
1936 #define HAVE_PRE_DECREMENT 1
1937 #define HAVE_PRE_INCREMENT 1
1939 /* Macros to check register numbers against specific register classes. */
1941 /* These assume that REGNO is a hard or pseudo reg number.
1942 They give nonzero only if REGNO is a hard reg of the suitable class
1943 or a pseudo reg currently allocated to a suitable hard reg.
1944 Since they use reg_renumber, they are safe only once reg_renumber
1945 has been allocated, which happens in local-alloc.c. */
1947 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1948 ((REGNO) < FIRST_PSEUDO_REGISTER \
1949 ? (REGNO) <= 31 || (REGNO) == 67 \
1950 : (reg_renumber[REGNO] >= 0 \
1951 && (reg_renumber[REGNO] <= 31 || reg_renumber[REGNO] == 67)))
1953 #define REGNO_OK_FOR_BASE_P(REGNO) \
1954 ((REGNO) < FIRST_PSEUDO_REGISTER \
1955 ? ((REGNO) > 0 && (REGNO) <= 31) || (REGNO) == 67 \
1956 : (reg_renumber[REGNO] > 0 \
1957 && (reg_renumber[REGNO] <= 31 || reg_renumber[REGNO] == 67)))
1959 /* Maximum number of registers that can appear in a valid memory address. */
1961 #define MAX_REGS_PER_ADDRESS 2
1963 /* Recognize any constant value that is a valid address. */
1965 #define CONSTANT_ADDRESS_P(X) \
1966 (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
1967 || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST \
1968 || GET_CODE (X) == HIGH)
1970 /* Nonzero if the constant value X is a legitimate general operand.
1971 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
1973 On the RS/6000, all integer constants are acceptable, most won't be valid
1974 for particular insns, though. Only easy FP constants are
1977 #define LEGITIMATE_CONSTANT_P(X) \
1978 (GET_CODE (X) != CONST_DOUBLE || GET_MODE (X) == VOIDmode \
1979 || (TARGET_POWERPC64 && GET_MODE (X) == DImode) \
1980 || easy_fp_constant (X, GET_MODE (X)))
1982 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1983 and check its validity for a certain class.
1984 We have two alternate definitions for each of them.
1985 The usual definition accepts all pseudo regs; the other rejects
1986 them unless they have been allocated suitable hard regs.
1987 The symbol REG_OK_STRICT causes the latter definition to be used.
1989 Most source files want to accept pseudo regs in the hope that
1990 they will get allocated to the class that the insn wants them to be in.
1991 Source files for reload pass need to be strict.
1992 After reload, it makes no difference, since pseudo regs have
1993 been eliminated by then. */
1995 #ifdef REG_OK_STRICT
1996 # define REG_OK_STRICT_FLAG 1
1998 # define REG_OK_STRICT_FLAG 0
2001 /* Nonzero if X is a hard reg that can be used as an index
2002 or if it is a pseudo reg in the non-strict case. */
2003 #define INT_REG_OK_FOR_INDEX_P(X, STRICT) \
2005 && (REGNO (X) <= 31 \
2006 || REGNO (X) == ARG_POINTER_REGNUM \
2007 || REGNO (X) >= FIRST_PSEUDO_REGISTER)) \
2008 || ((STRICT) && REGNO_OK_FOR_INDEX_P (REGNO (X))))
2010 /* Nonzero if X is a hard reg that can be used as a base reg
2011 or if it is a pseudo reg in the non-strict case. */
2012 #define INT_REG_OK_FOR_BASE_P(X, STRICT) \
2013 (REGNO (X) > 0 && INT_REG_OK_FOR_INDEX_P (X, (STRICT)))
2015 #define REG_OK_FOR_INDEX_P(X) INT_REG_OK_FOR_INDEX_P (X, REG_OK_STRICT_FLAG)
2016 #define REG_OK_FOR_BASE_P(X) INT_REG_OK_FOR_BASE_P (X, REG_OK_STRICT_FLAG)
2018 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
2019 that is a valid memory address for an instruction.
2020 The MODE argument is the machine mode for the MEM expression
2021 that wants to use this address.
2023 On the RS/6000, there are four valid address: a SYMBOL_REF that
2024 refers to a constant pool entry of an address (or the sum of it
2025 plus a constant), a short (16-bit signed) constant plus a register,
2026 the sum of two registers, or a register indirect, possibly with an
2027 auto-increment. For DFmode and DImode with an constant plus register,
2028 we must ensure that both words are addressable or PowerPC64 with offset
2031 For modes spanning multiple registers (DFmode in 32-bit GPRs,
2032 32-bit DImode, TImode), indexed addressing cannot be used because
2033 adjacent memory cells are accessed by adding word-sized offsets
2034 during assembly output. */
2036 #define CONSTANT_POOL_EXPR_P(X) (constant_pool_expr_p (X))
2038 #define TOC_RELATIVE_EXPR_P(X) (toc_relative_expr_p (X))
2040 /* SPE offset addressing is limited to 5-bits worth of double words. */
2041 #define SPE_CONST_OFFSET_OK(x) (((x) & ~0xf8) == 0)
2043 #define LEGITIMATE_CONSTANT_POOL_ADDRESS_P(X) \
2045 && GET_CODE (X) == PLUS \
2046 && GET_CODE (XEXP (X, 0)) == REG \
2047 && (TARGET_MINIMAL_TOC || REGNO (XEXP (X, 0)) == TOC_REGISTER) \
2048 && CONSTANT_POOL_EXPR_P (XEXP (X, 1)))
2050 #define LEGITIMATE_SMALL_DATA_P(MODE, X) \
2051 (DEFAULT_ABI == ABI_V4 \
2052 && !flag_pic && !TARGET_TOC \
2053 && (GET_CODE (X) == SYMBOL_REF || GET_CODE (X) == CONST) \
2054 && small_data_operand (X, MODE))
2056 #define LEGITIMATE_ADDRESS_INTEGER_P(X, OFFSET) \
2057 (GET_CODE (X) == CONST_INT \
2058 && (unsigned HOST_WIDE_INT) (INTVAL (X) + (OFFSET) + 0x8000) < 0x10000)
2060 #define LEGITIMATE_OFFSET_ADDRESS_P(MODE, X, STRICT) \
2061 (GET_CODE (X) == PLUS \
2062 && GET_CODE (XEXP (X, 0)) == REG \
2063 && INT_REG_OK_FOR_BASE_P (XEXP (X, 0), (STRICT)) \
2064 && LEGITIMATE_ADDRESS_INTEGER_P (XEXP (X, 1), 0) \
2065 && (! ALTIVEC_VECTOR_MODE (MODE) \
2066 || (GET_CODE (XEXP (X,1)) == CONST_INT && INTVAL (XEXP (X,1)) == 0)) \
2067 && (! SPE_VECTOR_MODE (MODE) \
2068 || (GET_CODE (XEXP (X, 1)) == CONST_INT \
2069 && SPE_CONST_OFFSET_OK (INTVAL (XEXP (X, 1))))) \
2070 && (((MODE) != DFmode && (MODE) != DImode) \
2072 ? LEGITIMATE_ADDRESS_INTEGER_P (XEXP (X, 1), 4) \
2073 : ! (INTVAL (XEXP (X, 1)) & 3))) \
2074 && ((MODE) != TImode \
2076 ? LEGITIMATE_ADDRESS_INTEGER_P (XEXP (X, 1), 12) \
2077 : (LEGITIMATE_ADDRESS_INTEGER_P (XEXP (X, 1), 8) \
2078 && ! (INTVAL (XEXP (X, 1)) & 3)))))
2080 #define LEGITIMATE_INDEXED_ADDRESS_P(X, STRICT) \
2081 (GET_CODE (X) == PLUS \
2082 && GET_CODE (XEXP (X, 0)) == REG \
2083 && GET_CODE (XEXP (X, 1)) == REG \
2084 && ((INT_REG_OK_FOR_BASE_P (XEXP (X, 0), (STRICT)) \
2085 && INT_REG_OK_FOR_INDEX_P (XEXP (X, 1), (STRICT))) \
2086 || (INT_REG_OK_FOR_BASE_P (XEXP (X, 1), (STRICT)) \
2087 && INT_REG_OK_FOR_INDEX_P (XEXP (X, 0), (STRICT)))))
2089 #define LEGITIMATE_INDIRECT_ADDRESS_P(X, STRICT) \
2090 (GET_CODE (X) == REG && INT_REG_OK_FOR_BASE_P (X, (STRICT)))
2092 #define LEGITIMATE_LO_SUM_ADDRESS_P(MODE, X, STRICT) \
2094 && ! flag_pic && ! TARGET_TOC \
2095 && GET_MODE_NUNITS (MODE) == 1 \
2096 && (GET_MODE_BITSIZE (MODE) <= 32 \
2097 || (TARGET_HARD_FLOAT && TARGET_FPRS && (MODE) == DFmode)) \
2098 && GET_CODE (X) == LO_SUM \
2099 && GET_CODE (XEXP (X, 0)) == REG \
2100 && INT_REG_OK_FOR_BASE_P (XEXP (X, 0), (STRICT)) \
2101 && CONSTANT_P (XEXP (X, 1)))
2103 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
2104 { if (rs6000_legitimate_address (MODE, X, REG_OK_STRICT_FLAG)) \
2108 /* Try machine-dependent ways of modifying an illegitimate address
2109 to be legitimate. If we find one, return the new, valid address.
2110 This macro is used in only one place: `memory_address' in explow.c.
2112 OLDX is the address as it was before break_out_memory_refs was called.
2113 In some cases it is useful to look at this to decide what needs to be done.
2115 MODE and WIN are passed so that this macro can use
2116 GO_IF_LEGITIMATE_ADDRESS.
2118 It is always safe for this macro to do nothing. It exists to recognize
2119 opportunities to optimize the output.
2121 On RS/6000, first check for the sum of a register with a constant
2122 integer that is out of range. If so, generate code to add the
2123 constant with the low-order 16 bits masked to the register and force
2124 this result into another register (this can be done with `cau').
2125 Then generate an address of REG+(CONST&0xffff), allowing for the
2126 possibility of bit 16 being a one.
2128 Then check for the sum of a register and something not constant, try to
2129 load the other things into a register and return the sum. */
2131 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
2132 { rtx result = rs6000_legitimize_address (X, OLDX, MODE); \
2133 if (result != NULL_RTX) \
2140 /* Try a machine-dependent way of reloading an illegitimate address
2141 operand. If we find one, push the reload and jump to WIN. This
2142 macro is used in only one place: `find_reloads_address' in reload.c.
2144 Implemented on rs6000 by rs6000_legitimize_reload_address.
2145 Note that (X) is evaluated twice; this is safe in current usage. */
2147 #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \
2150 (X) = rs6000_legitimize_reload_address ((X), (MODE), (OPNUM), \
2151 (int)(TYPE), (IND_LEVELS), &win); \
2156 /* Go to LABEL if ADDR (a legitimate address expression)
2157 has an effect that depends on the machine mode it is used for.
2159 On the RS/6000 this is true if the address is valid with a zero offset
2160 but not with an offset of four (this means it cannot be used as an
2161 address for DImode or DFmode) or is a pre-increment or decrement. Since
2162 we know it is valid, we just check for an address that is not valid with
2163 an offset of four. */
2165 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \
2166 { if (GET_CODE (ADDR) == PLUS \
2167 && LEGITIMATE_ADDRESS_INTEGER_P (XEXP (ADDR, 1), 0) \
2168 && ! LEGITIMATE_ADDRESS_INTEGER_P (XEXP (ADDR, 1), \
2169 (TARGET_32BIT ? 4 : 8))) \
2171 if (TARGET_UPDATE && GET_CODE (ADDR) == PRE_INC) \
2173 if (TARGET_UPDATE && GET_CODE (ADDR) == PRE_DEC) \
2175 if (GET_CODE (ADDR) == LO_SUM) \
2179 /* The register number of the register used to address a table of
2180 static data addresses in memory. In some cases this register is
2181 defined by a processor's "application binary interface" (ABI).
2182 When this macro is defined, RTL is generated for this register
2183 once, as with the stack pointer and frame pointer registers. If
2184 this macro is not defined, it is up to the machine-dependent files
2185 to allocate such a register (if necessary). */
2187 #define RS6000_PIC_OFFSET_TABLE_REGNUM 30
2188 #define PIC_OFFSET_TABLE_REGNUM (flag_pic ? RS6000_PIC_OFFSET_TABLE_REGNUM : INVALID_REGNUM)
2190 #define TOC_REGISTER (TARGET_MINIMAL_TOC ? 30 : 2)
2192 /* Define this macro if the register defined by
2193 `PIC_OFFSET_TABLE_REGNUM' is clobbered by calls. Do not define
2194 this macro if `PIC_OFFSET_TABLE_REGNUM' is not defined. */
2196 /* #define PIC_OFFSET_TABLE_REG_CALL_CLOBBERED */
2198 /* By generating position-independent code, when two different
2199 programs (A and B) share a common library (libC.a), the text of
2200 the library can be shared whether or not the library is linked at
2201 the same address for both programs. In some of these
2202 environments, position-independent code requires not only the use
2203 of different addressing modes, but also special code to enable the
2204 use of these addressing modes.
2206 The `FINALIZE_PIC' macro serves as a hook to emit these special
2207 codes once the function is being compiled into assembly code, but
2208 not before. (It is not done before, because in the case of
2209 compiling an inline function, it would lead to multiple PIC
2210 prologues being included in functions which used inline functions
2211 and were compiled to assembly language.) */
2213 /* #define FINALIZE_PIC */
2215 /* A C expression that is nonzero if X is a legitimate immediate
2216 operand on the target machine when generating position independent
2217 code. You can assume that X satisfies `CONSTANT_P', so you need
2218 not check this. You can also assume FLAG_PIC is true, so you need
2219 not check it either. You need not define this macro if all
2220 constants (including `SYMBOL_REF') can be immediate operands when
2221 generating position independent code. */
2223 /* #define LEGITIMATE_PIC_OPERAND_P (X) */
2225 /* In rare cases, correct code generation requires extra machine
2226 dependent processing between the second jump optimization pass and
2227 delayed branch scheduling. On those machines, define this macro
2228 as a C statement to act on the code starting at INSN. */
2230 /* #define MACHINE_DEPENDENT_REORG(INSN) */
2233 /* Define this if some processing needs to be done immediately before
2234 emitting code for an insn. */
2236 /* #define FINAL_PRESCAN_INSN(INSN,OPERANDS,NOPERANDS) */
2238 /* Specify the machine mode that this machine uses
2239 for the index in the tablejump instruction. */
2240 #define CASE_VECTOR_MODE SImode
2242 /* Define as C expression which evaluates to nonzero if the tablejump
2243 instruction expects the table to contain offsets from the address of the
2245 Do not define this if the table should contain absolute addresses. */
2246 #define CASE_VECTOR_PC_RELATIVE 1
2248 /* Define this as 1 if `char' should by default be signed; else as 0. */
2249 #define DEFAULT_SIGNED_CHAR 0
2251 /* This flag, if defined, says the same insns that convert to a signed fixnum
2252 also convert validly to an unsigned one. */
2254 /* #define FIXUNS_TRUNC_LIKE_FIX_TRUNC */
2256 /* Max number of bytes we can move from memory to memory
2257 in one reasonably fast instruction. */
2258 #define MOVE_MAX (! TARGET_POWERPC64 ? 4 : 8)
2259 #define MAX_MOVE_MAX 8
2261 /* Nonzero if access to memory by bytes is no faster than for words.
2262 Also non-zero if doing byte operations (specifically shifts) in registers
2264 #define SLOW_BYTE_ACCESS 1
2266 /* Define if operations between registers always perform the operation
2267 on the full register even if a narrower mode is specified. */
2268 #define WORD_REGISTER_OPERATIONS
2270 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
2271 will either zero-extend or sign-extend. The value of this macro should
2272 be the code that says which one of the two operations is implicitly
2273 done, NIL if none. */
2274 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
2276 /* Define if loading short immediate values into registers sign extends. */
2277 #define SHORT_IMMEDIATES_SIGN_EXTEND
2279 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
2280 is done just by pretending it is already truncated. */
2281 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
2283 /* Specify the machine mode that pointers have.
2284 After generation of rtl, the compiler makes no further distinction
2285 between pointers and any other objects of this machine mode. */
2286 #define Pmode (TARGET_32BIT ? SImode : DImode)
2288 /* Mode of a function address in a call instruction (for indexing purposes).
2289 Doesn't matter on RS/6000. */
2290 #define FUNCTION_MODE (TARGET_32BIT ? SImode : DImode)
2292 /* Define this if addresses of constant functions
2293 shouldn't be put through pseudo regs where they can be cse'd.
2294 Desirable on machines where ordinary constants are expensive
2295 but a CALL with constant address is cheap. */
2296 #define NO_FUNCTION_CSE
2298 /* Define this to be nonzero if shift instructions ignore all but the low-order
2301 The sle and sre instructions which allow SHIFT_COUNT_TRUNCATED
2302 have been dropped from the PowerPC architecture. */
2304 #define SHIFT_COUNT_TRUNCATED (TARGET_POWER ? 1 : 0)
2306 /* Compute the cost of computing a constant rtl expression RTX
2307 whose rtx-code is CODE. The body of this macro is a portion
2308 of a switch statement. If the code is computed here,
2309 return it with a return statement. Otherwise, break from the switch.
2311 On the RS/6000, if it is valid in the insn, it is free. So this
2312 always returns 0. */
2314 #define CONST_COSTS(RTX,CODE,OUTER_CODE) \
2319 case CONST_DOUBLE: \
2323 /* Provide the costs of a rtl expression. This is in the body of a
2326 #define RTX_COSTS(X,CODE,OUTER_CODE) \
2328 return ((GET_CODE (XEXP (X, 1)) == CONST_INT \
2329 && ((unsigned HOST_WIDE_INT) (INTVAL (XEXP (X, 1)) \
2330 + 0x8000) >= 0x10000) \
2331 && ((INTVAL (XEXP (X, 1)) & 0xffff) != 0)) \
2332 ? COSTS_N_INSNS (2) \
2333 : COSTS_N_INSNS (1)); \
2337 return ((GET_CODE (XEXP (X, 1)) == CONST_INT \
2338 && (INTVAL (XEXP (X, 1)) & (~ (HOST_WIDE_INT) 0xffff)) != 0 \
2339 && ((INTVAL (XEXP (X, 1)) & 0xffff) != 0)) \
2340 ? COSTS_N_INSNS (2) \
2341 : COSTS_N_INSNS (1)); \
2343 if (optimize_size) \
2344 return COSTS_N_INSNS (2); \
2345 switch (rs6000_cpu) \
2347 case PROCESSOR_RIOS1: \
2348 case PROCESSOR_PPC405: \
2349 return (GET_CODE (XEXP (X, 1)) != CONST_INT \
2350 ? COSTS_N_INSNS (5) \
2351 : INTVAL (XEXP (X, 1)) >= -256 && INTVAL (XEXP (X, 1)) <= 255 \
2352 ? COSTS_N_INSNS (3) : COSTS_N_INSNS (4)); \
2353 case PROCESSOR_RS64A: \
2354 return (GET_CODE (XEXP (X, 1)) != CONST_INT \
2355 ? GET_MODE (XEXP (X, 1)) != DImode \
2356 ? COSTS_N_INSNS (20) : COSTS_N_INSNS (34) \
2357 : INTVAL (XEXP (X, 1)) >= -256 && INTVAL (XEXP (X, 1)) <= 255 \
2358 ? COSTS_N_INSNS (8) : COSTS_N_INSNS (12)); \
2359 case PROCESSOR_RIOS2: \
2360 case PROCESSOR_MPCCORE: \
2361 case PROCESSOR_PPC604e: \
2362 return COSTS_N_INSNS (2); \
2363 case PROCESSOR_PPC601: \
2364 return COSTS_N_INSNS (5); \
2365 case PROCESSOR_PPC603: \
2366 case PROCESSOR_PPC7400: \
2367 case PROCESSOR_PPC750: \
2368 return (GET_CODE (XEXP (X, 1)) != CONST_INT \
2369 ? COSTS_N_INSNS (5) \
2370 : INTVAL (XEXP (X, 1)) >= -256 && INTVAL (XEXP (X, 1)) <= 255 \
2371 ? COSTS_N_INSNS (2) : COSTS_N_INSNS (3)); \
2372 case PROCESSOR_PPC7450: \
2373 return (GET_CODE (XEXP (X, 1)) != CONST_INT \
2374 ? COSTS_N_INSNS (4) \
2375 : COSTS_N_INSNS (3)); \
2376 case PROCESSOR_PPC403: \
2377 case PROCESSOR_PPC604: \
2378 case PROCESSOR_PPC8540: \
2379 return COSTS_N_INSNS (4); \
2380 case PROCESSOR_PPC620: \
2381 case PROCESSOR_PPC630: \
2382 case PROCESSOR_POWER4: \
2383 return (GET_CODE (XEXP (X, 1)) != CONST_INT \
2384 ? GET_MODE (XEXP (X, 1)) != DImode \
2385 ? COSTS_N_INSNS (5) : COSTS_N_INSNS (7) \
2386 : INTVAL (XEXP (X, 1)) >= -256 && INTVAL (XEXP (X, 1)) <= 255 \
2387 ? COSTS_N_INSNS (3) : COSTS_N_INSNS (4)); \
2391 if (GET_CODE (XEXP (X, 1)) == CONST_INT \
2392 && exact_log2 (INTVAL (XEXP (X, 1))) >= 0) \
2393 return COSTS_N_INSNS (2); \
2394 /* otherwise fall through to normal divide. */ \
2397 switch (rs6000_cpu) \
2399 case PROCESSOR_RIOS1: \
2400 return COSTS_N_INSNS (19); \
2401 case PROCESSOR_RIOS2: \
2402 return COSTS_N_INSNS (13); \
2403 case PROCESSOR_RS64A: \
2404 return (GET_MODE (XEXP (X, 1)) != DImode \
2405 ? COSTS_N_INSNS (65) \
2406 : COSTS_N_INSNS (67)); \
2407 case PROCESSOR_MPCCORE: \
2408 return COSTS_N_INSNS (6); \
2409 case PROCESSOR_PPC403: \
2410 return COSTS_N_INSNS (33); \
2411 case PROCESSOR_PPC405: \
2412 return COSTS_N_INSNS (35); \
2413 case PROCESSOR_PPC601: \
2414 return COSTS_N_INSNS (36); \
2415 case PROCESSOR_PPC603: \
2416 return COSTS_N_INSNS (37); \
2417 case PROCESSOR_PPC604: \
2418 case PROCESSOR_PPC604e: \
2419 return COSTS_N_INSNS (20); \
2420 case PROCESSOR_PPC620: \
2421 case PROCESSOR_PPC630: \
2422 case PROCESSOR_POWER4: \
2423 return (GET_MODE (XEXP (X, 1)) != DImode \
2424 ? COSTS_N_INSNS (21) \
2425 : COSTS_N_INSNS (37)); \
2426 case PROCESSOR_PPC750: \
2427 case PROCESSOR_PPC8540: \
2428 case PROCESSOR_PPC7400: \
2429 return COSTS_N_INSNS (19); \
2430 case PROCESSOR_PPC7450: \
2431 return COSTS_N_INSNS (23); \
2434 return COSTS_N_INSNS (4); \
2436 /* MEM should be slightly more expensive than (plus (reg) (const)) */ \
2439 /* Compute the cost of an address. This is meant to approximate the size
2440 and/or execution delay of an insn using that address. If the cost is
2441 approximated by the RTL complexity, including CONST_COSTS above, as
2442 is usually the case for CISC machines, this macro should not be defined.
2443 For aggressively RISCy machines, only one insn format is allowed, so
2444 this macro should be a constant. The value of this macro only matters
2445 for valid addresses.
2447 For the RS/6000, everything is cost 0. */
2449 #define ADDRESS_COST(RTX) 0
2451 /* Adjust the length of an INSN. LENGTH is the currently-computed length and
2452 should be adjusted to reflect any required changes. This macro is used when
2453 there is some systematic length adjustment required that would be difficult
2454 to express in the length attribute. */
2456 /* #define ADJUST_INSN_LENGTH(X,LENGTH) */
2458 /* Given a comparison code (EQ, NE, etc.) and the first operand of a
2459 COMPARE, return the mode to be used for the comparison. For
2460 floating-point, CCFPmode should be used. CCUNSmode should be used
2461 for unsigned comparisons. CCEQmode should be used when we are
2462 doing an inequality comparison on the result of a
2463 comparison. CCmode should be used in all other cases. */
2465 #define SELECT_CC_MODE(OP,X,Y) \
2466 (GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT ? CCFPmode \
2467 : (OP) == GTU || (OP) == LTU || (OP) == GEU || (OP) == LEU ? CCUNSmode \
2468 : (((OP) == EQ || (OP) == NE) && GET_RTX_CLASS (GET_CODE (X)) == '<' \
2469 ? CCEQmode : CCmode))
2471 /* Define the information needed to generate branch and scc insns. This is
2472 stored from the compare operation. Note that we can't use "rtx" here
2473 since it hasn't been defined! */
2475 extern GTY(()) rtx rs6000_compare_op0;
2476 extern GTY(()) rtx rs6000_compare_op1;
2477 extern int rs6000_compare_fp_p;
2479 /* Control the assembler format that we output. */
2481 /* A C string constant describing how to begin a comment in the target
2482 assembler language. The compiler assumes that the comment will end at
2483 the end of the line. */
2484 #define ASM_COMMENT_START " #"
2486 /* Implicit library calls should use memcpy, not bcopy, etc. */
2488 #define TARGET_MEM_FUNCTIONS
2490 /* Flag to say the TOC is initialized */
2491 extern int toc_initialized;
2493 /* Macro to output a special constant pool entry. Go to WIN if we output
2494 it. Otherwise, it is written the usual way.
2496 On the RS/6000, toc entries are handled this way. */
2498 #define ASM_OUTPUT_SPECIAL_POOL_ENTRY(FILE, X, MODE, ALIGN, LABELNO, WIN) \
2499 { if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (X, MODE)) \
2501 output_toc (FILE, X, LABELNO, MODE); \
2506 #ifdef HAVE_GAS_WEAK
2507 #define RS6000_WEAK 1
2509 #define RS6000_WEAK 0
2513 /* Used in lieu of ASM_WEAKEN_LABEL. */
2514 #define ASM_WEAKEN_DECL(FILE, DECL, NAME, VAL) \
2517 fputs ("\t.weak\t", (FILE)); \
2518 RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \
2519 if ((DECL) && TREE_CODE (DECL) == FUNCTION_DECL \
2520 && DEFAULT_ABI == ABI_AIX) \
2523 fputs ("[DS]", (FILE)); \
2524 fputs ("\n\t.weak\t.", (FILE)); \
2525 RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \
2527 fputc ('\n', (FILE)); \
2530 ASM_OUTPUT_DEF ((FILE), (NAME), (VAL)); \
2531 if ((DECL) && TREE_CODE (DECL) == FUNCTION_DECL \
2532 && DEFAULT_ABI == ABI_AIX) \
2534 fputs ("\t.set\t.", (FILE)); \
2535 RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \
2536 fputs (",.", (FILE)); \
2537 RS6000_OUTPUT_BASENAME ((FILE), (VAL)); \
2538 fputc ('\n', (FILE)); \
2545 /* This implements the `alias' attribute. */
2546 #undef ASM_OUTPUT_DEF_FROM_DECLS
2547 #define ASM_OUTPUT_DEF_FROM_DECLS(FILE, DECL, TARGET) \
2550 const char *alias = XSTR (XEXP (DECL_RTL (DECL), 0), 0); \
2551 const char *name = IDENTIFIER_POINTER (TARGET); \
2552 if (TREE_CODE (DECL) == FUNCTION_DECL \
2553 && DEFAULT_ABI == ABI_AIX) \
2555 if (TREE_PUBLIC (DECL)) \
2557 if (!RS6000_WEAK || !DECL_WEAK (DECL)) \
2559 fputs ("\t.globl\t.", FILE); \
2560 RS6000_OUTPUT_BASENAME (FILE, alias); \
2561 putc ('\n', FILE); \
2564 else if (TARGET_XCOFF) \
2566 fputs ("\t.lglobl\t.", FILE); \
2567 RS6000_OUTPUT_BASENAME (FILE, alias); \
2568 putc ('\n', FILE); \
2570 fputs ("\t.set\t.", FILE); \
2571 RS6000_OUTPUT_BASENAME (FILE, alias); \
2572 fputs (",.", FILE); \
2573 RS6000_OUTPUT_BASENAME (FILE, name); \
2574 fputc ('\n', FILE); \
2576 ASM_OUTPUT_DEF (FILE, alias, name); \
2580 /* Output to assembler file text saying following lines
2581 may contain character constants, extra white space, comments, etc. */
2583 #define ASM_APP_ON ""
2585 /* Output to assembler file text saying following lines
2586 no longer contain unusual constructs. */
2588 #define ASM_APP_OFF ""
2590 /* How to refer to registers in assembler output.
2591 This sequence is indexed by compiler's hard-register-number (see above). */
2593 extern char rs6000_reg_names[][8]; /* register names (0 vs. %r0). */
2595 #define REGISTER_NAMES \
2597 &rs6000_reg_names[ 0][0], /* r0 */ \
2598 &rs6000_reg_names[ 1][0], /* r1 */ \
2599 &rs6000_reg_names[ 2][0], /* r2 */ \
2600 &rs6000_reg_names[ 3][0], /* r3 */ \
2601 &rs6000_reg_names[ 4][0], /* r4 */ \
2602 &rs6000_reg_names[ 5][0], /* r5 */ \
2603 &rs6000_reg_names[ 6][0], /* r6 */ \
2604 &rs6000_reg_names[ 7][0], /* r7 */ \
2605 &rs6000_reg_names[ 8][0], /* r8 */ \
2606 &rs6000_reg_names[ 9][0], /* r9 */ \
2607 &rs6000_reg_names[10][0], /* r10 */ \
2608 &rs6000_reg_names[11][0], /* r11 */ \
2609 &rs6000_reg_names[12][0], /* r12 */ \
2610 &rs6000_reg_names[13][0], /* r13 */ \
2611 &rs6000_reg_names[14][0], /* r14 */ \
2612 &rs6000_reg_names[15][0], /* r15 */ \
2613 &rs6000_reg_names[16][0], /* r16 */ \
2614 &rs6000_reg_names[17][0], /* r17 */ \
2615 &rs6000_reg_names[18][0], /* r18 */ \
2616 &rs6000_reg_names[19][0], /* r19 */ \
2617 &rs6000_reg_names[20][0], /* r20 */ \
2618 &rs6000_reg_names[21][0], /* r21 */ \
2619 &rs6000_reg_names[22][0], /* r22 */ \
2620 &rs6000_reg_names[23][0], /* r23 */ \
2621 &rs6000_reg_names[24][0], /* r24 */ \
2622 &rs6000_reg_names[25][0], /* r25 */ \
2623 &rs6000_reg_names[26][0], /* r26 */ \
2624 &rs6000_reg_names[27][0], /* r27 */ \
2625 &rs6000_reg_names[28][0], /* r28 */ \
2626 &rs6000_reg_names[29][0], /* r29 */ \
2627 &rs6000_reg_names[30][0], /* r30 */ \
2628 &rs6000_reg_names[31][0], /* r31 */ \
2630 &rs6000_reg_names[32][0], /* fr0 */ \
2631 &rs6000_reg_names[33][0], /* fr1 */ \
2632 &rs6000_reg_names[34][0], /* fr2 */ \
2633 &rs6000_reg_names[35][0], /* fr3 */ \
2634 &rs6000_reg_names[36][0], /* fr4 */ \
2635 &rs6000_reg_names[37][0], /* fr5 */ \
2636 &rs6000_reg_names[38][0], /* fr6 */ \
2637 &rs6000_reg_names[39][0], /* fr7 */ \
2638 &rs6000_reg_names[40][0], /* fr8 */ \
2639 &rs6000_reg_names[41][0], /* fr9 */ \
2640 &rs6000_reg_names[42][0], /* fr10 */ \
2641 &rs6000_reg_names[43][0], /* fr11 */ \
2642 &rs6000_reg_names[44][0], /* fr12 */ \
2643 &rs6000_reg_names[45][0], /* fr13 */ \
2644 &rs6000_reg_names[46][0], /* fr14 */ \
2645 &rs6000_reg_names[47][0], /* fr15 */ \
2646 &rs6000_reg_names[48][0], /* fr16 */ \
2647 &rs6000_reg_names[49][0], /* fr17 */ \
2648 &rs6000_reg_names[50][0], /* fr18 */ \
2649 &rs6000_reg_names[51][0], /* fr19 */ \
2650 &rs6000_reg_names[52][0], /* fr20 */ \
2651 &rs6000_reg_names[53][0], /* fr21 */ \
2652 &rs6000_reg_names[54][0], /* fr22 */ \
2653 &rs6000_reg_names[55][0], /* fr23 */ \
2654 &rs6000_reg_names[56][0], /* fr24 */ \
2655 &rs6000_reg_names[57][0], /* fr25 */ \
2656 &rs6000_reg_names[58][0], /* fr26 */ \
2657 &rs6000_reg_names[59][0], /* fr27 */ \
2658 &rs6000_reg_names[60][0], /* fr28 */ \
2659 &rs6000_reg_names[61][0], /* fr29 */ \
2660 &rs6000_reg_names[62][0], /* fr30 */ \
2661 &rs6000_reg_names[63][0], /* fr31 */ \
2663 &rs6000_reg_names[64][0], /* mq */ \
2664 &rs6000_reg_names[65][0], /* lr */ \
2665 &rs6000_reg_names[66][0], /* ctr */ \
2666 &rs6000_reg_names[67][0], /* ap */ \
2668 &rs6000_reg_names[68][0], /* cr0 */ \
2669 &rs6000_reg_names[69][0], /* cr1 */ \
2670 &rs6000_reg_names[70][0], /* cr2 */ \
2671 &rs6000_reg_names[71][0], /* cr3 */ \
2672 &rs6000_reg_names[72][0], /* cr4 */ \
2673 &rs6000_reg_names[73][0], /* cr5 */ \
2674 &rs6000_reg_names[74][0], /* cr6 */ \
2675 &rs6000_reg_names[75][0], /* cr7 */ \
2677 &rs6000_reg_names[76][0], /* xer */ \
2679 &rs6000_reg_names[77][0], /* v0 */ \
2680 &rs6000_reg_names[78][0], /* v1 */ \
2681 &rs6000_reg_names[79][0], /* v2 */ \
2682 &rs6000_reg_names[80][0], /* v3 */ \
2683 &rs6000_reg_names[81][0], /* v4 */ \
2684 &rs6000_reg_names[82][0], /* v5 */ \
2685 &rs6000_reg_names[83][0], /* v6 */ \
2686 &rs6000_reg_names[84][0], /* v7 */ \
2687 &rs6000_reg_names[85][0], /* v8 */ \
2688 &rs6000_reg_names[86][0], /* v9 */ \
2689 &rs6000_reg_names[87][0], /* v10 */ \
2690 &rs6000_reg_names[88][0], /* v11 */ \
2691 &rs6000_reg_names[89][0], /* v12 */ \
2692 &rs6000_reg_names[90][0], /* v13 */ \
2693 &rs6000_reg_names[91][0], /* v14 */ \
2694 &rs6000_reg_names[92][0], /* v15 */ \
2695 &rs6000_reg_names[93][0], /* v16 */ \
2696 &rs6000_reg_names[94][0], /* v17 */ \
2697 &rs6000_reg_names[95][0], /* v18 */ \
2698 &rs6000_reg_names[96][0], /* v19 */ \
2699 &rs6000_reg_names[97][0], /* v20 */ \
2700 &rs6000_reg_names[98][0], /* v21 */ \
2701 &rs6000_reg_names[99][0], /* v22 */ \
2702 &rs6000_reg_names[100][0], /* v23 */ \
2703 &rs6000_reg_names[101][0], /* v24 */ \
2704 &rs6000_reg_names[102][0], /* v25 */ \
2705 &rs6000_reg_names[103][0], /* v26 */ \
2706 &rs6000_reg_names[104][0], /* v27 */ \
2707 &rs6000_reg_names[105][0], /* v28 */ \
2708 &rs6000_reg_names[106][0], /* v29 */ \
2709 &rs6000_reg_names[107][0], /* v30 */ \
2710 &rs6000_reg_names[108][0], /* v31 */ \
2711 &rs6000_reg_names[109][0], /* vrsave */ \
2712 &rs6000_reg_names[110][0], /* vscr */ \
2713 &rs6000_reg_names[111][0], /* spe_acc */ \
2714 &rs6000_reg_names[112][0], /* spefscr */ \
2717 /* print-rtl can't handle the above REGISTER_NAMES, so define the
2718 following for it. Switch to use the alternate names since
2719 they are more mnemonic. */
2721 #define DEBUG_REGISTER_NAMES \
2723 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \
2724 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \
2725 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", \
2726 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", \
2727 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", \
2728 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", \
2729 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", \
2730 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", \
2731 "mq", "lr", "ctr", "ap", \
2732 "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7", \
2734 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", \
2735 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", \
2736 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", \
2737 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", \
2739 , "spe_acc", "spefscr" \
2742 /* Table of additional register names to use in user input. */
2744 #define ADDITIONAL_REGISTER_NAMES \
2745 {{"r0", 0}, {"r1", 1}, {"r2", 2}, {"r3", 3}, \
2746 {"r4", 4}, {"r5", 5}, {"r6", 6}, {"r7", 7}, \
2747 {"r8", 8}, {"r9", 9}, {"r10", 10}, {"r11", 11}, \
2748 {"r12", 12}, {"r13", 13}, {"r14", 14}, {"r15", 15}, \
2749 {"r16", 16}, {"r17", 17}, {"r18", 18}, {"r19", 19}, \
2750 {"r20", 20}, {"r21", 21}, {"r22", 22}, {"r23", 23}, \
2751 {"r24", 24}, {"r25", 25}, {"r26", 26}, {"r27", 27}, \
2752 {"r28", 28}, {"r29", 29}, {"r30", 30}, {"r31", 31}, \
2753 {"fr0", 32}, {"fr1", 33}, {"fr2", 34}, {"fr3", 35}, \
2754 {"fr4", 36}, {"fr5", 37}, {"fr6", 38}, {"fr7", 39}, \
2755 {"fr8", 40}, {"fr9", 41}, {"fr10", 42}, {"fr11", 43}, \
2756 {"fr12", 44}, {"fr13", 45}, {"fr14", 46}, {"fr15", 47}, \
2757 {"fr16", 48}, {"fr17", 49}, {"fr18", 50}, {"fr19", 51}, \
2758 {"fr20", 52}, {"fr21", 53}, {"fr22", 54}, {"fr23", 55}, \
2759 {"fr24", 56}, {"fr25", 57}, {"fr26", 58}, {"fr27", 59}, \
2760 {"fr28", 60}, {"fr29", 61}, {"fr30", 62}, {"fr31", 63}, \
2761 {"v0", 77}, {"v1", 78}, {"v2", 79}, {"v3", 80}, \
2762 {"v4", 81}, {"v5", 82}, {"v6", 83}, {"v7", 84}, \
2763 {"v8", 85}, {"v9", 86}, {"v10", 87}, {"v11", 88}, \
2764 {"v12", 89}, {"v13", 90}, {"v14", 91}, {"v15", 92}, \
2765 {"v16", 93}, {"v17", 94}, {"v18", 95}, {"v19", 96}, \
2766 {"v20", 97}, {"v21", 98}, {"v22", 99}, {"v23", 100}, \
2767 {"v24", 101},{"v25", 102},{"v26", 103},{"v27", 104}, \
2768 {"v28", 105},{"v29", 106},{"v30", 107},{"v31", 108}, \
2769 {"vrsave", 109}, {"vscr", 110}, \
2770 {"spe_acc", 111}, {"spefscr", 112}, \
2771 /* no additional names for: mq, lr, ctr, ap */ \
2772 {"cr0", 68}, {"cr1", 69}, {"cr2", 70}, {"cr3", 71}, \
2773 {"cr4", 72}, {"cr5", 73}, {"cr6", 74}, {"cr7", 75}, \
2774 {"cc", 68}, {"sp", 1}, {"toc", 2} }
2776 /* Text to write out after a CALL that may be replaced by glue code by
2777 the loader. This depends on the AIX version. */
2778 #define RS6000_CALL_GLUE "cror 31,31,31"
2780 /* This is how to output an element of a case-vector that is relative. */
2782 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
2783 do { char buf[100]; \
2784 fputs ("\t.long ", FILE); \
2785 ASM_GENERATE_INTERNAL_LABEL (buf, "L", VALUE); \
2786 assemble_name (FILE, buf); \
2788 ASM_GENERATE_INTERNAL_LABEL (buf, "L", REL); \
2789 assemble_name (FILE, buf); \
2790 putc ('\n', FILE); \
2793 /* This is how to output an assembler line
2794 that says to advance the location counter
2795 to a multiple of 2**LOG bytes. */
2797 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
2799 fprintf (FILE, "\t.align %d\n", (LOG))
2801 /* Store in OUTPUT a string (made with alloca) containing
2802 an assembler-name for a local static variable named NAME.
2803 LABELNO is an integer which is different for each call. */
2805 #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \
2806 ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \
2807 sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO)))
2809 /* Pick up the return address upon entry to a procedure. Used for
2810 dwarf2 unwind information. This also enables the table driven
2813 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM)
2814 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LINK_REGISTER_REGNUM)
2816 /* Describe how we implement __builtin_eh_return. */
2817 #define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + 3 : INVALID_REGNUM)
2818 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 10)
2820 /* Print operand X (an rtx) in assembler syntax to file FILE.
2821 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
2822 For `%' followed by punctuation, CODE is the punctuation and X is null. */
2824 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
2826 /* Define which CODE values are valid. */
2828 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
2831 /* Print a memory address as an operand to reference that memory location. */
2833 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
2835 /* Define the codes that are matched by predicates in rs6000.c. */
2837 #define PREDICATE_CODES \
2838 {"any_operand", {CONST_INT, CONST_DOUBLE, CONST, SYMBOL_REF, \
2839 LABEL_REF, SUBREG, REG, MEM, PARALLEL}}, \
2840 {"zero_constant", {CONST_INT, CONST_DOUBLE, CONST, SYMBOL_REF, \
2841 LABEL_REF, SUBREG, REG, MEM}}, \
2842 {"short_cint_operand", {CONST_INT}}, \
2843 {"u_short_cint_operand", {CONST_INT}}, \
2844 {"non_short_cint_operand", {CONST_INT}}, \
2845 {"exact_log2_cint_operand", {CONST_INT}}, \
2846 {"gpc_reg_operand", {SUBREG, REG}}, \
2847 {"cc_reg_operand", {SUBREG, REG}}, \
2848 {"cc_reg_not_cr0_operand", {SUBREG, REG}}, \
2849 {"reg_or_short_operand", {SUBREG, REG, CONST_INT}}, \
2850 {"reg_or_neg_short_operand", {SUBREG, REG, CONST_INT}}, \
2851 {"reg_or_aligned_short_operand", {SUBREG, REG, CONST_INT}}, \
2852 {"reg_or_u_short_operand", {SUBREG, REG, CONST_INT}}, \
2853 {"reg_or_cint_operand", {SUBREG, REG, CONST_INT}}, \
2854 {"reg_or_arith_cint_operand", {SUBREG, REG, CONST_INT}}, \
2855 {"reg_or_add_cint64_operand", {SUBREG, REG, CONST_INT}}, \
2856 {"reg_or_sub_cint64_operand", {SUBREG, REG, CONST_INT}}, \
2857 {"reg_or_logical_cint_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}}, \
2858 {"got_operand", {SYMBOL_REF, CONST, LABEL_REF}}, \
2859 {"got_no_const_operand", {SYMBOL_REF, LABEL_REF}}, \
2860 {"easy_fp_constant", {CONST_DOUBLE}}, \
2861 {"zero_fp_constant", {CONST_DOUBLE}}, \
2862 {"reg_or_mem_operand", {SUBREG, MEM, REG}}, \
2863 {"lwa_operand", {SUBREG, MEM, REG}}, \
2864 {"volatile_mem_operand", {MEM}}, \
2865 {"offsettable_mem_operand", {MEM}}, \
2866 {"mem_or_easy_const_operand", {SUBREG, MEM, CONST_DOUBLE}}, \
2867 {"add_operand", {SUBREG, REG, CONST_INT}}, \
2868 {"non_add_cint_operand", {CONST_INT}}, \
2869 {"and_operand", {SUBREG, REG, CONST_INT}}, \
2870 {"and64_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}}, \
2871 {"and64_2_operand", {SUBREG, REG, CONST_INT}}, \
2872 {"logical_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}}, \
2873 {"non_logical_cint_operand", {CONST_INT, CONST_DOUBLE}}, \
2874 {"mask_operand", {CONST_INT}}, \
2875 {"mask_operand_wrap", {CONST_INT}}, \
2876 {"mask64_operand", {CONST_INT}}, \
2877 {"mask64_2_operand", {CONST_INT}}, \
2878 {"count_register_operand", {REG}}, \
2879 {"xer_operand", {REG}}, \
2880 {"symbol_ref_operand", {SYMBOL_REF}}, \
2881 {"call_operand", {SYMBOL_REF, REG}}, \
2882 {"current_file_function_operand", {SYMBOL_REF}}, \
2883 {"input_operand", {SUBREG, MEM, REG, CONST_INT, \
2884 CONST_DOUBLE, SYMBOL_REF}}, \
2885 {"load_multiple_operation", {PARALLEL}}, \
2886 {"store_multiple_operation", {PARALLEL}}, \
2887 {"vrsave_operation", {PARALLEL}}, \
2888 {"branch_comparison_operator", {EQ, NE, LE, LT, GE, \
2889 GT, LEU, LTU, GEU, GTU, \
2890 UNORDERED, ORDERED, \
2892 {"branch_positive_comparison_operator", {EQ, LT, GT, LTU, GTU, \
2894 {"scc_comparison_operator", {EQ, NE, LE, LT, GE, \
2895 GT, LEU, LTU, GEU, GTU, \
2896 UNORDERED, ORDERED, \
2898 {"trap_comparison_operator", {EQ, NE, LE, LT, GE, \
2899 GT, LEU, LTU, GEU, GTU}}, \
2900 {"boolean_operator", {AND, IOR, XOR}}, \
2901 {"boolean_or_operator", {IOR, XOR}}, \
2902 {"altivec_register_operand", {REG}}, \
2903 {"min_max_operator", {SMIN, SMAX, UMIN, UMAX}},
2905 /* uncomment for disabling the corresponding default options */
2906 /* #define MACHINE_no_sched_interblock */
2907 /* #define MACHINE_no_sched_speculative */
2908 /* #define MACHINE_no_sched_speculative_load */
2910 /* General flags. */
2911 extern int flag_pic;
2912 extern int optimize;
2913 extern int flag_expensive_optimizations;
2914 extern int frame_pointer_needed;
2916 enum rs6000_builtins
2918 /* AltiVec builtins. */
2919 ALTIVEC_BUILTIN_ST_INTERNAL_4si,
2920 ALTIVEC_BUILTIN_LD_INTERNAL_4si,
2921 ALTIVEC_BUILTIN_ST_INTERNAL_8hi,
2922 ALTIVEC_BUILTIN_LD_INTERNAL_8hi,
2923 ALTIVEC_BUILTIN_ST_INTERNAL_16qi,
2924 ALTIVEC_BUILTIN_LD_INTERNAL_16qi,
2925 ALTIVEC_BUILTIN_ST_INTERNAL_4sf,
2926 ALTIVEC_BUILTIN_LD_INTERNAL_4sf,
2927 ALTIVEC_BUILTIN_VADDUBM,
2928 ALTIVEC_BUILTIN_VADDUHM,
2929 ALTIVEC_BUILTIN_VADDUWM,
2930 ALTIVEC_BUILTIN_VADDFP,
2931 ALTIVEC_BUILTIN_VADDCUW,
2932 ALTIVEC_BUILTIN_VADDUBS,
2933 ALTIVEC_BUILTIN_VADDSBS,
2934 ALTIVEC_BUILTIN_VADDUHS,
2935 ALTIVEC_BUILTIN_VADDSHS,
2936 ALTIVEC_BUILTIN_VADDUWS,
2937 ALTIVEC_BUILTIN_VADDSWS,
2938 ALTIVEC_BUILTIN_VAND,
2939 ALTIVEC_BUILTIN_VANDC,
2940 ALTIVEC_BUILTIN_VAVGUB,
2941 ALTIVEC_BUILTIN_VAVGSB,
2942 ALTIVEC_BUILTIN_VAVGUH,
2943 ALTIVEC_BUILTIN_VAVGSH,
2944 ALTIVEC_BUILTIN_VAVGUW,
2945 ALTIVEC_BUILTIN_VAVGSW,
2946 ALTIVEC_BUILTIN_VCFUX,
2947 ALTIVEC_BUILTIN_VCFSX,
2948 ALTIVEC_BUILTIN_VCTSXS,
2949 ALTIVEC_BUILTIN_VCTUXS,
2950 ALTIVEC_BUILTIN_VCMPBFP,
2951 ALTIVEC_BUILTIN_VCMPEQUB,
2952 ALTIVEC_BUILTIN_VCMPEQUH,
2953 ALTIVEC_BUILTIN_VCMPEQUW,
2954 ALTIVEC_BUILTIN_VCMPEQFP,
2955 ALTIVEC_BUILTIN_VCMPGEFP,
2956 ALTIVEC_BUILTIN_VCMPGTUB,
2957 ALTIVEC_BUILTIN_VCMPGTSB,
2958 ALTIVEC_BUILTIN_VCMPGTUH,
2959 ALTIVEC_BUILTIN_VCMPGTSH,
2960 ALTIVEC_BUILTIN_VCMPGTUW,
2961 ALTIVEC_BUILTIN_VCMPGTSW,
2962 ALTIVEC_BUILTIN_VCMPGTFP,
2963 ALTIVEC_BUILTIN_VEXPTEFP,
2964 ALTIVEC_BUILTIN_VLOGEFP,
2965 ALTIVEC_BUILTIN_VMADDFP,
2966 ALTIVEC_BUILTIN_VMAXUB,
2967 ALTIVEC_BUILTIN_VMAXSB,
2968 ALTIVEC_BUILTIN_VMAXUH,
2969 ALTIVEC_BUILTIN_VMAXSH,
2970 ALTIVEC_BUILTIN_VMAXUW,
2971 ALTIVEC_BUILTIN_VMAXSW,
2972 ALTIVEC_BUILTIN_VMAXFP,
2973 ALTIVEC_BUILTIN_VMHADDSHS,
2974 ALTIVEC_BUILTIN_VMHRADDSHS,
2975 ALTIVEC_BUILTIN_VMLADDUHM,
2976 ALTIVEC_BUILTIN_VMRGHB,
2977 ALTIVEC_BUILTIN_VMRGHH,
2978 ALTIVEC_BUILTIN_VMRGHW,
2979 ALTIVEC_BUILTIN_VMRGLB,
2980 ALTIVEC_BUILTIN_VMRGLH,
2981 ALTIVEC_BUILTIN_VMRGLW,
2982 ALTIVEC_BUILTIN_VMSUMUBM,
2983 ALTIVEC_BUILTIN_VMSUMMBM,
2984 ALTIVEC_BUILTIN_VMSUMUHM,
2985 ALTIVEC_BUILTIN_VMSUMSHM,
2986 ALTIVEC_BUILTIN_VMSUMUHS,
2987 ALTIVEC_BUILTIN_VMSUMSHS,
2988 ALTIVEC_BUILTIN_VMINUB,
2989 ALTIVEC_BUILTIN_VMINSB,
2990 ALTIVEC_BUILTIN_VMINUH,
2991 ALTIVEC_BUILTIN_VMINSH,
2992 ALTIVEC_BUILTIN_VMINUW,
2993 ALTIVEC_BUILTIN_VMINSW,
2994 ALTIVEC_BUILTIN_VMINFP,
2995 ALTIVEC_BUILTIN_VMULEUB,
2996 ALTIVEC_BUILTIN_VMULESB,
2997 ALTIVEC_BUILTIN_VMULEUH,
2998 ALTIVEC_BUILTIN_VMULESH,
2999 ALTIVEC_BUILTIN_VMULOUB,
3000 ALTIVEC_BUILTIN_VMULOSB,
3001 ALTIVEC_BUILTIN_VMULOUH,
3002 ALTIVEC_BUILTIN_VMULOSH,
3003 ALTIVEC_BUILTIN_VNMSUBFP,
3004 ALTIVEC_BUILTIN_VNOR,
3005 ALTIVEC_BUILTIN_VOR,
3006 ALTIVEC_BUILTIN_VSEL_4SI,
3007 ALTIVEC_BUILTIN_VSEL_4SF,
3008 ALTIVEC_BUILTIN_VSEL_8HI,
3009 ALTIVEC_BUILTIN_VSEL_16QI,
3010 ALTIVEC_BUILTIN_VPERM_4SI,
3011 ALTIVEC_BUILTIN_VPERM_4SF,
3012 ALTIVEC_BUILTIN_VPERM_8HI,
3013 ALTIVEC_BUILTIN_VPERM_16QI,
3014 ALTIVEC_BUILTIN_VPKUHUM,
3015 ALTIVEC_BUILTIN_VPKUWUM,
3016 ALTIVEC_BUILTIN_VPKPX,
3017 ALTIVEC_BUILTIN_VPKUHSS,
3018 ALTIVEC_BUILTIN_VPKSHSS,
3019 ALTIVEC_BUILTIN_VPKUWSS,
3020 ALTIVEC_BUILTIN_VPKSWSS,
3021 ALTIVEC_BUILTIN_VPKUHUS,
3022 ALTIVEC_BUILTIN_VPKSHUS,
3023 ALTIVEC_BUILTIN_VPKUWUS,
3024 ALTIVEC_BUILTIN_VPKSWUS,
3025 ALTIVEC_BUILTIN_VREFP,
3026 ALTIVEC_BUILTIN_VRFIM,
3027 ALTIVEC_BUILTIN_VRFIN,
3028 ALTIVEC_BUILTIN_VRFIP,
3029 ALTIVEC_BUILTIN_VRFIZ,
3030 ALTIVEC_BUILTIN_VRLB,
3031 ALTIVEC_BUILTIN_VRLH,
3032 ALTIVEC_BUILTIN_VRLW,
3033 ALTIVEC_BUILTIN_VRSQRTEFP,
3034 ALTIVEC_BUILTIN_VSLB,
3035 ALTIVEC_BUILTIN_VSLH,
3036 ALTIVEC_BUILTIN_VSLW,
3037 ALTIVEC_BUILTIN_VSL,
3038 ALTIVEC_BUILTIN_VSLO,
3039 ALTIVEC_BUILTIN_VSPLTB,
3040 ALTIVEC_BUILTIN_VSPLTH,
3041 ALTIVEC_BUILTIN_VSPLTW,
3042 ALTIVEC_BUILTIN_VSPLTISB,
3043 ALTIVEC_BUILTIN_VSPLTISH,
3044 ALTIVEC_BUILTIN_VSPLTISW,
3045 ALTIVEC_BUILTIN_VSRB,
3046 ALTIVEC_BUILTIN_VSRH,
3047 ALTIVEC_BUILTIN_VSRW,
3048 ALTIVEC_BUILTIN_VSRAB,
3049 ALTIVEC_BUILTIN_VSRAH,
3050 ALTIVEC_BUILTIN_VSRAW,
3051 ALTIVEC_BUILTIN_VSR,
3052 ALTIVEC_BUILTIN_VSRO,
3053 ALTIVEC_BUILTIN_VSUBUBM,
3054 ALTIVEC_BUILTIN_VSUBUHM,
3055 ALTIVEC_BUILTIN_VSUBUWM,
3056 ALTIVEC_BUILTIN_VSUBFP,
3057 ALTIVEC_BUILTIN_VSUBCUW,
3058 ALTIVEC_BUILTIN_VSUBUBS,
3059 ALTIVEC_BUILTIN_VSUBSBS,
3060 ALTIVEC_BUILTIN_VSUBUHS,
3061 ALTIVEC_BUILTIN_VSUBSHS,
3062 ALTIVEC_BUILTIN_VSUBUWS,
3063 ALTIVEC_BUILTIN_VSUBSWS,
3064 ALTIVEC_BUILTIN_VSUM4UBS,
3065 ALTIVEC_BUILTIN_VSUM4SBS,
3066 ALTIVEC_BUILTIN_VSUM4SHS,
3067 ALTIVEC_BUILTIN_VSUM2SWS,
3068 ALTIVEC_BUILTIN_VSUMSWS,
3069 ALTIVEC_BUILTIN_VXOR,
3070 ALTIVEC_BUILTIN_VSLDOI_16QI,
3071 ALTIVEC_BUILTIN_VSLDOI_8HI,
3072 ALTIVEC_BUILTIN_VSLDOI_4SI,
3073 ALTIVEC_BUILTIN_VSLDOI_4SF,
3074 ALTIVEC_BUILTIN_VUPKHSB,
3075 ALTIVEC_BUILTIN_VUPKHPX,
3076 ALTIVEC_BUILTIN_VUPKHSH,
3077 ALTIVEC_BUILTIN_VUPKLSB,
3078 ALTIVEC_BUILTIN_VUPKLPX,
3079 ALTIVEC_BUILTIN_VUPKLSH,
3080 ALTIVEC_BUILTIN_MTVSCR,
3081 ALTIVEC_BUILTIN_MFVSCR,
3082 ALTIVEC_BUILTIN_DSSALL,
3083 ALTIVEC_BUILTIN_DSS,
3084 ALTIVEC_BUILTIN_LVSL,
3085 ALTIVEC_BUILTIN_LVSR,
3086 ALTIVEC_BUILTIN_DSTT,
3087 ALTIVEC_BUILTIN_DSTST,
3088 ALTIVEC_BUILTIN_DSTSTT,
3089 ALTIVEC_BUILTIN_DST,
3090 ALTIVEC_BUILTIN_LVEBX,
3091 ALTIVEC_BUILTIN_LVEHX,
3092 ALTIVEC_BUILTIN_LVEWX,
3093 ALTIVEC_BUILTIN_LVXL,
3094 ALTIVEC_BUILTIN_LVX,
3095 ALTIVEC_BUILTIN_STVX,
3096 ALTIVEC_BUILTIN_STVEBX,
3097 ALTIVEC_BUILTIN_STVEHX,
3098 ALTIVEC_BUILTIN_STVEWX,
3099 ALTIVEC_BUILTIN_STVXL,
3100 ALTIVEC_BUILTIN_VCMPBFP_P,
3101 ALTIVEC_BUILTIN_VCMPEQFP_P,
3102 ALTIVEC_BUILTIN_VCMPEQUB_P,
3103 ALTIVEC_BUILTIN_VCMPEQUH_P,
3104 ALTIVEC_BUILTIN_VCMPEQUW_P,
3105 ALTIVEC_BUILTIN_VCMPGEFP_P,
3106 ALTIVEC_BUILTIN_VCMPGTFP_P,
3107 ALTIVEC_BUILTIN_VCMPGTSB_P,
3108 ALTIVEC_BUILTIN_VCMPGTSH_P,
3109 ALTIVEC_BUILTIN_VCMPGTSW_P,
3110 ALTIVEC_BUILTIN_VCMPGTUB_P,
3111 ALTIVEC_BUILTIN_VCMPGTUH_P,
3112 ALTIVEC_BUILTIN_VCMPGTUW_P,
3113 ALTIVEC_BUILTIN_ABSS_V4SI,
3114 ALTIVEC_BUILTIN_ABSS_V8HI,
3115 ALTIVEC_BUILTIN_ABSS_V16QI,
3116 ALTIVEC_BUILTIN_ABS_V4SI,
3117 ALTIVEC_BUILTIN_ABS_V4SF,
3118 ALTIVEC_BUILTIN_ABS_V8HI,
3119 ALTIVEC_BUILTIN_ABS_V16QI
3121 , SPE_BUILTIN_EVADDW,
3124 SPE_BUILTIN_EVDIVWS,
3125 SPE_BUILTIN_EVDIVWU,
3127 SPE_BUILTIN_EVFSADD,
3128 SPE_BUILTIN_EVFSDIV,
3129 SPE_BUILTIN_EVFSMUL,
3130 SPE_BUILTIN_EVFSSUB,
3134 SPE_BUILTIN_EVLHHESPLATX,
3135 SPE_BUILTIN_EVLHHOSSPLATX,
3136 SPE_BUILTIN_EVLHHOUSPLATX,
3137 SPE_BUILTIN_EVLWHEX,
3138 SPE_BUILTIN_EVLWHOSX,
3139 SPE_BUILTIN_EVLWHOUX,
3140 SPE_BUILTIN_EVLWHSPLATX,
3141 SPE_BUILTIN_EVLWWSPLATX,
3142 SPE_BUILTIN_EVMERGEHI,
3143 SPE_BUILTIN_EVMERGEHILO,
3144 SPE_BUILTIN_EVMERGELO,
3145 SPE_BUILTIN_EVMERGELOHI,
3146 SPE_BUILTIN_EVMHEGSMFAA,
3147 SPE_BUILTIN_EVMHEGSMFAN,
3148 SPE_BUILTIN_EVMHEGSMIAA,
3149 SPE_BUILTIN_EVMHEGSMIAN,
3150 SPE_BUILTIN_EVMHEGUMIAA,
3151 SPE_BUILTIN_EVMHEGUMIAN,
3152 SPE_BUILTIN_EVMHESMF,
3153 SPE_BUILTIN_EVMHESMFA,
3154 SPE_BUILTIN_EVMHESMFAAW,
3155 SPE_BUILTIN_EVMHESMFANW,
3156 SPE_BUILTIN_EVMHESMI,
3157 SPE_BUILTIN_EVMHESMIA,
3158 SPE_BUILTIN_EVMHESMIAAW,
3159 SPE_BUILTIN_EVMHESMIANW,
3160 SPE_BUILTIN_EVMHESSF,
3161 SPE_BUILTIN_EVMHESSFA,
3162 SPE_BUILTIN_EVMHESSFAAW,
3163 SPE_BUILTIN_EVMHESSFANW,
3164 SPE_BUILTIN_EVMHESSIAAW,
3165 SPE_BUILTIN_EVMHESSIANW,
3166 SPE_BUILTIN_EVMHEUMI,
3167 SPE_BUILTIN_EVMHEUMIA,
3168 SPE_BUILTIN_EVMHEUMIAAW,
3169 SPE_BUILTIN_EVMHEUMIANW,
3170 SPE_BUILTIN_EVMHEUSIAAW,
3171 SPE_BUILTIN_EVMHEUSIANW,
3172 SPE_BUILTIN_EVMHOGSMFAA,
3173 SPE_BUILTIN_EVMHOGSMFAN,
3174 SPE_BUILTIN_EVMHOGSMIAA,
3175 SPE_BUILTIN_EVMHOGSMIAN,
3176 SPE_BUILTIN_EVMHOGUMIAA,
3177 SPE_BUILTIN_EVMHOGUMIAN,
3178 SPE_BUILTIN_EVMHOSMF,
3179 SPE_BUILTIN_EVMHOSMFA,
3180 SPE_BUILTIN_EVMHOSMFAAW,
3181 SPE_BUILTIN_EVMHOSMFANW,
3182 SPE_BUILTIN_EVMHOSMI,
3183 SPE_BUILTIN_EVMHOSMIA,
3184 SPE_BUILTIN_EVMHOSMIAAW,
3185 SPE_BUILTIN_EVMHOSMIANW,
3186 SPE_BUILTIN_EVMHOSSF,
3187 SPE_BUILTIN_EVMHOSSFA,
3188 SPE_BUILTIN_EVMHOSSFAAW,
3189 SPE_BUILTIN_EVMHOSSFANW,
3190 SPE_BUILTIN_EVMHOSSIAAW,
3191 SPE_BUILTIN_EVMHOSSIANW,
3192 SPE_BUILTIN_EVMHOUMI,
3193 SPE_BUILTIN_EVMHOUMIA,
3194 SPE_BUILTIN_EVMHOUMIAAW,
3195 SPE_BUILTIN_EVMHOUMIANW,
3196 SPE_BUILTIN_EVMHOUSIAAW,
3197 SPE_BUILTIN_EVMHOUSIANW,
3198 SPE_BUILTIN_EVMWHSMF,
3199 SPE_BUILTIN_EVMWHSMFA,
3200 SPE_BUILTIN_EVMWHSMI,
3201 SPE_BUILTIN_EVMWHSMIA,
3202 SPE_BUILTIN_EVMWHSSF,
3203 SPE_BUILTIN_EVMWHSSFA,
3204 SPE_BUILTIN_EVMWHUMI,
3205 SPE_BUILTIN_EVMWHUMIA,
3206 SPE_BUILTIN_EVMWLSMF,
3207 SPE_BUILTIN_EVMWLSMFA,
3208 SPE_BUILTIN_EVMWLSMFAAW,
3209 SPE_BUILTIN_EVMWLSMFANW,
3210 SPE_BUILTIN_EVMWLSMIAAW,
3211 SPE_BUILTIN_EVMWLSMIANW,
3212 SPE_BUILTIN_EVMWLSSF,
3213 SPE_BUILTIN_EVMWLSSFA,
3214 SPE_BUILTIN_EVMWLSSFAAW,
3215 SPE_BUILTIN_EVMWLSSFANW,
3216 SPE_BUILTIN_EVMWLSSIAAW,
3217 SPE_BUILTIN_EVMWLSSIANW,
3218 SPE_BUILTIN_EVMWLUMI,
3219 SPE_BUILTIN_EVMWLUMIA,
3220 SPE_BUILTIN_EVMWLUMIAAW,
3221 SPE_BUILTIN_EVMWLUMIANW,
3222 SPE_BUILTIN_EVMWLUSIAAW,
3223 SPE_BUILTIN_EVMWLUSIANW,
3224 SPE_BUILTIN_EVMWSMF,
3225 SPE_BUILTIN_EVMWSMFA,
3226 SPE_BUILTIN_EVMWSMFAA,
3227 SPE_BUILTIN_EVMWSMFAN,
3228 SPE_BUILTIN_EVMWSMI,
3229 SPE_BUILTIN_EVMWSMIA,
3230 SPE_BUILTIN_EVMWSMIAA,
3231 SPE_BUILTIN_EVMWSMIAN,
3232 SPE_BUILTIN_EVMWHSSFAA,
3233 SPE_BUILTIN_EVMWSSF,
3234 SPE_BUILTIN_EVMWSSFA,
3235 SPE_BUILTIN_EVMWSSFAA,
3236 SPE_BUILTIN_EVMWSSFAN,
3237 SPE_BUILTIN_EVMWUMI,
3238 SPE_BUILTIN_EVMWUMIA,
3239 SPE_BUILTIN_EVMWUMIAA,
3240 SPE_BUILTIN_EVMWUMIAN,
3249 SPE_BUILTIN_EVSTDDX,
3250 SPE_BUILTIN_EVSTDHX,
3251 SPE_BUILTIN_EVSTDWX,
3252 SPE_BUILTIN_EVSTWHEX,
3253 SPE_BUILTIN_EVSTWHOX,
3254 SPE_BUILTIN_EVSTWWEX,
3255 SPE_BUILTIN_EVSTWWOX,
3256 SPE_BUILTIN_EVSUBFW,
3259 SPE_BUILTIN_EVADDSMIAAW,
3260 SPE_BUILTIN_EVADDSSIAAW,
3261 SPE_BUILTIN_EVADDUMIAAW,
3262 SPE_BUILTIN_EVADDUSIAAW,
3263 SPE_BUILTIN_EVCNTLSW,
3264 SPE_BUILTIN_EVCNTLZW,
3265 SPE_BUILTIN_EVEXTSB,
3266 SPE_BUILTIN_EVEXTSH,
3267 SPE_BUILTIN_EVFSABS,
3268 SPE_BUILTIN_EVFSCFSF,
3269 SPE_BUILTIN_EVFSCFSI,
3270 SPE_BUILTIN_EVFSCFUF,
3271 SPE_BUILTIN_EVFSCFUI,
3272 SPE_BUILTIN_EVFSCTSF,
3273 SPE_BUILTIN_EVFSCTSI,
3274 SPE_BUILTIN_EVFSCTSIZ,
3275 SPE_BUILTIN_EVFSCTUF,
3276 SPE_BUILTIN_EVFSCTUI,
3277 SPE_BUILTIN_EVFSCTUIZ,
3278 SPE_BUILTIN_EVFSNABS,
3279 SPE_BUILTIN_EVFSNEG,
3283 SPE_BUILTIN_EVSUBFSMIAAW,
3284 SPE_BUILTIN_EVSUBFSSIAAW,
3285 SPE_BUILTIN_EVSUBFUMIAAW,
3286 SPE_BUILTIN_EVSUBFUSIAAW,
3287 SPE_BUILTIN_EVADDIW,
3291 SPE_BUILTIN_EVLHHESPLAT,
3292 SPE_BUILTIN_EVLHHOSSPLAT,
3293 SPE_BUILTIN_EVLHHOUSPLAT,
3295 SPE_BUILTIN_EVLWHOS,
3296 SPE_BUILTIN_EVLWHOU,
3297 SPE_BUILTIN_EVLWHSPLAT,
3298 SPE_BUILTIN_EVLWWSPLAT,
3301 SPE_BUILTIN_EVSRWIS,
3302 SPE_BUILTIN_EVSRWIU,
3306 SPE_BUILTIN_EVSTWHE,
3307 SPE_BUILTIN_EVSTWHO,
3308 SPE_BUILTIN_EVSTWWE,
3309 SPE_BUILTIN_EVSTWWO,
3310 SPE_BUILTIN_EVSUBIFW,
3313 SPE_BUILTIN_EVCMPEQ,
3314 SPE_BUILTIN_EVCMPGTS,
3315 SPE_BUILTIN_EVCMPGTU,
3316 SPE_BUILTIN_EVCMPLTS,
3317 SPE_BUILTIN_EVCMPLTU,
3318 SPE_BUILTIN_EVFSCMPEQ,
3319 SPE_BUILTIN_EVFSCMPGT,
3320 SPE_BUILTIN_EVFSCMPLT,
3321 SPE_BUILTIN_EVFSTSTEQ,
3322 SPE_BUILTIN_EVFSTSTGT,
3323 SPE_BUILTIN_EVFSTSTLT,
3325 /* EVSEL compares. */
3326 SPE_BUILTIN_EVSEL_CMPEQ,
3327 SPE_BUILTIN_EVSEL_CMPGTS,
3328 SPE_BUILTIN_EVSEL_CMPGTU,
3329 SPE_BUILTIN_EVSEL_CMPLTS,
3330 SPE_BUILTIN_EVSEL_CMPLTU,
3331 SPE_BUILTIN_EVSEL_FSCMPEQ,
3332 SPE_BUILTIN_EVSEL_FSCMPGT,
3333 SPE_BUILTIN_EVSEL_FSCMPLT,
3334 SPE_BUILTIN_EVSEL_FSTSTEQ,
3335 SPE_BUILTIN_EVSEL_FSTSTGT,
3336 SPE_BUILTIN_EVSEL_FSTSTLT,
3338 SPE_BUILTIN_EVSPLATFI,
3339 SPE_BUILTIN_EVSPLATI,
3340 SPE_BUILTIN_EVMWHSSMAA,
3341 SPE_BUILTIN_EVMWHSMFAA,
3342 SPE_BUILTIN_EVMWHSMIAA,
3343 SPE_BUILTIN_EVMWHUSIAA,
3344 SPE_BUILTIN_EVMWHUMIAA,
3345 SPE_BUILTIN_EVMWHSSFAN,
3346 SPE_BUILTIN_EVMWHSSIAN,
3347 SPE_BUILTIN_EVMWHSMFAN,
3348 SPE_BUILTIN_EVMWHSMIAN,
3349 SPE_BUILTIN_EVMWHUSIAN,
3350 SPE_BUILTIN_EVMWHUMIAN,
3351 SPE_BUILTIN_EVMWHGSSFAA,
3352 SPE_BUILTIN_EVMWHGSMFAA,
3353 SPE_BUILTIN_EVMWHGSMIAA,
3354 SPE_BUILTIN_EVMWHGUMIAA,
3355 SPE_BUILTIN_EVMWHGSSFAN,
3356 SPE_BUILTIN_EVMWHGSMFAN,
3357 SPE_BUILTIN_EVMWHGSMIAN,
3358 SPE_BUILTIN_EVMWHGUMIAN,
3359 SPE_BUILTIN_MTSPEFSCR,
3360 SPE_BUILTIN_MFSPEFSCR,
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