gcc/config/rs6000/altivec.md

   1 ;; AltiVec patterns.
   2 ;; Copyright (C) 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
   3 ;; Contributed by Aldy Hernandez (aldy@quesejoda.com)
   4
   5 ;; This file is part of GCC.
   6
   7 ;; GCC is free software; you can redistribute it and/or modify it
   8 ;; under the terms of the GNU General Public License as published
   9 ;; by the Free Software Foundation; either version 2, or (at your
  10 ;; option) any later version.
  11
  12 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
  13 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  14 ;; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  15 ;; License for more details.
  16
  17 ;; You should have received a copy of the GNU General Public License
  18 ;; along with GCC; see the file COPYING.  If not, write to the
  19 ;; Free Software Foundation, 59 Temple Place - Suite 330, Boston,
  20 ;; MA 02111-1307, USA.
  21
  22 (define_constants
  23   [(UNSPEC_VCMPBFP       50)
  24    (UNSPEC_VCMPEQUB      51)
  25    (UNSPEC_VCMPEQUH      52)
  26    (UNSPEC_VCMPEQUW      53)
  27    (UNSPEC_VCMPEQFP      54)
  28    (UNSPEC_VCMPGEFP      55)
  29    (UNSPEC_VCMPGTUB      56)
  30    (UNSPEC_VCMPGTSB      57)
  31    (UNSPEC_VCMPGTUH      58)
  32    (UNSPEC_VCMPGTSH      59)
  33    (UNSPEC_VCMPGTUW      60)
  34    (UNSPEC_VCMPGTSW      61)
  35    (UNSPEC_VCMPGTFP      62)
  36    (UNSPEC_VSLW         109)
  37    (UNSPEC_SUBS         126)
  38    (UNSPEC_VSEL4SI      159)
  39    (UNSPEC_VSEL4SF      160)
  40    (UNSPEC_VSEL8HI      161)
  41    (UNSPEC_VSEL16QI     162)
  42    (UNSPEC_SET_VSCR     213)
  43    (UNSPEC_VCOND_V4SI   301)
  44    (UNSPEC_VCOND_V4SF   302)
  45    (UNSPEC_VCOND_V8HI   303)
  46    (UNSPEC_VCOND_V16QI  304)
  47    (UNSPEC_VCONDU_V4SI  305)
  48    (UNSPEC_VCONDU_V8HI  306)
  49    (UNSPEC_VCONDU_V16QI 307)
  50    ])
  51
  52 ;; Vec int modes
  53 (define_mode_macro VI [V4SI V8HI V16QI])
  54 ;; Short vec in modes
  55 (define_mode_macro VIshort [V8HI V16QI])
  56 ;; Vec float modes
  57 (define_mode_macro VF [V4SF])
  58 ;; Vec modes, pity mode macros are not composable
  59 (define_mode_macro V [V4SI V8HI V16QI V4SF])
  60
  61 (define_mode_attr VI_char [(V4SI "w") (V8HI "h") (V16QI "b")])
  62
  63 ;; Generic LVX load instruction.
  64 (define_insn "altivec_lvx_<mode>"
  65   [(set (match_operand:V 0 "altivec_register_operand" "=v")
  66         (match_operand:V 1 "memory_operand" "m"))]
  67   "TARGET_ALTIVEC"
  68   "lvx %0,%y1"
  69   [(set_attr "type" "vecload")])
  70
  71 ;; Generic STVX store instruction.
  72 (define_insn "altivec_stvx_<mode>"
  73   [(set (match_operand:V 0 "memory_operand" "=m")
  74         (match_operand:V 1 "altivec_register_operand" "v"))]
  75   "TARGET_ALTIVEC"
  76   "stvx %1,%y0"
  77   [(set_attr "type" "vecstore")])
  78
  79 ;; Vector move instructions.
  80 (define_expand "mov<mode>"
  81   [(set (match_operand:V 0 "nonimmediate_operand" "")
  82         (match_operand:V 1 "any_operand" ""))]
  83   "TARGET_ALTIVEC"
  84 {
  85   rs6000_emit_move (operands[0], operands[1], <MODE>mode);
  86   DONE;
  87 })
  88
  89 (define_insn "*mov<mode>_internal"
  90   [(set (match_operand:V 0 "nonimmediate_operand" "=m,v,v,o,r,r,v")
  91         (match_operand:V 1 "input_operand" "v,m,v,r,o,r,W"))]
  92   "TARGET_ALTIVEC
  93    && (register_operand (operands[0], <MODE>mode)
  94        || register_operand (operands[1], <MODE>mode))"
  95 {
  96   switch (which_alternative)
  97     {
  98     case 0: return "stvx %1,%y0";
  99     case 1: return "lvx %0,%y1";
 100     case 2: return "vor %0,%1,%1";
 101     case 3: return "#";
 102     case 4: return "#";
 103     case 5: return "#";
 104     case 6: return output_vec_const_move (operands);
 105     default: gcc_unreachable ();
 106     }
 107 }
 108   [(set_attr "type" "vecstore,vecload,vecsimple,store,load,*,*")])
 109
 110 (define_split
 111   [(set (match_operand:V4SI 0 "nonimmediate_operand" "")
 112         (match_operand:V4SI 1 "input_operand" ""))]
 113   "TARGET_ALTIVEC && reload_completed
 114    && gpr_or_gpr_p (operands[0], operands[1])"
 115   [(pc)]
 116 {
 117   rs6000_split_multireg_move (operands[0], operands[1]); DONE;
 118 })
 119
 120 (define_split
 121   [(set (match_operand:V4SI 0 "altivec_register_operand" "")
 122         (match_operand:V4SI 1 "easy_vector_constant_add_self" ""))]
 123   "TARGET_ALTIVEC && reload_completed"
 124   [(set (match_dup 0) (match_dup 3))
 125    (set (match_dup 0)
 126         (plus:V4SI (match_dup 0)
 127                    (match_dup 0)))]
 128 {
 129   operands[3] = gen_easy_vector_constant_add_self (operands[1]);
 130 })
 131
 132 (define_split
 133   [(set (match_operand:V8HI 0 "nonimmediate_operand" "")
 134         (match_operand:V8HI 1 "input_operand" ""))]
 135   "TARGET_ALTIVEC && reload_completed
 136    && gpr_or_gpr_p (operands[0], operands[1])"
 137   [(pc)]
 138 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
 139
 140 (define_split
 141   [(set (match_operand:V8HI 0 "altivec_register_operand" "")
 142         (match_operand:V8HI 1 "easy_vector_constant_add_self" ""))]
 143   "TARGET_ALTIVEC && reload_completed"
 144   [(set (match_dup 0) (match_dup 3))
 145    (set (match_dup 0)
 146         (plus:V8HI (match_dup 0)
 147                    (match_dup 0)))]
 148 {
 149   operands[3] = gen_easy_vector_constant_add_self (operands[1]);
 150 })
 151
 152 (define_split
 153   [(set (match_operand:V16QI 0 "nonimmediate_operand" "")
 154         (match_operand:V16QI 1 "input_operand" ""))]
 155   "TARGET_ALTIVEC && reload_completed
 156    && gpr_or_gpr_p (operands[0], operands[1])"
 157   [(pc)]
 158 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
 159
 160 (define_split
 161   [(set (match_operand:V16QI 0 "altivec_register_operand" "")
 162         (match_operand:V16QI 1 "easy_vector_constant_add_self" ""))]
 163   "TARGET_ALTIVEC && reload_completed"
 164   [(set (match_dup 0) (match_dup 3))
 165    (set (match_dup 0)
 166         (plus:V16QI (match_dup 0)
 167                    (match_dup 0)))]
 168 {
 169   operands[3] = gen_easy_vector_constant_add_self (operands[1]);
 170 })
 171
 172 (define_split
 173   [(set (match_operand:V4SF 0 "nonimmediate_operand" "")
 174         (match_operand:V4SF 1 "input_operand" ""))]
 175   "TARGET_ALTIVEC && reload_completed
 176    && gpr_or_gpr_p (operands[0], operands[1])"
 177   [(pc)]
 178 {
 179   rs6000_split_multireg_move (operands[0], operands[1]); DONE;
 180 })
 181
 182 (define_insn "get_vrsave_internal"
 183   [(set (match_operand:SI 0 "register_operand" "=r")
 184         (unspec:SI [(reg:SI 109)] 214))]
 185   "TARGET_ALTIVEC"
 186 {
 187   if (TARGET_MACHO)
 188      return "mfspr %0,256";
 189   else
 190      return "mfvrsave %0";
 191 }
 192   [(set_attr "type" "*")])
 193
 194 (define_insn "*set_vrsave_internal"
 195   [(match_parallel 0 "vrsave_operation"
 196      [(set (reg:SI 109)
 197            (unspec_volatile:SI [(match_operand:SI 1 "register_operand" "r")
 198                                 (reg:SI 109)] 30))])]
 199   "TARGET_ALTIVEC"
 200 {
 201   if (TARGET_MACHO)
 202     return "mtspr 256,%1";
 203   else
 204     return "mtvrsave %1";
 205 }
 206   [(set_attr "type" "*")])
 207
 208 (define_insn "*save_world"
 209  [(match_parallel 0 "save_world_operation"
 210                   [(clobber (match_operand:SI 1 "register_operand" "=l"))
 211                    (use (match_operand:SI 2 "call_operand" "s"))])]
 212  "TARGET_MACHO && (DEFAULT_ABI == ABI_DARWIN) && TARGET_32BIT"
 213  "bl %z2"
 214   [(set_attr "type" "branch")
 215    (set_attr "length" "4")])
 216
 217 (define_insn "*restore_world"
 218  [(match_parallel 0 "restore_world_operation"
 219                   [(return)
 220                    (use (match_operand:SI 1 "register_operand" "l"))
 221                    (use (match_operand:SI 2 "call_operand" "s"))
 222                    (clobber (match_operand:SI 3 "gpc_reg_operand" "=r"))])]
 223  "TARGET_MACHO && (DEFAULT_ABI == ABI_DARWIN) && TARGET_32BIT"
 224  "b %z2")
 225
 226 ;; Simple binary operations.
 227
 228 ;; add
 229 (define_insn "add<mode>3"
 230   [(set (match_operand:VI 0 "register_operand" "=v")
 231         (plus:VI (match_operand:VI 1 "register_operand" "v")
 232                  (match_operand:VI 2 "register_operand" "v")))]
 233   "TARGET_ALTIVEC"
 234   "vaddu<VI_char>m %0,%1,%2"
 235   [(set_attr "type" "vecsimple")])
 236
 237 (define_insn "addv4sf3"
 238   [(set (match_operand:V4SF 0 "register_operand" "=v")
 239         (plus:V4SF (match_operand:V4SF 1 "register_operand" "v")
 240                    (match_operand:V4SF 2 "register_operand" "v")))]
 241   "TARGET_ALTIVEC"
 242   "vaddfp %0,%1,%2"
 243   [(set_attr "type" "vecfloat")])
 244
 245 (define_insn "altivec_vaddcuw"
 246   [(set (match_operand:V4SI 0 "register_operand" "=v")
 247         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
 248                       (match_operand:V4SI 2 "register_operand" "v")] 35))]
 249   "TARGET_ALTIVEC"
 250   "vaddcuw %0,%1,%2"
 251   [(set_attr "type" "vecsimple")])
 252
 253 (define_insn "altivec_vaddu<VI_char>s"
 254   [(set (match_operand:VI 0 "register_operand" "=v")
 255         (unspec:VI [(match_operand:VI 1 "register_operand" "v")
 256                     (match_operand:VI 2 "register_operand" "v")] 36))
 257    (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
 258   "TARGET_ALTIVEC"
 259   "vaddu<VI_char>s %0,%1,%2"
 260   [(set_attr "type" "vecsimple")])
 261
 262 (define_insn "altivec_vadds<VI_char>s"
 263   [(set (match_operand:VI 0 "register_operand" "=v")
 264         (unspec:VI [(match_operand:VI 1 "register_operand" "v")
 265                     (match_operand:VI 2 "register_operand" "v")] 37))
 266    (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
 267   "TARGET_ALTIVEC"
 268   "vadds<VI_char>s %0,%1,%2"
 269   [(set_attr "type" "vecsimple")])
 270
 271 ;; sub
 272 (define_insn "sub<mode>3"
 273   [(set (match_operand:VI 0 "register_operand" "=v")
 274         (minus:VI (match_operand:VI 1 "register_operand" "v")
 275                   (match_operand:VI 2 "register_operand" "v")))]
 276   "TARGET_ALTIVEC"
 277   "vsubu<VI_char>m %0,%1,%2"
 278   [(set_attr "type" "vecsimple")])
 279
 280 (define_insn "subv4sf3"
 281   [(set (match_operand:V4SF 0 "register_operand" "=v")
 282         (minus:V4SF (match_operand:V4SF 1 "register_operand" "v")
 283                     (match_operand:V4SF 2 "register_operand" "v")))]
 284   "TARGET_ALTIVEC"
 285   "vsubfp %0,%1,%2"
 286   [(set_attr "type" "vecfloat")])
 287
 288 (define_insn "altivec_vsubcuw"
 289   [(set (match_operand:V4SI 0 "register_operand" "=v")
 290         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
 291                       (match_operand:V4SI 2 "register_operand" "v")] 124))]
 292   "TARGET_ALTIVEC"
 293   "vsubcuw %0,%1,%2"
 294   [(set_attr "type" "vecsimple")])
 295
 296 (define_insn "altivec_vsubu<VI_char>s"
 297   [(set (match_operand:VI 0 "register_operand" "=v")
 298         (unspec:VI [(match_operand:VI 1 "register_operand" "v")
 299                     (match_operand:VI 2 "register_operand" "v")] 125))
 300    (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
 301   "TARGET_ALTIVEC"
 302   "vsubu<VI_char>s %0,%1,%2"
 303   [(set_attr "type" "vecsimple")])
 304
 305 (define_insn "altivec_vsubs<VI_char>s"
 306   [(set (match_operand:VI 0 "register_operand" "=v")
 307         (unspec:VI [(match_operand:VI 1 "register_operand" "v")
 308                     (match_operand:VI 2 "register_operand" "v")] UNSPEC_SUBS))
 309    (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
 310   "TARGET_ALTIVEC"
 311   "vsubs<VI_char>s %0,%1,%2"
 312   [(set_attr "type" "vecsimple")])
 313
 314 ;;
 315 (define_insn "altivec_vavgu<VI_char>"
 316   [(set (match_operand:VI 0 "register_operand" "=v")
 317         (unspec:VI [(match_operand:VI 1 "register_operand" "v")
 318                     (match_operand:VI 2 "register_operand" "v")] 44))]
 319   "TARGET_ALTIVEC"
 320   "vavgu<VI_char> %0,%1,%2"
 321   [(set_attr "type" "vecsimple")])
 322
 323 (define_insn "altivec_vavgs<VI_char>"
 324   [(set (match_operand:VI 0 "register_operand" "=v")
 325         (unspec:VI [(match_operand:VI 1 "register_operand" "v")
 326                     (match_operand:VI 2 "register_operand" "v")] 45))]
 327   "TARGET_ALTIVEC"
 328   "vavgs<VI_char> %0,%1,%2"
 329   [(set_attr "type" "vecsimple")])
 330
 331 (define_insn "altivec_vcmpbfp"
 332   [(set (match_operand:V4SI 0 "register_operand" "=v")
 333         (unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v")
 334                       (match_operand:V4SF 2 "register_operand" "v")]
 335                       UNSPEC_VCMPBFP))]
 336   "TARGET_ALTIVEC"
 337   "vcmpbfp %0,%1,%2"
 338   [(set_attr "type" "veccmp")])
 339
 340 (define_insn "altivec_vcmpequb"
 341   [(set (match_operand:V16QI 0 "register_operand" "=v")
 342         (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
 343                        (match_operand:V16QI 2 "register_operand" "v")]
 344                        UNSPEC_VCMPEQUB))]
 345   "TARGET_ALTIVEC"
 346   "vcmpequb %0,%1,%2"
 347   [(set_attr "type" "vecsimple")])
 348
 349 (define_insn "altivec_vcmpequh"
 350   [(set (match_operand:V8HI 0 "register_operand" "=v")
 351         (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
 352                       (match_operand:V8HI 2 "register_operand" "v")]
 353                       UNSPEC_VCMPEQUH))]
 354   "TARGET_ALTIVEC"
 355   "vcmpequh %0,%1,%2"
 356   [(set_attr "type" "vecsimple")])
 357
 358 (define_insn "altivec_vcmpequw"
 359   [(set (match_operand:V4SI 0 "register_operand" "=v")
 360         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
 361                       (match_operand:V4SI 2 "register_operand" "v")]
 362                       UNSPEC_VCMPEQUW))]
 363   "TARGET_ALTIVEC"
 364   "vcmpequw %0,%1,%2"
 365   [(set_attr "type" "vecsimple")])
 366
 367 (define_insn "altivec_vcmpeqfp"
 368   [(set (match_operand:V4SI 0 "register_operand" "=v")
 369         (unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v")
 370                       (match_operand:V4SF 2 "register_operand" "v")]
 371                       UNSPEC_VCMPEQFP))]
 372   "TARGET_ALTIVEC"
 373   "vcmpeqfp %0,%1,%2"
 374   [(set_attr "type" "veccmp")])
 375
 376 (define_insn "altivec_vcmpgefp"
 377   [(set (match_operand:V4SI 0 "register_operand" "=v")
 378         (unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v")
 379                       (match_operand:V4SF 2 "register_operand" "v")]
 380                        UNSPEC_VCMPGEFP))]
 381   "TARGET_ALTIVEC"
 382   "vcmpgefp %0,%1,%2"
 383   [(set_attr "type" "veccmp")])
 384
 385 (define_insn "altivec_vcmpgtub"
 386   [(set (match_operand:V16QI 0 "register_operand" "=v")
 387         (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
 388                        (match_operand:V16QI 2 "register_operand" "v")]
 389                        UNSPEC_VCMPGTUB))]
 390   "TARGET_ALTIVEC"
 391   "vcmpgtub %0,%1,%2"
 392   [(set_attr "type" "vecsimple")])
 393
 394 (define_insn "altivec_vcmpgtsb"
 395   [(set (match_operand:V16QI 0 "register_operand" "=v")
 396         (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
 397                        (match_operand:V16QI 2 "register_operand" "v")]
 398                        UNSPEC_VCMPGTSB))]
 399   "TARGET_ALTIVEC"
 400   "vcmpgtsb %0,%1,%2"
 401   [(set_attr "type" "vecsimple")])
 402
 403 (define_insn "altivec_vcmpgtuh"
 404   [(set (match_operand:V8HI 0 "register_operand" "=v")
 405         (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
 406                       (match_operand:V8HI 2 "register_operand" "v")]
 407                       UNSPEC_VCMPGTUH))]
 408   "TARGET_ALTIVEC"
 409   "vcmpgtuh %0,%1,%2"
 410   [(set_attr "type" "vecsimple")])
 411
 412 (define_insn "altivec_vcmpgtsh"
 413   [(set (match_operand:V8HI 0 "register_operand" "=v")
 414         (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
 415                       (match_operand:V8HI 2 "register_operand" "v")]
 416                       UNSPEC_VCMPGTSH))]
 417   "TARGET_ALTIVEC"
 418   "vcmpgtsh %0,%1,%2"
 419   [(set_attr "type" "vecsimple")])
 420
 421 (define_insn "altivec_vcmpgtuw"
 422   [(set (match_operand:V4SI 0 "register_operand" "=v")
 423         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
 424                       (match_operand:V4SI 2 "register_operand" "v")]
 425                       UNSPEC_VCMPGTUW))]
 426   "TARGET_ALTIVEC"
 427   "vcmpgtuw %0,%1,%2"
 428   [(set_attr "type" "vecsimple")])
 429
 430 (define_insn "altivec_vcmpgtsw"
 431   [(set (match_operand:V4SI 0 "register_operand" "=v")
 432         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
 433                       (match_operand:V4SI 2 "register_operand" "v")]
 434                       UNSPEC_VCMPGTSW))]
 435   "TARGET_ALTIVEC"
 436   "vcmpgtsw %0,%1,%2"
 437   [(set_attr "type" "vecsimple")])
 438
 439 (define_insn "altivec_vcmpgtfp"
 440   [(set (match_operand:V4SI 0 "register_operand" "=v")
 441         (unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v")
 442                       (match_operand:V4SF 2 "register_operand" "v")]
 443                       UNSPEC_VCMPGTFP))]
 444   "TARGET_ALTIVEC"
 445   "vcmpgtfp %0,%1,%2"
 446   [(set_attr "type" "veccmp")])
 447
 448 ;; Fused multiply add
 449 (define_insn "altivec_vmaddfp"
 450   [(set (match_operand:V4SF 0 "register_operand" "=v")
 451         (plus:V4SF (mult:V4SF (match_operand:V4SF 1 "register_operand" "v")
 452                               (match_operand:V4SF 2 "register_operand" "v"))
 453                    (match_operand:V4SF 3 "register_operand" "v")))]
 454   "TARGET_ALTIVEC"
 455   "vmaddfp %0,%1,%2,%3"
 456   [(set_attr "type" "vecfloat")])
 457
 458 ;; We do multiply as a fused multiply-add with an add of a -0.0 vector.
 459
 460 (define_expand "mulv4sf3"
 461   [(use (match_operand:V4SF 0 "register_operand" ""))
 462    (use (match_operand:V4SF 1 "register_operand" ""))
 463    (use (match_operand:V4SF 2 "register_operand" ""))]
 464   "TARGET_ALTIVEC && TARGET_FUSED_MADD"
 465   "
 466 {
 467   rtx neg0;
 468
 469   /* Generate [-0.0, -0.0, -0.0, -0.0].  */
 470   neg0 = gen_reg_rtx (V4SFmode);
 471   emit_insn (gen_altivec_vspltisw_v4sf (neg0, constm1_rtx));
 472   emit_insn (gen_altivec_vslw_v4sf (neg0, neg0, neg0));
 473
 474   /* Use the multiply-add.  */
 475   emit_insn (gen_altivec_vmaddfp (operands[0], operands[1], operands[2],
 476                                   neg0));
 477   DONE;
 478 }")
 479
 480 ;; 32 bit integer multiplication
 481 ;; A_high = Operand_0 & 0xFFFF0000 >> 16
 482 ;; A_low = Operand_0 & 0xFFFF
 483 ;; B_high = Operand_1 & 0xFFFF0000 >> 16
 484 ;; B_low = Operand_1 & 0xFFFF
 485 ;; result = A_low * B_low + (A_high * B_low + B_high * A_low) << 16
 486
 487 ;; (define_insn "mulv4si3"
 488 ;;   [(set (match_operand:V4SI 0 "register_operand" "=v")
 489 ;;         (mult:V4SI (match_operand:V4SI 1 "register_operand" "v")
 490 ;;                    (match_operand:V4SI 2 "register_operand" "v")))]
 491 (define_expand "mulv4si3"
 492   [(use (match_operand:V4SI 0 "register_operand" ""))
 493    (use (match_operand:V4SI 1 "register_operand" ""))
 494    (use (match_operand:V4SI 2 "register_operand" ""))]
 495    "TARGET_ALTIVEC"
 496    "
 497  {
 498    rtx zero;
 499    rtx swap;
 500    rtx small_swap;
 501    rtx sixteen;
 502    rtx one;
 503    rtx two;
 504    rtx low_product;
 505    rtx high_product;
 506
 507    zero = gen_reg_rtx (V4SImode);
 508    emit_insn (gen_altivec_vspltisw (zero, const0_rtx));
 509
 510    sixteen = gen_reg_rtx (V4SImode);
 511    emit_insn (gen_altivec_vspltisw (sixteen,  gen_rtx_CONST_INT (V4SImode, -16)));
 512
 513    swap = gen_reg_rtx (V4SImode);
 514    emit_insn (gen_altivec_vrlw (swap, operands[2], sixteen));
 515
 516    one = gen_reg_rtx (V8HImode);
 517    convert_move (one, operands[1], 0);
 518
 519    two = gen_reg_rtx (V8HImode);
 520    convert_move (two, operands[2], 0);
 521
 522    small_swap = gen_reg_rtx (V8HImode);
 523    convert_move (small_swap, swap, 0);
 524
 525    low_product = gen_reg_rtx (V4SImode);
 526    emit_insn (gen_altivec_vmulouh (low_product, one, two));
 527
 528    high_product = gen_reg_rtx (V4SImode);
 529    emit_insn (gen_altivec_vmsumuhm (high_product, one, small_swap, zero));
 530
 531    emit_insn (gen_altivec_vslw (high_product, high_product, sixteen));
 532
 533    emit_insn (gen_addv4si3 (operands[0], high_product, low_product));
 534
 535    DONE;
 536  }")
 537
 538
 539 ;; Fused multiply subtract
 540 (define_insn "altivec_vnmsubfp"
 541   [(set (match_operand:V4SF 0 "register_operand" "=v")
 542         (neg:V4SF (minus:V4SF (mult:V4SF (match_operand:V4SF 1 "register_operand" "v")
 543                                (match_operand:V4SF 2 "register_operand" "v"))
 544                     (match_operand:V4SF 3 "register_operand" "v"))))]
 545   "TARGET_ALTIVEC"
 546   "vnmsubfp %0,%1,%2,%3"
 547   [(set_attr "type" "vecfloat")])
 548
 549 (define_insn "altivec_vmsumu<VI_char>m"
 550   [(set (match_operand:V4SI 0 "register_operand" "=v")
 551         (unspec:V4SI [(match_operand:VIshort 1 "register_operand" "v")
 552                       (match_operand:VIshort 2 "register_operand" "v")
 553                       (match_operand:V4SI 3 "register_operand" "v")] 65))]
 554   "TARGET_ALTIVEC"
 555   "vmsumu<VI_char>m %0,%1,%2,%3"
 556   [(set_attr "type" "veccomplex")])
 557
 558 (define_insn "altivec_vmsumm<VI_char>m"
 559   [(set (match_operand:V4SI 0 "register_operand" "=v")
 560         (unspec:V4SI [(match_operand:VIshort 1 "register_operand" "v")
 561                       (match_operand:VIshort 2 "register_operand" "v")
 562                       (match_operand:V4SI 3 "register_operand" "v")] 66))]
 563   "TARGET_ALTIVEC"
 564   "vmsumm<VI_char>m %0,%1,%2,%3"
 565   [(set_attr "type" "veccomplex")])
 566
 567 (define_insn "altivec_vmsumshm"
 568   [(set (match_operand:V4SI 0 "register_operand" "=v")
 569         (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
 570                       (match_operand:V8HI 2 "register_operand" "v")
 571                       (match_operand:V4SI 3 "register_operand" "v")] 68))]
 572   "TARGET_ALTIVEC"
 573   "vmsumshm %0,%1,%2,%3"
 574   [(set_attr "type" "veccomplex")])
 575
 576 (define_insn "altivec_vmsumuhs"
 577   [(set (match_operand:V4SI 0 "register_operand" "=v")
 578         (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
 579                       (match_operand:V8HI 2 "register_operand" "v")
 580                       (match_operand:V4SI 3 "register_operand" "v")] 69))
 581    (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
 582   "TARGET_ALTIVEC"
 583   "vmsumuhs %0,%1,%2,%3"
 584   [(set_attr "type" "veccomplex")])
 585
 586 (define_insn "altivec_vmsumshs"
 587   [(set (match_operand:V4SI 0 "register_operand" "=v")
 588         (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
 589                       (match_operand:V8HI 2 "register_operand" "v")
 590                       (match_operand:V4SI 3 "register_operand" "v")] 70))
 591    (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
 592   "TARGET_ALTIVEC"
 593   "vmsumshs %0,%1,%2,%3"
 594   [(set_attr "type" "veccomplex")])
 595
 596 ;; max
 597
 598 (define_insn "umax<mode>3"
 599   [(set (match_operand:VI 0 "register_operand" "=v")
 600         (umax:VI (match_operand:VI 1 "register_operand" "v")
 601                  (match_operand:VI 2 "register_operand" "v")))]
 602   "TARGET_ALTIVEC"
 603   "vmaxu<VI_char> %0,%1,%2"
 604   [(set_attr "type" "vecsimple")])
 605
 606 (define_insn "smax<mode>3"
 607   [(set (match_operand:VI 0 "register_operand" "=v")
 608         (smax:VI (match_operand:VI 1 "register_operand" "v")
 609                  (match_operand:VI 2 "register_operand" "v")))]
 610   "TARGET_ALTIVEC"
 611   "vmaxs<VI_char> %0,%1,%2"
 612   [(set_attr "type" "vecsimple")])
 613
 614 (define_insn "smaxv4sf3"
 615   [(set (match_operand:V4SF 0 "register_operand" "=v")
 616         (smax:V4SF (match_operand:V4SF 1 "register_operand" "v")
 617                    (match_operand:V4SF 2 "register_operand" "v")))]
 618   "TARGET_ALTIVEC"
 619   "vmaxfp %0,%1,%2"
 620   [(set_attr "type" "veccmp")])
 621
 622 (define_insn "umin<mode>3"
 623   [(set (match_operand:VI 0 "register_operand" "=v")
 624         (umin:VI (match_operand:VI 1 "register_operand" "v")
 625                  (match_operand:VI 2 "register_operand" "v")))]
 626   "TARGET_ALTIVEC"
 627   "vminu<VI_char> %0,%1,%2"
 628   [(set_attr "type" "vecsimple")])
 629
 630 (define_insn "smin<mode>3"
 631   [(set (match_operand:VI 0 "register_operand" "=v")
 632         (smin:VI (match_operand:VI 1 "register_operand" "v")
 633                  (match_operand:VI 2 "register_operand" "v")))]
 634   "TARGET_ALTIVEC"
 635   "vmins<VI_char> %0,%1,%2"
 636   [(set_attr "type" "vecsimple")])
 637
 638 (define_insn "sminv4sf3"
 639   [(set (match_operand:V4SF 0 "register_operand" "=v")
 640         (smin:V4SF (match_operand:V4SF 1 "register_operand" "v")
 641                    (match_operand:V4SF 2 "register_operand" "v")))]
 642   "TARGET_ALTIVEC"
 643   "vminfp %0,%1,%2"
 644   [(set_attr "type" "veccmp")])
 645
 646 (define_insn "altivec_vmhaddshs"
 647   [(set (match_operand:V8HI 0 "register_operand" "=v")
 648         (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
 649                       (match_operand:V8HI 2 "register_operand" "v")
 650                       (match_operand:V8HI 3 "register_operand" "v")] 71))
 651    (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
 652   "TARGET_ALTIVEC"
 653   "vmhaddshs %0,%1,%2,%3"
 654   [(set_attr "type" "veccomplex")])
 655 (define_insn "altivec_vmhraddshs"
 656   [(set (match_operand:V8HI 0 "register_operand" "=v")
 657         (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
 658                       (match_operand:V8HI 2 "register_operand" "v")
 659                       (match_operand:V8HI 3 "register_operand" "v")] 72))
 660    (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
 661   "TARGET_ALTIVEC"
 662   "vmhraddshs %0,%1,%2,%3"
 663   [(set_attr "type" "veccomplex")])
 664 (define_insn "altivec_vmladduhm"
 665   [(set (match_operand:V8HI 0 "register_operand" "=v")
 666         (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
 667                       (match_operand:V8HI 2 "register_operand" "v")
 668                       (match_operand:V8HI 3 "register_operand" "v")] 73))]
 669   "TARGET_ALTIVEC"
 670   "vmladduhm %0,%1,%2,%3"
 671   [(set_attr "type" "veccomplex")])
 672
 673 (define_insn "altivec_vmrghb"
 674   [(set (match_operand:V16QI 0 "register_operand" "=v")
 675         (vec_merge:V16QI (vec_select:V16QI (match_operand:V16QI 1 "register_operand" "v")
 676                                            (parallel [(const_int 8)
 677                                                       (const_int 9)
 678                                                       (const_int 10)
 679                                                       (const_int 11)
 680                                                       (const_int 12)
 681                                                       (const_int 13)
 682                                                       (const_int 14)
 683                                                       (const_int 15)
 684                                                       (const_int 0)
 685                                                       (const_int 1)
 686                                                       (const_int 2)
 687                                                       (const_int 3)
 688                                                       (const_int 4)
 689                                                       (const_int 5)
 690                                                       (const_int 6)
 691                                                       (const_int 7)]))
 692                       (match_operand:V16QI 2 "register_operand" "v")
 693                       (const_int 255)))]
 694   "TARGET_ALTIVEC"
 695   "vmrghb %0,%1,%2"
 696   [(set_attr "type" "vecperm")])
 697
 698 (define_insn "altivec_vmrghh"
 699   [(set (match_operand:V8HI 0 "register_operand" "=v")
 700         (vec_merge:V8HI (vec_select:V8HI (match_operand:V8HI 1 "register_operand" "v")
 701                                            (parallel [(const_int 4)
 702                                                       (const_int 5)
 703                                                       (const_int 6)
 704                                                       (const_int 7)
 705                                                       (const_int 0)
 706                                                       (const_int 1)
 707                                                       (const_int 2)
 708                                                       (const_int 3)]))
 709                       (match_operand:V8HI 2 "register_operand" "v")
 710                       (const_int 15)))]
 711   "TARGET_ALTIVEC"
 712   "vmrghh %0,%1,%2"
 713   [(set_attr "type" "vecperm")])
 714
 715 (define_insn "altivec_vmrghw"
 716   [(set (match_operand:V4SI 0 "register_operand" "=v")
 717         (vec_merge:V4SI (vec_select:V4SI (match_operand:V4SI 1 "register_operand" "v")
 718                                          (parallel [(const_int 2)
 719                                                     (const_int 3)
 720                                                     (const_int 0)
 721                                                     (const_int 1)]))
 722                       (match_operand:V4SI 2 "register_operand" "v")
 723                       (const_int 12)))]
 724   "TARGET_ALTIVEC"
 725   "vmrghw %0,%1,%2"
 726   [(set_attr "type" "vecperm")])
 727
 728 (define_insn "altivec_vmrglb"
 729   [(set (match_operand:V16QI 0 "register_operand" "=v")
 730         (vec_merge:V16QI (vec_select:V16QI (match_operand:V16QI 2 "register_operand" "v")
 731                                            (parallel [(const_int 0)
 732                                                       (const_int 1)
 733                                                       (const_int 2)
 734                                                       (const_int 3)
 735                                                       (const_int 4)
 736                                                       (const_int 5)
 737                                                       (const_int 6)
 738                                                       (const_int 7)
 739                                                       (const_int 8)
 740                                                       (const_int 9)
 741                                                       (const_int 10)
 742                                                       (const_int 11)
 743                                                       (const_int 12)
 744                                                       (const_int 13)
 745                                                       (const_int 14)
 746                                                       (const_int 15)]))
 747                       (match_operand:V16QI 1 "register_operand" "v")
 748                       (const_int 255)))]
 749   "TARGET_ALTIVEC"
 750   "vmrglb %0,%1,%2"
 751   [(set_attr "type" "vecperm")])
 752
 753 (define_insn "altivec_vmrglh"
 754   [(set (match_operand:V8HI 0 "register_operand" "=v")
 755         (vec_merge:V8HI (vec_select:V8HI (match_operand:V8HI 2 "register_operand" "v")
 756                                            (parallel [(const_int 0)
 757                                                       (const_int 1)
 758                                                       (const_int 2)
 759                                                       (const_int 3)
 760                                                       (const_int 4)
 761                                                       (const_int 5)
 762                                                       (const_int 6)
 763                                                       (const_int 7)]))
 764                       (match_operand:V8HI 1 "register_operand" "v")
 765                       (const_int 15)))]
 766   "TARGET_ALTIVEC"
 767   "vmrglh %0,%1,%2"
 768   [(set_attr "type" "vecperm")])
 769
 770 (define_insn "altivec_vmrglw"
 771   [(set (match_operand:V4SI 0 "register_operand" "=v")
 772         (vec_merge:V4SI (vec_select:V4SI (match_operand:V4SI 2 "register_operand" "v")
 773                                          (parallel [(const_int 0)
 774                                                     (const_int 1)
 775                                                     (const_int 2)
 776                                                     (const_int 3)]))
 777                       (match_operand:V4SI 1 "register_operand" "v")
 778                       (const_int 12)))]
 779   "TARGET_ALTIVEC"
 780   "vmrglw %0,%1,%2"
 781   [(set_attr "type" "vecperm")])
 782
 783 (define_insn "altivec_vmuleub"
 784   [(set (match_operand:V8HI 0 "register_operand" "=v")
 785         (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")
 786                       (match_operand:V16QI 2 "register_operand" "v")] 83))]
 787   "TARGET_ALTIVEC"
 788   "vmuleub %0,%1,%2"
 789   [(set_attr "type" "veccomplex")])
 790
 791 (define_insn "altivec_vmulesb"
 792   [(set (match_operand:V8HI 0 "register_operand" "=v")
 793         (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")
 794                       (match_operand:V16QI 2 "register_operand" "v")] 84))]
 795   "TARGET_ALTIVEC"
 796   "vmulesb %0,%1,%2"
 797   [(set_attr "type" "veccomplex")])
 798
 799 (define_insn "altivec_vmuleuh"
 800   [(set (match_operand:V4SI 0 "register_operand" "=v")
 801         (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
 802                       (match_operand:V8HI 2 "register_operand" "v")] 85))]
 803   "TARGET_ALTIVEC"
 804   "vmuleuh %0,%1,%2"
 805   [(set_attr "type" "veccomplex")])
 806
 807 (define_insn "altivec_vmulesh"
 808   [(set (match_operand:V4SI 0 "register_operand" "=v")
 809         (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
 810                       (match_operand:V8HI 2 "register_operand" "v")] 86))]
 811   "TARGET_ALTIVEC"
 812   "vmulesh %0,%1,%2"
 813   [(set_attr "type" "veccomplex")])
 814
 815 (define_insn "altivec_vmuloub"
 816   [(set (match_operand:V8HI 0 "register_operand" "=v")
 817         (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")
 818                       (match_operand:V16QI 2 "register_operand" "v")] 87))]
 819   "TARGET_ALTIVEC"
 820   "vmuloub %0,%1,%2"
 821   [(set_attr "type" "veccomplex")])
 822
 823 (define_insn "altivec_vmulosb"
 824   [(set (match_operand:V8HI 0 "register_operand" "=v")
 825         (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")
 826                       (match_operand:V16QI 2 "register_operand" "v")] 88))]
 827   "TARGET_ALTIVEC"
 828   "vmulosb %0,%1,%2"
 829   [(set_attr "type" "veccomplex")])
 830
 831 (define_insn "altivec_vmulouh"
 832   [(set (match_operand:V4SI 0 "register_operand" "=v")
 833         (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
 834                       (match_operand:V8HI 2 "register_operand" "v")] 89))]
 835   "TARGET_ALTIVEC"
 836   "vmulouh %0,%1,%2"
 837   [(set_attr "type" "veccomplex")])
 838
 839 (define_insn "altivec_vmulosh"
 840   [(set (match_operand:V4SI 0 "register_operand" "=v")
 841         (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
 842                       (match_operand:V8HI 2 "register_operand" "v")] 90))]
 843   "TARGET_ALTIVEC"
 844   "vmulosh %0,%1,%2"
 845   [(set_attr "type" "veccomplex")])
 846
 847
 848 ;; logical ops
 849
 850 (define_insn "and<mode>3"
 851   [(set (match_operand:VI 0 "register_operand" "=v")
 852         (and:VI (match_operand:VI 1 "register_operand" "v")
 853                 (match_operand:VI 2 "register_operand" "v")))]
 854   "TARGET_ALTIVEC"
 855   "vand %0,%1,%2"
 856   [(set_attr "type" "vecsimple")])
 857
 858 (define_insn "ior<mode>3"
 859   [(set (match_operand:VI 0 "register_operand" "=v")
 860         (ior:VI (match_operand:VI 1 "register_operand" "v")
 861                 (match_operand:VI 2 "register_operand" "v")))]
 862   "TARGET_ALTIVEC"
 863   "vor %0,%1,%2"
 864   [(set_attr "type" "vecsimple")])
 865
 866 (define_insn "xor<mode>3"
 867   [(set (match_operand:VI 0 "register_operand" "=v")
 868         (xor:VI (match_operand:VI 1 "register_operand" "v")
 869                 (match_operand:VI 2 "register_operand" "v")))]
 870   "TARGET_ALTIVEC"
 871   "vxor %0,%1,%2"
 872   [(set_attr "type" "vecsimple")])
 873
 874 (define_insn "one_cmpl<mode>2"
 875   [(set (match_operand:VI 0 "register_operand" "=v")
 876         (not:VI (match_operand:VI 1 "register_operand" "v")))]
 877   "TARGET_ALTIVEC"
 878   "vnor %0,%1,%1"
 879   [(set_attr "type" "vecsimple")])
 880
 881 (define_insn "altivec_nor<mode>3"
 882   [(set (match_operand:VI 0 "register_operand" "=v")
 883         (not:VI (ior:VI (match_operand:VI 1 "register_operand" "v")
 884                         (match_operand:VI 2 "register_operand" "v"))))]
 885   "TARGET_ALTIVEC"
 886   "vnor %0,%1,%2"
 887   [(set_attr "type" "vecsimple")])
 888
 889 (define_insn "andc<mode>3"
 890   [(set (match_operand:VI 0 "register_operand" "=v")
 891         (and:VI (not:VI (match_operand:VI 2 "register_operand" "v"))
 892                 (match_operand:VI 1 "register_operand" "v")))]
 893   "TARGET_ALTIVEC"
 894   "vandc %0,%1,%2"
 895   [(set_attr "type" "vecsimple")])
 896
 897 (define_insn "*andc3_v4sf"
 898   [(set (match_operand:V4SF 0 "register_operand" "=v")
 899         (and:V4SF (not:V4SF (match_operand:V4SF 2 "register_operand" "v"))
 900                   (match_operand:V4SF 1 "register_operand" "v")))]
 901   "TARGET_ALTIVEC"
 902   "vandc %0,%1,%2"
 903   [(set_attr "type" "vecsimple")])
 904
 905 (define_insn "altivec_vpkuhum"
 906   [(set (match_operand:V16QI 0 "register_operand" "=v")
 907         (unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v")
 908                        (match_operand:V8HI 2 "register_operand" "v")] 93))]
 909   "TARGET_ALTIVEC"
 910   "vpkuhum %0,%1,%2"
 911   [(set_attr "type" "vecperm")])
 912
 913 (define_insn "altivec_vpkuwum"
 914   [(set (match_operand:V8HI 0 "register_operand" "=v")
 915         (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v")
 916                       (match_operand:V4SI 2 "register_operand" "v")] 94))]
 917   "TARGET_ALTIVEC"
 918   "vpkuwum %0,%1,%2"
 919   [(set_attr "type" "vecperm")])
 920
 921 (define_insn "altivec_vpkpx"
 922   [(set (match_operand:V8HI 0 "register_operand" "=v")
 923         (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v")
 924                       (match_operand:V4SI 2 "register_operand" "v")] 95))]
 925   "TARGET_ALTIVEC"
 926   "vpkpx %0,%1,%2"
 927   [(set_attr "type" "vecperm")])
 928
 929 (define_insn "altivec_vpkuhss"
 930   [(set (match_operand:V16QI 0 "register_operand" "=v")
 931         (unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v")
 932                        (match_operand:V8HI 2 "register_operand" "v")] 96))
 933    (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
 934   "TARGET_ALTIVEC"
 935   "vpkuhss %0,%1,%2"
 936   [(set_attr "type" "vecperm")])
 937
 938 (define_insn "altivec_vpkshss"
 939   [(set (match_operand:V16QI 0 "register_operand" "=v")
 940         (unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v")
 941                        (match_operand:V8HI 2 "register_operand" "v")] 97))
 942    (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
 943   "TARGET_ALTIVEC"
 944   "vpkshss %0,%1,%2"
 945   [(set_attr "type" "vecperm")])
 946
 947 (define_insn "altivec_vpkuwss"
 948   [(set (match_operand:V8HI 0 "register_operand" "=v")
 949         (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v")
 950                       (match_operand:V4SI 2 "register_operand" "v")] 98))
 951    (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
 952   "TARGET_ALTIVEC"
 953   "vpkuwss %0,%1,%2"
 954   [(set_attr "type" "vecperm")])
 955
 956 (define_insn "altivec_vpkswss"
 957   [(set (match_operand:V8HI 0 "register_operand" "=v")
 958         (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v")
 959                       (match_operand:V4SI 2 "register_operand" "v")] 99))
 960    (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
 961   "TARGET_ALTIVEC"
 962   "vpkswss %0,%1,%2"
 963   [(set_attr "type" "vecperm")])
 964
 965 (define_insn "altivec_vpkuhus"
 966   [(set (match_operand:V16QI 0 "register_operand" "=v")
 967         (unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v")
 968                        (match_operand:V8HI 2 "register_operand" "v")] 100))
 969    (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
 970   "TARGET_ALTIVEC"
 971   "vpkuhus %0,%1,%2"
 972   [(set_attr "type" "vecperm")])
 973
 974 (define_insn "altivec_vpkshus"
 975   [(set (match_operand:V16QI 0 "register_operand" "=v")
 976         (unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v")
 977                        (match_operand:V8HI 2 "register_operand" "v")] 101))
 978    (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
 979   "TARGET_ALTIVEC"
 980   "vpkshus %0,%1,%2"
 981   [(set_attr "type" "vecperm")])
 982
 983 (define_insn "altivec_vpkuwus"
 984   [(set (match_operand:V8HI 0 "register_operand" "=v")
 985         (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v")
 986                       (match_operand:V4SI 2 "register_operand" "v")] 102))
 987    (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
 988   "TARGET_ALTIVEC"
 989   "vpkuwus %0,%1,%2"
 990   [(set_attr "type" "vecperm")])
 991
 992 (define_insn "altivec_vpkswus"
 993   [(set (match_operand:V8HI 0 "register_operand" "=v")
 994         (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v")
 995                       (match_operand:V4SI 2 "register_operand" "v")] 103))
 996    (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
 997   "TARGET_ALTIVEC"
 998   "vpkswus %0,%1,%2"
 999   [(set_attr "type" "vecperm")])
1000
1001 (define_insn "altivec_vrl<VI_char>"
1002   [(set (match_operand:VI 0 "register_operand" "=v")
1003         (unspec:VI [(match_operand:VI 1 "register_operand" "v")
1004                     (match_operand:VI 2 "register_operand" "v")] 104))]
1005   "TARGET_ALTIVEC"
1006   "vrl<VI_char> %0,%1,%2"
1007   [(set_attr "type" "vecsimple")])
1008
1009 (define_insn "altivec_vsl<VI_char>"
1010   [(set (match_operand:VI 0 "register_operand" "=v")
1011         (unspec:VI [(match_operand:VI 1 "register_operand" "v")
1012                     (match_operand:VI 2 "register_operand" "v")] 107))]
1013   "TARGET_ALTIVEC"
1014   "vsl<VI_char> %0,%1,%2"
1015   [(set_attr "type" "vecsimple")])
1016
1017 (define_insn "altivec_vslw_v4sf"
1018   [(set (match_operand:V4SF 0 "register_operand" "=v")
1019         (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")
1020                       (match_operand:V4SF 2 "register_operand" "v")] UNSPEC_VSLW))]
1021   "TARGET_ALTIVEC"
1022   "vslw %0,%1,%2"
1023   [(set_attr "type" "vecsimple")])
1024
1025 (define_insn "altivec_vsl"
1026   [(set (match_operand:V4SI 0 "register_operand" "=v")
1027         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1028                       (match_operand:V4SI 2 "register_operand" "v")] 110))]
1029   "TARGET_ALTIVEC"
1030   "vsl %0,%1,%2"
1031   [(set_attr "type" "vecperm")])
1032
1033 (define_insn "altivec_vslo"
1034   [(set (match_operand:V4SI 0 "register_operand" "=v")
1035         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1036                       (match_operand:V4SI 2 "register_operand" "v")] 111))]
1037   "TARGET_ALTIVEC"
1038   "vslo %0,%1,%2"
1039   [(set_attr "type" "vecperm")])
1040
1041 (define_insn "lshr<mode>3"
1042   [(set (match_operand:VI 0 "register_operand" "=v")
1043         (lshiftrt:VI (match_operand:VI 1 "register_operand" "v")
1044                     (match_operand:VI 2 "register_operand" "v") ))]
1045   "TARGET_ALTIVEC"
1046   "vsr<VI_char> %0,%1,%2"
1047   [(set_attr "type" "vecsimple")])
1048
1049 (define_insn "ashr<mode>3"
1050   [(set (match_operand:VI 0 "register_operand" "=v")
1051         (ashiftrt:VI (match_operand:VI 1 "register_operand" "v")
1052                     (match_operand:VI 2 "register_operand" "v") ))]
1053   "TARGET_ALTIVEC"
1054   "vsra<VI_char> %0,%1,%2"
1055   [(set_attr "type" "vecsimple")])
1056
1057 (define_insn "altivec_vsr"
1058   [(set (match_operand:V4SI 0 "register_operand" "=v")
1059         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1060                       (match_operand:V4SI 2 "register_operand" "v")] 118))]
1061   "TARGET_ALTIVEC"
1062   "vsr %0,%1,%2"
1063   [(set_attr "type" "vecperm")])
1064
1065 (define_insn "altivec_vsro"
1066   [(set (match_operand:V4SI 0 "register_operand" "=v")
1067         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1068                       (match_operand:V4SI 2 "register_operand" "v")] 119))]
1069   "TARGET_ALTIVEC"
1070   "vsro %0,%1,%2"
1071   [(set_attr "type" "vecperm")])
1072
1073 (define_insn "altivec_vsum4ubs"
1074   [(set (match_operand:V4SI 0 "register_operand" "=v")
1075         (unspec:V4SI [(match_operand:V16QI 1 "register_operand" "v")
1076                       (match_operand:V4SI 2 "register_operand" "v")] 131))
1077    (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
1078   "TARGET_ALTIVEC"
1079   "vsum4ubs %0,%1,%2"
1080   [(set_attr "type" "veccomplex")])
1081
1082 (define_insn "altivec_vsum4s<VI_char>s"
1083   [(set (match_operand:V4SI 0 "register_operand" "=v")
1084         (unspec:V4SI [(match_operand:VIshort 1 "register_operand" "v")
1085                       (match_operand:V4SI 2 "register_operand" "v")] 132))
1086    (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
1087   "TARGET_ALTIVEC"
1088   "vsum4s<VI_char>s %0,%1,%2"
1089   [(set_attr "type" "veccomplex")])
1090
1091 (define_insn "altivec_vsum2sws"
1092   [(set (match_operand:V4SI 0 "register_operand" "=v")
1093         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1094                       (match_operand:V4SI 2 "register_operand" "v")] 134))
1095    (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
1096   "TARGET_ALTIVEC"
1097   "vsum2sws %0,%1,%2"
1098   [(set_attr "type" "veccomplex")])
1099
1100 (define_insn "altivec_vsumsws"
1101   [(set (match_operand:V4SI 0 "register_operand" "=v")
1102         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1103                       (match_operand:V4SI 2 "register_operand" "v")] 135))
1104    (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
1105   "TARGET_ALTIVEC"
1106   "vsumsws %0,%1,%2"
1107   [(set_attr "type" "veccomplex")])
1108
1109 (define_insn "altivec_vspltb"
1110   [(set (match_operand:V16QI 0 "register_operand" "=v")
1111         (vec_duplicate:V16QI
1112          (vec_select:QI (match_operand:V16QI 1 "register_operand" "v")
1113                         (parallel
1114                          [(match_operand:QI 2 "immediate_operand" "i")]))))]
1115   "TARGET_ALTIVEC"
1116   "vspltb %0,%1,%2"
1117   [(set_attr "type" "vecperm")])
1118
1119 (define_insn "altivec_vsplth"
1120   [(set (match_operand:V8HI 0 "register_operand" "=v")
1121         (vec_duplicate:V8HI
1122          (vec_select:HI (match_operand:V8HI 1 "register_operand" "v")
1123                         (parallel
1124                          [(match_operand:QI 2 "immediate_operand" "i")]))))]
1125   "TARGET_ALTIVEC"
1126   "vsplth %0,%1,%2"
1127   [(set_attr "type" "vecperm")])
1128
1129 (define_insn "altivec_vspltw"
1130   [(set (match_operand:V4SI 0 "register_operand" "=v")
1131         (vec_duplicate:V4SI
1132          (vec_select:SI (match_operand:V4SI 1 "register_operand" "v")
1133                         (parallel
1134                          [(match_operand:QI 2 "immediate_operand" "i")]))))]
1135   "TARGET_ALTIVEC"
1136   "vspltw %0,%1,%2"
1137   [(set_attr "type" "vecperm")])
1138
1139 (define_insn "altivec_vspltis<VI_char>"
1140   [(set (match_operand:VI 0 "register_operand" "=v")
1141         (vec_duplicate:VI
1142          (match_operand:QI 1 "const_int_operand" "i")))]
1143   "TARGET_ALTIVEC"
1144   "vspltis<VI_char> %0,%1"
1145   [(set_attr "type" "vecperm")])
1146
1147 (define_insn "altivec_vspltisw_v4sf"
1148   [(set (match_operand:V4SF 0 "register_operand" "=v")
1149         (vec_duplicate:V4SF
1150          (float:SF (match_operand:QI 1 "const_int_operand" "i"))))]
1151   "TARGET_ALTIVEC"
1152   "vspltisw %0,%1"
1153   [(set_attr "type" "vecperm")])
1154
1155 (define_insn "ftruncv4sf2"
1156   [(set (match_operand:V4SF 0 "register_operand" "=v")
1157         (fix:V4SF (match_operand:V4SF 1 "register_operand" "v")))]
1158   "TARGET_ALTIVEC"
1159   "vrfiz %0,%1"
1160   [(set_attr "type" "vecfloat")])
1161
1162 (define_insn "altivec_vperm_v4sf"
1163   [(set (match_operand:V4SF 0 "register_operand" "=v")
1164         (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")
1165                       (match_operand:V4SF 2 "register_operand" "v")
1166                       (match_operand:V16QI 3 "register_operand" "v")] 145))]
1167   "TARGET_ALTIVEC"
1168   "vperm %0,%1,%2,%3"
1169   [(set_attr "type" "vecperm")])
1170
1171 (define_insn "altivec_vperm_<mode>"
1172   [(set (match_operand:VI 0 "register_operand" "=v")
1173         (unspec:VI [(match_operand:VI 1 "register_operand" "v")
1174                     (match_operand:VI 2 "register_operand" "v")
1175                     (match_operand:V16QI 3 "register_operand" "v")] 144))]
1176   "TARGET_ALTIVEC"
1177   "vperm %0,%1,%2,%3"
1178   [(set_attr "type" "vecperm")])
1179
1180 (define_insn "altivec_vrfip"
1181   [(set (match_operand:V4SF 0 "register_operand" "=v")
1182         (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")] 148))]
1183   "TARGET_ALTIVEC"
1184   "vrfip %0,%1"
1185   [(set_attr "type" "vecfloat")])
1186
1187 (define_insn "altivec_vrfin"
1188   [(set (match_operand:V4SF 0 "register_operand" "=v")
1189         (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")] 149))]
1190   "TARGET_ALTIVEC"
1191   "vrfin %0,%1"
1192   [(set_attr "type" "vecfloat")])
1193
1194 (define_insn "altivec_vrfim"
1195   [(set (match_operand:V4SF 0 "register_operand" "=v")
1196         (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")] 150))]
1197   "TARGET_ALTIVEC"
1198   "vrfim %0,%1"
1199   [(set_attr "type" "vecfloat")])
1200
1201 (define_insn "altivec_vcfux"
1202   [(set (match_operand:V4SF 0 "register_operand" "=v")
1203         (unspec:V4SF [(match_operand:V4SI 1 "register_operand" "v")
1204                       (match_operand:QI 2 "immediate_operand" "i")] 151))]
1205   "TARGET_ALTIVEC"
1206   "vcfux %0,%1,%2"
1207   [(set_attr "type" "vecfloat")])
1208
1209 (define_insn "altivec_vcfsx"
1210   [(set (match_operand:V4SF 0 "register_operand" "=v")
1211         (unspec:V4SF [(match_operand:V4SI 1 "register_operand" "v")
1212                       (match_operand:QI 2 "immediate_operand" "i")] 152))]
1213   "TARGET_ALTIVEC"
1214   "vcfsx %0,%1,%2"
1215   [(set_attr "type" "vecfloat")])
1216
1217 (define_insn "altivec_vctuxs"
1218   [(set (match_operand:V4SI 0 "register_operand" "=v")
1219         (unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v")
1220                       (match_operand:QI 2 "immediate_operand" "i")] 153))
1221    (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
1222   "TARGET_ALTIVEC"
1223   "vctuxs %0,%1,%2"
1224   [(set_attr "type" "vecfloat")])
1225
1226 (define_insn "altivec_vctsxs"
1227   [(set (match_operand:V4SI 0 "register_operand" "=v")
1228         (unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v")
1229                       (match_operand:QI 2 "immediate_operand" "i")] 154))
1230    (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
1231   "TARGET_ALTIVEC"
1232   "vctsxs %0,%1,%2"
1233   [(set_attr "type" "vecfloat")])
1234
1235 (define_insn "altivec_vlogefp"
1236   [(set (match_operand:V4SF 0 "register_operand" "=v")
1237         (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")] 155))]
1238   "TARGET_ALTIVEC"
1239   "vlogefp %0,%1"
1240   [(set_attr "type" "vecfloat")])
1241
1242 (define_insn "altivec_vexptefp"
1243   [(set (match_operand:V4SF 0 "register_operand" "=v")
1244         (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")] 156))]
1245   "TARGET_ALTIVEC"
1246   "vexptefp %0,%1"
1247   [(set_attr "type" "vecfloat")])
1248
1249 (define_insn "altivec_vrsqrtefp"
1250   [(set (match_operand:V4SF 0 "register_operand" "=v")
1251         (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")] 157))]
1252   "TARGET_ALTIVEC"
1253   "vrsqrtefp %0,%1"
1254   [(set_attr "type" "vecfloat")])
1255
1256 (define_insn "altivec_vrefp"
1257   [(set (match_operand:V4SF 0 "register_operand" "=v")
1258         (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")] 158))]
1259   "TARGET_ALTIVEC"
1260   "vrefp %0,%1"
1261   [(set_attr "type" "vecfloat")])
1262
1263 (define_expand "vcondv4si"
1264         [(set (match_operand:V4SI 0 "register_operand" "=v")
1265               (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1266                (match_operand:V4SI 2 "register_operand" "v")
1267                (match_operand:V4SI 3 "comparison_operator" "")
1268                (match_operand:V4SI 4 "register_operand" "v")
1269                (match_operand:V4SI 5 "register_operand" "v")
1270                ] UNSPEC_VCOND_V4SI))]
1271         "TARGET_ALTIVEC"
1272         "
1273 {
1274         if (rs6000_emit_vector_cond_expr (operands[0], operands[1], operands[2],
1275                                           operands[3], operands[4], operands[5]))
1276         DONE;
1277         else
1278         FAIL;
1279 }
1280         ")
1281
1282 (define_expand "vconduv4si"
1283         [(set (match_operand:V4SI 0 "register_operand" "=v")
1284               (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1285                (match_operand:V4SI 2 "register_operand" "v")
1286                (match_operand:V4SI 3 "comparison_operator" "")
1287                (match_operand:V4SI 4 "register_operand" "v")
1288                (match_operand:V4SI 5 "register_operand" "v")
1289                ] UNSPEC_VCONDU_V4SI))]
1290         "TARGET_ALTIVEC"
1291         "
1292 {
1293         if (rs6000_emit_vector_cond_expr (operands[0], operands[1], operands[2],
1294                                           operands[3], operands[4], operands[5]))
1295         DONE;
1296         else
1297         FAIL;
1298 }
1299         ")
1300
1301 (define_expand "vcondv4sf"
1302         [(set (match_operand:V4SF 0 "register_operand" "=v")
1303               (unspec:V4SF [(match_operand:V4SI 1 "register_operand" "v")
1304                (match_operand:V4SF 2 "register_operand" "v")
1305                (match_operand:V4SF 3 "comparison_operator" "")
1306                (match_operand:V4SF 4 "register_operand" "v")
1307                (match_operand:V4SF 5 "register_operand" "v")
1308                ] UNSPEC_VCOND_V4SF))]
1309         "TARGET_ALTIVEC"
1310         "
1311 {
1312         if (rs6000_emit_vector_cond_expr (operands[0], operands[1], operands[2],
1313                                           operands[3], operands[4], operands[5]))
1314         DONE;
1315         else
1316         FAIL;
1317 }
1318         ")
1319
1320 (define_expand "vcondv8hi"
1321         [(set (match_operand:V4SF 0 "register_operand" "=v")
1322               (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v")
1323                (match_operand:V8HI 2 "register_operand" "v")
1324                (match_operand:V8HI 3 "comparison_operator" "")
1325                (match_operand:V8HI 4 "register_operand" "v")
1326                (match_operand:V8HI 5 "register_operand" "v")
1327                ] UNSPEC_VCOND_V8HI))]
1328         "TARGET_ALTIVEC"
1329         "
1330 {
1331         if (rs6000_emit_vector_cond_expr (operands[0], operands[1], operands[2],
1332                                           operands[3], operands[4], operands[5]))
1333         DONE;
1334         else
1335         FAIL;
1336 }
1337         ")
1338
1339 (define_expand "vconduv8hi"
1340         [(set (match_operand:V4SF 0 "register_operand" "=v")
1341               (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v")
1342                (match_operand:V8HI 2 "register_operand" "v")
1343                (match_operand:V8HI 3 "comparison_operator" "")
1344                (match_operand:V8HI 4 "register_operand" "v")
1345                (match_operand:V8HI 5 "register_operand" "v")
1346                ] UNSPEC_VCONDU_V8HI))]
1347         "TARGET_ALTIVEC"
1348         "
1349 {
1350         if (rs6000_emit_vector_cond_expr (operands[0], operands[1], operands[2],
1351                                           operands[3], operands[4], operands[5]))
1352         DONE;
1353         else
1354         FAIL;
1355 }
1356         ")
1357
1358 (define_expand "vcondv16qi"
1359         [(set (match_operand:V4SF 0 "register_operand" "=v")
1360               (unspec:V16QI [(match_operand:V4SI 1 "register_operand" "v")
1361                (match_operand:V16QI 2 "register_operand" "v")
1362                (match_operand:V16QI 3 "comparison_operator" "")
1363                (match_operand:V16QI 4 "register_operand" "v")
1364                (match_operand:V16QI 5 "register_operand" "v")
1365                ] UNSPEC_VCOND_V16QI))]
1366         "TARGET_ALTIVEC"
1367         "
1368 {
1369         if (rs6000_emit_vector_cond_expr (operands[0], operands[1], operands[2],
1370                                           operands[3], operands[4], operands[5]))
1371         DONE;
1372         else
1373         FAIL;
1374 }
1375         ")
1376
1377 (define_expand "vconduv16qi"
1378         [(set (match_operand:V4SF 0 "register_operand" "=v")
1379               (unspec:V16QI [(match_operand:V4SI 1 "register_operand" "v")
1380                (match_operand:V16QI 2 "register_operand" "v")
1381                (match_operand:V16QI 3 "comparison_operator" "")
1382                (match_operand:V16QI 4 "register_operand" "v")
1383                (match_operand:V16QI 5 "register_operand" "v")
1384                ] UNSPEC_VCONDU_V16QI))]
1385         "TARGET_ALTIVEC"
1386         "
1387 {
1388         if (rs6000_emit_vector_cond_expr (operands[0], operands[1], operands[2],
1389                                           operands[3], operands[4], operands[5]))
1390         DONE;
1391         else
1392         FAIL;
1393 }
1394         ")
1395
1396
1397 (define_insn "altivec_vsel_v4si"
1398   [(set (match_operand:V4SI 0 "register_operand" "=v")
1399         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1400                       (match_operand:V4SI 2 "register_operand" "v")
1401                       (match_operand:V4SI 3 "register_operand" "v")]
1402                       UNSPEC_VSEL4SI))]
1403   "TARGET_ALTIVEC"
1404   "vsel %0,%1,%2,%3"
1405   [(set_attr "type" "vecperm")])
1406
1407 (define_insn "altivec_vsel_v4sf"
1408   [(set (match_operand:V4SF 0 "register_operand" "=v")
1409         (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")
1410                       (match_operand:V4SF 2 "register_operand" "v")
1411                       (match_operand:V4SI 3 "register_operand" "v")]
1412                       UNSPEC_VSEL4SF))]
1413   "TARGET_ALTIVEC"
1414   "vsel %0,%1,%2,%3"
1415   [(set_attr "type" "vecperm")])
1416
1417 (define_insn "altivec_vsel_v8hi"
1418   [(set (match_operand:V8HI 0 "register_operand" "=v")
1419         (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
1420                       (match_operand:V8HI 2 "register_operand" "v")
1421                       (match_operand:V8HI 3 "register_operand" "v")]
1422                       UNSPEC_VSEL8HI))]
1423   "TARGET_ALTIVEC"
1424   "vsel %0,%1,%2,%3"
1425   [(set_attr "type" "vecperm")])
1426
1427 (define_insn "altivec_vsel_v16qi"
1428   [(set (match_operand:V16QI 0 "register_operand" "=v")
1429         (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
1430                        (match_operand:V16QI 2 "register_operand" "v")
1431                        (match_operand:V16QI 3 "register_operand" "v")]
1432                        UNSPEC_VSEL16QI))]
1433   "TARGET_ALTIVEC"
1434   "vsel %0,%1,%2,%3"
1435   [(set_attr "type" "vecperm")])
1436
1437 (define_insn "altivec_vsldoi_v4si"
1438   [(set (match_operand:V4SI 0 "register_operand" "=v")
1439         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1440                       (match_operand:V4SI 2 "register_operand" "v")
1441                       (match_operand:QI 3 "immediate_operand" "i")] 163))]
1442   "TARGET_ALTIVEC"
1443   "vsldoi %0,%1,%2,%3"
1444   [(set_attr "type" "vecperm")])
1445
1446 (define_insn "altivec_vsldoi_v4sf"
1447   [(set (match_operand:V4SF 0 "register_operand" "=v")
1448         (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")
1449                       (match_operand:V4SF 2 "register_operand" "v")
1450                       (match_operand:QI 3 "immediate_operand" "i")] 164))]
1451   "TARGET_ALTIVEC"
1452   "vsldoi %0,%1,%2,%3"
1453   [(set_attr "type" "vecperm")])
1454
1455 (define_insn "altivec_vsldoi_v8hi"
1456   [(set (match_operand:V8HI 0 "register_operand" "=v")
1457         (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
1458                       (match_operand:V8HI 2 "register_operand" "v")
1459                       (match_operand:QI 3 "immediate_operand" "i")] 165))]
1460   "TARGET_ALTIVEC"
1461   "vsldoi %0,%1,%2,%3"
1462   [(set_attr "type" "vecperm")])
1463
1464 (define_insn "altivec_vsldoi_v16qi"
1465   [(set (match_operand:V16QI 0 "register_operand" "=v")
1466         (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
1467                        (match_operand:V16QI 2 "register_operand" "v")
1468                        (match_operand:QI 3 "immediate_operand" "i")] 166))]
1469   "TARGET_ALTIVEC"
1470   "vsldoi %0,%1,%2,%3"
1471   [(set_attr "type" "vecperm")])
1472
1473 (define_insn "altivec_vupkhsb"
1474   [(set (match_operand:V8HI 0 "register_operand" "=v")
1475         (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")] 167))]
1476   "TARGET_ALTIVEC"
1477   "vupkhsb %0,%1"
1478   [(set_attr "type" "vecperm")])
1479
1480 (define_insn "altivec_vupkhpx"
1481   [(set (match_operand:V4SI 0 "register_operand" "=v")
1482         (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")] 168))]
1483   "TARGET_ALTIVEC"
1484   "vupkhpx %0,%1"
1485   [(set_attr "type" "vecperm")])
1486
1487 (define_insn "altivec_vupkhsh"
1488   [(set (match_operand:V4SI 0 "register_operand" "=v")
1489         (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")] 169))]
1490   "TARGET_ALTIVEC"
1491   "vupkhsh %0,%1"
1492   [(set_attr "type" "vecperm")])
1493
1494 (define_insn "altivec_vupklsb"
1495   [(set (match_operand:V8HI 0 "register_operand" "=v")
1496         (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")] 170))]
1497   "TARGET_ALTIVEC"
1498   "vupklsb %0,%1"
1499   [(set_attr "type" "vecperm")])
1500
1501 (define_insn "altivec_vupklpx"
1502   [(set (match_operand:V4SI 0 "register_operand" "=v")
1503         (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")] 171))]
1504   "TARGET_ALTIVEC"
1505   "vupklpx %0,%1"
1506   [(set_attr "type" "vecperm")])
1507
1508 (define_insn "altivec_vupklsh"
1509   [(set (match_operand:V4SI 0 "register_operand" "=v")
1510         (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")] 172))]
1511   "TARGET_ALTIVEC"
1512   "vupklsh %0,%1"
1513   [(set_attr "type" "vecperm")])
1514
1515 ;; AltiVec predicates.
1516
1517 (define_expand "cr6_test_for_zero"
1518   [(set (match_operand:SI 0 "register_operand" "=r")
1519         (eq:SI (reg:CC 74)
1520                (const_int 0)))]
1521   "TARGET_ALTIVEC"
1522   "")
1523
1524 (define_expand "cr6_test_for_zero_reverse"
1525   [(set (match_operand:SI 0 "register_operand" "=r")
1526         (eq:SI (reg:CC 74)
1527                (const_int 0)))
1528    (set (match_dup 0) (minus:SI (const_int 1) (match_dup 0)))]
1529   "TARGET_ALTIVEC"
1530   "")
1531
1532 (define_expand "cr6_test_for_lt"
1533   [(set (match_operand:SI 0 "register_operand" "=r")
1534         (lt:SI (reg:CC 74)
1535                (const_int 0)))]
1536   "TARGET_ALTIVEC"
1537   "")
1538
1539 (define_expand "cr6_test_for_lt_reverse"
1540   [(set (match_operand:SI 0 "register_operand" "=r")
1541         (lt:SI (reg:CC 74)
1542                (const_int 0)))
1543    (set (match_dup 0) (minus:SI (const_int 1) (match_dup 0)))]
1544   "TARGET_ALTIVEC"
1545   "")
1546
1547 ;; We can get away with generating the opcode on the fly (%3 below)
1548 ;; because all the predicates have the same scheduling parameters.
1549
1550 (define_insn "altivec_predicate_v4sf"
1551   [(set (reg:CC 74)
1552         (unspec:CC [(match_operand:V4SF 1 "register_operand" "v")
1553                     (match_operand:V4SF 2 "register_operand" "v")
1554                     (match_operand 3 "any_operand" "")] 174))
1555    (clobber (match_scratch:V4SF 0 "=v"))]
1556   "TARGET_ALTIVEC"
1557   "%3 %0,%1,%2"
1558 [(set_attr "type" "veccmp")])
1559
1560 (define_insn "altivec_predicate_<mode>"
1561   [(set (reg:CC 74)
1562         (unspec:CC [(match_operand:VI 1 "register_operand" "v")
1563                     (match_operand:VI 2 "register_operand" "v")
1564                     (match_operand 3 "any_operand" "")] 173))
1565    (clobber (match_scratch:VI 0 "=v"))]
1566   "TARGET_ALTIVEC"
1567   "%3 %0,%1,%2"
1568 [(set_attr "type" "veccmp")])
1569
1570 (define_insn "altivec_mtvscr"
1571   [(set (reg:SI 110)
1572         (unspec_volatile:SI
1573          [(match_operand:V4SI 0 "register_operand" "v")] 186))]
1574   "TARGET_ALTIVEC"
1575   "mtvscr %0"
1576   [(set_attr "type" "vecsimple")])
1577
1578 (define_insn "altivec_mfvscr"
1579   [(set (match_operand:V8HI 0 "register_operand" "=v")
1580         (unspec_volatile:V8HI [(reg:SI 110)] 187))]
1581   "TARGET_ALTIVEC"
1582   "mfvscr %0"
1583   [(set_attr "type" "vecsimple")])
1584
1585 (define_insn "altivec_dssall"
1586   [(unspec_volatile [(const_int 0)] 188)]
1587   "TARGET_ALTIVEC"
1588   "dssall"
1589   [(set_attr "type" "vecsimple")])
1590
1591 (define_insn "altivec_dss"
1592   [(unspec_volatile [(match_operand:QI 0 "immediate_operand" "i")] 189)]
1593   "TARGET_ALTIVEC"
1594   "dss %0"
1595   [(set_attr "type" "vecsimple")])
1596
1597 (define_insn "altivec_dst"
1598   [(unspec [(match_operand 0 "register_operand" "b")
1599             (match_operand:SI 1 "register_operand" "r")
1600             (match_operand:QI 2 "immediate_operand" "i")] 190)]
1601   "TARGET_ALTIVEC && GET_MODE (operands[0]) == Pmode"
1602   "dst %0,%1,%2"
1603   [(set_attr "type" "vecsimple")])
1604
1605 (define_insn "altivec_dstt"
1606   [(unspec [(match_operand 0 "register_operand" "b")
1607             (match_operand:SI 1 "register_operand" "r")
1608             (match_operand:QI 2 "immediate_operand" "i")] 191)]
1609   "TARGET_ALTIVEC && GET_MODE (operands[0]) == Pmode"
1610   "dstt %0,%1,%2"
1611   [(set_attr "type" "vecsimple")])
1612
1613 (define_insn "altivec_dstst"
1614   [(unspec [(match_operand 0 "register_operand" "b")
1615             (match_operand:SI 1 "register_operand" "r")
1616             (match_operand:QI 2 "immediate_operand" "i")] 192)]
1617   "TARGET_ALTIVEC && GET_MODE (operands[0]) == Pmode"
1618   "dstst %0,%1,%2"
1619   [(set_attr "type" "vecsimple")])
1620
1621 (define_insn "altivec_dststt"
1622   [(unspec [(match_operand 0 "register_operand" "b")
1623             (match_operand:SI 1 "register_operand" "r")
1624             (match_operand:QI 2 "immediate_operand" "i")] 193)]
1625   "TARGET_ALTIVEC && GET_MODE (operands[0]) == Pmode"
1626   "dststt %0,%1,%2"
1627   [(set_attr "type" "vecsimple")])
1628
1629 (define_insn "altivec_lvsl"
1630   [(set (match_operand:V16QI 0 "register_operand" "=v")
1631         (unspec:V16QI [(match_operand 1 "memory_operand" "m")] 194))]
1632   "TARGET_ALTIVEC"
1633   "lvsl %0,%y1"
1634   [(set_attr "type" "vecload")])
1635
1636 (define_insn "altivec_lvsr"
1637   [(set (match_operand:V16QI 0 "register_operand" "=v")
1638         (unspec:V16QI [(match_operand 1 "memory_operand" "m")] 195))]
1639   "TARGET_ALTIVEC"
1640   "lvsr %0,%y1"
1641   [(set_attr "type" "vecload")])
1642
1643 (define_expand "build_vector_mask_for_load"
1644   [(set (match_operand:V16QI 0 "register_operand" "=v")
1645         (unspec:V16QI [(match_operand 1 "memory_operand" "m")] 195))]
1646   "TARGET_ALTIVEC"
1647   "
1648 {
1649   rtx addr;
1650   rtx temp;
1651
1652   gcc_assert (GET_CODE (operands[1]) == MEM);
1653
1654   addr = XEXP (operands[1], 0);
1655   temp = gen_reg_rtx (GET_MODE (addr));
1656   emit_insn (gen_rtx_SET (VOIDmode, temp,
1657                           gen_rtx_NEG (GET_MODE (addr), addr)));
1658   emit_insn (gen_altivec_lvsr (operands[0],
1659                                gen_rtx_MEM (GET_MODE (operands[1]), temp)));
1660   DONE;
1661 }")
1662
1663 ;; Parallel some of the LVE* and STV*'s with unspecs because some have
1664 ;; identical rtl but different instructions-- and gcc gets confused.
1665
1666 (define_insn "altivec_lve<VI_char>x"
1667   [(parallel
1668     [(set (match_operand:VI 0 "register_operand" "=v")
1669           (match_operand:VI 1 "memory_operand" "m"))
1670      (unspec [(const_int 0)] 196)])]
1671   "TARGET_ALTIVEC"
1672   "lve<VI_char>x %0,%y1"
1673   [(set_attr "type" "vecload")])
1674
1675 (define_insn "altivec_lvxl"
1676   [(parallel
1677     [(set (match_operand:V4SI 0 "register_operand" "=v")
1678           (match_operand:V4SI 1 "memory_operand" "m"))
1679      (unspec [(const_int 0)] UNSPEC_SET_VSCR)])]
1680   "TARGET_ALTIVEC"
1681   "lvxl %0,%y1"
1682   [(set_attr "type" "vecload")])
1683
1684 (define_insn "altivec_lvx"
1685   [(set (match_operand:V4SI 0 "register_operand" "=v")
1686         (match_operand:V4SI 1 "memory_operand" "m"))]
1687   "TARGET_ALTIVEC"
1688   "lvx %0,%y1"
1689   [(set_attr "type" "vecload")])
1690
1691 (define_insn "altivec_stvx"
1692   [(parallel
1693     [(set (match_operand:V4SI 0 "memory_operand" "=m")
1694           (match_operand:V4SI 1 "register_operand" "v"))
1695      (unspec [(const_int 0)] 201)])]
1696   "TARGET_ALTIVEC"
1697   "stvx %1,%y0"
1698   [(set_attr "type" "vecstore")])
1699
1700 (define_insn "altivec_stvxl"
1701   [(parallel
1702     [(set (match_operand:V4SI 0 "memory_operand" "=m")
1703           (match_operand:V4SI 1 "register_operand" "v"))
1704      (unspec [(const_int 0)] 202)])]
1705   "TARGET_ALTIVEC"
1706   "stvxl %1,%y0"
1707   [(set_attr "type" "vecstore")])
1708
1709 (define_insn "altivec_stve<VI_char>x"
1710   [(parallel
1711     [(set (match_operand:VI 0 "memory_operand" "=m")
1712           (match_operand:VI 1 "register_operand" "v"))
1713      (unspec [(const_int 0)] 203)])]
1714   "TARGET_ALTIVEC"
1715   "stve<VI_char>x %1,%y0"
1716   [(set_attr "type" "vecstore")])
1717
1718 ;; Generate
1719 ;;    vspltis? SCRATCH0,0
1720 ;;    vsubu?m SCRATCH2,SCRATCH1,%1
1721 ;;    vmaxs? %0,%1,SCRATCH2"
1722 (define_expand "abs<mode>2"
1723   [(set (match_dup 2) (vec_duplicate:VI (const_int 0)))
1724    (set (match_dup 3)
1725         (minus:VI (match_dup 2)
1726                   (match_operand:VI 1 "register_operand" "v")))
1727    (set (match_operand:VI 0 "register_operand" "=v")
1728         (smax:VI (match_dup 1) (match_dup 3)))]
1729   "TARGET_ALTIVEC"
1730 {
1731   operands[2] = gen_reg_rtx (GET_MODE (operands[0]));
1732   operands[3] = gen_reg_rtx (GET_MODE (operands[0]));
1733 })
1734
1735 ;; Generate
1736 ;;    vspltisw SCRATCH1,-1
1737 ;;    vslw SCRATCH2,SCRATCH1,SCRATCH1
1738 ;;    vandc %0,%1,SCRATCH2
1739 (define_expand "absv4sf2"
1740   [(set (match_dup 2)
1741         (vec_duplicate:V4SF (float:SF (const_int -1))))
1742    (set (match_dup 3)
1743         (unspec:V4SF [(match_dup 2) (match_dup 2)] UNSPEC_VSLW))
1744    (set (match_operand:V4SF 0 "register_operand" "=v")
1745         (and:V4SF (not:V4SF (match_dup 3))
1746                   (match_operand:V4SF 1 "register_operand" "v")))]
1747   "TARGET_ALTIVEC"
1748 {
1749   operands[2] = gen_reg_rtx (V4SFmode);
1750   operands[3] = gen_reg_rtx (V4SFmode);
1751 })
1752
1753 ;; Generate
1754 ;;    vspltis? SCRATCH0,0
1755 ;;    vsubs?s SCRATCH2,SCRATCH1,%1
1756 ;;    vmaxs? %0,%1,SCRATCH2"
1757 (define_expand "altivec_abss_<mode>"
1758   [(set (match_dup 2) (vec_duplicate:VI (const_int 0)))
1759    (parallel [(set (match_dup 3)
1760                    (unspec:VI [(match_dup 2)
1761                                (match_operand:VI 1 "register_operand" "v")]
1762                               UNSPEC_SUBS))
1763               (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))])
1764    (set (match_operand:VI 0 "register_operand" "=v")
1765         (smax:VI (match_dup 1) (match_dup 3)))]
1766   "TARGET_ALTIVEC"
1767 {
1768   operands[2] = gen_reg_rtx (GET_MODE (operands[0]));
1769   operands[3] = gen_reg_rtx (GET_MODE (operands[0]));
1770 })
1771
1772 (define_insn "vec_realign_load_v4sf"
1773   [(set (match_operand:V4SF 0 "register_operand" "=v")
1774         (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")
1775                       (match_operand:V4SF 2 "register_operand" "v")
1776                       (match_operand:V16QI 3 "register_operand" "v")] 216))]
1777   "TARGET_ALTIVEC"
1778   "vperm %0,%1,%2,%3"
1779   [(set_attr "type" "vecperm")])
1780
1781 (define_insn "vec_realign_load_<mode>"
1782   [(set (match_operand:VI 0 "register_operand" "=v")
1783         (unspec:VI [(match_operand:VI 1 "register_operand" "v")
1784                     (match_operand:VI 2 "register_operand" "v")
1785                     (match_operand:V16QI 3 "register_operand" "v")] 215))]
1786   "TARGET_ALTIVEC"
1787   "vperm %0,%1,%2,%3"
1788   [(set_attr "type" "vecperm")])