1 /* Subroutines for insn-output.c for Matsushita MN10300 series
2 Copyright (C) 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004,
3 2005, 2006, 2007, 2008, 2009 Free Software Foundation, Inc.
4 Contributed by Jeff Law (law@cygnus.com).
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
24 #include "coretypes.h"
29 #include "hard-reg-set.h"
31 #include "insn-config.h"
32 #include "conditions.h"
34 #include "insn-attr.h"
45 #include "target-def.h"
47 /* This is used by GOTaddr2picreg to uniquely identify
49 int mn10300_unspec_int_label_counter;
51 /* This is used in the am33_2.0-linux-gnu port, in which global symbol
52 names are not prefixed by underscores, to tell whether to prefix a
53 label with a plus sign or not, so that the assembler can tell
54 symbol names from register names. */
55 int mn10300_protect_label;
57 /* The selected processor. */
58 enum processor_type mn10300_processor = PROCESSOR_DEFAULT;
60 /* The size of the callee register save area. Right now we save everything
61 on entry since it costs us nothing in code size. It does cost us from a
62 speed standpoint, so we want to optimize this sooner or later. */
63 #define REG_SAVE_BYTES (4 * df_regs_ever_live_p (2) \
64 + 4 * df_regs_ever_live_p (3) \
65 + 4 * df_regs_ever_live_p (6) \
66 + 4 * df_regs_ever_live_p (7) \
67 + 16 * (df_regs_ever_live_p (14) || df_regs_ever_live_p (15) \
68 || df_regs_ever_live_p (16) || df_regs_ever_live_p (17)))
71 static bool mn10300_handle_option (size_t, const char *, int);
72 static bool mn10300_legitimate_address_p (enum machine_mode, rtx, bool);
73 static int mn10300_address_cost_1 (rtx, int *);
74 static int mn10300_address_cost (rtx, bool);
75 static bool mn10300_rtx_costs (rtx, int, int, int *, bool);
76 static void mn10300_file_start (void);
77 static bool mn10300_return_in_memory (const_tree, const_tree);
78 static rtx mn10300_builtin_saveregs (void);
79 static void mn10300_va_start (tree, rtx);
80 static rtx mn10300_legitimize_address (rtx, rtx, enum machine_mode);
81 static bool mn10300_pass_by_reference (CUMULATIVE_ARGS *, enum machine_mode,
83 static int mn10300_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode,
85 static unsigned int mn10300_case_values_threshold (void);
86 static void mn10300_encode_section_info (tree, rtx, int);
87 static void mn10300_asm_trampoline_template (FILE *);
88 static void mn10300_trampoline_init (rtx, tree, rtx);
89 static rtx mn10300_function_value (const_tree, const_tree, bool);
90 static rtx mn10300_libcall_value (enum machine_mode, const_rtx);
92 /* Initialize the GCC target structure. */
93 #undef TARGET_ASM_ALIGNED_HI_OP
94 #define TARGET_ASM_ALIGNED_HI_OP "\t.hword\t"
96 #undef TARGET_LEGITIMIZE_ADDRESS
97 #define TARGET_LEGITIMIZE_ADDRESS mn10300_legitimize_address
99 #undef TARGET_RTX_COSTS
100 #define TARGET_RTX_COSTS mn10300_rtx_costs
101 #undef TARGET_ADDRESS_COST
102 #define TARGET_ADDRESS_COST mn10300_address_cost
104 #undef TARGET_ASM_FILE_START
105 #define TARGET_ASM_FILE_START mn10300_file_start
106 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
107 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
109 #undef TARGET_DEFAULT_TARGET_FLAGS
110 #define TARGET_DEFAULT_TARGET_FLAGS MASK_MULT_BUG | MASK_PTR_A0D0
111 #undef TARGET_HANDLE_OPTION
112 #define TARGET_HANDLE_OPTION mn10300_handle_option
114 #undef TARGET_ENCODE_SECTION_INFO
115 #define TARGET_ENCODE_SECTION_INFO mn10300_encode_section_info
117 #undef TARGET_PROMOTE_PROTOTYPES
118 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
119 #undef TARGET_RETURN_IN_MEMORY
120 #define TARGET_RETURN_IN_MEMORY mn10300_return_in_memory
121 #undef TARGET_PASS_BY_REFERENCE
122 #define TARGET_PASS_BY_REFERENCE mn10300_pass_by_reference
123 #undef TARGET_CALLEE_COPIES
124 #define TARGET_CALLEE_COPIES hook_bool_CUMULATIVE_ARGS_mode_tree_bool_true
125 #undef TARGET_ARG_PARTIAL_BYTES
126 #define TARGET_ARG_PARTIAL_BYTES mn10300_arg_partial_bytes
128 #undef TARGET_EXPAND_BUILTIN_SAVEREGS
129 #define TARGET_EXPAND_BUILTIN_SAVEREGS mn10300_builtin_saveregs
130 #undef TARGET_EXPAND_BUILTIN_VA_START
131 #define TARGET_EXPAND_BUILTIN_VA_START mn10300_va_start
133 #undef TARGET_CASE_VALUES_THRESHOLD
134 #define TARGET_CASE_VALUES_THRESHOLD mn10300_case_values_threshold
136 #undef TARGET_LEGITIMATE_ADDRESS_P
137 #define TARGET_LEGITIMATE_ADDRESS_P mn10300_legitimate_address_p
139 #undef TARGET_ASM_TRAMPOLINE_TEMPLATE
140 #define TARGET_ASM_TRAMPOLINE_TEMPLATE mn10300_asm_trampoline_template
141 #undef TARGET_TRAMPOLINE_INIT
142 #define TARGET_TRAMPOLINE_INIT mn10300_trampoline_init
144 #undef TARGET_FUNCTION_VALUE
145 #define TARGET_FUNCTION_VALUE mn10300_function_value
146 #undef TARGET_LIBCALL_VALUE
147 #define TARGET_LIBCALL_VALUE mn10300_libcall_value
149 struct gcc_target targetm = TARGET_INITIALIZER;
151 /* Implement TARGET_HANDLE_OPTION. */
154 mn10300_handle_option (size_t code,
155 const char *arg ATTRIBUTE_UNUSED,
161 mn10300_processor = value ? PROCESSOR_AM33 : PROCESSOR_MN10300;
164 mn10300_processor = (value
166 : MIN (PROCESSOR_AM33, PROCESSOR_DEFAULT));
173 /* Implement OVERRIDE_OPTIONS. */
176 mn10300_override_options (void)
179 target_flags &= ~MASK_MULT_BUG;
183 mn10300_file_start (void)
185 default_file_start ();
188 fprintf (asm_out_file, "\t.am33_2\n");
189 else if (TARGET_AM33)
190 fprintf (asm_out_file, "\t.am33\n");
194 /* Print operand X using operand code CODE to assembly language output file
198 print_operand (FILE *file, rtx x, int code)
204 if (cc_status.mdep.fpCC)
206 switch (code == 'b' ? GET_CODE (x)
207 : reverse_condition_maybe_unordered (GET_CODE (x)))
210 fprintf (file, "ne");
213 fprintf (file, "eq");
216 fprintf (file, "ge");
219 fprintf (file, "gt");
222 fprintf (file, "le");
225 fprintf (file, "lt");
228 fprintf (file, "lge");
231 fprintf (file, "uo");
234 fprintf (file, "lg");
237 fprintf (file, "ue");
240 fprintf (file, "uge");
243 fprintf (file, "ug");
246 fprintf (file, "ule");
249 fprintf (file, "ul");
256 /* These are normal and reversed branches. */
257 switch (code == 'b' ? GET_CODE (x) : reverse_condition (GET_CODE (x)))
260 fprintf (file, "ne");
263 fprintf (file, "eq");
266 fprintf (file, "ge");
269 fprintf (file, "gt");
272 fprintf (file, "le");
275 fprintf (file, "lt");
278 fprintf (file, "cc");
281 fprintf (file, "hi");
284 fprintf (file, "ls");
287 fprintf (file, "cs");
294 /* This is used for the operand to a call instruction;
295 if it's a REG, enclose it in parens, else output
296 the operand normally. */
297 if (GET_CODE (x) == REG)
300 print_operand (file, x, 0);
304 print_operand (file, x, 0);
308 switch (GET_CODE (x))
312 output_address (XEXP (x, 0));
317 fprintf (file, "fd%d", REGNO (x) - 18);
325 /* These are the least significant word in a 64bit value. */
327 switch (GET_CODE (x))
331 output_address (XEXP (x, 0));
336 fprintf (file, "%s", reg_names[REGNO (x)]);
340 fprintf (file, "%s", reg_names[subreg_regno (x)]);
348 switch (GET_MODE (x))
351 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
352 REAL_VALUE_TO_TARGET_DOUBLE (rv, val);
353 fprintf (file, "0x%lx", val[0]);
356 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
357 REAL_VALUE_TO_TARGET_SINGLE (rv, val[0]);
358 fprintf (file, "0x%lx", val[0]);
362 print_operand_address (file,
363 GEN_INT (CONST_DOUBLE_LOW (x)));
374 split_double (x, &low, &high);
375 fprintf (file, "%ld", (long)INTVAL (low));
384 /* Similarly, but for the most significant word. */
386 switch (GET_CODE (x))
390 x = adjust_address (x, SImode, 4);
391 output_address (XEXP (x, 0));
396 fprintf (file, "%s", reg_names[REGNO (x) + 1]);
400 fprintf (file, "%s", reg_names[subreg_regno (x) + 1]);
408 switch (GET_MODE (x))
411 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
412 REAL_VALUE_TO_TARGET_DOUBLE (rv, val);
413 fprintf (file, "0x%lx", val[1]);
419 print_operand_address (file,
420 GEN_INT (CONST_DOUBLE_HIGH (x)));
431 split_double (x, &low, &high);
432 fprintf (file, "%ld", (long)INTVAL (high));
443 if (GET_CODE (XEXP (x, 0)) == REG)
444 output_address (gen_rtx_PLUS (SImode, XEXP (x, 0), const0_rtx));
446 output_address (XEXP (x, 0));
451 gcc_assert (INTVAL (x) >= -128 && INTVAL (x) <= 255);
452 fprintf (file, "%d", (int)((~INTVAL (x)) & 0xff));
456 gcc_assert (INTVAL (x) >= -128 && INTVAL (x) <= 255);
457 fprintf (file, "%d", (int)(INTVAL (x) & 0xff));
460 /* For shift counts. The hardware ignores the upper bits of
461 any immediate, but the assembler will flag an out of range
462 shift count as an error. So we mask off the high bits
463 of the immediate here. */
465 if (GET_CODE (x) == CONST_INT)
467 fprintf (file, "%d", (int)(INTVAL (x) & 0x1f));
473 switch (GET_CODE (x))
477 output_address (XEXP (x, 0));
486 fprintf (file, "%s", reg_names[REGNO (x)]);
490 fprintf (file, "%s", reg_names[subreg_regno (x)]);
493 /* This will only be single precision.... */
499 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
500 REAL_VALUE_TO_TARGET_SINGLE (rv, val);
501 fprintf (file, "0x%lx", val);
511 print_operand_address (file, x);
520 /* Output assembly language output for the address ADDR to FILE. */
523 print_operand_address (FILE *file, rtx addr)
525 switch (GET_CODE (addr))
528 print_operand_address (file, XEXP (addr, 0));
532 print_operand (file, addr, 0);
537 if (REG_P (XEXP (addr, 0))
538 && REG_OK_FOR_BASE_P (XEXP (addr, 0)))
539 base = XEXP (addr, 0), index = XEXP (addr, 1);
540 else if (REG_P (XEXP (addr, 1))
541 && REG_OK_FOR_BASE_P (XEXP (addr, 1)))
542 base = XEXP (addr, 1), index = XEXP (addr, 0);
545 print_operand (file, index, 0);
547 print_operand (file, base, 0);;
551 output_addr_const (file, addr);
554 output_addr_const (file, addr);
559 /* Count the number of FP registers that have to be saved. */
561 fp_regs_to_save (void)
568 for (i = FIRST_FP_REGNUM; i <= LAST_FP_REGNUM; ++i)
569 if (df_regs_ever_live_p (i) && ! call_really_used_regs[i])
575 /* Print a set of registers in the format required by "movm" and "ret".
576 Register K is saved if bit K of MASK is set. The data and address
577 registers can be stored individually, but the extended registers cannot.
578 We assume that the mask already takes that into account. For instance,
579 bits 14 to 17 must have the same value. */
582 mn10300_print_reg_list (FILE *file, int mask)
590 for (i = 0; i < FIRST_EXTENDED_REGNUM; i++)
591 if ((mask & (1 << i)) != 0)
595 fputs (reg_names [i], file);
599 if ((mask & 0x3c000) != 0)
601 gcc_assert ((mask & 0x3c000) == 0x3c000);
604 fputs ("exreg1", file);
612 can_use_return_insn (void)
614 /* size includes the fixed stack space needed for function calls. */
615 int size = get_frame_size () + crtl->outgoing_args_size;
617 /* And space for the return pointer. */
618 size += crtl->outgoing_args_size ? 4 : 0;
620 return (reload_completed
622 && !df_regs_ever_live_p (2)
623 && !df_regs_ever_live_p (3)
624 && !df_regs_ever_live_p (6)
625 && !df_regs_ever_live_p (7)
626 && !df_regs_ever_live_p (14)
627 && !df_regs_ever_live_p (15)
628 && !df_regs_ever_live_p (16)
629 && !df_regs_ever_live_p (17)
630 && fp_regs_to_save () == 0
631 && !frame_pointer_needed);
634 /* Returns the set of live, callee-saved registers as a bitmask. The
635 callee-saved extended registers cannot be stored individually, so
636 all of them will be included in the mask if any one of them is used. */
639 mn10300_get_live_callee_saved_regs (void)
645 for (i = 0; i <= LAST_EXTENDED_REGNUM; i++)
646 if (df_regs_ever_live_p (i) && ! call_really_used_regs[i])
648 if ((mask & 0x3c000) != 0)
654 /* Generate an instruction that pushes several registers onto the stack.
655 Register K will be saved if bit K in MASK is set. The function does
656 nothing if MASK is zero.
658 To be compatible with the "movm" instruction, the lowest-numbered
659 register must be stored in the lowest slot. If MASK is the set
660 { R1,...,RN }, where R1...RN are ordered least first, the generated
661 instruction will have the form:
664 (set (reg:SI 9) (plus:SI (reg:SI 9) (const_int -N*4)))
665 (set (mem:SI (plus:SI (reg:SI 9)
669 (set (mem:SI (plus:SI (reg:SI 9)
674 mn10300_gen_multiple_store (int mask)
683 /* Count how many registers need to be saved. */
685 for (i = 0; i <= LAST_EXTENDED_REGNUM; i++)
686 if ((mask & (1 << i)) != 0)
689 /* We need one PARALLEL element to update the stack pointer and
690 an additional element for each register that is stored. */
691 par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count + 1));
693 /* Create the instruction that updates the stack pointer. */
695 = gen_rtx_SET (SImode,
697 gen_rtx_PLUS (SImode,
699 GEN_INT (-count * 4)));
701 /* Create each store. */
703 for (i = LAST_EXTENDED_REGNUM; i >= 0; i--)
704 if ((mask & (1 << i)) != 0)
706 rtx address = gen_rtx_PLUS (SImode,
708 GEN_INT (-pari * 4));
709 XVECEXP(par, 0, pari)
710 = gen_rtx_SET (VOIDmode,
711 gen_rtx_MEM (SImode, address),
712 gen_rtx_REG (SImode, i));
716 par = emit_insn (par);
717 RTX_FRAME_RELATED_P (par) = 1;
722 expand_prologue (void)
726 /* SIZE includes the fixed stack space needed for function calls. */
727 size = get_frame_size () + crtl->outgoing_args_size;
728 size += (crtl->outgoing_args_size ? 4 : 0);
730 /* If we use any of the callee-saved registers, save them now. */
731 mn10300_gen_multiple_store (mn10300_get_live_callee_saved_regs ());
733 if (TARGET_AM33_2 && fp_regs_to_save ())
735 int num_regs_to_save = fp_regs_to_save (), i;
737 enum { save_sp_merge,
739 save_sp_partial_merge,
741 save_a0_no_merge } strategy;
742 unsigned int strategy_size = (unsigned)-1, this_strategy_size;
746 /* We have several different strategies to save FP registers.
747 We can store them using SP offsets, which is beneficial if
748 there are just a few registers to save, or we can use `a0' in
749 post-increment mode (`a0' is the only call-clobbered address
750 register that is never used to pass information to a
751 function). Furthermore, if we don't need a frame pointer, we
752 can merge the two SP adds into a single one, but this isn't
753 always beneficial; sometimes we can just split the two adds
754 so that we don't exceed a 16-bit constant size. The code
755 below will select which strategy to use, so as to generate
756 smallest code. Ties are broken in favor or shorter sequences
757 (in terms of number of instructions). */
759 #define SIZE_ADD_AX(S) ((((S) >= (1 << 15)) || ((S) < -(1 << 15))) ? 6 \
760 : (((S) >= (1 << 7)) || ((S) < -(1 << 7))) ? 4 : 2)
761 #define SIZE_ADD_SP(S) ((((S) >= (1 << 15)) || ((S) < -(1 << 15))) ? 6 \
762 : (((S) >= (1 << 7)) || ((S) < -(1 << 7))) ? 4 : 3)
763 #define SIZE_FMOV_LIMIT(S,N,L,SIZE1,SIZE2,ELSE) \
764 (((S) >= (L)) ? (SIZE1) * (N) \
765 : ((S) + 4 * (N) >= (L)) ? (((L) - (S)) / 4 * (SIZE2) \
766 + ((S) + 4 * (N) - (L)) / 4 * (SIZE1)) \
768 #define SIZE_FMOV_SP_(S,N) \
769 (SIZE_FMOV_LIMIT ((S), (N), (1 << 24), 7, 6, \
770 SIZE_FMOV_LIMIT ((S), (N), (1 << 8), 6, 4, \
771 (S) ? 4 * (N) : 3 + 4 * ((N) - 1))))
772 #define SIZE_FMOV_SP(S,N) (SIZE_FMOV_SP_ ((unsigned HOST_WIDE_INT)(S), (N)))
774 /* Consider alternative save_sp_merge only if we don't need the
775 frame pointer and size is nonzero. */
776 if (! frame_pointer_needed && size)
778 /* Insn: add -(size + 4 * num_regs_to_save), sp. */
779 this_strategy_size = SIZE_ADD_SP (-(size + 4 * num_regs_to_save));
780 /* Insn: fmov fs#, (##, sp), for each fs# to be saved. */
781 this_strategy_size += SIZE_FMOV_SP (size, num_regs_to_save);
783 if (this_strategy_size < strategy_size)
785 strategy = save_sp_merge;
786 strategy_size = this_strategy_size;
790 /* Consider alternative save_sp_no_merge unconditionally. */
791 /* Insn: add -4 * num_regs_to_save, sp. */
792 this_strategy_size = SIZE_ADD_SP (-4 * num_regs_to_save);
793 /* Insn: fmov fs#, (##, sp), for each fs# to be saved. */
794 this_strategy_size += SIZE_FMOV_SP (0, num_regs_to_save);
797 /* Insn: add -size, sp. */
798 this_strategy_size += SIZE_ADD_SP (-size);
801 if (this_strategy_size < strategy_size)
803 strategy = save_sp_no_merge;
804 strategy_size = this_strategy_size;
807 /* Consider alternative save_sp_partial_merge only if we don't
808 need a frame pointer and size is reasonably large. */
809 if (! frame_pointer_needed && size + 4 * num_regs_to_save > 128)
811 /* Insn: add -128, sp. */
812 this_strategy_size = SIZE_ADD_SP (-128);
813 /* Insn: fmov fs#, (##, sp), for each fs# to be saved. */
814 this_strategy_size += SIZE_FMOV_SP (128 - 4 * num_regs_to_save,
818 /* Insn: add 128-size, sp. */
819 this_strategy_size += SIZE_ADD_SP (128 - size);
822 if (this_strategy_size < strategy_size)
824 strategy = save_sp_partial_merge;
825 strategy_size = this_strategy_size;
829 /* Consider alternative save_a0_merge only if we don't need a
830 frame pointer, size is nonzero and the user hasn't
831 changed the calling conventions of a0. */
832 if (! frame_pointer_needed && size
833 && call_really_used_regs [FIRST_ADDRESS_REGNUM]
834 && ! fixed_regs[FIRST_ADDRESS_REGNUM])
836 /* Insn: add -(size + 4 * num_regs_to_save), sp. */
837 this_strategy_size = SIZE_ADD_SP (-(size + 4 * num_regs_to_save));
838 /* Insn: mov sp, a0. */
839 this_strategy_size++;
842 /* Insn: add size, a0. */
843 this_strategy_size += SIZE_ADD_AX (size);
845 /* Insn: fmov fs#, (a0+), for each fs# to be saved. */
846 this_strategy_size += 3 * num_regs_to_save;
848 if (this_strategy_size < strategy_size)
850 strategy = save_a0_merge;
851 strategy_size = this_strategy_size;
855 /* Consider alternative save_a0_no_merge if the user hasn't
856 changed the calling conventions of a0. */
857 if (call_really_used_regs [FIRST_ADDRESS_REGNUM]
858 && ! fixed_regs[FIRST_ADDRESS_REGNUM])
860 /* Insn: add -4 * num_regs_to_save, sp. */
861 this_strategy_size = SIZE_ADD_SP (-4 * num_regs_to_save);
862 /* Insn: mov sp, a0. */
863 this_strategy_size++;
864 /* Insn: fmov fs#, (a0+), for each fs# to be saved. */
865 this_strategy_size += 3 * num_regs_to_save;
868 /* Insn: add -size, sp. */
869 this_strategy_size += SIZE_ADD_SP (-size);
872 if (this_strategy_size < strategy_size)
874 strategy = save_a0_no_merge;
875 strategy_size = this_strategy_size;
879 /* Emit the initial SP add, common to all strategies. */
882 case save_sp_no_merge:
883 case save_a0_no_merge:
884 emit_insn (gen_addsi3 (stack_pointer_rtx,
886 GEN_INT (-4 * num_regs_to_save)));
890 case save_sp_partial_merge:
891 emit_insn (gen_addsi3 (stack_pointer_rtx,
894 xsize = 128 - 4 * num_regs_to_save;
900 emit_insn (gen_addsi3 (stack_pointer_rtx,
902 GEN_INT (-(size + 4 * num_regs_to_save))));
903 /* We'll have to adjust FP register saves according to the
906 /* Since we've already created the stack frame, don't do it
907 again at the end of the function. */
915 /* Now prepare register a0, if we have decided to use it. */
919 case save_sp_no_merge:
920 case save_sp_partial_merge:
925 case save_a0_no_merge:
926 reg = gen_rtx_REG (SImode, FIRST_ADDRESS_REGNUM);
927 emit_insn (gen_movsi (reg, stack_pointer_rtx));
929 emit_insn (gen_addsi3 (reg, reg, GEN_INT (xsize)));
930 reg = gen_rtx_POST_INC (SImode, reg);
937 /* Now actually save the FP registers. */
938 for (i = FIRST_FP_REGNUM; i <= LAST_FP_REGNUM; ++i)
939 if (df_regs_ever_live_p (i) && ! call_really_used_regs [i])
947 /* If we aren't using `a0', use an SP offset. */
950 addr = gen_rtx_PLUS (SImode,
955 addr = stack_pointer_rtx;
960 insn = emit_insn (gen_movsi (gen_rtx_MEM (SImode, addr),
961 gen_rtx_REG (SImode, i)));
963 RTX_FRAME_RELATED_P (insn) = 1;
967 /* Now put the frame pointer into the frame pointer register. */
968 if (frame_pointer_needed)
969 emit_move_insn (frame_pointer_rtx, stack_pointer_rtx);
971 /* Allocate stack for this frame. */
973 emit_insn (gen_addsi3 (stack_pointer_rtx,
976 if (flag_pic && df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM))
977 emit_insn (gen_GOTaddr2picreg ());
981 expand_epilogue (void)
985 /* SIZE includes the fixed stack space needed for function calls. */
986 size = get_frame_size () + crtl->outgoing_args_size;
987 size += (crtl->outgoing_args_size ? 4 : 0);
989 if (TARGET_AM33_2 && fp_regs_to_save ())
991 int num_regs_to_save = fp_regs_to_save (), i;
994 /* We have several options to restore FP registers. We could
995 load them from SP offsets, but, if there are enough FP
996 registers to restore, we win if we use a post-increment
999 /* If we have a frame pointer, it's the best option, because we
1000 already know it has the value we want. */
1001 if (frame_pointer_needed)
1002 reg = gen_rtx_REG (SImode, FRAME_POINTER_REGNUM);
1003 /* Otherwise, we may use `a1', since it's call-clobbered and
1004 it's never used for return values. But only do so if it's
1005 smaller than using SP offsets. */
1008 enum { restore_sp_post_adjust,
1009 restore_sp_pre_adjust,
1010 restore_sp_partial_adjust,
1011 restore_a1 } strategy;
1012 unsigned int this_strategy_size, strategy_size = (unsigned)-1;
1014 /* Consider using sp offsets before adjusting sp. */
1015 /* Insn: fmov (##,sp),fs#, for each fs# to be restored. */
1016 this_strategy_size = SIZE_FMOV_SP (size, num_regs_to_save);
1017 /* If size is too large, we'll have to adjust SP with an
1019 if (size + 4 * num_regs_to_save + REG_SAVE_BYTES > 255)
1021 /* Insn: add size + 4 * num_regs_to_save, sp. */
1022 this_strategy_size += SIZE_ADD_SP (size + 4 * num_regs_to_save);
1024 /* If we don't have to restore any non-FP registers,
1025 we'll be able to save one byte by using rets. */
1026 if (! REG_SAVE_BYTES)
1027 this_strategy_size--;
1029 if (this_strategy_size < strategy_size)
1031 strategy = restore_sp_post_adjust;
1032 strategy_size = this_strategy_size;
1035 /* Consider using sp offsets after adjusting sp. */
1036 /* Insn: add size, sp. */
1037 this_strategy_size = SIZE_ADD_SP (size);
1038 /* Insn: fmov (##,sp),fs#, for each fs# to be restored. */
1039 this_strategy_size += SIZE_FMOV_SP (0, num_regs_to_save);
1040 /* We're going to use ret to release the FP registers
1041 save area, so, no savings. */
1043 if (this_strategy_size < strategy_size)
1045 strategy = restore_sp_pre_adjust;
1046 strategy_size = this_strategy_size;
1049 /* Consider using sp offsets after partially adjusting sp.
1050 When size is close to 32Kb, we may be able to adjust SP
1051 with an imm16 add instruction while still using fmov
1053 if (size + 4 * num_regs_to_save + REG_SAVE_BYTES > 255)
1055 /* Insn: add size + 4 * num_regs_to_save
1056 + REG_SAVE_BYTES - 252,sp. */
1057 this_strategy_size = SIZE_ADD_SP (size + 4 * num_regs_to_save
1058 + REG_SAVE_BYTES - 252);
1059 /* Insn: fmov (##,sp),fs#, fo each fs# to be restored. */
1060 this_strategy_size += SIZE_FMOV_SP (252 - REG_SAVE_BYTES
1061 - 4 * num_regs_to_save,
1063 /* We're going to use ret to release the FP registers
1064 save area, so, no savings. */
1066 if (this_strategy_size < strategy_size)
1068 strategy = restore_sp_partial_adjust;
1069 strategy_size = this_strategy_size;
1073 /* Consider using a1 in post-increment mode, as long as the
1074 user hasn't changed the calling conventions of a1. */
1075 if (call_really_used_regs [FIRST_ADDRESS_REGNUM + 1]
1076 && ! fixed_regs[FIRST_ADDRESS_REGNUM+1])
1078 /* Insn: mov sp,a1. */
1079 this_strategy_size = 1;
1082 /* Insn: add size,a1. */
1083 this_strategy_size += SIZE_ADD_AX (size);
1085 /* Insn: fmov (a1+),fs#, for each fs# to be restored. */
1086 this_strategy_size += 3 * num_regs_to_save;
1087 /* If size is large enough, we may be able to save a
1089 if (size + 4 * num_regs_to_save + REG_SAVE_BYTES > 255)
1091 /* Insn: mov a1,sp. */
1092 this_strategy_size += 2;
1094 /* If we don't have to restore any non-FP registers,
1095 we'll be able to save one byte by using rets. */
1096 if (! REG_SAVE_BYTES)
1097 this_strategy_size--;
1099 if (this_strategy_size < strategy_size)
1101 strategy = restore_a1;
1102 strategy_size = this_strategy_size;
1108 case restore_sp_post_adjust:
1111 case restore_sp_pre_adjust:
1112 emit_insn (gen_addsi3 (stack_pointer_rtx,
1118 case restore_sp_partial_adjust:
1119 emit_insn (gen_addsi3 (stack_pointer_rtx,
1121 GEN_INT (size + 4 * num_regs_to_save
1122 + REG_SAVE_BYTES - 252)));
1123 size = 252 - REG_SAVE_BYTES - 4 * num_regs_to_save;
1127 reg = gen_rtx_REG (SImode, FIRST_ADDRESS_REGNUM + 1);
1128 emit_insn (gen_movsi (reg, stack_pointer_rtx));
1130 emit_insn (gen_addsi3 (reg, reg, GEN_INT (size)));
1138 /* Adjust the selected register, if any, for post-increment. */
1140 reg = gen_rtx_POST_INC (SImode, reg);
1142 for (i = FIRST_FP_REGNUM; i <= LAST_FP_REGNUM; ++i)
1143 if (df_regs_ever_live_p (i) && ! call_really_used_regs [i])
1151 /* If we aren't using a post-increment register, use an
1153 addr = gen_rtx_PLUS (SImode,
1158 addr = stack_pointer_rtx;
1162 emit_insn (gen_movsi (gen_rtx_REG (SImode, i),
1163 gen_rtx_MEM (SImode, addr)));
1166 /* If we were using the restore_a1 strategy and the number of
1167 bytes to be released won't fit in the `ret' byte, copy `a1'
1168 to `sp', to avoid having to use `add' to adjust it. */
1169 if (! frame_pointer_needed && reg && size + REG_SAVE_BYTES > 255)
1171 emit_move_insn (stack_pointer_rtx, XEXP (reg, 0));
1176 /* Maybe cut back the stack, except for the register save area.
1178 If the frame pointer exists, then use the frame pointer to
1181 If the stack size + register save area is more than 255 bytes,
1182 then the stack must be cut back here since the size + register
1183 save size is too big for a ret/retf instruction.
1185 Else leave it alone, it will be cut back as part of the
1186 ret/retf instruction, or there wasn't any stack to begin with.
1188 Under no circumstances should the register save area be
1189 deallocated here, that would leave a window where an interrupt
1190 could occur and trash the register save area. */
1191 if (frame_pointer_needed)
1193 emit_move_insn (stack_pointer_rtx, frame_pointer_rtx);
1196 else if (size + REG_SAVE_BYTES > 255)
1198 emit_insn (gen_addsi3 (stack_pointer_rtx,
1204 /* Adjust the stack and restore callee-saved registers, if any. */
1205 if (size || df_regs_ever_live_p (2) || df_regs_ever_live_p (3)
1206 || df_regs_ever_live_p (6) || df_regs_ever_live_p (7)
1207 || df_regs_ever_live_p (14) || df_regs_ever_live_p (15)
1208 || df_regs_ever_live_p (16) || df_regs_ever_live_p (17)
1209 || frame_pointer_needed)
1210 emit_jump_insn (gen_return_internal_regs
1211 (GEN_INT (size + REG_SAVE_BYTES)));
1213 emit_jump_insn (gen_return_internal ());
1216 /* Update the condition code from the insn. */
1219 notice_update_cc (rtx body, rtx insn)
1221 switch (get_attr_cc (insn))
1224 /* Insn does not affect CC at all. */
1228 /* Insn does not change CC, but the 0'th operand has been changed. */
1229 if (cc_status.value1 != 0
1230 && reg_overlap_mentioned_p (recog_data.operand[0], cc_status.value1))
1231 cc_status.value1 = 0;
1235 /* Insn sets the Z,N flags of CC to recog_data.operand[0].
1236 V,C are unusable. */
1238 cc_status.flags |= CC_NO_CARRY | CC_OVERFLOW_UNUSABLE;
1239 cc_status.value1 = recog_data.operand[0];
1243 /* Insn sets the Z,N,V flags of CC to recog_data.operand[0].
1246 cc_status.flags |= CC_NO_CARRY;
1247 cc_status.value1 = recog_data.operand[0];
1251 /* The insn is a compare instruction. */
1253 cc_status.value1 = SET_SRC (body);
1254 if (GET_CODE (cc_status.value1) == COMPARE
1255 && GET_MODE (XEXP (cc_status.value1, 0)) == SFmode)
1256 cc_status.mdep.fpCC = 1;
1260 /* Insn doesn't leave CC in a usable state. */
1269 /* Recognize the PARALLEL rtx generated by mn10300_gen_multiple_store().
1270 This function is for MATCH_PARALLEL and so assumes OP is known to be
1271 parallel. If OP is a multiple store, return a mask indicating which
1272 registers it saves. Return 0 otherwise. */
1275 store_multiple_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1283 count = XVECLEN (op, 0);
1287 /* Check that first instruction has the form (set (sp) (plus A B)) */
1288 elt = XVECEXP (op, 0, 0);
1289 if (GET_CODE (elt) != SET
1290 || GET_CODE (SET_DEST (elt)) != REG
1291 || REGNO (SET_DEST (elt)) != STACK_POINTER_REGNUM
1292 || GET_CODE (SET_SRC (elt)) != PLUS)
1295 /* Check that A is the stack pointer and B is the expected stack size.
1296 For OP to match, each subsequent instruction should push a word onto
1297 the stack. We therefore expect the first instruction to create
1298 COUNT-1 stack slots. */
1299 elt = SET_SRC (elt);
1300 if (GET_CODE (XEXP (elt, 0)) != REG
1301 || REGNO (XEXP (elt, 0)) != STACK_POINTER_REGNUM
1302 || GET_CODE (XEXP (elt, 1)) != CONST_INT
1303 || INTVAL (XEXP (elt, 1)) != -(count - 1) * 4)
1306 /* Now go through the rest of the vector elements. They must be
1307 ordered so that the first instruction stores the highest-numbered
1308 register to the highest stack slot and that subsequent instructions
1309 store a lower-numbered register to the slot below.
1311 LAST keeps track of the smallest-numbered register stored so far.
1312 MASK is the set of stored registers. */
1313 last = LAST_EXTENDED_REGNUM + 1;
1315 for (i = 1; i < count; i++)
1317 /* Check that element i is a (set (mem M) R) and that R is valid. */
1318 elt = XVECEXP (op, 0, i);
1319 if (GET_CODE (elt) != SET
1320 || GET_CODE (SET_DEST (elt)) != MEM
1321 || GET_CODE (SET_SRC (elt)) != REG
1322 || REGNO (SET_SRC (elt)) >= last)
1325 /* R was OK, so provisionally add it to MASK. We return 0 in any
1326 case if the rest of the instruction has a flaw. */
1327 last = REGNO (SET_SRC (elt));
1328 mask |= (1 << last);
1330 /* Check that M has the form (plus (sp) (const_int -I*4)) */
1331 elt = XEXP (SET_DEST (elt), 0);
1332 if (GET_CODE (elt) != PLUS
1333 || GET_CODE (XEXP (elt, 0)) != REG
1334 || REGNO (XEXP (elt, 0)) != STACK_POINTER_REGNUM
1335 || GET_CODE (XEXP (elt, 1)) != CONST_INT
1336 || INTVAL (XEXP (elt, 1)) != -i * 4)
1340 /* All or none of the callee-saved extended registers must be in the set. */
1341 if ((mask & 0x3c000) != 0
1342 && (mask & 0x3c000) != 0x3c000)
1348 /* What (if any) secondary registers are needed to move IN with mode
1349 MODE into a register in register class RCLASS.
1351 We might be able to simplify this. */
1353 mn10300_secondary_reload_class (enum reg_class rclass, enum machine_mode mode,
1358 /* Strip off any SUBREG expressions from IN. Basically we want
1359 to know if IN is a pseudo or (subreg (pseudo)) as those can
1360 turn into MEMs during reload. */
1361 while (GET_CODE (inner) == SUBREG)
1362 inner = SUBREG_REG (inner);
1364 /* Memory loads less than a full word wide can't have an
1365 address or stack pointer destination. They must use
1366 a data register as an intermediate register. */
1367 if ((GET_CODE (in) == MEM
1368 || (GET_CODE (inner) == REG
1369 && REGNO (inner) >= FIRST_PSEUDO_REGISTER))
1370 && (mode == QImode || mode == HImode)
1371 && (rclass == ADDRESS_REGS || rclass == SP_REGS
1372 || rclass == SP_OR_ADDRESS_REGS))
1375 return DATA_OR_EXTENDED_REGS;
1379 /* We can't directly load sp + const_int into a data register;
1380 we must use an address register as an intermediate. */
1381 if (rclass != SP_REGS
1382 && rclass != ADDRESS_REGS
1383 && rclass != SP_OR_ADDRESS_REGS
1384 && rclass != SP_OR_EXTENDED_REGS
1385 && rclass != ADDRESS_OR_EXTENDED_REGS
1386 && rclass != SP_OR_ADDRESS_OR_EXTENDED_REGS
1387 && (in == stack_pointer_rtx
1388 || (GET_CODE (in) == PLUS
1389 && (XEXP (in, 0) == stack_pointer_rtx
1390 || XEXP (in, 1) == stack_pointer_rtx))))
1391 return ADDRESS_REGS;
1393 if (GET_CODE (in) == PLUS
1394 && (XEXP (in, 0) == stack_pointer_rtx
1395 || XEXP (in, 1) == stack_pointer_rtx))
1396 return GENERAL_REGS;
1399 && rclass == FP_REGS)
1401 /* We can't load directly into an FP register from a
1402 constant address. */
1403 if (GET_CODE (in) == MEM
1404 && CONSTANT_ADDRESS_P (XEXP (in, 0)))
1405 return (TARGET_AM33 ? DATA_OR_EXTENDED_REGS : DATA_REGS);
1407 /* Handle case were a pseudo may not get a hard register
1408 but has an equivalent memory location defined. */
1409 if (GET_CODE (inner) == REG
1410 && REGNO (inner) >= FIRST_PSEUDO_REGISTER
1411 && reg_equiv_mem [REGNO (inner)]
1412 && CONSTANT_ADDRESS_P (XEXP (reg_equiv_mem [REGNO (inner)], 0)))
1413 return (TARGET_AM33 ? DATA_OR_EXTENDED_REGS : DATA_REGS);
1416 /* Otherwise assume no secondary reloads are needed. */
1421 initial_offset (int from, int to)
1423 /* The difference between the argument pointer and the frame pointer
1424 is the size of the callee register save area. */
1425 if (from == ARG_POINTER_REGNUM && to == FRAME_POINTER_REGNUM)
1427 if (df_regs_ever_live_p (2) || df_regs_ever_live_p (3)
1428 || df_regs_ever_live_p (6) || df_regs_ever_live_p (7)
1429 || df_regs_ever_live_p (14) || df_regs_ever_live_p (15)
1430 || df_regs_ever_live_p (16) || df_regs_ever_live_p (17)
1431 || fp_regs_to_save ()
1432 || frame_pointer_needed)
1433 return REG_SAVE_BYTES
1434 + 4 * fp_regs_to_save ();
1439 /* The difference between the argument pointer and the stack pointer is
1440 the sum of the size of this function's frame, the callee register save
1441 area, and the fixed stack space needed for function calls (if any). */
1442 if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
1444 if (df_regs_ever_live_p (2) || df_regs_ever_live_p (3)
1445 || df_regs_ever_live_p (6) || df_regs_ever_live_p (7)
1446 || df_regs_ever_live_p (14) || df_regs_ever_live_p (15)
1447 || df_regs_ever_live_p (16) || df_regs_ever_live_p (17)
1448 || fp_regs_to_save ()
1449 || frame_pointer_needed)
1450 return (get_frame_size () + REG_SAVE_BYTES
1451 + 4 * fp_regs_to_save ()
1452 + (crtl->outgoing_args_size
1453 ? crtl->outgoing_args_size + 4 : 0));
1455 return (get_frame_size ()
1456 + (crtl->outgoing_args_size
1457 ? crtl->outgoing_args_size + 4 : 0));
1460 /* The difference between the frame pointer and stack pointer is the sum
1461 of the size of this function's frame and the fixed stack space needed
1462 for function calls (if any). */
1463 if (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
1464 return (get_frame_size ()
1465 + (crtl->outgoing_args_size
1466 ? crtl->outgoing_args_size + 4 : 0));
1471 /* Worker function for TARGET_RETURN_IN_MEMORY. */
1474 mn10300_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED)
1476 /* Return values > 8 bytes in length in memory. */
1477 return (int_size_in_bytes (type) > 8
1478 || int_size_in_bytes (type) == 0
1479 || TYPE_MODE (type) == BLKmode);
1482 /* Flush the argument registers to the stack for a stdarg function;
1483 return the new argument pointer. */
1485 mn10300_builtin_saveregs (void)
1488 tree fntype = TREE_TYPE (current_function_decl);
1489 int argadj = ((!(TYPE_ARG_TYPES (fntype) != 0
1490 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype)))
1491 != void_type_node)))
1492 ? UNITS_PER_WORD : 0);
1493 alias_set_type set = get_varargs_alias_set ();
1496 offset = plus_constant (crtl->args.arg_offset_rtx, argadj);
1498 offset = crtl->args.arg_offset_rtx;
1500 mem = gen_rtx_MEM (SImode, crtl->args.internal_arg_pointer);
1501 set_mem_alias_set (mem, set);
1502 emit_move_insn (mem, gen_rtx_REG (SImode, 0));
1504 mem = gen_rtx_MEM (SImode,
1505 plus_constant (crtl->args.internal_arg_pointer, 4));
1506 set_mem_alias_set (mem, set);
1507 emit_move_insn (mem, gen_rtx_REG (SImode, 1));
1509 return copy_to_reg (expand_binop (Pmode, add_optab,
1510 crtl->args.internal_arg_pointer,
1511 offset, 0, 0, OPTAB_LIB_WIDEN));
1515 mn10300_va_start (tree valist, rtx nextarg)
1517 nextarg = expand_builtin_saveregs ();
1518 std_expand_builtin_va_start (valist, nextarg);
1521 /* Return true when a parameter should be passed by reference. */
1524 mn10300_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
1525 enum machine_mode mode, const_tree type,
1526 bool named ATTRIBUTE_UNUSED)
1528 unsigned HOST_WIDE_INT size;
1531 size = int_size_in_bytes (type);
1533 size = GET_MODE_SIZE (mode);
1535 return (size > 8 || size == 0);
1538 /* Return an RTX to represent where a value with mode MODE will be returned
1539 from a function. If the result is 0, the argument is pushed. */
1542 function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode,
1543 tree type, int named ATTRIBUTE_UNUSED)
1548 /* We only support using 2 data registers as argument registers. */
1551 /* Figure out the size of the object to be passed. */
1552 if (mode == BLKmode)
1553 size = int_size_in_bytes (type);
1555 size = GET_MODE_SIZE (mode);
1557 /* Figure out the alignment of the object to be passed. */
1560 cum->nbytes = (cum->nbytes + 3) & ~3;
1562 /* Don't pass this arg via a register if all the argument registers
1564 if (cum->nbytes > nregs * UNITS_PER_WORD)
1567 /* Don't pass this arg via a register if it would be split between
1568 registers and memory. */
1569 if (type == NULL_TREE
1570 && cum->nbytes + size > nregs * UNITS_PER_WORD)
1573 switch (cum->nbytes / UNITS_PER_WORD)
1576 result = gen_rtx_REG (mode, 0);
1579 result = gen_rtx_REG (mode, 1);
1588 /* Return the number of bytes of registers to use for an argument passed
1589 partially in registers and partially in memory. */
1592 mn10300_arg_partial_bytes (CUMULATIVE_ARGS *cum, enum machine_mode mode,
1593 tree type, bool named ATTRIBUTE_UNUSED)
1597 /* We only support using 2 data registers as argument registers. */
1600 /* Figure out the size of the object to be passed. */
1601 if (mode == BLKmode)
1602 size = int_size_in_bytes (type);
1604 size = GET_MODE_SIZE (mode);
1606 /* Figure out the alignment of the object to be passed. */
1609 cum->nbytes = (cum->nbytes + 3) & ~3;
1611 /* Don't pass this arg via a register if all the argument registers
1613 if (cum->nbytes > nregs * UNITS_PER_WORD)
1616 if (cum->nbytes + size <= nregs * UNITS_PER_WORD)
1619 /* Don't pass this arg via a register if it would be split between
1620 registers and memory. */
1621 if (type == NULL_TREE
1622 && cum->nbytes + size > nregs * UNITS_PER_WORD)
1625 return nregs * UNITS_PER_WORD - cum->nbytes;
1628 /* Return the location of the function's value. This will be either
1629 $d0 for integer functions, $a0 for pointers, or a PARALLEL of both
1630 $d0 and $a0 if the -mreturn-pointer-on-do flag is set. Note that
1631 we only return the PARALLEL for outgoing values; we do not want
1632 callers relying on this extra copy. */
1635 mn10300_function_value (const_tree valtype,
1636 const_tree fn_decl_or_type ATTRIBUTE_UNUSED,
1640 enum machine_mode mode = TYPE_MODE (valtype);
1642 if (! POINTER_TYPE_P (valtype))
1643 return gen_rtx_REG (mode, FIRST_DATA_REGNUM);
1644 else if (! TARGET_PTR_A0D0 || ! outgoing
1645 || cfun->returns_struct)
1646 return gen_rtx_REG (mode, FIRST_ADDRESS_REGNUM);
1648 rv = gen_rtx_PARALLEL (mode, rtvec_alloc (2));
1650 = gen_rtx_EXPR_LIST (VOIDmode,
1651 gen_rtx_REG (mode, FIRST_ADDRESS_REGNUM),
1655 = gen_rtx_EXPR_LIST (VOIDmode,
1656 gen_rtx_REG (mode, FIRST_DATA_REGNUM),
1661 /* Implements TARGET_LIBCALL_VALUE. */
1664 mn10300_libcall_value (enum machine_mode mode,
1665 const_rtx fun ATTRIBUTE_UNUSED)
1667 return gen_rtx_REG (mode, FIRST_DATA_REGNUM);
1670 /* Implements FUNCTION_VALUE_REGNO_P. */
1673 mn10300_function_value_regno_p (const unsigned int regno)
1675 return (regno == FIRST_DATA_REGNUM || regno == FIRST_ADDRESS_REGNUM);
1678 /* Output a tst insn. */
1680 output_tst (rtx operand, rtx insn)
1685 /* We can save a byte if we can find a register which has the value
1687 temp = PREV_INSN (insn);
1688 while (optimize && temp)
1692 /* We allow the search to go through call insns. We record
1693 the fact that we've past a CALL_INSN and reject matches which
1694 use call clobbered registers. */
1695 if (GET_CODE (temp) == CODE_LABEL
1696 || GET_CODE (temp) == JUMP_INSN
1697 || GET_CODE (temp) == BARRIER)
1700 if (GET_CODE (temp) == CALL_INSN)
1703 if (GET_CODE (temp) == NOTE)
1705 temp = PREV_INSN (temp);
1709 /* It must be an insn, see if it is a simple set. */
1710 set = single_set (temp);
1713 temp = PREV_INSN (temp);
1717 /* Are we setting a data register to zero (this does not win for
1720 If it's a call clobbered register, have we past a call?
1722 Make sure the register we find isn't the same as ourself;
1723 the mn10300 can't encode that.
1725 ??? reg_set_between_p return nonzero anytime we pass a CALL_INSN
1726 so the code to detect calls here isn't doing anything useful. */
1727 if (REG_P (SET_DEST (set))
1728 && SET_SRC (set) == CONST0_RTX (GET_MODE (SET_DEST (set)))
1729 && !reg_set_between_p (SET_DEST (set), temp, insn)
1730 && (REGNO_REG_CLASS (REGNO (SET_DEST (set)))
1731 == REGNO_REG_CLASS (REGNO (operand)))
1732 && REGNO_REG_CLASS (REGNO (SET_DEST (set))) != EXTENDED_REGS
1733 && REGNO (SET_DEST (set)) != REGNO (operand)
1735 || ! call_really_used_regs [REGNO (SET_DEST (set))]))
1738 xoperands[0] = operand;
1739 xoperands[1] = SET_DEST (set);
1741 output_asm_insn ("cmp %1,%0", xoperands);
1745 if (REGNO_REG_CLASS (REGNO (operand)) == EXTENDED_REGS
1746 && REG_P (SET_DEST (set))
1747 && SET_SRC (set) == CONST0_RTX (GET_MODE (SET_DEST (set)))
1748 && !reg_set_between_p (SET_DEST (set), temp, insn)
1749 && (REGNO_REG_CLASS (REGNO (SET_DEST (set)))
1750 != REGNO_REG_CLASS (REGNO (operand)))
1751 && REGNO_REG_CLASS (REGNO (SET_DEST (set))) == EXTENDED_REGS
1752 && REGNO (SET_DEST (set)) != REGNO (operand)
1754 || ! call_really_used_regs [REGNO (SET_DEST (set))]))
1757 xoperands[0] = operand;
1758 xoperands[1] = SET_DEST (set);
1760 output_asm_insn ("cmp %1,%0", xoperands);
1763 temp = PREV_INSN (temp);
1769 impossible_plus_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1771 if (GET_CODE (op) != PLUS)
1774 if (XEXP (op, 0) == stack_pointer_rtx
1775 || XEXP (op, 1) == stack_pointer_rtx)
1781 /* Similarly, but when using a zero_extract pattern for a btst where
1782 the source operand might end up in memory. */
1784 mask_ok_for_mem_btst (int len, int bit)
1786 unsigned int mask = 0;
1795 /* MASK must bit into an 8bit value. */
1796 return (((mask & 0xff) == mask)
1797 || ((mask & 0xff00) == mask)
1798 || ((mask & 0xff0000) == mask)
1799 || ((mask & 0xff000000) == mask));
1802 /* Return 1 if X contains a symbolic expression. We know these
1803 expressions will have one of a few well defined forms, so
1804 we need only check those forms. */
1806 symbolic_operand (register rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1808 switch (GET_CODE (op))
1815 return ((GET_CODE (XEXP (op, 0)) == SYMBOL_REF
1816 || GET_CODE (XEXP (op, 0)) == LABEL_REF)
1817 && GET_CODE (XEXP (op, 1)) == CONST_INT);
1823 /* Try machine dependent ways of modifying an illegitimate address
1824 to be legitimate. If we find one, return the new valid address.
1825 This macro is used in only one place: `memory_address' in explow.c.
1827 OLDX is the address as it was before break_out_memory_refs was called.
1828 In some cases it is useful to look at this to decide what needs to be done.
1830 Normally it is always safe for this macro to do nothing. It exists to
1831 recognize opportunities to optimize the output.
1833 But on a few ports with segmented architectures and indexed addressing
1834 (mn10300, hppa) it is used to rewrite certain problematical addresses. */
1836 mn10300_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
1837 enum machine_mode mode ATTRIBUTE_UNUSED)
1839 if (flag_pic && ! legitimate_pic_operand_p (x))
1840 x = legitimize_pic_address (oldx, NULL_RTX);
1842 /* Uh-oh. We might have an address for x[n-100000]. This needs
1843 special handling to avoid creating an indexed memory address
1844 with x-100000 as the base. */
1845 if (GET_CODE (x) == PLUS
1846 && symbolic_operand (XEXP (x, 1), VOIDmode))
1848 /* Ugly. We modify things here so that the address offset specified
1849 by the index expression is computed first, then added to x to form
1850 the entire address. */
1852 rtx regx1, regy1, regy2, y;
1854 /* Strip off any CONST. */
1856 if (GET_CODE (y) == CONST)
1859 if (GET_CODE (y) == PLUS || GET_CODE (y) == MINUS)
1861 regx1 = force_reg (Pmode, force_operand (XEXP (x, 0), 0));
1862 regy1 = force_reg (Pmode, force_operand (XEXP (y, 0), 0));
1863 regy2 = force_reg (Pmode, force_operand (XEXP (y, 1), 0));
1864 regx1 = force_reg (Pmode,
1865 gen_rtx_fmt_ee (GET_CODE (y), Pmode, regx1, regy2));
1866 return force_reg (Pmode, gen_rtx_PLUS (Pmode, regx1, regy1));
1872 /* Convert a non-PIC address in `orig' to a PIC address using @GOT or
1873 @GOTOFF in `reg'. */
1875 legitimize_pic_address (rtx orig, rtx reg)
1877 if (GET_CODE (orig) == LABEL_REF
1878 || (GET_CODE (orig) == SYMBOL_REF
1879 && (CONSTANT_POOL_ADDRESS_P (orig)
1880 || ! MN10300_GLOBAL_P (orig))))
1883 reg = gen_reg_rtx (Pmode);
1885 emit_insn (gen_symGOTOFF2reg (reg, orig));
1888 else if (GET_CODE (orig) == SYMBOL_REF)
1891 reg = gen_reg_rtx (Pmode);
1893 emit_insn (gen_symGOT2reg (reg, orig));
1899 /* Return zero if X references a SYMBOL_REF or LABEL_REF whose symbol
1900 isn't protected by a PIC unspec; nonzero otherwise. */
1902 legitimate_pic_operand_p (rtx x)
1904 register const char *fmt;
1907 if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF)
1910 if (GET_CODE (x) == UNSPEC
1911 && (XINT (x, 1) == UNSPEC_PIC
1912 || XINT (x, 1) == UNSPEC_GOT
1913 || XINT (x, 1) == UNSPEC_GOTOFF
1914 || XINT (x, 1) == UNSPEC_PLT
1915 || XINT (x, 1) == UNSPEC_GOTSYM_OFF))
1918 fmt = GET_RTX_FORMAT (GET_CODE (x));
1919 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
1925 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
1926 if (! legitimate_pic_operand_p (XVECEXP (x, i, j)))
1929 else if (fmt[i] == 'e' && ! legitimate_pic_operand_p (XEXP (x, i)))
1936 /* Return TRUE if the address X, taken from a (MEM:MODE X) rtx, is
1937 legitimate, and FALSE otherwise.
1939 On the mn10300, the value in the address register must be
1940 in the same memory space/segment as the effective address.
1942 This is problematical for reload since it does not understand
1943 that base+index != index+base in a memory reference.
1945 Note it is still possible to use reg+reg addressing modes,
1946 it's just much more difficult. For a discussion of a possible
1947 workaround and solution, see the comments in pa.c before the
1948 function record_unscaled_index_insn_codes. */
1951 mn10300_legitimate_address_p (enum machine_mode mode, rtx x, bool strict)
1953 if (CONSTANT_ADDRESS_P (x)
1954 && (! flag_pic || legitimate_pic_operand_p (x)))
1957 if (RTX_OK_FOR_BASE_P (x, strict))
1961 && GET_CODE (x) == POST_INC
1962 && RTX_OK_FOR_BASE_P (XEXP (x, 0), strict)
1963 && (mode == SImode || mode == SFmode || mode == HImode))
1966 if (GET_CODE (x) == PLUS)
1968 rtx base = 0, index = 0;
1970 if (REG_P (XEXP (x, 0))
1971 && REGNO_STRICT_OK_FOR_BASE_P (REGNO (XEXP (x, 0)), strict))
1974 index = XEXP (x, 1);
1977 if (REG_P (XEXP (x, 1))
1978 && REGNO_STRICT_OK_FOR_BASE_P (REGNO (XEXP (x, 1)), strict))
1981 index = XEXP (x, 0);
1984 if (base != 0 && index != 0)
1986 if (GET_CODE (index) == CONST_INT)
1988 if (GET_CODE (index) == CONST
1989 && GET_CODE (XEXP (index, 0)) != PLUS
1991 || legitimate_pic_operand_p (index)))
2000 mn10300_address_cost_1 (rtx x, int *unsig)
2002 switch (GET_CODE (x))
2005 switch (REGNO_REG_CLASS (REGNO (x)))
2031 return (mn10300_address_cost_1 (XEXP (x, 0), unsig)
2032 + mn10300_address_cost_1 (XEXP (x, 1), unsig));
2037 return mn10300_address_cost (XEXP (x, 0), !optimize_size);
2041 return mn10300_address_cost_1 (XEXP (x, 0), unsig);
2044 if (INTVAL (x) == 0)
2046 if (INTVAL (x) + (*unsig ? 0 : 0x80) < 0x100)
2048 if (INTVAL (x) + (*unsig ? 0 : 0x8000) < 0x10000)
2050 if (INTVAL (x) + (*unsig ? 0 : 0x800000) < 0x1000000)
2066 mn10300_address_cost (rtx x, bool speed ATTRIBUTE_UNUSED)
2069 return mn10300_address_cost_1 (x, &s);
2073 mn10300_rtx_costs (rtx x, int code, int outer_code, int *total, bool speed ATTRIBUTE_UNUSED)
2078 /* Zeros are extremely cheap. */
2079 if (INTVAL (x) == 0 && (outer_code == SET || outer_code == COMPARE))
2081 /* If it fits in 8 bits, then it's still relatively cheap. */
2082 else if (INT_8_BITS (INTVAL (x)))
2084 /* This is the "base" cost, includes constants where either the
2085 upper or lower 16bits are all zeros. */
2086 else if (INT_16_BITS (INTVAL (x))
2087 || (INTVAL (x) & 0xffff) == 0
2088 || (INTVAL (x) & 0xffff0000) == 0)
2097 /* These are more costly than a CONST_INT, but we can relax them,
2098 so they're less costly than a CONST_DOUBLE. */
2103 /* We don't optimize CONST_DOUBLEs well nor do we relax them well,
2104 so their cost is very high. */
2109 /* This is cheap, we can use btst. */
2110 if (outer_code == COMPARE)
2114 /* ??? This probably needs more work. */
2126 /* Check whether a constant used to initialize a DImode or DFmode can
2127 use a clr instruction. The code here must be kept in sync with
2131 mn10300_wide_const_load_uses_clr (rtx operands[2])
2135 if (GET_CODE (operands[0]) != REG
2136 || REGNO_REG_CLASS (REGNO (operands[0])) != DATA_REGS)
2139 switch (GET_CODE (operands[1]))
2144 split_double (operands[1], &low, &high);
2145 val[0] = INTVAL (low);
2146 val[1] = INTVAL (high);
2151 if (GET_MODE (operands[1]) == DFmode)
2155 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
2156 REAL_VALUE_TO_TARGET_DOUBLE (rv, val);
2158 else if (GET_MODE (operands[1]) == VOIDmode
2159 || GET_MODE (operands[1]) == DImode)
2161 val[0] = CONST_DOUBLE_LOW (operands[1]);
2162 val[1] = CONST_DOUBLE_HIGH (operands[1]);
2170 return val[0] == 0 || val[1] == 0;
2172 /* If using PIC, mark a SYMBOL_REF for a non-global symbol so that we
2173 may access it using GOTOFF instead of GOT. */
2176 mn10300_encode_section_info (tree decl, rtx rtl, int first ATTRIBUTE_UNUSED)
2180 if (GET_CODE (rtl) != MEM)
2182 symbol = XEXP (rtl, 0);
2183 if (GET_CODE (symbol) != SYMBOL_REF)
2187 SYMBOL_REF_FLAG (symbol) = (*targetm.binds_local_p) (decl);
2190 /* Dispatch tables on the mn10300 are extremely expensive in terms of code
2191 and readonly data size. So we crank up the case threshold value to
2192 encourage a series of if/else comparisons to implement many small switch
2193 statements. In theory, this value could be increased much more if we
2194 were solely optimizing for space, but we keep it "reasonable" to avoid
2195 serious code efficiency lossage. */
2197 unsigned int mn10300_case_values_threshold (void)
2202 /* Worker function for TARGET_ASM_TRAMPOLINE_TEMPLATE. */
2205 mn10300_asm_trampoline_template (FILE *f)
2207 fprintf (f, "\tadd -4,sp\n");
2208 fprintf (f, "\t.long 0x0004fffa\n");
2209 fprintf (f, "\tmov (0,sp),a0\n");
2210 fprintf (f, "\tadd 4,sp\n");
2211 fprintf (f, "\tmov (13,a0),a1\n");
2212 fprintf (f, "\tmov (17,a0),a0\n");
2213 fprintf (f, "\tjmp (a0)\n");
2214 fprintf (f, "\t.long 0\n");
2215 fprintf (f, "\t.long 0\n");
2218 /* Worker function for TARGET_TRAMPOLINE_INIT. */
2221 mn10300_trampoline_init (rtx m_tramp, tree fndecl, rtx chain_value)
2223 rtx fnaddr = XEXP (DECL_RTL (fndecl), 0);
2226 emit_block_move (m_tramp, assemble_trampoline_template (),
2227 GEN_INT (TRAMPOLINE_SIZE), BLOCK_OP_NORMAL);
2229 mem = adjust_address (m_tramp, SImode, 0x14);
2230 emit_move_insn (mem, chain_value);
2231 mem = adjust_address (m_tramp, SImode, 0x18);
2232 emit_move_insn (mem, fnaddr);