1 /* Subroutines for insn-output.c for Matsushita MN10300 series
2 Copyright (C) 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004,
3 2005, 2006, 2007, 2008, 2009, 2010, 2011 Free Software Foundation, Inc.
4 Contributed by Jeff Law (law@cygnus.com).
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
24 #include "coretypes.h"
29 #include "hard-reg-set.h"
30 #include "insn-config.h"
31 #include "conditions.h"
33 #include "insn-attr.h"
41 #include "diagnostic-core.h"
43 #include "tm-constrs.h"
45 #include "target-def.h"
50 /* This is used in the am33_2.0-linux-gnu port, in which global symbol
51 names are not prefixed by underscores, to tell whether to prefix a
52 label with a plus sign or not, so that the assembler can tell
53 symbol names from register names. */
54 int mn10300_protect_label;
56 /* Selected processor type for tuning. */
57 enum processor_type mn10300_tune_cpu = PROCESSOR_DEFAULT;
59 /* The size of the callee register save area. Right now we save everything
60 on entry since it costs us nothing in code size. It does cost us from a
61 speed standpoint, so we want to optimize this sooner or later. */
62 #define REG_SAVE_BYTES (4 * df_regs_ever_live_p (2) \
63 + 4 * df_regs_ever_live_p (3) \
64 + 4 * df_regs_ever_live_p (6) \
65 + 4 * df_regs_ever_live_p (7) \
66 + 16 * (df_regs_ever_live_p (14) \
67 || df_regs_ever_live_p (15) \
68 || df_regs_ever_live_p (16) \
69 || df_regs_ever_live_p (17)))
76 static int cc_flags_for_mode(enum machine_mode);
77 static int cc_flags_for_code(enum rtx_code);
79 /* Implement TARGET_OPTION_OVERRIDE. */
82 mn10300_option_override (void)
85 target_flags &= ~MASK_MULT_BUG;
88 /* Disable scheduling for the MN10300 as we do
89 not have timing information available for it. */
90 flag_schedule_insns = 0;
91 flag_schedule_insns_after_reload = 0;
93 /* Force enable splitting of wide types, as otherwise it is trivial
94 to run out of registers. Indeed, this works so well that register
95 allocation problems are now more common *without* optimization,
96 when this flag is not enabled by default. */
97 flag_split_wide_types = 1;
100 if (mn10300_tune_string)
102 if (strcasecmp (mn10300_tune_string, "mn10300") == 0)
103 mn10300_tune_cpu = PROCESSOR_MN10300;
104 else if (strcasecmp (mn10300_tune_string, "am33") == 0)
105 mn10300_tune_cpu = PROCESSOR_AM33;
106 else if (strcasecmp (mn10300_tune_string, "am33-2") == 0)
107 mn10300_tune_cpu = PROCESSOR_AM33_2;
108 else if (strcasecmp (mn10300_tune_string, "am34") == 0)
109 mn10300_tune_cpu = PROCESSOR_AM34;
111 error ("-mtune= expects mn10300, am33, am33-2, or am34");
116 mn10300_file_start (void)
118 default_file_start ();
121 fprintf (asm_out_file, "\t.am33_2\n");
122 else if (TARGET_AM33)
123 fprintf (asm_out_file, "\t.am33\n");
126 /* Note: This list must match the liw_op attribute in mn10300.md. */
128 static const char *liw_op_names[] =
130 "add", "cmp", "sub", "mov",
136 /* Print operand X using operand code CODE to assembly language output file
140 mn10300_print_operand (FILE *file, rtx x, int code)
146 unsigned int liw_op = UINTVAL (x);
148 gcc_assert (TARGET_ALLOW_LIW);
149 gcc_assert (liw_op < LIW_OP_MAX);
150 fputs (liw_op_names[liw_op], file);
157 enum rtx_code cmp = GET_CODE (x);
158 enum machine_mode mode = GET_MODE (XEXP (x, 0));
163 cmp = reverse_condition (cmp);
164 have_flags = cc_flags_for_mode (mode);
175 /* bge is smaller than bnc. */
176 str = (have_flags & CC_FLAG_V ? "ge" : "nc");
179 str = (have_flags & CC_FLAG_V ? "lt" : "ns");
227 gcc_checking_assert ((cc_flags_for_code (cmp) & ~have_flags) == 0);
233 /* This is used for the operand to a call instruction;
234 if it's a REG, enclose it in parens, else output
235 the operand normally. */
239 mn10300_print_operand (file, x, 0);
243 mn10300_print_operand (file, x, 0);
247 switch (GET_CODE (x))
251 output_address (XEXP (x, 0));
256 fprintf (file, "fd%d", REGNO (x) - 18);
264 /* These are the least significant word in a 64bit value. */
266 switch (GET_CODE (x))
270 output_address (XEXP (x, 0));
275 fprintf (file, "%s", reg_names[REGNO (x)]);
279 fprintf (file, "%s", reg_names[subreg_regno (x)]);
287 switch (GET_MODE (x))
290 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
291 REAL_VALUE_TO_TARGET_DOUBLE (rv, val);
292 fprintf (file, "0x%lx", val[0]);
295 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
296 REAL_VALUE_TO_TARGET_SINGLE (rv, val[0]);
297 fprintf (file, "0x%lx", val[0]);
301 mn10300_print_operand_address (file,
302 GEN_INT (CONST_DOUBLE_LOW (x)));
313 split_double (x, &low, &high);
314 fprintf (file, "%ld", (long)INTVAL (low));
323 /* Similarly, but for the most significant word. */
325 switch (GET_CODE (x))
329 x = adjust_address (x, SImode, 4);
330 output_address (XEXP (x, 0));
335 fprintf (file, "%s", reg_names[REGNO (x) + 1]);
339 fprintf (file, "%s", reg_names[subreg_regno (x) + 1]);
347 switch (GET_MODE (x))
350 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
351 REAL_VALUE_TO_TARGET_DOUBLE (rv, val);
352 fprintf (file, "0x%lx", val[1]);
358 mn10300_print_operand_address (file,
359 GEN_INT (CONST_DOUBLE_HIGH (x)));
370 split_double (x, &low, &high);
371 fprintf (file, "%ld", (long)INTVAL (high));
382 if (REG_P (XEXP (x, 0)))
383 output_address (gen_rtx_PLUS (SImode, XEXP (x, 0), const0_rtx));
385 output_address (XEXP (x, 0));
390 gcc_assert (INTVAL (x) >= -128 && INTVAL (x) <= 255);
391 fprintf (file, "%d", (int)((~INTVAL (x)) & 0xff));
395 gcc_assert (INTVAL (x) >= -128 && INTVAL (x) <= 255);
396 fprintf (file, "%d", (int)(INTVAL (x) & 0xff));
399 /* For shift counts. The hardware ignores the upper bits of
400 any immediate, but the assembler will flag an out of range
401 shift count as an error. So we mask off the high bits
402 of the immediate here. */
406 fprintf (file, "%d", (int)(INTVAL (x) & 0x1f));
412 switch (GET_CODE (x))
416 output_address (XEXP (x, 0));
425 fprintf (file, "%s", reg_names[REGNO (x)]);
429 fprintf (file, "%s", reg_names[subreg_regno (x)]);
432 /* This will only be single precision.... */
438 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
439 REAL_VALUE_TO_TARGET_SINGLE (rv, val);
440 fprintf (file, "0x%lx", val);
450 mn10300_print_operand_address (file, x);
459 /* Output assembly language output for the address ADDR to FILE. */
462 mn10300_print_operand_address (FILE *file, rtx addr)
464 switch (GET_CODE (addr))
467 mn10300_print_operand (file, XEXP (addr, 0), 0);
472 mn10300_print_operand (file, XEXP (addr, 0), 0);
475 mn10300_print_operand (file, XEXP (addr, 1), 0);
479 mn10300_print_operand (file, addr, 0);
483 rtx base = XEXP (addr, 0);
484 rtx index = XEXP (addr, 1);
486 if (REG_P (index) && !REG_OK_FOR_INDEX_P (index))
492 gcc_assert (REG_P (index) && REG_OK_FOR_INDEX_P (index));
494 gcc_assert (REG_OK_FOR_BASE_P (base));
496 mn10300_print_operand (file, index, 0);
498 mn10300_print_operand (file, base, 0);
502 output_addr_const (file, addr);
505 output_addr_const (file, addr);
510 /* Implement TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA.
512 Used for PIC-specific UNSPECs. */
515 mn10300_asm_output_addr_const_extra (FILE *file, rtx x)
517 if (GET_CODE (x) == UNSPEC)
522 /* GLOBAL_OFFSET_TABLE or local symbols, no suffix. */
523 output_addr_const (file, XVECEXP (x, 0, 0));
526 output_addr_const (file, XVECEXP (x, 0, 0));
527 fputs ("@GOT", file);
530 output_addr_const (file, XVECEXP (x, 0, 0));
531 fputs ("@GOTOFF", file);
534 output_addr_const (file, XVECEXP (x, 0, 0));
535 fputs ("@PLT", file);
537 case UNSPEC_GOTSYM_OFF:
538 assemble_name (file, GOT_SYMBOL_NAME);
540 output_addr_const (file, XVECEXP (x, 0, 0));
552 /* Count the number of FP registers that have to be saved. */
554 fp_regs_to_save (void)
561 for (i = FIRST_FP_REGNUM; i <= LAST_FP_REGNUM; ++i)
562 if (df_regs_ever_live_p (i) && ! call_really_used_regs[i])
568 /* Print a set of registers in the format required by "movm" and "ret".
569 Register K is saved if bit K of MASK is set. The data and address
570 registers can be stored individually, but the extended registers cannot.
571 We assume that the mask already takes that into account. For instance,
572 bits 14 to 17 must have the same value. */
575 mn10300_print_reg_list (FILE *file, int mask)
583 for (i = 0; i < FIRST_EXTENDED_REGNUM; i++)
584 if ((mask & (1 << i)) != 0)
588 fputs (reg_names [i], file);
592 if ((mask & 0x3c000) != 0)
594 gcc_assert ((mask & 0x3c000) == 0x3c000);
597 fputs ("exreg1", file);
604 /* If the MDR register is never clobbered, we can use the RETF instruction
605 which takes the address from the MDR register. This is 3 cycles faster
606 than having to load the address from the stack. */
609 mn10300_can_use_retf_insn (void)
611 /* Don't bother if we're not optimizing. In this case we won't
612 have proper access to df_regs_ever_live_p. */
616 /* EH returns alter the saved return address; MDR is not current. */
617 if (crtl->calls_eh_return)
620 /* Obviously not if MDR is ever clobbered. */
621 if (df_regs_ever_live_p (MDR_REG))
624 /* ??? Careful not to use this during expand_epilogue etc. */
625 gcc_assert (!in_sequence_p ());
626 return leaf_function_p ();
630 mn10300_can_use_rets_insn (void)
632 return !mn10300_initial_offset (ARG_POINTER_REGNUM, STACK_POINTER_REGNUM);
635 /* Returns the set of live, callee-saved registers as a bitmask. The
636 callee-saved extended registers cannot be stored individually, so
637 all of them will be included in the mask if any one of them is used. */
640 mn10300_get_live_callee_saved_regs (void)
646 for (i = 0; i <= LAST_EXTENDED_REGNUM; i++)
647 if (df_regs_ever_live_p (i) && ! call_really_used_regs[i])
649 if ((mask & 0x3c000) != 0)
658 RTX_FRAME_RELATED_P (r) = 1;
662 /* Generate an instruction that pushes several registers onto the stack.
663 Register K will be saved if bit K in MASK is set. The function does
664 nothing if MASK is zero.
666 To be compatible with the "movm" instruction, the lowest-numbered
667 register must be stored in the lowest slot. If MASK is the set
668 { R1,...,RN }, where R1...RN are ordered least first, the generated
669 instruction will have the form:
672 (set (reg:SI 9) (plus:SI (reg:SI 9) (const_int -N*4)))
673 (set (mem:SI (plus:SI (reg:SI 9)
677 (set (mem:SI (plus:SI (reg:SI 9)
682 mn10300_gen_multiple_store (unsigned int mask)
684 /* The order in which registers are stored, from SP-4 through SP-N*4. */
685 static const unsigned int store_order[8] = {
686 /* e2, e3: never saved */
687 FIRST_EXTENDED_REGNUM + 4,
688 FIRST_EXTENDED_REGNUM + 5,
689 FIRST_EXTENDED_REGNUM + 6,
690 FIRST_EXTENDED_REGNUM + 7,
691 /* e0, e1, mdrq, mcrh, mcrl, mcvf: never saved. */
692 FIRST_DATA_REGNUM + 2,
693 FIRST_DATA_REGNUM + 3,
694 FIRST_ADDRESS_REGNUM + 2,
695 FIRST_ADDRESS_REGNUM + 3,
696 /* d0, d1, a0, a1, mdr, lir, lar: never saved. */
706 for (i = count = 0; i < ARRAY_SIZE(store_order); ++i)
708 unsigned regno = store_order[i];
710 if (((mask >> regno) & 1) == 0)
714 x = plus_constant (stack_pointer_rtx, count * -4);
715 x = gen_frame_mem (SImode, x);
716 x = gen_rtx_SET (VOIDmode, x, gen_rtx_REG (SImode, regno));
719 /* Remove the register from the mask so that... */
720 mask &= ~(1u << regno);
723 /* ... we can make sure that we didn't try to use a register
724 not listed in the store order. */
725 gcc_assert (mask == 0);
727 /* Create the instruction that updates the stack pointer. */
728 x = plus_constant (stack_pointer_rtx, count * -4);
729 x = gen_rtx_SET (VOIDmode, stack_pointer_rtx, x);
732 /* We need one PARALLEL element to update the stack pointer and
733 an additional element for each register that is stored. */
734 x = gen_rtx_PARALLEL (VOIDmode, gen_rtvec_v (count + 1, elts));
739 mn10300_expand_prologue (void)
741 HOST_WIDE_INT size = mn10300_frame_size ();
743 /* If we use any of the callee-saved registers, save them now. */
744 mn10300_gen_multiple_store (mn10300_get_live_callee_saved_regs ());
746 if (TARGET_AM33_2 && fp_regs_to_save ())
748 int num_regs_to_save = fp_regs_to_save (), i;
754 save_sp_partial_merge,
758 unsigned int strategy_size = (unsigned)-1, this_strategy_size;
761 /* We have several different strategies to save FP registers.
762 We can store them using SP offsets, which is beneficial if
763 there are just a few registers to save, or we can use `a0' in
764 post-increment mode (`a0' is the only call-clobbered address
765 register that is never used to pass information to a
766 function). Furthermore, if we don't need a frame pointer, we
767 can merge the two SP adds into a single one, but this isn't
768 always beneficial; sometimes we can just split the two adds
769 so that we don't exceed a 16-bit constant size. The code
770 below will select which strategy to use, so as to generate
771 smallest code. Ties are broken in favor or shorter sequences
772 (in terms of number of instructions). */
774 #define SIZE_ADD_AX(S) ((((S) >= (1 << 15)) || ((S) < -(1 << 15))) ? 6 \
775 : (((S) >= (1 << 7)) || ((S) < -(1 << 7))) ? 4 : 2)
776 #define SIZE_ADD_SP(S) ((((S) >= (1 << 15)) || ((S) < -(1 << 15))) ? 6 \
777 : (((S) >= (1 << 7)) || ((S) < -(1 << 7))) ? 4 : 3)
779 /* We add 0 * (S) in two places to promote to the type of S,
780 so that all arms of the conditional have the same type. */
781 #define SIZE_FMOV_LIMIT(S,N,L,SIZE1,SIZE2,ELSE) \
782 (((S) >= (L)) ? 0 * (S) + (SIZE1) * (N) \
783 : ((S) + 4 * (N) >= (L)) ? (((L) - (S)) / 4 * (SIZE2) \
784 + ((S) + 4 * (N) - (L)) / 4 * (SIZE1)) \
786 #define SIZE_FMOV_SP_(S,N) \
787 (SIZE_FMOV_LIMIT ((S), (N), (1 << 24), 7, 6, \
788 SIZE_FMOV_LIMIT ((S), (N), (1 << 8), 6, 4, \
789 (S) ? 4 * (N) : 3 + 4 * ((N) - 1))))
790 #define SIZE_FMOV_SP(S,N) (SIZE_FMOV_SP_ ((unsigned HOST_WIDE_INT)(S), (N)))
792 /* Consider alternative save_sp_merge only if we don't need the
793 frame pointer and size is nonzero. */
794 if (! frame_pointer_needed && size)
796 /* Insn: add -(size + 4 * num_regs_to_save), sp. */
797 this_strategy_size = SIZE_ADD_SP (-(size + 4 * num_regs_to_save));
798 /* Insn: fmov fs#, (##, sp), for each fs# to be saved. */
799 this_strategy_size += SIZE_FMOV_SP (size, num_regs_to_save);
801 if (this_strategy_size < strategy_size)
803 strategy = save_sp_merge;
804 strategy_size = this_strategy_size;
808 /* Consider alternative save_sp_no_merge unconditionally. */
809 /* Insn: add -4 * num_regs_to_save, sp. */
810 this_strategy_size = SIZE_ADD_SP (-4 * num_regs_to_save);
811 /* Insn: fmov fs#, (##, sp), for each fs# to be saved. */
812 this_strategy_size += SIZE_FMOV_SP (0, num_regs_to_save);
815 /* Insn: add -size, sp. */
816 this_strategy_size += SIZE_ADD_SP (-size);
819 if (this_strategy_size < strategy_size)
821 strategy = save_sp_no_merge;
822 strategy_size = this_strategy_size;
825 /* Consider alternative save_sp_partial_merge only if we don't
826 need a frame pointer and size is reasonably large. */
827 if (! frame_pointer_needed && size + 4 * num_regs_to_save > 128)
829 /* Insn: add -128, sp. */
830 this_strategy_size = SIZE_ADD_SP (-128);
831 /* Insn: fmov fs#, (##, sp), for each fs# to be saved. */
832 this_strategy_size += SIZE_FMOV_SP (128 - 4 * num_regs_to_save,
836 /* Insn: add 128-size, sp. */
837 this_strategy_size += SIZE_ADD_SP (128 - size);
840 if (this_strategy_size < strategy_size)
842 strategy = save_sp_partial_merge;
843 strategy_size = this_strategy_size;
847 /* Consider alternative save_a0_merge only if we don't need a
848 frame pointer, size is nonzero and the user hasn't
849 changed the calling conventions of a0. */
850 if (! frame_pointer_needed && size
851 && call_really_used_regs [FIRST_ADDRESS_REGNUM]
852 && ! fixed_regs[FIRST_ADDRESS_REGNUM])
854 /* Insn: add -(size + 4 * num_regs_to_save), sp. */
855 this_strategy_size = SIZE_ADD_SP (-(size + 4 * num_regs_to_save));
856 /* Insn: mov sp, a0. */
857 this_strategy_size++;
860 /* Insn: add size, a0. */
861 this_strategy_size += SIZE_ADD_AX (size);
863 /* Insn: fmov fs#, (a0+), for each fs# to be saved. */
864 this_strategy_size += 3 * num_regs_to_save;
866 if (this_strategy_size < strategy_size)
868 strategy = save_a0_merge;
869 strategy_size = this_strategy_size;
873 /* Consider alternative save_a0_no_merge if the user hasn't
874 changed the calling conventions of a0. */
875 if (call_really_used_regs [FIRST_ADDRESS_REGNUM]
876 && ! fixed_regs[FIRST_ADDRESS_REGNUM])
878 /* Insn: add -4 * num_regs_to_save, sp. */
879 this_strategy_size = SIZE_ADD_SP (-4 * num_regs_to_save);
880 /* Insn: mov sp, a0. */
881 this_strategy_size++;
882 /* Insn: fmov fs#, (a0+), for each fs# to be saved. */
883 this_strategy_size += 3 * num_regs_to_save;
886 /* Insn: add -size, sp. */
887 this_strategy_size += SIZE_ADD_SP (-size);
890 if (this_strategy_size < strategy_size)
892 strategy = save_a0_no_merge;
893 strategy_size = this_strategy_size;
897 /* Emit the initial SP add, common to all strategies. */
900 case save_sp_no_merge:
901 case save_a0_no_merge:
902 F (emit_insn (gen_addsi3 (stack_pointer_rtx,
904 GEN_INT (-4 * num_regs_to_save))));
908 case save_sp_partial_merge:
909 F (emit_insn (gen_addsi3 (stack_pointer_rtx,
912 xsize = 128 - 4 * num_regs_to_save;
918 F (emit_insn (gen_addsi3 (stack_pointer_rtx,
920 GEN_INT (-(size + 4 * num_regs_to_save)))));
921 /* We'll have to adjust FP register saves according to the
924 /* Since we've already created the stack frame, don't do it
925 again at the end of the function. */
933 /* Now prepare register a0, if we have decided to use it. */
937 case save_sp_no_merge:
938 case save_sp_partial_merge:
943 case save_a0_no_merge:
944 reg = gen_rtx_REG (SImode, FIRST_ADDRESS_REGNUM);
945 F (emit_insn (gen_movsi (reg, stack_pointer_rtx)));
947 F (emit_insn (gen_addsi3 (reg, reg, GEN_INT (xsize))));
948 reg = gen_rtx_POST_INC (SImode, reg);
955 /* Now actually save the FP registers. */
956 for (i = FIRST_FP_REGNUM; i <= LAST_FP_REGNUM; ++i)
957 if (df_regs_ever_live_p (i) && ! call_really_used_regs [i])
965 /* If we aren't using `a0', use an SP offset. */
968 addr = gen_rtx_PLUS (SImode,
973 addr = stack_pointer_rtx;
978 F (emit_insn (gen_movsf (gen_rtx_MEM (SFmode, addr),
979 gen_rtx_REG (SFmode, i))));
983 /* Now put the frame pointer into the frame pointer register. */
984 if (frame_pointer_needed)
985 F (emit_move_insn (frame_pointer_rtx, stack_pointer_rtx));
987 /* Allocate stack for this frame. */
989 F (emit_insn (gen_addsi3 (stack_pointer_rtx,
993 if (flag_pic && df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM))
994 emit_insn (gen_load_pic ());
998 mn10300_expand_epilogue (void)
1000 HOST_WIDE_INT size = mn10300_frame_size ();
1001 int reg_save_bytes = REG_SAVE_BYTES;
1003 if (TARGET_AM33_2 && fp_regs_to_save ())
1005 int num_regs_to_save = fp_regs_to_save (), i;
1008 /* We have several options to restore FP registers. We could
1009 load them from SP offsets, but, if there are enough FP
1010 registers to restore, we win if we use a post-increment
1013 /* If we have a frame pointer, it's the best option, because we
1014 already know it has the value we want. */
1015 if (frame_pointer_needed)
1016 reg = gen_rtx_REG (SImode, FRAME_POINTER_REGNUM);
1017 /* Otherwise, we may use `a1', since it's call-clobbered and
1018 it's never used for return values. But only do so if it's
1019 smaller than using SP offsets. */
1022 enum { restore_sp_post_adjust,
1023 restore_sp_pre_adjust,
1024 restore_sp_partial_adjust,
1025 restore_a1 } strategy;
1026 unsigned int this_strategy_size, strategy_size = (unsigned)-1;
1028 /* Consider using sp offsets before adjusting sp. */
1029 /* Insn: fmov (##,sp),fs#, for each fs# to be restored. */
1030 this_strategy_size = SIZE_FMOV_SP (size, num_regs_to_save);
1031 /* If size is too large, we'll have to adjust SP with an
1033 if (size + 4 * num_regs_to_save + reg_save_bytes > 255)
1035 /* Insn: add size + 4 * num_regs_to_save, sp. */
1036 this_strategy_size += SIZE_ADD_SP (size + 4 * num_regs_to_save);
1038 /* If we don't have to restore any non-FP registers,
1039 we'll be able to save one byte by using rets. */
1040 if (! reg_save_bytes)
1041 this_strategy_size--;
1043 if (this_strategy_size < strategy_size)
1045 strategy = restore_sp_post_adjust;
1046 strategy_size = this_strategy_size;
1049 /* Consider using sp offsets after adjusting sp. */
1050 /* Insn: add size, sp. */
1051 this_strategy_size = SIZE_ADD_SP (size);
1052 /* Insn: fmov (##,sp),fs#, for each fs# to be restored. */
1053 this_strategy_size += SIZE_FMOV_SP (0, num_regs_to_save);
1054 /* We're going to use ret to release the FP registers
1055 save area, so, no savings. */
1057 if (this_strategy_size < strategy_size)
1059 strategy = restore_sp_pre_adjust;
1060 strategy_size = this_strategy_size;
1063 /* Consider using sp offsets after partially adjusting sp.
1064 When size is close to 32Kb, we may be able to adjust SP
1065 with an imm16 add instruction while still using fmov
1067 if (size + 4 * num_regs_to_save + reg_save_bytes > 255)
1069 /* Insn: add size + 4 * num_regs_to_save
1070 + reg_save_bytes - 252,sp. */
1071 this_strategy_size = SIZE_ADD_SP (size + 4 * num_regs_to_save
1072 + reg_save_bytes - 252);
1073 /* Insn: fmov (##,sp),fs#, fo each fs# to be restored. */
1074 this_strategy_size += SIZE_FMOV_SP (252 - reg_save_bytes
1075 - 4 * num_regs_to_save,
1077 /* We're going to use ret to release the FP registers
1078 save area, so, no savings. */
1080 if (this_strategy_size < strategy_size)
1082 strategy = restore_sp_partial_adjust;
1083 strategy_size = this_strategy_size;
1087 /* Consider using a1 in post-increment mode, as long as the
1088 user hasn't changed the calling conventions of a1. */
1089 if (call_really_used_regs [FIRST_ADDRESS_REGNUM + 1]
1090 && ! fixed_regs[FIRST_ADDRESS_REGNUM+1])
1092 /* Insn: mov sp,a1. */
1093 this_strategy_size = 1;
1096 /* Insn: add size,a1. */
1097 this_strategy_size += SIZE_ADD_AX (size);
1099 /* Insn: fmov (a1+),fs#, for each fs# to be restored. */
1100 this_strategy_size += 3 * num_regs_to_save;
1101 /* If size is large enough, we may be able to save a
1103 if (size + 4 * num_regs_to_save + reg_save_bytes > 255)
1105 /* Insn: mov a1,sp. */
1106 this_strategy_size += 2;
1108 /* If we don't have to restore any non-FP registers,
1109 we'll be able to save one byte by using rets. */
1110 if (! reg_save_bytes)
1111 this_strategy_size--;
1113 if (this_strategy_size < strategy_size)
1115 strategy = restore_a1;
1116 strategy_size = this_strategy_size;
1122 case restore_sp_post_adjust:
1125 case restore_sp_pre_adjust:
1126 emit_insn (gen_addsi3 (stack_pointer_rtx,
1132 case restore_sp_partial_adjust:
1133 emit_insn (gen_addsi3 (stack_pointer_rtx,
1135 GEN_INT (size + 4 * num_regs_to_save
1136 + reg_save_bytes - 252)));
1137 size = 252 - reg_save_bytes - 4 * num_regs_to_save;
1141 reg = gen_rtx_REG (SImode, FIRST_ADDRESS_REGNUM + 1);
1142 emit_insn (gen_movsi (reg, stack_pointer_rtx));
1144 emit_insn (gen_addsi3 (reg, reg, GEN_INT (size)));
1152 /* Adjust the selected register, if any, for post-increment. */
1154 reg = gen_rtx_POST_INC (SImode, reg);
1156 for (i = FIRST_FP_REGNUM; i <= LAST_FP_REGNUM; ++i)
1157 if (df_regs_ever_live_p (i) && ! call_really_used_regs [i])
1165 /* If we aren't using a post-increment register, use an
1167 addr = gen_rtx_PLUS (SImode,
1172 addr = stack_pointer_rtx;
1176 emit_insn (gen_movsf (gen_rtx_REG (SFmode, i),
1177 gen_rtx_MEM (SFmode, addr)));
1180 /* If we were using the restore_a1 strategy and the number of
1181 bytes to be released won't fit in the `ret' byte, copy `a1'
1182 to `sp', to avoid having to use `add' to adjust it. */
1183 if (! frame_pointer_needed && reg && size + reg_save_bytes > 255)
1185 emit_move_insn (stack_pointer_rtx, XEXP (reg, 0));
1190 /* Maybe cut back the stack, except for the register save area.
1192 If the frame pointer exists, then use the frame pointer to
1195 If the stack size + register save area is more than 255 bytes,
1196 then the stack must be cut back here since the size + register
1197 save size is too big for a ret/retf instruction.
1199 Else leave it alone, it will be cut back as part of the
1200 ret/retf instruction, or there wasn't any stack to begin with.
1202 Under no circumstances should the register save area be
1203 deallocated here, that would leave a window where an interrupt
1204 could occur and trash the register save area. */
1205 if (frame_pointer_needed)
1207 emit_move_insn (stack_pointer_rtx, frame_pointer_rtx);
1210 else if (size + reg_save_bytes > 255)
1212 emit_insn (gen_addsi3 (stack_pointer_rtx,
1218 /* Adjust the stack and restore callee-saved registers, if any. */
1219 if (mn10300_can_use_rets_insn ())
1220 emit_jump_insn (ret_rtx);
1222 emit_jump_insn (gen_return_ret (GEN_INT (size + REG_SAVE_BYTES)));
1225 /* Recognize the PARALLEL rtx generated by mn10300_gen_multiple_store().
1226 This function is for MATCH_PARALLEL and so assumes OP is known to be
1227 parallel. If OP is a multiple store, return a mask indicating which
1228 registers it saves. Return 0 otherwise. */
1231 mn10300_store_multiple_operation (rtx op,
1232 enum machine_mode mode ATTRIBUTE_UNUSED)
1240 count = XVECLEN (op, 0);
1244 /* Check that first instruction has the form (set (sp) (plus A B)) */
1245 elt = XVECEXP (op, 0, 0);
1246 if (GET_CODE (elt) != SET
1247 || (! REG_P (SET_DEST (elt)))
1248 || REGNO (SET_DEST (elt)) != STACK_POINTER_REGNUM
1249 || GET_CODE (SET_SRC (elt)) != PLUS)
1252 /* Check that A is the stack pointer and B is the expected stack size.
1253 For OP to match, each subsequent instruction should push a word onto
1254 the stack. We therefore expect the first instruction to create
1255 COUNT-1 stack slots. */
1256 elt = SET_SRC (elt);
1257 if ((! REG_P (XEXP (elt, 0)))
1258 || REGNO (XEXP (elt, 0)) != STACK_POINTER_REGNUM
1259 || (! CONST_INT_P (XEXP (elt, 1)))
1260 || INTVAL (XEXP (elt, 1)) != -(count - 1) * 4)
1264 for (i = 1; i < count; i++)
1266 /* Check that element i is a (set (mem M) R). */
1267 /* ??? Validate the register order a-la mn10300_gen_multiple_store.
1268 Remember: the ordering is *not* monotonic. */
1269 elt = XVECEXP (op, 0, i);
1270 if (GET_CODE (elt) != SET
1271 || (! MEM_P (SET_DEST (elt)))
1272 || (! REG_P (SET_SRC (elt))))
1275 /* Remember which registers are to be saved. */
1276 last = REGNO (SET_SRC (elt));
1277 mask |= (1 << last);
1279 /* Check that M has the form (plus (sp) (const_int -I*4)) */
1280 elt = XEXP (SET_DEST (elt), 0);
1281 if (GET_CODE (elt) != PLUS
1282 || (! REG_P (XEXP (elt, 0)))
1283 || REGNO (XEXP (elt, 0)) != STACK_POINTER_REGNUM
1284 || (! CONST_INT_P (XEXP (elt, 1)))
1285 || INTVAL (XEXP (elt, 1)) != -i * 4)
1289 /* All or none of the callee-saved extended registers must be in the set. */
1290 if ((mask & 0x3c000) != 0
1291 && (mask & 0x3c000) != 0x3c000)
1297 /* Implement TARGET_PREFERRED_RELOAD_CLASS. */
1300 mn10300_preferred_reload_class (rtx x, reg_class_t rclass)
1302 if (x == stack_pointer_rtx && rclass != SP_REGS)
1303 return (TARGET_AM33 ? GENERAL_REGS : ADDRESS_REGS);
1306 && !HARD_REGISTER_P (x))
1307 || (GET_CODE (x) == SUBREG
1308 && REG_P (SUBREG_REG (x))
1309 && !HARD_REGISTER_P (SUBREG_REG (x))))
1310 return LIMIT_RELOAD_CLASS (GET_MODE (x), rclass);
1315 /* Implement TARGET_PREFERRED_OUTPUT_RELOAD_CLASS. */
1318 mn10300_preferred_output_reload_class (rtx x, reg_class_t rclass)
1320 if (x == stack_pointer_rtx && rclass != SP_REGS)
1321 return (TARGET_AM33 ? GENERAL_REGS : ADDRESS_REGS);
1325 /* Implement TARGET_SECONDARY_RELOAD. */
1328 mn10300_secondary_reload (bool in_p, rtx x, reg_class_t rclass_i,
1329 enum machine_mode mode, secondary_reload_info *sri)
1331 enum reg_class rclass = (enum reg_class) rclass_i;
1332 enum reg_class xclass = NO_REGS;
1333 unsigned int xregno = INVALID_REGNUM;
1338 if (xregno >= FIRST_PSEUDO_REGISTER)
1339 xregno = true_regnum (x);
1340 if (xregno != INVALID_REGNUM)
1341 xclass = REGNO_REG_CLASS (xregno);
1346 /* Memory load/stores less than a full word wide can't have an
1347 address or stack pointer destination. They must use a data
1348 register as an intermediate register. */
1349 if (rclass != DATA_REGS
1350 && (mode == QImode || mode == HImode)
1351 && xclass == NO_REGS)
1354 /* We can only move SP to/from an address register. */
1356 && rclass == SP_REGS
1357 && xclass != ADDRESS_REGS)
1358 return ADDRESS_REGS;
1360 && xclass == SP_REGS
1361 && rclass != ADDRESS_REGS
1362 && rclass != SP_OR_ADDRESS_REGS)
1363 return ADDRESS_REGS;
1366 /* We can't directly load sp + const_int into a register;
1367 we must use an address register as an scratch. */
1369 && rclass != SP_REGS
1370 && rclass != SP_OR_ADDRESS_REGS
1371 && rclass != SP_OR_GENERAL_REGS
1372 && GET_CODE (x) == PLUS
1373 && (XEXP (x, 0) == stack_pointer_rtx
1374 || XEXP (x, 1) == stack_pointer_rtx))
1376 sri->icode = CODE_FOR_reload_plus_sp_const;
1380 /* We can only move MDR to/from a data register. */
1381 if (rclass == MDR_REGS && xclass != DATA_REGS)
1383 if (xclass == MDR_REGS && rclass != DATA_REGS)
1386 /* We can't load/store an FP register from a constant address. */
1388 && (rclass == FP_REGS || xclass == FP_REGS)
1389 && (xclass == NO_REGS || rclass == NO_REGS))
1393 if (xregno >= FIRST_PSEUDO_REGISTER && xregno != INVALID_REGNUM)
1395 addr = reg_equiv_mem (xregno);
1397 addr = XEXP (addr, 0);
1402 if (addr && CONSTANT_ADDRESS_P (addr))
1403 return GENERAL_REGS;
1406 /* Otherwise assume no secondary reloads are needed. */
1411 mn10300_frame_size (void)
1413 /* size includes the fixed stack space needed for function calls. */
1414 int size = get_frame_size () + crtl->outgoing_args_size;
1416 /* And space for the return pointer. */
1417 size += crtl->outgoing_args_size ? 4 : 0;
1423 mn10300_initial_offset (int from, int to)
1427 gcc_assert (from == ARG_POINTER_REGNUM || from == FRAME_POINTER_REGNUM);
1428 gcc_assert (to == FRAME_POINTER_REGNUM || to == STACK_POINTER_REGNUM);
1430 if (to == STACK_POINTER_REGNUM)
1431 diff = mn10300_frame_size ();
1433 /* The difference between the argument pointer and the frame pointer
1434 is the size of the callee register save area. */
1435 if (from == ARG_POINTER_REGNUM)
1437 diff += REG_SAVE_BYTES;
1438 diff += 4 * fp_regs_to_save ();
1444 /* Worker function for TARGET_RETURN_IN_MEMORY. */
1447 mn10300_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED)
1449 /* Return values > 8 bytes in length in memory. */
1450 return (int_size_in_bytes (type) > 8
1451 || int_size_in_bytes (type) == 0
1452 || TYPE_MODE (type) == BLKmode);
1455 /* Flush the argument registers to the stack for a stdarg function;
1456 return the new argument pointer. */
1458 mn10300_builtin_saveregs (void)
1461 tree fntype = TREE_TYPE (current_function_decl);
1462 int argadj = ((!stdarg_p (fntype))
1463 ? UNITS_PER_WORD : 0);
1464 alias_set_type set = get_varargs_alias_set ();
1467 offset = plus_constant (crtl->args.arg_offset_rtx, argadj);
1469 offset = crtl->args.arg_offset_rtx;
1471 mem = gen_rtx_MEM (SImode, crtl->args.internal_arg_pointer);
1472 set_mem_alias_set (mem, set);
1473 emit_move_insn (mem, gen_rtx_REG (SImode, 0));
1475 mem = gen_rtx_MEM (SImode,
1476 plus_constant (crtl->args.internal_arg_pointer, 4));
1477 set_mem_alias_set (mem, set);
1478 emit_move_insn (mem, gen_rtx_REG (SImode, 1));
1480 return copy_to_reg (expand_binop (Pmode, add_optab,
1481 crtl->args.internal_arg_pointer,
1482 offset, 0, 0, OPTAB_LIB_WIDEN));
1486 mn10300_va_start (tree valist, rtx nextarg)
1488 nextarg = expand_builtin_saveregs ();
1489 std_expand_builtin_va_start (valist, nextarg);
1492 /* Return true when a parameter should be passed by reference. */
1495 mn10300_pass_by_reference (cumulative_args_t cum ATTRIBUTE_UNUSED,
1496 enum machine_mode mode, const_tree type,
1497 bool named ATTRIBUTE_UNUSED)
1499 unsigned HOST_WIDE_INT size;
1502 size = int_size_in_bytes (type);
1504 size = GET_MODE_SIZE (mode);
1506 return (size > 8 || size == 0);
1509 /* Return an RTX to represent where a value with mode MODE will be returned
1510 from a function. If the result is NULL_RTX, the argument is pushed. */
1513 mn10300_function_arg (cumulative_args_t cum_v, enum machine_mode mode,
1514 const_tree type, bool named ATTRIBUTE_UNUSED)
1516 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
1517 rtx result = NULL_RTX;
1520 /* We only support using 2 data registers as argument registers. */
1523 /* Figure out the size of the object to be passed. */
1524 if (mode == BLKmode)
1525 size = int_size_in_bytes (type);
1527 size = GET_MODE_SIZE (mode);
1529 cum->nbytes = (cum->nbytes + 3) & ~3;
1531 /* Don't pass this arg via a register if all the argument registers
1533 if (cum->nbytes > nregs * UNITS_PER_WORD)
1536 /* Don't pass this arg via a register if it would be split between
1537 registers and memory. */
1538 if (type == NULL_TREE
1539 && cum->nbytes + size > nregs * UNITS_PER_WORD)
1542 switch (cum->nbytes / UNITS_PER_WORD)
1545 result = gen_rtx_REG (mode, FIRST_ARGUMENT_REGNUM);
1548 result = gen_rtx_REG (mode, FIRST_ARGUMENT_REGNUM + 1);
1557 /* Update the data in CUM to advance over an argument
1558 of mode MODE and data type TYPE.
1559 (TYPE is null for libcalls where that information may not be available.) */
1562 mn10300_function_arg_advance (cumulative_args_t cum_v, enum machine_mode mode,
1563 const_tree type, bool named ATTRIBUTE_UNUSED)
1565 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
1567 cum->nbytes += (mode != BLKmode
1568 ? (GET_MODE_SIZE (mode) + 3) & ~3
1569 : (int_size_in_bytes (type) + 3) & ~3);
1572 /* Return the number of bytes of registers to use for an argument passed
1573 partially in registers and partially in memory. */
1576 mn10300_arg_partial_bytes (cumulative_args_t cum_v, enum machine_mode mode,
1577 tree type, bool named ATTRIBUTE_UNUSED)
1579 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
1582 /* We only support using 2 data registers as argument registers. */
1585 /* Figure out the size of the object to be passed. */
1586 if (mode == BLKmode)
1587 size = int_size_in_bytes (type);
1589 size = GET_MODE_SIZE (mode);
1591 cum->nbytes = (cum->nbytes + 3) & ~3;
1593 /* Don't pass this arg via a register if all the argument registers
1595 if (cum->nbytes > nregs * UNITS_PER_WORD)
1598 if (cum->nbytes + size <= nregs * UNITS_PER_WORD)
1601 /* Don't pass this arg via a register if it would be split between
1602 registers and memory. */
1603 if (type == NULL_TREE
1604 && cum->nbytes + size > nregs * UNITS_PER_WORD)
1607 return nregs * UNITS_PER_WORD - cum->nbytes;
1610 /* Return the location of the function's value. This will be either
1611 $d0 for integer functions, $a0 for pointers, or a PARALLEL of both
1612 $d0 and $a0 if the -mreturn-pointer-on-do flag is set. Note that
1613 we only return the PARALLEL for outgoing values; we do not want
1614 callers relying on this extra copy. */
1617 mn10300_function_value (const_tree valtype,
1618 const_tree fn_decl_or_type ATTRIBUTE_UNUSED,
1622 enum machine_mode mode = TYPE_MODE (valtype);
1624 if (! POINTER_TYPE_P (valtype))
1625 return gen_rtx_REG (mode, FIRST_DATA_REGNUM);
1626 else if (! TARGET_PTR_A0D0 || ! outgoing
1627 || cfun->returns_struct)
1628 return gen_rtx_REG (mode, FIRST_ADDRESS_REGNUM);
1630 rv = gen_rtx_PARALLEL (mode, rtvec_alloc (2));
1632 = gen_rtx_EXPR_LIST (VOIDmode,
1633 gen_rtx_REG (mode, FIRST_ADDRESS_REGNUM),
1637 = gen_rtx_EXPR_LIST (VOIDmode,
1638 gen_rtx_REG (mode, FIRST_DATA_REGNUM),
1643 /* Implements TARGET_LIBCALL_VALUE. */
1646 mn10300_libcall_value (enum machine_mode mode,
1647 const_rtx fun ATTRIBUTE_UNUSED)
1649 return gen_rtx_REG (mode, FIRST_DATA_REGNUM);
1652 /* Implements FUNCTION_VALUE_REGNO_P. */
1655 mn10300_function_value_regno_p (const unsigned int regno)
1657 return (regno == FIRST_DATA_REGNUM || regno == FIRST_ADDRESS_REGNUM);
1660 /* Output an addition operation. */
1663 mn10300_output_add (rtx operands[3], bool need_flags)
1665 rtx dest, src1, src2;
1666 unsigned int dest_regnum, src1_regnum, src2_regnum;
1667 enum reg_class src1_class, src2_class, dest_class;
1673 dest_regnum = true_regnum (dest);
1674 src1_regnum = true_regnum (src1);
1676 dest_class = REGNO_REG_CLASS (dest_regnum);
1677 src1_class = REGNO_REG_CLASS (src1_regnum);
1679 if (CONST_INT_P (src2))
1681 gcc_assert (dest_regnum == src1_regnum);
1683 if (src2 == const1_rtx && !need_flags)
1685 if (INTVAL (src2) == 4 && !need_flags && dest_class != DATA_REGS)
1688 gcc_assert (!need_flags || dest_class != SP_REGS);
1691 else if (CONSTANT_P (src2))
1694 src2_regnum = true_regnum (src2);
1695 src2_class = REGNO_REG_CLASS (src2_regnum);
1697 if (dest_regnum == src1_regnum)
1699 if (dest_regnum == src2_regnum)
1702 /* The rest of the cases are reg = reg+reg. For AM33, we can implement
1703 this directly, as below, but when optimizing for space we can sometimes
1704 do better by using a mov+add. For MN103, we claimed that we could
1705 implement a three-operand add because the various move and add insns
1706 change sizes across register classes, and we can often do better than
1707 reload in choosing which operand to move. */
1708 if (TARGET_AM33 && optimize_insn_for_speed_p ())
1709 return "add %2,%1,%0";
1711 /* Catch cases where no extended register was used. */
1712 if (src1_class != EXTENDED_REGS
1713 && src2_class != EXTENDED_REGS
1714 && dest_class != EXTENDED_REGS)
1716 /* We have to copy one of the sources into the destination, then
1717 add the other source to the destination.
1719 Carefully select which source to copy to the destination; a
1720 naive implementation will waste a byte when the source classes
1721 are different and the destination is an address register.
1722 Selecting the lowest cost register copy will optimize this
1724 if (src1_class == dest_class)
1725 return "mov %1,%0\n\tadd %2,%0";
1727 return "mov %2,%0\n\tadd %1,%0";
1730 /* At least one register is an extended register. */
1732 /* The three operand add instruction on the am33 is a win iff the
1733 output register is an extended register, or if both source
1734 registers are extended registers. */
1735 if (dest_class == EXTENDED_REGS || src1_class == src2_class)
1736 return "add %2,%1,%0";
1738 /* It is better to copy one of the sources to the destination, then
1739 perform a 2 address add. The destination in this case must be
1740 an address or data register and one of the sources must be an
1741 extended register and the remaining source must not be an extended
1744 The best code for this case is to copy the extended reg to the
1745 destination, then emit a two address add. */
1746 if (src1_class == EXTENDED_REGS)
1747 return "mov %1,%0\n\tadd %2,%0";
1749 return "mov %2,%0\n\tadd %1,%0";
1752 /* Return 1 if X contains a symbolic expression. We know these
1753 expressions will have one of a few well defined forms, so
1754 we need only check those forms. */
1757 mn10300_symbolic_operand (rtx op,
1758 enum machine_mode mode ATTRIBUTE_UNUSED)
1760 switch (GET_CODE (op))
1767 return ((GET_CODE (XEXP (op, 0)) == SYMBOL_REF
1768 || GET_CODE (XEXP (op, 0)) == LABEL_REF)
1769 && CONST_INT_P (XEXP (op, 1)));
1775 /* Try machine dependent ways of modifying an illegitimate address
1776 to be legitimate. If we find one, return the new valid address.
1777 This macro is used in only one place: `memory_address' in explow.c.
1779 OLDX is the address as it was before break_out_memory_refs was called.
1780 In some cases it is useful to look at this to decide what needs to be done.
1782 Normally it is always safe for this macro to do nothing. It exists to
1783 recognize opportunities to optimize the output.
1785 But on a few ports with segmented architectures and indexed addressing
1786 (mn10300, hppa) it is used to rewrite certain problematical addresses. */
1789 mn10300_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
1790 enum machine_mode mode ATTRIBUTE_UNUSED)
1792 if (flag_pic && ! mn10300_legitimate_pic_operand_p (x))
1793 x = mn10300_legitimize_pic_address (oldx, NULL_RTX);
1795 /* Uh-oh. We might have an address for x[n-100000]. This needs
1796 special handling to avoid creating an indexed memory address
1797 with x-100000 as the base. */
1798 if (GET_CODE (x) == PLUS
1799 && mn10300_symbolic_operand (XEXP (x, 1), VOIDmode))
1801 /* Ugly. We modify things here so that the address offset specified
1802 by the index expression is computed first, then added to x to form
1803 the entire address. */
1805 rtx regx1, regy1, regy2, y;
1807 /* Strip off any CONST. */
1809 if (GET_CODE (y) == CONST)
1812 if (GET_CODE (y) == PLUS || GET_CODE (y) == MINUS)
1814 regx1 = force_reg (Pmode, force_operand (XEXP (x, 0), 0));
1815 regy1 = force_reg (Pmode, force_operand (XEXP (y, 0), 0));
1816 regy2 = force_reg (Pmode, force_operand (XEXP (y, 1), 0));
1817 regx1 = force_reg (Pmode,
1818 gen_rtx_fmt_ee (GET_CODE (y), Pmode, regx1,
1820 return force_reg (Pmode, gen_rtx_PLUS (Pmode, regx1, regy1));
1826 /* Convert a non-PIC address in `orig' to a PIC address using @GOT or
1827 @GOTOFF in `reg'. */
1830 mn10300_legitimize_pic_address (rtx orig, rtx reg)
1834 if (GET_CODE (orig) == LABEL_REF
1835 || (GET_CODE (orig) == SYMBOL_REF
1836 && (CONSTANT_POOL_ADDRESS_P (orig)
1837 || ! MN10300_GLOBAL_P (orig))))
1840 reg = gen_reg_rtx (Pmode);
1842 x = gen_rtx_UNSPEC (SImode, gen_rtvec (1, orig), UNSPEC_GOTOFF);
1843 x = gen_rtx_CONST (SImode, x);
1844 emit_move_insn (reg, x);
1846 x = emit_insn (gen_addsi3 (reg, reg, pic_offset_table_rtx));
1848 else if (GET_CODE (orig) == SYMBOL_REF)
1851 reg = gen_reg_rtx (Pmode);
1853 x = gen_rtx_UNSPEC (SImode, gen_rtvec (1, orig), UNSPEC_GOT);
1854 x = gen_rtx_CONST (SImode, x);
1855 x = gen_rtx_PLUS (SImode, pic_offset_table_rtx, x);
1856 x = gen_const_mem (SImode, x);
1858 x = emit_move_insn (reg, x);
1863 set_unique_reg_note (x, REG_EQUAL, orig);
1867 /* Return zero if X references a SYMBOL_REF or LABEL_REF whose symbol
1868 isn't protected by a PIC unspec; nonzero otherwise. */
1871 mn10300_legitimate_pic_operand_p (rtx x)
1876 if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF)
1879 if (GET_CODE (x) == UNSPEC
1880 && (XINT (x, 1) == UNSPEC_PIC
1881 || XINT (x, 1) == UNSPEC_GOT
1882 || XINT (x, 1) == UNSPEC_GOTOFF
1883 || XINT (x, 1) == UNSPEC_PLT
1884 || XINT (x, 1) == UNSPEC_GOTSYM_OFF))
1887 fmt = GET_RTX_FORMAT (GET_CODE (x));
1888 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
1894 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
1895 if (! mn10300_legitimate_pic_operand_p (XVECEXP (x, i, j)))
1898 else if (fmt[i] == 'e'
1899 && ! mn10300_legitimate_pic_operand_p (XEXP (x, i)))
1906 /* Return TRUE if the address X, taken from a (MEM:MODE X) rtx, is
1907 legitimate, and FALSE otherwise.
1909 On the mn10300, the value in the address register must be
1910 in the same memory space/segment as the effective address.
1912 This is problematical for reload since it does not understand
1913 that base+index != index+base in a memory reference.
1915 Note it is still possible to use reg+reg addressing modes,
1916 it's just much more difficult. For a discussion of a possible
1917 workaround and solution, see the comments in pa.c before the
1918 function record_unscaled_index_insn_codes. */
1921 mn10300_legitimate_address_p (enum machine_mode mode, rtx x, bool strict)
1925 if (CONSTANT_ADDRESS_P (x))
1926 return !flag_pic || mn10300_legitimate_pic_operand_p (x);
1928 if (RTX_OK_FOR_BASE_P (x, strict))
1931 if (TARGET_AM33 && (mode == SImode || mode == SFmode || mode == HImode))
1933 if (GET_CODE (x) == POST_INC)
1934 return RTX_OK_FOR_BASE_P (XEXP (x, 0), strict);
1935 if (GET_CODE (x) == POST_MODIFY)
1936 return (RTX_OK_FOR_BASE_P (XEXP (x, 0), strict)
1937 && CONSTANT_ADDRESS_P (XEXP (x, 1)));
1940 if (GET_CODE (x) != PLUS)
1944 index = XEXP (x, 1);
1950 /* ??? Without AM33 generalized (Ri,Rn) addressing, reg+reg
1951 addressing is hard to satisfy. */
1955 return (REGNO_GENERAL_P (REGNO (base), strict)
1956 && REGNO_GENERAL_P (REGNO (index), strict));
1959 if (!REGNO_STRICT_OK_FOR_BASE_P (REGNO (base), strict))
1962 if (CONST_INT_P (index))
1963 return IN_RANGE (INTVAL (index), -1 - 0x7fffffff, 0x7fffffff);
1965 if (CONSTANT_ADDRESS_P (index))
1966 return !flag_pic || mn10300_legitimate_pic_operand_p (index);
1972 mn10300_regno_in_class_p (unsigned regno, int rclass, bool strict)
1974 if (regno >= FIRST_PSEUDO_REGISTER)
1980 regno = reg_renumber[regno];
1981 if (regno == INVALID_REGNUM)
1984 return TEST_HARD_REG_BIT (reg_class_contents[rclass], regno);
1988 mn10300_legitimize_reload_address (rtx x,
1989 enum machine_mode mode ATTRIBUTE_UNUSED,
1990 int opnum, int type,
1991 int ind_levels ATTRIBUTE_UNUSED)
1993 bool any_change = false;
1995 /* See above re disabling reg+reg addressing for MN103. */
1999 if (GET_CODE (x) != PLUS)
2002 if (XEXP (x, 0) == stack_pointer_rtx)
2004 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
2005 GENERAL_REGS, GET_MODE (x), VOIDmode, 0, 0,
2006 opnum, (enum reload_type) type);
2009 if (XEXP (x, 1) == stack_pointer_rtx)
2011 push_reload (XEXP (x, 1), NULL_RTX, &XEXP (x, 1), NULL,
2012 GENERAL_REGS, GET_MODE (x), VOIDmode, 0, 0,
2013 opnum, (enum reload_type) type);
2017 return any_change ? x : NULL_RTX;
2020 /* Implement TARGET_LEGITIMATE_CONSTANT_P. Returns TRUE if X is a valid
2021 constant. Note that some "constants" aren't valid, such as TLS
2022 symbols and unconverted GOT-based references, so we eliminate
2026 mn10300_legitimate_constant_p (enum machine_mode mode ATTRIBUTE_UNUSED, rtx x)
2028 switch (GET_CODE (x))
2033 if (GET_CODE (x) == PLUS)
2035 if (! CONST_INT_P (XEXP (x, 1)))
2040 /* Only some unspecs are valid as "constants". */
2041 if (GET_CODE (x) == UNSPEC)
2043 switch (XINT (x, 1))
2055 /* We must have drilled down to a symbol. */
2056 if (! mn10300_symbolic_operand (x, Pmode))
2067 /* Undo pic address legitimization for the benefit of debug info. */
2070 mn10300_delegitimize_address (rtx orig_x)
2072 rtx x = orig_x, ret, addend = NULL;
2077 if (GET_CODE (x) != PLUS || GET_MODE (x) != Pmode)
2080 if (XEXP (x, 0) == pic_offset_table_rtx)
2082 /* With the REG+REG addressing of AM33, var-tracking can re-assemble
2083 some odd-looking "addresses" that were never valid in the first place.
2084 We need to look harder to avoid warnings being emitted. */
2085 else if (GET_CODE (XEXP (x, 0)) == PLUS)
2087 rtx x0 = XEXP (x, 0);
2088 rtx x00 = XEXP (x0, 0);
2089 rtx x01 = XEXP (x0, 1);
2091 if (x00 == pic_offset_table_rtx)
2093 else if (x01 == pic_offset_table_rtx)
2103 if (GET_CODE (x) != CONST)
2106 if (GET_CODE (x) != UNSPEC)
2109 ret = XVECEXP (x, 0, 0);
2110 if (XINT (x, 1) == UNSPEC_GOTOFF)
2112 else if (XINT (x, 1) == UNSPEC_GOT)
2117 gcc_assert (GET_CODE (ret) == SYMBOL_REF);
2118 if (need_mem != MEM_P (orig_x))
2120 if (need_mem && addend)
2123 ret = gen_rtx_PLUS (Pmode, addend, ret);
2127 /* For addresses, costs are relative to "MOV (Rm),Rn". For AM33 this is
2128 the 3-byte fully general instruction; for MN103 this is the 2-byte form
2129 with an address register. */
2132 mn10300_address_cost (rtx x, bool speed)
2137 switch (GET_CODE (x))
2142 /* We assume all of these require a 32-bit constant, even though
2143 some symbol and label references can be relaxed. */
2144 return speed ? 1 : 4;
2152 /* Assume any symbolic offset is a 32-bit constant. */
2153 i = (CONST_INT_P (XEXP (x, 1)) ? INTVAL (XEXP (x, 1)) : 0x12345678);
2154 if (IN_RANGE (i, -128, 127))
2155 return speed ? 0 : 1;
2158 if (IN_RANGE (i, -0x800000, 0x7fffff))
2164 index = XEXP (x, 1);
2165 if (register_operand (index, SImode))
2167 /* Attempt to minimize the number of registers in the address.
2168 This is similar to what other ports do. */
2169 if (register_operand (base, SImode))
2173 index = XEXP (x, 0);
2176 /* Assume any symbolic offset is a 32-bit constant. */
2177 i = (CONST_INT_P (XEXP (x, 1)) ? INTVAL (XEXP (x, 1)) : 0x12345678);
2178 if (IN_RANGE (i, -128, 127))
2179 return speed ? 0 : 1;
2180 if (IN_RANGE (i, -32768, 32767))
2181 return speed ? 0 : 2;
2182 return speed ? 2 : 6;
2185 return rtx_cost (x, MEM, 0, speed);
2189 /* Implement the TARGET_REGISTER_MOVE_COST hook.
2191 Recall that the base value of 2 is required by assumptions elsewhere
2192 in the body of the compiler, and that cost 2 is special-cased as an
2193 early exit from reload meaning no work is required. */
2196 mn10300_register_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED,
2197 reg_class_t ifrom, reg_class_t ito)
2199 enum reg_class from = (enum reg_class) ifrom;
2200 enum reg_class to = (enum reg_class) ito;
2201 enum reg_class scratch, test;
2203 /* Simplify the following code by unifying the fp register classes. */
2204 if (to == FP_ACC_REGS)
2206 if (from == FP_ACC_REGS)
2209 /* Diagnose invalid moves by costing them as two moves. */
2214 scratch = (TARGET_AM33 ? GENERAL_REGS : ADDRESS_REGS);
2215 else if (to == MDR_REGS)
2216 scratch = DATA_REGS;
2217 else if (to == FP_REGS && to != from)
2218 scratch = GENERAL_REGS;
2222 if (from == SP_REGS)
2223 scratch = (TARGET_AM33 ? GENERAL_REGS : ADDRESS_REGS);
2224 else if (from == MDR_REGS)
2225 scratch = DATA_REGS;
2226 else if (from == FP_REGS && to != from)
2227 scratch = GENERAL_REGS;
2229 if (scratch != NO_REGS && !reg_class_subset_p (test, scratch))
2230 return (mn10300_register_move_cost (VOIDmode, from, scratch)
2231 + mn10300_register_move_cost (VOIDmode, scratch, to));
2233 /* From here on, all we need consider are legal combinations. */
2237 /* The scale here is bytes * 2. */
2239 if (from == to && (to == ADDRESS_REGS || to == DATA_REGS))
2242 if (from == SP_REGS)
2243 return (to == ADDRESS_REGS ? 2 : 6);
2245 /* For MN103, all remaining legal moves are two bytes. */
2250 return (from == ADDRESS_REGS ? 4 : 6);
2252 if ((from == ADDRESS_REGS || from == DATA_REGS)
2253 && (to == ADDRESS_REGS || to == DATA_REGS))
2256 if (to == EXTENDED_REGS)
2257 return (to == from ? 6 : 4);
2259 /* What's left are SP_REGS, FP_REGS, or combinations of the above. */
2264 /* The scale here is cycles * 2. */
2268 if (from == FP_REGS)
2271 /* All legal moves between integral registers are single cycle. */
2276 /* Implement the TARGET_MEMORY_MOVE_COST hook.
2278 Given lack of the form of the address, this must be speed-relative,
2279 though we should never be less expensive than a size-relative register
2280 move cost above. This is not a problem. */
2283 mn10300_memory_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED,
2284 reg_class_t iclass, bool in ATTRIBUTE_UNUSED)
2286 enum reg_class rclass = (enum reg_class) iclass;
2288 if (rclass == FP_REGS)
2293 /* Implement the TARGET_RTX_COSTS hook.
2295 Speed-relative costs are relative to COSTS_N_INSNS, which is intended
2296 to represent cycles. Size-relative costs are in bytes. */
2299 mn10300_rtx_costs (rtx x, int code, int outer_code, int opno ATTRIBUTE_UNUSED,
2300 int *ptotal, bool speed)
2302 /* This value is used for SYMBOL_REF etc where we want to pretend
2303 we have a full 32-bit constant. */
2304 HOST_WIDE_INT i = 0x12345678;
2314 if (outer_code == SET)
2316 /* 16-bit integer loads have latency 1, 32-bit loads 2. */
2317 if (IN_RANGE (i, -32768, 32767))
2318 total = COSTS_N_INSNS (1);
2320 total = COSTS_N_INSNS (2);
2324 /* 16-bit integer operands don't affect latency;
2325 24-bit and 32-bit operands add a cycle. */
2326 if (IN_RANGE (i, -32768, 32767))
2329 total = COSTS_N_INSNS (1);
2334 if (outer_code == SET)
2338 else if (IN_RANGE (i, -128, 127))
2340 else if (IN_RANGE (i, -32768, 32767))
2347 /* Reference here is ADD An,Dn, vs ADD imm,Dn. */
2348 if (IN_RANGE (i, -128, 127))
2350 else if (IN_RANGE (i, -32768, 32767))
2352 else if (TARGET_AM33 && IN_RANGE (i, -0x01000000, 0x00ffffff))
2364 /* We assume all of these require a 32-bit constant, even though
2365 some symbol and label references can be relaxed. */
2369 switch (XINT (x, 1))
2375 case UNSPEC_GOTSYM_OFF:
2376 /* The PIC unspecs also resolve to a 32-bit constant. */
2380 /* Assume any non-listed unspec is some sort of arithmetic. */
2381 goto do_arith_costs;
2385 /* Notice the size difference of INC and INC4. */
2386 if (!speed && outer_code == SET && CONST_INT_P (XEXP (x, 1)))
2388 i = INTVAL (XEXP (x, 1));
2389 if (i == 1 || i == 4)
2391 total = 1 + rtx_cost (XEXP (x, 0), PLUS, 0, speed);
2395 goto do_arith_costs;
2409 total = (speed ? COSTS_N_INSNS (1) : 2);
2413 /* Notice the size difference of ASL2 and variants. */
2414 if (!speed && CONST_INT_P (XEXP (x, 1)))
2415 switch (INTVAL (XEXP (x, 1)))
2430 total = (speed ? COSTS_N_INSNS (1) : 3);
2434 total = (speed ? COSTS_N_INSNS (3) : 2);
2441 total = (speed ? COSTS_N_INSNS (39)
2442 /* Include space to load+retrieve MDR. */
2443 : code == MOD || code == UMOD ? 6 : 4);
2447 total = mn10300_address_cost (XEXP (x, 0), speed);
2449 total = COSTS_N_INSNS (2 + total);
2453 /* Probably not implemented. Assume external call. */
2454 total = (speed ? COSTS_N_INSNS (10) : 7);
2466 /* If using PIC, mark a SYMBOL_REF for a non-global symbol so that we
2467 may access it using GOTOFF instead of GOT. */
2470 mn10300_encode_section_info (tree decl, rtx rtl, int first)
2474 default_encode_section_info (decl, rtl, first);
2479 symbol = XEXP (rtl, 0);
2480 if (GET_CODE (symbol) != SYMBOL_REF)
2484 SYMBOL_REF_FLAG (symbol) = (*targetm.binds_local_p) (decl);
2487 /* Dispatch tables on the mn10300 are extremely expensive in terms of code
2488 and readonly data size. So we crank up the case threshold value to
2489 encourage a series of if/else comparisons to implement many small switch
2490 statements. In theory, this value could be increased much more if we
2491 were solely optimizing for space, but we keep it "reasonable" to avoid
2492 serious code efficiency lossage. */
2495 mn10300_case_values_threshold (void)
2500 /* Worker function for TARGET_TRAMPOLINE_INIT. */
2503 mn10300_trampoline_init (rtx m_tramp, tree fndecl, rtx chain_value)
2505 rtx mem, disp, fnaddr = XEXP (DECL_RTL (fndecl), 0);
2507 /* This is a strict alignment target, which means that we play
2508 some games to make sure that the locations at which we need
2509 to store <chain> and <disp> wind up at aligned addresses.
2512 0xfc 0xdd mov chain,a1
2514 0xf8 0xed 0x00 btst 0,d1
2518 Note that the two extra insns are effectively nops; they
2519 clobber the flags but do not affect the contents of D0 or D1. */
2521 disp = expand_binop (SImode, sub_optab, fnaddr,
2522 plus_constant (XEXP (m_tramp, 0), 11),
2523 NULL_RTX, 1, OPTAB_DIRECT);
2525 mem = adjust_address (m_tramp, SImode, 0);
2526 emit_move_insn (mem, gen_int_mode (0xddfc0028, SImode));
2527 mem = adjust_address (m_tramp, SImode, 4);
2528 emit_move_insn (mem, chain_value);
2529 mem = adjust_address (m_tramp, SImode, 8);
2530 emit_move_insn (mem, gen_int_mode (0xdc00edf8, SImode));
2531 mem = adjust_address (m_tramp, SImode, 12);
2532 emit_move_insn (mem, disp);
2535 /* Output the assembler code for a C++ thunk function.
2536 THUNK_DECL is the declaration for the thunk function itself, FUNCTION
2537 is the decl for the target function. DELTA is an immediate constant
2538 offset to be added to the THIS parameter. If VCALL_OFFSET is nonzero
2539 the word at the adjusted address *(*THIS' + VCALL_OFFSET) should be
2540 additionally added to THIS. Finally jump to the entry point of
2544 mn10300_asm_output_mi_thunk (FILE * file,
2545 tree thunk_fndecl ATTRIBUTE_UNUSED,
2546 HOST_WIDE_INT delta,
2547 HOST_WIDE_INT vcall_offset,
2552 /* Get the register holding the THIS parameter. Handle the case
2553 where there is a hidden first argument for a returned structure. */
2554 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
2555 _this = reg_names [FIRST_ARGUMENT_REGNUM + 1];
2557 _this = reg_names [FIRST_ARGUMENT_REGNUM];
2559 fprintf (file, "\t%s Thunk Entry Point:\n", ASM_COMMENT_START);
2562 fprintf (file, "\tadd %d, %s\n", (int) delta, _this);
2566 const char * scratch = reg_names [FIRST_ADDRESS_REGNUM + 1];
2568 fprintf (file, "\tmov %s, %s\n", _this, scratch);
2569 fprintf (file, "\tmov (%s), %s\n", scratch, scratch);
2570 fprintf (file, "\tadd %d, %s\n", (int) vcall_offset, scratch);
2571 fprintf (file, "\tmov (%s), %s\n", scratch, scratch);
2572 fprintf (file, "\tadd %s, %s\n", scratch, _this);
2575 fputs ("\tjmp ", file);
2576 assemble_name (file, XSTR (XEXP (DECL_RTL (function), 0), 0));
2580 /* Return true if mn10300_output_mi_thunk would be able to output the
2581 assembler code for the thunk function specified by the arguments
2582 it is passed, and false otherwise. */
2585 mn10300_can_output_mi_thunk (const_tree thunk_fndecl ATTRIBUTE_UNUSED,
2586 HOST_WIDE_INT delta ATTRIBUTE_UNUSED,
2587 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED,
2588 const_tree function ATTRIBUTE_UNUSED)
2594 mn10300_hard_regno_mode_ok (unsigned int regno, enum machine_mode mode)
2596 if (REGNO_REG_CLASS (regno) == FP_REGS
2597 || REGNO_REG_CLASS (regno) == FP_ACC_REGS)
2598 /* Do not store integer values in FP registers. */
2599 return GET_MODE_CLASS (mode) == MODE_FLOAT && ((regno & 1) == 0);
2601 if (((regno) & 1) == 0 || GET_MODE_SIZE (mode) == 4)
2604 if (REGNO_REG_CLASS (regno) == DATA_REGS
2605 || (TARGET_AM33 && REGNO_REG_CLASS (regno) == ADDRESS_REGS)
2606 || REGNO_REG_CLASS (regno) == EXTENDED_REGS)
2607 return GET_MODE_SIZE (mode) <= 4;
2613 mn10300_modes_tieable (enum machine_mode mode1, enum machine_mode mode2)
2615 if (GET_MODE_CLASS (mode1) == MODE_FLOAT
2616 && GET_MODE_CLASS (mode2) != MODE_FLOAT)
2619 if (GET_MODE_CLASS (mode2) == MODE_FLOAT
2620 && GET_MODE_CLASS (mode1) != MODE_FLOAT)
2625 || (GET_MODE_SIZE (mode1) <= 4 && GET_MODE_SIZE (mode2) <= 4))
2632 cc_flags_for_mode (enum machine_mode mode)
2637 return CC_FLAG_Z | CC_FLAG_N | CC_FLAG_C | CC_FLAG_V;
2639 return CC_FLAG_Z | CC_FLAG_N | CC_FLAG_C;
2641 return CC_FLAG_Z | CC_FLAG_N;
2650 cc_flags_for_code (enum rtx_code code)
2663 case GT: /* ~(Z|(N^V)) */
2664 case LE: /* Z|(N^V) */
2665 return CC_FLAG_Z | CC_FLAG_N | CC_FLAG_V;
2671 case GTU: /* ~(C | Z) */
2672 case LEU: /* C | Z */
2673 return CC_FLAG_Z | CC_FLAG_C;
2691 mn10300_select_cc_mode (enum rtx_code code, rtx x, rtx y ATTRIBUTE_UNUSED)
2695 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
2696 return CC_FLOATmode;
2698 req = cc_flags_for_code (code);
2700 if (req & CC_FLAG_V)
2702 if (req & CC_FLAG_C)
2708 is_load_insn (rtx insn)
2710 if (GET_CODE (PATTERN (insn)) != SET)
2713 return MEM_P (SET_SRC (PATTERN (insn)));
2717 is_store_insn (rtx insn)
2719 if (GET_CODE (PATTERN (insn)) != SET)
2722 return MEM_P (SET_DEST (PATTERN (insn)));
2725 /* Update scheduling costs for situations that cannot be
2726 described using the attributes and DFA machinery.
2727 DEP is the insn being scheduled.
2728 INSN is the previous insn.
2729 COST is the current cycle cost for DEP. */
2732 mn10300_adjust_sched_cost (rtx insn, rtx link, rtx dep, int cost)
2734 int timings = get_attr_timings (insn);
2739 if (GET_CODE (insn) == PARALLEL)
2740 insn = XVECEXP (insn, 0, 0);
2742 if (GET_CODE (dep) == PARALLEL)
2743 dep = XVECEXP (dep, 0, 0);
2745 /* For the AM34 a load instruction that follows a
2746 store instruction incurs an extra cycle of delay. */
2747 if (mn10300_tune_cpu == PROCESSOR_AM34
2748 && is_load_insn (dep)
2749 && is_store_insn (insn))
2752 /* For the AM34 a non-store, non-branch FPU insn that follows
2753 another FPU insn incurs a one cycle throughput increase. */
2754 else if (mn10300_tune_cpu == PROCESSOR_AM34
2755 && ! is_store_insn (insn)
2757 && GET_CODE (PATTERN (dep)) == SET
2758 && GET_CODE (PATTERN (insn)) == SET
2759 && GET_MODE_CLASS (GET_MODE (SET_SRC (PATTERN (dep)))) == MODE_FLOAT
2760 && GET_MODE_CLASS (GET_MODE (SET_SRC (PATTERN (insn)))) == MODE_FLOAT)
2763 /* Resolve the conflict described in section 1-7-4 of
2764 Chapter 3 of the MN103E Series Instruction Manual
2767 "When the preceeding instruction is a CPU load or
2768 store instruction, a following FPU instruction
2769 cannot be executed until the CPU completes the
2770 latency period even though there are no register
2771 or flag dependencies between them." */
2773 /* Only the AM33-2 (and later) CPUs have FPU instructions. */
2774 if (! TARGET_AM33_2)
2777 /* If a data dependence already exists then the cost is correct. */
2778 if (REG_NOTE_KIND (link) == 0)
2781 /* Check that the instruction about to scheduled is an FPU instruction. */
2782 if (GET_CODE (PATTERN (dep)) != SET)
2785 if (GET_MODE_CLASS (GET_MODE (SET_SRC (PATTERN (dep)))) != MODE_FLOAT)
2788 /* Now check to see if the previous instruction is a load or store. */
2789 if (! is_load_insn (insn) && ! is_store_insn (insn))
2792 /* XXX: Verify: The text of 1-7-4 implies that the restriction
2793 only applies when an INTEGER load/store preceeds an FPU
2794 instruction, but is this true ? For now we assume that it is. */
2795 if (GET_MODE_CLASS (GET_MODE (SET_SRC (PATTERN (insn)))) != MODE_INT)
2798 /* Extract the latency value from the timings attribute. */
2799 return timings < 100 ? (timings % 10) : (timings % 100);
2803 mn10300_conditional_register_usage (void)
2809 for (i = FIRST_EXTENDED_REGNUM;
2810 i <= LAST_EXTENDED_REGNUM; i++)
2811 fixed_regs[i] = call_used_regs[i] = 1;
2815 for (i = FIRST_FP_REGNUM;
2816 i <= LAST_FP_REGNUM; i++)
2817 fixed_regs[i] = call_used_regs[i] = 1;
2820 fixed_regs[PIC_OFFSET_TABLE_REGNUM] =
2821 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1;
2824 /* Worker function for TARGET_MD_ASM_CLOBBERS.
2825 We do this in the mn10300 backend to maintain source compatibility
2826 with the old cc0-based compiler. */
2829 mn10300_md_asm_clobbers (tree outputs ATTRIBUTE_UNUSED,
2830 tree inputs ATTRIBUTE_UNUSED,
2833 clobbers = tree_cons (NULL_TREE, build_string (5, "EPSW"),
2838 /* A helper function for splitting cbranch patterns after reload. */
2841 mn10300_split_cbranch (enum machine_mode cmp_mode, rtx cmp_op, rtx label_ref)
2845 flags = gen_rtx_REG (cmp_mode, CC_REG);
2846 x = gen_rtx_COMPARE (cmp_mode, XEXP (cmp_op, 0), XEXP (cmp_op, 1));
2847 x = gen_rtx_SET (VOIDmode, flags, x);
2850 x = gen_rtx_fmt_ee (GET_CODE (cmp_op), VOIDmode, flags, const0_rtx);
2851 x = gen_rtx_IF_THEN_ELSE (VOIDmode, x, label_ref, pc_rtx);
2852 x = gen_rtx_SET (VOIDmode, pc_rtx, x);
2856 /* A helper function for matching parallels that set the flags. */
2859 mn10300_match_ccmode (rtx insn, enum machine_mode cc_mode)
2862 enum machine_mode flags_mode;
2864 gcc_checking_assert (XVECLEN (PATTERN (insn), 0) == 2);
2866 op1 = XVECEXP (PATTERN (insn), 0, 1);
2867 gcc_checking_assert (GET_CODE (SET_SRC (op1)) == COMPARE);
2869 flags = SET_DEST (op1);
2870 flags_mode = GET_MODE (flags);
2872 if (GET_MODE (SET_SRC (op1)) != flags_mode)
2874 if (GET_MODE_CLASS (flags_mode) != MODE_CC)
2877 /* Ensure that the mode of FLAGS is compatible with CC_MODE. */
2878 if (cc_flags_for_mode (flags_mode) & ~cc_flags_for_mode (cc_mode))
2884 /* This function is used to help split:
2886 (set (reg) (and (reg) (int)))
2890 (set (reg) (shift (reg) (int))
2891 (set (reg) (shift (reg) (int))
2893 where the shitfs will be shorter than the "and" insn.
2895 It returns the number of bits that should be shifted. A positive
2896 values means that the low bits are to be cleared (and hence the
2897 shifts should be right followed by left) whereas a negative value
2898 means that the high bits are to be cleared (left followed by right).
2899 Zero is returned when it would not be economical to split the AND. */
2902 mn10300_split_and_operand_count (rtx op)
2904 HOST_WIDE_INT val = INTVAL (op);
2909 /* High bit is set, look for bits clear at the bottom. */
2910 count = exact_log2 (-val);
2913 /* This is only size win if we can use the asl2 insn. Otherwise we
2914 would be replacing 1 6-byte insn with 2 3-byte insns. */
2915 if (count > (optimize_insn_for_speed_p () ? 2 : 4))
2921 /* High bit is clear, look for bits set at the bottom. */
2922 count = exact_log2 (val + 1);
2924 /* Again, this is only a size win with asl2. */
2925 if (count > (optimize_insn_for_speed_p () ? 2 : 4))
2934 enum attr_liw_op op;
2939 /* Decide if the given insn is a candidate for LIW bundling. If it is then
2940 extract the operands and LIW attributes from the insn and use them to fill
2941 in the liw_data structure. Return true upon success or false if the insn
2942 cannot be bundled. */
2945 extract_bundle (rtx insn, struct liw_data * pdata)
2947 bool allow_consts = true;
2950 gcc_assert (pdata != NULL);
2952 if (insn == NULL_RTX)
2954 /* Make sure that we are dealing with a simple SET insn. */
2955 p = single_set (insn);
2959 /* Make sure that it could go into one of the LIW pipelines. */
2960 pdata->slot = get_attr_liw (insn);
2961 if (pdata->slot == LIW_BOTH)
2964 pdata->op = get_attr_liw_op (insn);
2969 pdata->dest = SET_DEST (p);
2970 pdata->src = SET_SRC (p);
2973 pdata->dest = XEXP (SET_SRC (p), 0);
2974 pdata->src = XEXP (SET_SRC (p), 1);
2981 /* The AND, OR and XOR long instruction words only accept register arguments. */
2982 allow_consts = false;
2985 pdata->dest = SET_DEST (p);
2986 pdata->src = XEXP (SET_SRC (p), 1);
2990 if (! REG_P (pdata->dest))
2993 if (REG_P (pdata->src))
2996 return allow_consts && satisfies_constraint_O (pdata->src);
2999 /* Make sure that it is OK to execute LIW1 and LIW2 in parallel. GCC generated
3000 the instructions with the assumption that LIW1 would be executed before LIW2
3001 so we must check for overlaps between their sources and destinations. */
3004 check_liw_constraints (struct liw_data * pliw1, struct liw_data * pliw2)
3006 /* Check for slot conflicts. */
3007 if (pliw2->slot == pliw1->slot && pliw1->slot != LIW_EITHER)
3010 /* If either operation is a compare, then "dest" is really an input; the real
3011 destination is CC_REG. So these instructions need different checks. */
3013 /* Changing "CMP ; OP" into "CMP | OP" is OK because the comparison will
3014 check its values prior to any changes made by OP. */
3015 if (pliw1->op == LIW_OP_CMP)
3017 /* Two sequential comparisons means dead code, which ought to
3018 have been eliminated given that bundling only happens with
3019 optimization. We cannot bundle them in any case. */
3020 gcc_assert (pliw1->op != pliw2->op);
3024 /* Changing "OP ; CMP" into "OP | CMP" does not work if the value being compared
3025 is the destination of OP, as the CMP will look at the old value, not the new
3027 if (pliw2->op == LIW_OP_CMP)
3029 if (REGNO (pliw2->dest) == REGNO (pliw1->dest))
3032 if (REG_P (pliw2->src))
3033 return REGNO (pliw2->src) != REGNO (pliw1->dest);
3038 /* Changing "OP1 ; OP2" into "OP1 | OP2" does not work if they both write to the
3039 same destination register. */
3040 if (REGNO (pliw2->dest) == REGNO (pliw1->dest))
3043 /* Changing "OP1 ; OP2" into "OP1 | OP2" generally does not work if the destination
3044 of OP1 is the source of OP2. The exception is when OP1 is a MOVE instruction when
3045 we can replace the source in OP2 with the source of OP1. */
3046 if (REG_P (pliw2->src) && REGNO (pliw2->src) == REGNO (pliw1->dest))
3048 if (pliw1->op == LIW_OP_MOV && REG_P (pliw1->src))
3050 if (! REG_P (pliw1->src)
3051 && (pliw2->op == LIW_OP_AND
3052 || pliw2->op == LIW_OP_OR
3053 || pliw2->op == LIW_OP_XOR))
3056 pliw2->src = pliw1->src;
3062 /* Everything else is OK. */
3066 /* Combine pairs of insns into LIW bundles. */
3069 mn10300_bundle_liw (void)
3073 for (r = get_insns (); r != NULL_RTX; r = next_nonnote_nondebug_insn (r))
3076 struct liw_data liw1, liw2;
3079 if (! extract_bundle (insn1, & liw1))
3082 insn2 = next_nonnote_nondebug_insn (insn1);
3083 if (! extract_bundle (insn2, & liw2))
3086 /* Check for source/destination overlap. */
3087 if (! check_liw_constraints (& liw1, & liw2))
3090 if (liw1.slot == LIW_OP2 || liw2.slot == LIW_OP1)
3092 struct liw_data temp;
3099 delete_insn (insn2);
3101 if (liw1.op == LIW_OP_CMP)
3102 insn2 = gen_cmp_liw (liw2.dest, liw2.src, liw1.dest, liw1.src,
3104 else if (liw2.op == LIW_OP_CMP)
3105 insn2 = gen_liw_cmp (liw1.dest, liw1.src, liw2.dest, liw2.src,
3108 insn2 = gen_liw (liw1.dest, liw2.dest, liw1.src, liw2.src,
3109 GEN_INT (liw1.op), GEN_INT (liw2.op));
3111 insn2 = emit_insn_after (insn2, insn1);
3112 delete_insn (insn1);
3117 #define DUMP(reason, insn) \
3122 fprintf (dump_file, reason "\n"); \
3123 if (insn != NULL_RTX) \
3124 print_rtl_single (dump_file, insn); \
3125 fprintf(dump_file, "\n"); \
3130 /* Replace the BRANCH insn with a Lcc insn that goes to LABEL.
3131 Insert a SETLB insn just before LABEL. */
3134 mn10300_insert_setlb_lcc (rtx label, rtx branch)
3136 rtx lcc, comparison, cmp_reg;
3138 if (LABEL_NUSES (label) > 1)
3142 /* This label is used both as an entry point to the loop
3143 and as a loop-back point for the loop. We need to separate
3144 these two functions so that the SETLB happens upon entry,
3145 but the loop-back does not go to the SETLB instruction. */
3146 DUMP ("Inserting SETLB insn after:", label);
3147 insn = emit_insn_after (gen_setlb (), label);
3148 label = gen_label_rtx ();
3149 emit_label_after (label, insn);
3150 DUMP ("Created new loop-back label:", label);
3154 DUMP ("Inserting SETLB insn before:", label);
3155 emit_insn_before (gen_setlb (), label);
3158 comparison = XEXP (SET_SRC (PATTERN (branch)), 0);
3159 cmp_reg = XEXP (comparison, 0);
3160 gcc_assert (REG_P (cmp_reg));
3162 /* If the comparison has not already been split out of the branch
3164 gcc_assert (REGNO (cmp_reg) == CC_REG);
3166 if (GET_MODE (cmp_reg) == CC_FLOATmode)
3167 lcc = gen_FLcc (comparison, label);
3169 lcc = gen_Lcc (comparison, label);
3171 lcc = emit_jump_insn_before (lcc, branch);
3172 mark_jump_label (XVECEXP (PATTERN (lcc), 0, 0), lcc, 0);
3173 JUMP_LABEL (lcc) = label;
3174 DUMP ("Replacing branch insn...", branch);
3175 DUMP ("... with Lcc insn:", lcc);
3176 delete_insn (branch);
3180 mn10300_block_contains_call (struct basic_block_def * block)
3184 FOR_BB_INSNS (block, insn)
3192 mn10300_loop_contains_call_insn (loop_p loop)
3195 bool result = false;
3198 bbs = get_loop_body (loop);
3200 for (i = 0; i < loop->num_nodes; i++)
3201 if (mn10300_block_contains_call (bbs[i]))
3212 mn10300_scan_for_setlb_lcc (void)
3215 loop_iterator liter;
3218 DUMP ("Looking for loops that can use the SETLB insn", NULL_RTX);
3221 compute_bb_for_insn ();
3223 /* Find the loops. */
3224 if (flow_loops_find (& loops) < 1)
3225 DUMP ("No loops found", NULL_RTX);
3226 current_loops = & loops;
3228 /* FIXME: For now we only investigate innermost loops. In practice however
3229 if an inner loop is not suitable for use with the SETLB/Lcc insns, it may
3230 be the case that its parent loop is suitable. Thus we should check all
3231 loops, but work from the innermost outwards. */
3232 FOR_EACH_LOOP (liter, loop, LI_ONLY_INNERMOST)
3234 const char * reason = NULL;
3236 /* Check to see if we can modify this loop. If we cannot
3237 then set 'reason' to describe why it could not be done. */
3238 if (loop->latch == NULL)
3239 reason = "it contains multiple latches";
3240 else if (loop->header != loop->latch)
3241 /* FIXME: We could handle loops that span multiple blocks,
3242 but this requires a lot more work tracking down the branches
3243 that need altering, so for now keep things simple. */
3244 reason = "the loop spans multiple blocks";
3245 else if (mn10300_loop_contains_call_insn (loop))
3246 reason = "it contains CALL insns";
3249 rtx branch = BB_END (loop->latch);
3251 gcc_assert (JUMP_P (branch));
3252 if (single_set (branch) == NULL_RTX || ! any_condjump_p (branch))
3253 /* We cannot optimize tablejumps and the like. */
3254 /* FIXME: We could handle unconditional jumps. */
3255 reason = "it is not a simple loop";
3261 flow_loop_dump (loop, dump_file, NULL, 0);
3263 label = BB_HEAD (loop->header);
3264 gcc_assert (LABEL_P (label));
3266 mn10300_insert_setlb_lcc (label, branch);
3270 if (dump_file && reason != NULL)
3271 fprintf (dump_file, "Loop starting with insn %d is not suitable because %s\n",
3272 INSN_UID (BB_HEAD (loop->header)),
3276 #if 0 /* FIXME: We should free the storage we allocated, but
3277 for some unknown reason this leads to seg-faults. */
3278 FOR_EACH_LOOP (liter, loop, 0)
3279 free_simple_loop_desc (loop);
3281 flow_loops_free (current_loops);
3284 current_loops = NULL;
3286 df_finish_pass (false);
3288 DUMP ("SETLB scan complete", NULL_RTX);
3292 mn10300_reorg (void)
3294 /* These are optimizations, so only run them if optimizing. */
3295 if (TARGET_AM33 && (optimize > 0 || optimize_size))
3297 if (TARGET_ALLOW_SETLB)
3298 mn10300_scan_for_setlb_lcc ();
3300 if (TARGET_ALLOW_LIW)
3301 mn10300_bundle_liw ();
3305 /* Initialize the GCC target structure. */
3307 #undef TARGET_MACHINE_DEPENDENT_REORG
3308 #define TARGET_MACHINE_DEPENDENT_REORG mn10300_reorg
3310 #undef TARGET_ASM_ALIGNED_HI_OP
3311 #define TARGET_ASM_ALIGNED_HI_OP "\t.hword\t"
3313 #undef TARGET_LEGITIMIZE_ADDRESS
3314 #define TARGET_LEGITIMIZE_ADDRESS mn10300_legitimize_address
3316 #undef TARGET_ADDRESS_COST
3317 #define TARGET_ADDRESS_COST mn10300_address_cost
3318 #undef TARGET_REGISTER_MOVE_COST
3319 #define TARGET_REGISTER_MOVE_COST mn10300_register_move_cost
3320 #undef TARGET_MEMORY_MOVE_COST
3321 #define TARGET_MEMORY_MOVE_COST mn10300_memory_move_cost
3322 #undef TARGET_RTX_COSTS
3323 #define TARGET_RTX_COSTS mn10300_rtx_costs
3325 #undef TARGET_ASM_FILE_START
3326 #define TARGET_ASM_FILE_START mn10300_file_start
3327 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
3328 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
3330 #undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA
3331 #define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA mn10300_asm_output_addr_const_extra
3333 #undef TARGET_OPTION_OVERRIDE
3334 #define TARGET_OPTION_OVERRIDE mn10300_option_override
3336 #undef TARGET_ENCODE_SECTION_INFO
3337 #define TARGET_ENCODE_SECTION_INFO mn10300_encode_section_info
3339 #undef TARGET_PROMOTE_PROTOTYPES
3340 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
3341 #undef TARGET_RETURN_IN_MEMORY
3342 #define TARGET_RETURN_IN_MEMORY mn10300_return_in_memory
3343 #undef TARGET_PASS_BY_REFERENCE
3344 #define TARGET_PASS_BY_REFERENCE mn10300_pass_by_reference
3345 #undef TARGET_CALLEE_COPIES
3346 #define TARGET_CALLEE_COPIES hook_bool_CUMULATIVE_ARGS_mode_tree_bool_true
3347 #undef TARGET_ARG_PARTIAL_BYTES
3348 #define TARGET_ARG_PARTIAL_BYTES mn10300_arg_partial_bytes
3349 #undef TARGET_FUNCTION_ARG
3350 #define TARGET_FUNCTION_ARG mn10300_function_arg
3351 #undef TARGET_FUNCTION_ARG_ADVANCE
3352 #define TARGET_FUNCTION_ARG_ADVANCE mn10300_function_arg_advance
3354 #undef TARGET_EXPAND_BUILTIN_SAVEREGS
3355 #define TARGET_EXPAND_BUILTIN_SAVEREGS mn10300_builtin_saveregs
3356 #undef TARGET_EXPAND_BUILTIN_VA_START
3357 #define TARGET_EXPAND_BUILTIN_VA_START mn10300_va_start
3359 #undef TARGET_CASE_VALUES_THRESHOLD
3360 #define TARGET_CASE_VALUES_THRESHOLD mn10300_case_values_threshold
3362 #undef TARGET_LEGITIMATE_ADDRESS_P
3363 #define TARGET_LEGITIMATE_ADDRESS_P mn10300_legitimate_address_p
3364 #undef TARGET_DELEGITIMIZE_ADDRESS
3365 #define TARGET_DELEGITIMIZE_ADDRESS mn10300_delegitimize_address
3366 #undef TARGET_LEGITIMATE_CONSTANT_P
3367 #define TARGET_LEGITIMATE_CONSTANT_P mn10300_legitimate_constant_p
3369 #undef TARGET_PREFERRED_RELOAD_CLASS
3370 #define TARGET_PREFERRED_RELOAD_CLASS mn10300_preferred_reload_class
3371 #undef TARGET_PREFERRED_OUTPUT_RELOAD_CLASS
3372 #define TARGET_PREFERRED_OUTPUT_RELOAD_CLASS \
3373 mn10300_preferred_output_reload_class
3374 #undef TARGET_SECONDARY_RELOAD
3375 #define TARGET_SECONDARY_RELOAD mn10300_secondary_reload
3377 #undef TARGET_TRAMPOLINE_INIT
3378 #define TARGET_TRAMPOLINE_INIT mn10300_trampoline_init
3380 #undef TARGET_FUNCTION_VALUE
3381 #define TARGET_FUNCTION_VALUE mn10300_function_value
3382 #undef TARGET_LIBCALL_VALUE
3383 #define TARGET_LIBCALL_VALUE mn10300_libcall_value
3385 #undef TARGET_ASM_OUTPUT_MI_THUNK
3386 #define TARGET_ASM_OUTPUT_MI_THUNK mn10300_asm_output_mi_thunk
3387 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
3388 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK mn10300_can_output_mi_thunk
3390 #undef TARGET_SCHED_ADJUST_COST
3391 #define TARGET_SCHED_ADJUST_COST mn10300_adjust_sched_cost
3393 #undef TARGET_CONDITIONAL_REGISTER_USAGE
3394 #define TARGET_CONDITIONAL_REGISTER_USAGE mn10300_conditional_register_usage
3396 #undef TARGET_MD_ASM_CLOBBERS
3397 #define TARGET_MD_ASM_CLOBBERS mn10300_md_asm_clobbers
3399 #undef TARGET_FLAGS_REGNUM
3400 #define TARGET_FLAGS_REGNUM CC_REG
3402 struct gcc_target targetm = TARGET_INITIALIZER;