|| [istarget m68k-*-uclinux*]
|| [istarget mips*-*-elf*]
|| [istarget xstormy16-*]
- || [istarget xtensa-*-elf]
+ || [istarget xtensa*-*-elf]
|| [istarget *-*-vxworks*] } {
set profiling_available_saved 0
} else {
|| ([istarget powerpc*-*-*]
&& ([check_effective_target_powerpc_spe]
|| [check_effective_target_powerpc_altivec]))
- || [istarget spu-*-*] } {
+ || [istarget spu-*-*]
+ || ([istarget arm*-*-*] && [check_effective_target_arm_neon]) } {
set et_vect_cmdline_needed_saved 0
}
}
|| [istarget x86_64-*-*]
|| [istarget sparc*-*-*]
|| [istarget alpha*-*-*]
- || [istarget ia64-*-*] } {
+ || [istarget ia64-*-*]
+ || [check_effective_target_arm32] } {
set et_vect_int_saved 1
}
}
}
}
+# Return 1 is this is an ARM target where -mthumb causes Thumb-1 to be
+# used.
+
+proc check_effective_target_arm_thumb1_ok { } {
+ return [check_no_compiler_messages arm_thumb1_ok assembly {
+ #if !defined(__arm__) || !defined(__thumb__) || defined(__thumb2__)
+ #error FOO
+ #endif
+ } "-mthumb"]
+}
+
# Return 1 if the target supports executing NEON instructions, 0
# otherwise. Cache the result.
} "-mfpu=neon -mfloat-abi=softfp"]
}
+# Return 1 if this is a ARM target with NEON enabled.
+
+proc check_effective_target_arm_neon { } {
+ if { [check_effective_target_arm32] } {
+ return [check_no_compiler_messages arm_neon object {
+ #ifndef __ARM_NEON__
+ #error not NEON
+ #else
+ int dummy;
+ #endif
+ }]
+ } else {
+ return 0
+ }
+}
+
# Return 1 if this a Loongson-2E or -2F target using an ABI that supports
# the Loongson vector modes.
}
}
+# Return 1 if this is a SPU target with a toolchain that
+# supports automatic overlay generation.
+
+proc check_effective_target_spu_auto_overlay { } {
+ if { [istarget spu*-*-elf*] } {
+ return [check_no_compiler_messages spu_auto_overlay executable {
+ int main (void) { }
+ } "-Wl,--auto-overlay" ]
+ } else {
+ return 0
+ }
+}
+
# The VxWorks SPARC simulator accepts only EM_SPARC executables and
# chokes on EM_SPARC32PLUS or EM_SPARCV9 executables. Return 1 if the
# test environment appears to run executables on such a simulator.
&& ![istarget powerpc-*-linux*paired*])
|| [istarget ia64-*-*]
|| [istarget i?86-*-*]
- || [istarget x86_64-*-*] } {
+ || [istarget x86_64-*-*]
+ || [check_effective_target_arm32] } {
set et_vect_shift_saved 1
}
}
&& ![istarget powerpc-*-linux*paired*])
&& [check_effective_target_ilp32])
|| [istarget x86_64-*-*]
+ || [check_effective_target_arm32]
|| ([istarget sparc*-*-*] && [check_effective_target_ilp32]) } {
set answer 1
} else {
|| [istarget spu-*-*]
|| [istarget mipsisa64*-*-*]
|| [istarget x86_64-*-*]
- || [istarget ia64-*-*] } {
+ || [istarget ia64-*-*]
+ || [check_effective_target_arm32] } {
set et_vect_float_saved 1
}
}
verbose "check_effective_target_unaligned_stack: using cached result" 2
} else {
set et_unaligned_stack_saved 0
- if { ( [istarget i?86-*-*] || [istarget x86_64-*-*] )
- && (! [istarget *-*-darwin*] ) } {
- set et_unaligned_stack_saved 1
- }
}
verbose "check_effective_target_unaligned_stack: returning $et_unaligned_stack_saved" 2
return $et_unaligned_stack_saved
set et_vect_no_align_saved 0
if { [istarget mipsisa64*-*-*]
|| [istarget sparc*-*-*]
- || [istarget ia64-*-*] } {
+ || [istarget ia64-*-*]
+ || [check_effective_target_arm32] } {
set et_vect_no_align_saved 1
}
}
if { ([istarget powerpc*-*-*] && ![istarget powerpc-*-linux*paired*])
|| [istarget spu-*-*]
|| [istarget i?86-*-*]
- || [istarget x86_64-*-*] } {
+ || [istarget x86_64-*-*]
+ || [check_effective_target_arm32] } {
set et_vect_int_mult_saved 1
}
}
return $et_vect_extract_even_odd_saved
}
+# Return 1 if the target supports vector even/odd elements extraction of
+# vectors with SImode elements or larger, 0 otherwise.
+
+proc check_effective_target_vect_extract_even_odd_wide { } {
+ global et_vect_extract_even_odd_wide_saved
+
+ if [info exists et_vect_extract_even_odd_wide_saved] {
+ verbose "check_effective_target_vect_extract_even_odd_wide: using cached result" 2
+ } else {
+ set et_vect_extract_even_odd_wide_saved 0
+ if { [istarget powerpc*-*-*]
+ || [istarget i?86-*-*]
+ || [istarget x86_64-*-*] } {
+ set et_vect_extract_even_odd_wide_saved 1
+ }
+ }
+
+ verbose "check_effective_target_vect_extract_even_wide_odd: returning $et_vect_extract_even_odd_wide_saved" 2
+ return $et_vect_extract_even_odd_wide_saved
+}
+
# Return 1 if the target supports vector interleaving, 0 otherwise.
proc check_effective_target_vect_interleave { } {
return $et_vect_strided_saved
}
+# Return 1 if the target supports vector interleaving and extract even/odd
+# for wide element types, 0 otherwise.
+proc check_effective_target_vect_strided_wide { } {
+ global et_vect_strided_wide_saved
+
+ if [info exists et_vect_strided_wide_saved] {
+ verbose "check_effective_target_vect_strided_wide: using cached result" 2
+ } else {
+ set et_vect_strided_wide_saved 0
+ if { [check_effective_target_vect_interleave]
+ && [check_effective_target_vect_extract_even_odd_wide] } {
+ set et_vect_strided_wide_saved 1
+ }
+ }
+
+ verbose "check_effective_target_vect_strided_wide: returning $et_vect_strided_wide_saved" 2
+ return $et_vect_strided_wide_saved
+}
+
# Return 1 if the target supports section-anchors
proc check_effective_target_section_anchors { } {
int dummy[sizeof (__WCHAR_TYPE__) >= 4 ? 1 : -1];
}]
}
+
+# Return 1 if the target supports automatic stack alignment.
+
+proc check_effective_target_automatic_stack_alignment { } {
+ if { [istarget i?86*-*-*]
+ || [istarget x86_64-*-*] } then {
+ return 1
+ } else {
+ return 0
+ }
+}
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