/* Register to Stack convert for GNU compiler.
- Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
- 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
+ Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
+ 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008
+ Free Software Foundation, Inc.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2, or (at your option)
+ the Free Software Foundation; either version 3, or (at your option)
any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
License for more details.
You should have received a copy of the GNU General Public License
- along with GCC; see the file COPYING. If not, write to the Free
- Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
- 02110-1301, USA. */
+ along with GCC; see the file COPYING3. If not see
+ <http://www.gnu.org/licenses/>. */
/* This pass converts stack-like registers from the "flat register
file" model that gcc uses, to a stack convention that the 387 uses.
#include "recog.h"
#include "output.h"
#include "basic-block.h"
+#include "cfglayout.h"
#include "varray.h"
#include "reload.h"
#include "ggc.h"
#include "timevar.h"
#include "tree-pass.h"
#include "target.h"
+#include "df.h"
#include "vecprim.h"
#ifdef STACK_REGS
/* Forward declarations */
-static int stack_regs_mentioned_p (rtx pat);
+static int stack_regs_mentioned_p (const_rtx pat);
static void pop_stack (stack, int);
static rtx *get_true_reg (rtx *);
/* Return nonzero if any stack register is mentioned somewhere within PAT. */
static int
-stack_regs_mentioned_p (rtx pat)
+stack_regs_mentioned_p (const_rtx pat)
{
const char *fmt;
int i;
/* Return nonzero if INSN mentions stacked registers, else return zero. */
int
-stack_regs_mentioned (rtx insn)
+stack_regs_mentioned (const_rtx insn)
{
unsigned int uid, max;
int test;
GET_MODE (*pat));
*pat = FP_MODE_REG (REGNO (subreg) + regno_off,
GET_MODE (subreg));
- default:
return pat;
}
}
return pat;
pat = & XEXP (*pat, 0);
break;
+
+ default:
+ return pat;
}
}
\f
if (GET_CODE (body) == PARALLEL)
{
- clobber_reg = alloca (XVECLEN (body, 0) * sizeof (rtx));
+ clobber_reg = XALLOCAVEC (rtx, XVECLEN (body, 0));
for (i = 0; i < XVECLEN (body, 0); i++)
if (GET_CODE (XVECEXP (body, 0, i)) == CLOBBER)
static void
replace_reg (rtx *reg, int regno)
{
- gcc_assert (regno >= FIRST_STACK_REG);
- gcc_assert (regno <= LAST_STACK_REG);
+ gcc_assert (IN_RANGE (regno, FIRST_STACK_REG, LAST_STACK_REG));
gcc_assert (STACK_REG_P (*reg));
gcc_assert (SCALAR_FLOAT_MODE_P (GET_MODE (*reg))
static void
remove_regno_note (rtx insn, enum reg_note note, unsigned int regno)
{
- rtx *note_link, this;
+ rtx *note_link, this_rtx;
note_link = ®_NOTES (insn);
- for (this = *note_link; this; this = XEXP (this, 1))
- if (REG_NOTE_KIND (this) == note
- && REG_P (XEXP (this, 0)) && REGNO (XEXP (this, 0)) == regno)
+ for (this_rtx = *note_link; this_rtx; this_rtx = XEXP (this_rtx, 1))
+ if (REG_NOTE_KIND (this_rtx) == note
+ && REG_P (XEXP (this_rtx, 0)) && REGNO (XEXP (this_rtx, 0)) == regno)
{
- *note_link = XEXP (this, 1);
+ *note_link = XEXP (this_rtx, 1);
return;
}
else
- note_link = &XEXP (this, 1);
+ note_link = &XEXP (this_rtx, 1);
gcc_unreachable ();
}
else
pop_insn = emit_insn_before (pop_rtx, insn);
- REG_NOTES (pop_insn)
- = gen_rtx_EXPR_LIST (REG_DEAD, FP_MODE_REG (FIRST_STACK_REG, DFmode),
- REG_NOTES (pop_insn));
+ add_reg_note (pop_insn, REG_DEAD, FP_MODE_REG (FIRST_STACK_REG, DFmode));
regstack->reg[regstack->top - (hard_regno - FIRST_STACK_REG)]
= regstack->reg[regstack->top];
hard_regno = get_hard_regnum (regstack, reg);
- gcc_assert (hard_regno >= FIRST_STACK_REG);
if (hard_regno == FIRST_STACK_REG)
return;
+ if (hard_regno == -1)
+ {
+ /* Something failed if the register wasn't on the stack. If we had
+ malformed asms, we zapped the instruction itself, but that didn't
+ produce the same pattern of register sets as before. To prevent
+ further failure, adjust REGSTACK to include REG at TOP. */
+ gcc_assert (any_malformed_asm);
+ regstack->reg[++regstack->top] = REGNO (reg);
+ return;
+ }
+ gcc_assert (hard_regno >= FIRST_STACK_REG);
other_reg = regstack->top - (hard_regno - FIRST_STACK_REG);
push_rtx = gen_movxf (top_stack_reg, top_stack_reg);
emit_insn_before (push_rtx, insn);
- REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_DEAD, top_stack_reg,
- REG_NOTES (insn));
+ add_reg_note (insn, REG_DEAD, top_stack_reg);
}
replace_reg (psrc, FIRST_STACK_REG);
special case with i387 UNSPEC_TAN, where destination is live
(an argument to fptan) but inherent load of 1.0 is modelled
as a load from a constant. */
- if (! (GET_CODE (pat) == PARALLEL
- && XVECLEN (pat, 0) == 2
- && GET_CODE (XVECEXP (pat, 0, 1)) == SET
- && GET_CODE (SET_SRC (XVECEXP (pat, 0, 1))) == UNSPEC
- && XINT (SET_SRC (XVECEXP (pat, 0, 1)), 1) == UNSPEC_TAN))
+ if (GET_CODE (pat) == PARALLEL
+ && XVECLEN (pat, 0) == 2
+ && GET_CODE (XVECEXP (pat, 0, 1)) == SET
+ && GET_CODE (SET_SRC (XVECEXP (pat, 0, 1))) == UNSPEC
+ && XINT (SET_SRC (XVECEXP (pat, 0, 1)), 1) == UNSPEC_TAN)
+ emit_swap_insn (insn, regstack, dest);
+ else
gcc_assert (get_hard_regnum (regstack, dest) < FIRST_STACK_REG);
gcc_assert (regstack->top < REG_STACK_SIZE);
if (STACK_REG_P (*src)
&& find_regno_note (insn, REG_DEAD, REGNO (*src)))
{
- emit_pop_insn (insn, regstack, *src, EMIT_AFTER);
+ /* USEs are ignored for liveness information so USEs of dead
+ register might happen. */
+ if (TEST_HARD_REG_BIT (regstack->reg_set, REGNO (*src)))
+ emit_pop_insn (insn, regstack, *src, EMIT_AFTER);
return control_flow_insn_deleted;
}
- /* ??? Uninitialized USE should not happen. */
- else
- gcc_assert (get_hard_regnum (regstack, *src) != -1);
+ /* Uninitialized USE might happen for functions returning uninitialized
+ value. We will properly initialize the USE on the edge to EXIT_BLOCK,
+ so it is safe to ignore the use here. This is consistent with behavior
+ of dataflow analyzer that ignores USE too. (This also imply that
+ forcibly initializing the register to NaN here would lead to ICE later,
+ since the REG_DEAD notes are not issued.) */
break;
case CLOBBER:
else
{
/* Both operands are REG. If neither operand is already
- at the top of stack, choose to make the one that is the dest
- the new top of stack. */
+ at the top of stack, choose to make the one that is the
+ dest the new top of stack. */
int src1_hard_regnum, src2_hard_regnum;
src1_hard_regnum = get_hard_regnum (regstack, *src1);
src2_hard_regnum = get_hard_regnum (regstack, *src2);
- gcc_assert (src1_hard_regnum != -1);
- gcc_assert (src2_hard_regnum != -1);
+
+ /* If the source is not live, this is yet another case of
+ uninitialized variables. Load up a NaN instead. */
+ if (src1_hard_regnum == -1)
+ {
+ rtx pat2 = gen_rtx_CLOBBER (VOIDmode, *src1);
+ rtx insn2 = emit_insn_before (pat2, insn);
+ control_flow_insn_deleted
+ |= move_nan_for_stack_reg (insn2, regstack, *src1);
+ }
+ if (src2_hard_regnum == -1)
+ {
+ rtx pat2 = gen_rtx_CLOBBER (VOIDmode, *src2);
+ rtx insn2 = emit_insn_before (pat2, insn);
+ control_flow_insn_deleted
+ |= move_nan_for_stack_reg (insn2, regstack, *src2);
+ }
if (src1_hard_regnum != FIRST_STACK_REG
&& src2_hard_regnum != FIRST_STACK_REG)
case UNSPEC_FSCALE_FRACT:
case UNSPEC_FPREM_F:
case UNSPEC_FPREM1_F:
- /* These insns operate on the top two stack slots.
+ /* These insns operate on the top two stack slots,
first part of double input, double output insn. */
src1 = get_true_reg (&XVECEXP (pat_src, 0, 0));
case UNSPEC_FSCALE_EXP:
case UNSPEC_FPREM_U:
case UNSPEC_FPREM1_U:
- /* These insns operate on the top two stack slots./
+ /* These insns operate on the top two stack slots,
second part of double input, double output insn. */
src1 = get_true_reg (&XVECEXP (pat_src, 0, 0));
src2 = get_true_reg (&XVECEXP (pat_src, 0, 1));
- src1_note = find_regno_note (insn, REG_DEAD, REGNO (*src1));
- src2_note = find_regno_note (insn, REG_DEAD, REGNO (*src2));
-
- /* Inputs should never die, they are
- replaced with outputs. */
- gcc_assert (!src1_note);
- gcc_assert (!src2_note);
-
- swap_to_top (insn, regstack, *src1, *src2);
-
/* Push the result back onto stack. Fill empty slot from
first part of insn and fix top of stack pointer. */
if (STACK_REG_P (*dest))
replace_reg (src2, FIRST_STACK_REG + 1);
break;
+ case UNSPEC_C2_FLAG:
+ /* This insn operates on the top two stack slots,
+ third part of C2 setting double input insn. */
+
+ src1 = get_true_reg (&XVECEXP (pat_src, 0, 0));
+ src2 = get_true_reg (&XVECEXP (pat_src, 0, 1));
+
+ replace_reg (src1, FIRST_STACK_REG);
+ replace_reg (src2, FIRST_STACK_REG + 1);
+ break;
+
case UNSPEC_SAHF:
/* (unspec [(unspec [(compare)] UNSPEC_FNSTSW)] UNSPEC_SAHF)
The combination matches the PPRO fcomi instruction. */
for (i = 0, note = REG_NOTES (insn); note; note = XEXP (note, 1))
i++;
- note_reg = alloca (i * sizeof (rtx));
- note_loc = alloca (i * sizeof (rtx *));
- note_kind = alloca (i * sizeof (enum reg_note));
+ note_reg = XALLOCAVEC (rtx, i);
+ note_loc = XALLOCAVEC (rtx *, i);
+ note_kind = XALLOCAVEC (enum reg_note, i);
n_notes = 0;
for (note = REG_NOTES (insn); note; note = XEXP (note, 1))
if (GET_CODE (body) == PARALLEL)
{
- clobber_reg = alloca (XVECLEN (body, 0) * sizeof (rtx));
- clobber_loc = alloca (XVECLEN (body, 0) * sizeof (rtx *));
+ clobber_reg = XALLOCAVEC (rtx, XVECLEN (body, 0));
+ clobber_loc = XALLOCAVEC (rtx *, XVECLEN (body, 0));
for (i = 0; i < XVECLEN (body, 0); i++)
if (GET_CODE (XVECEXP (body, 0, i)) == CLOBBER)
is no longer needed once this has executed. */
static void
-change_stack (rtx insn, stack old, stack new, enum emit_where where)
+change_stack (rtx insn, stack old, stack new_stack, enum emit_where where)
{
int reg;
int update_end = 0;
+ int i;
/* Stack adjustments for the first insn in a block update the
current_block's stack_in instead of inserting insns directly.
&& starting_stack_p
&& where == EMIT_BEFORE)
{
- BLOCK_INFO (current_block)->stack_in = *new;
+ BLOCK_INFO (current_block)->stack_in = *new_stack;
starting_stack_p = false;
- *old = *new;
+ *old = *new_stack;
return;
}
insn = NEXT_INSN (insn);
}
+ /* Initialize partially dead variables. */
+ for (i = FIRST_STACK_REG; i < LAST_STACK_REG + 1; i++)
+ if (TEST_HARD_REG_BIT (new_stack->reg_set, i)
+ && !TEST_HARD_REG_BIT (old->reg_set, i))
+ {
+ old->reg[++old->top] = i;
+ SET_HARD_REG_BIT (old->reg_set, i);
+ emit_insn_before (gen_rtx_SET (VOIDmode,
+ FP_MODE_REG (i, SFmode), not_a_num), insn);
+ }
+
/* Pop any registers that are not needed in the new block. */
/* If the destination block's stack already has a specified layout
and contains two or more registers, use a more intelligent algorithm
to pop registers that minimizes the number number of fxchs below. */
- if (new->top > 0)
+ if (new_stack->top > 0)
{
bool slots[REG_STACK_SIZE];
int pops[REG_STACK_SIZE];
int next, dest, topsrc;
/* First pass to determine the free slots. */
- for (reg = 0; reg <= new->top; reg++)
- slots[reg] = TEST_HARD_REG_BIT (new->reg_set, old->reg[reg]);
+ for (reg = 0; reg <= new_stack->top; reg++)
+ slots[reg] = TEST_HARD_REG_BIT (new_stack->reg_set, old->reg[reg]);
/* Second pass to allocate preferred slots. */
topsrc = -1;
- for (reg = old->top; reg > new->top; reg--)
- if (TEST_HARD_REG_BIT (new->reg_set, old->reg[reg]))
+ for (reg = old->top; reg > new_stack->top; reg--)
+ if (TEST_HARD_REG_BIT (new_stack->reg_set, old->reg[reg]))
{
dest = -1;
- for (next = 0; next <= new->top; next++)
- if (!slots[next] && new->reg[next] == old->reg[reg])
+ for (next = 0; next <= new_stack->top; next++)
+ if (!slots[next] && new_stack->reg[next] == old->reg[reg])
{
/* If this is a preference for the new top of stack, record
the fact by remembering it's old->reg in topsrc. */
- if (next == new->top)
+ if (next == new_stack->top)
topsrc = reg;
slots[next] = true;
dest = next;
slot is still unallocated, in which case we should place the
top of stack there. */
if (topsrc != -1)
- for (reg = 0; reg < new->top; reg++)
+ for (reg = 0; reg < new_stack->top; reg++)
if (!slots[reg])
{
pops[topsrc] = reg;
- slots[new->top] = false;
+ slots[new_stack->top] = false;
slots[reg] = true;
break;
}
/* Third pass allocates remaining slots and emits pop insns. */
- next = new->top;
- for (reg = old->top; reg > new->top; reg--)
+ next = new_stack->top;
+ for (reg = old->top; reg > new_stack->top; reg--)
{
dest = pops[reg];
if (dest == -1)
live = 0;
for (reg = 0; reg <= old->top; reg++)
- if (TEST_HARD_REG_BIT (new->reg_set, old->reg[reg]))
+ if (TEST_HARD_REG_BIT (new_stack->reg_set, old->reg[reg]))
live++;
next = live;
while (old->top >= live)
- if (TEST_HARD_REG_BIT (new->reg_set, old->reg[old->top]))
+ if (TEST_HARD_REG_BIT (new_stack->reg_set, old->reg[old->top]))
{
- while (TEST_HARD_REG_BIT (new->reg_set, old->reg[next]))
+ while (TEST_HARD_REG_BIT (new_stack->reg_set, old->reg[next]))
next--;
emit_pop_insn (insn, old, FP_MODE_REG (old->reg[next], DFmode),
EMIT_BEFORE);
EMIT_BEFORE);
}
- if (new->top == -2)
+ if (new_stack->top == -2)
{
/* If the new block has never been processed, then it can inherit
the old stack order. */
- new->top = old->top;
- memcpy (new->reg, old->reg, sizeof (new->reg));
+ new_stack->top = old->top;
+ memcpy (new_stack->reg, old->reg, sizeof (new_stack->reg));
}
else
{
/* By now, the only difference should be the order of the stack,
not their depth or liveliness. */
- GO_IF_HARD_REG_EQUAL (old->reg_set, new->reg_set, win);
- gcc_unreachable ();
- win:
- gcc_assert (old->top == new->top);
+ gcc_assert (hard_reg_set_equal_p (old->reg_set, new_stack->reg_set));
+ gcc_assert (old->top == new_stack->top);
- /* If the stack is not empty (new->top != -1), loop here emitting
+ /* If the stack is not empty (new_stack->top != -1), loop here emitting
swaps until the stack is correct.
The worst case number of swaps emitted is N + 2, where N is the
other regs. But since we never swap any other reg away from
its correct slot, this algorithm will converge. */
- if (new->top != -1)
+ if (new_stack->top != -1)
do
{
/* Swap the reg at top of stack into the position it is
supposed to be in, until the correct top of stack appears. */
- while (old->reg[old->top] != new->reg[new->top])
+ while (old->reg[old->top] != new_stack->reg[new_stack->top])
{
- for (reg = new->top; reg >= 0; reg--)
- if (new->reg[reg] == old->reg[old->top])
+ for (reg = new_stack->top; reg >= 0; reg--)
+ if (new_stack->reg[reg] == old->reg[old->top])
break;
gcc_assert (reg != -1);
incorrect reg to the top of stack, and let the while loop
above fix it. */
- for (reg = new->top; reg >= 0; reg--)
- if (new->reg[reg] != old->reg[reg])
+ for (reg = new_stack->top; reg >= 0; reg--)
+ if (new_stack->reg[reg] != old->reg[reg])
{
emit_swap_insn (insn, old,
FP_MODE_REG (old->reg[reg], DFmode));
/* At this point there must be no differences. */
for (reg = old->top; reg >= 0; reg--)
- gcc_assert (old->reg[reg] == new->reg[reg]);
+ gcc_assert (old->reg[reg] == new_stack->reg[reg]);
}
if (update_end)
if (retvalue)
{
value_reg_low = REGNO (retvalue);
- value_reg_high = value_reg_low
- + hard_regno_nregs[value_reg_low][GET_MODE (retvalue)] - 1;
+ value_reg_high = END_HARD_REGNO (retvalue) - 1;
}
output_stack = &BLOCK_INFO (EXIT_BLOCK_PTR)->stack_in;
for (reg = 0; reg <= src_stack->top; ++reg)
if (TEST_HARD_REG_BIT (dest_stack->reg_set, src_stack->reg[reg]))
dest_stack->reg[++dest_stack->top] = src_stack->reg[reg];
+
+ /* Push in any partially dead values. */
+ for (reg = FIRST_STACK_REG; reg < LAST_STACK_REG + 1; reg++)
+ if (TEST_HARD_REG_BIT (dest_stack->reg_set, reg)
+ && !TEST_HARD_REG_BIT (src_stack->reg_set, reg))
+ dest_stack->reg[++dest_stack->top] = reg;
}
/* Something failed if the stack lives don't match. If we had malformed
asms, we zapped the instruction itself, but that didn't produce the
same pattern of register kills as before. */
- GO_IF_HARD_REG_EQUAL (regstack.reg_set, bi->out_reg_set, win);
- gcc_assert (any_malformed_asm);
- win:
+
+ gcc_assert (hard_reg_set_equal_p (regstack.reg_set, bi->out_reg_set)
+ || any_malformed_asm);
bi->stack_out = regstack;
bi->done = true;
}
/* See if there is something to do. Flow analysis is quite
expensive so we might save some compilation time. */
for (i = FIRST_STACK_REG; i <= LAST_STACK_REG; i++)
- if (regs_ever_live[i])
+ if (df_regs_ever_live_p (i))
break;
if (i > LAST_STACK_REG)
return false;
- /* Ok, floating point instructions exist. If not optimizing,
- build the CFG and run life analysis.
- Also need to rebuild life when superblock scheduling is done
- as it don't update liveness yet. */
- if (!optimize
- || ((flag_sched2_use_superblocks || flag_sched2_use_traces)
- && flag_schedule_insns_after_reload))
- {
- count_or_remove_death_notes (NULL, 1);
- life_analysis (PROP_DEATH_NOTES);
- }
+ df_note_add_problem ();
+ df_analyze ();
+
mark_dfs_back_edges ();
/* Set up block info for each basic block. */
/* Copy live_at_end and live_at_start into temporaries. */
for (reg = FIRST_STACK_REG; reg <= LAST_STACK_REG; reg++)
{
- if (REGNO_REG_SET_P (bb->il.rtl->global_live_at_end, reg))
+ if (REGNO_REG_SET_P (DF_LR_OUT (bb), reg))
SET_HARD_REG_BIT (bi->out_reg_set, reg);
- if (REGNO_REG_SET_P (bb->il.rtl->global_live_at_start, reg))
+ if (REGNO_REG_SET_P (DF_LR_IN (bb), reg))
SET_HARD_REG_BIT (bi->stack_in.reg_set, reg);
}
}
??? We can't load from constant memory in PIC mode, because
we're inserting these instructions before the prologue and
the PIC register hasn't been set up. In that case, fall back
- on zero, which we can get from `ldz'. */
+ on zero, which we can get from `fldz'. */
if ((flag_pic && !TARGET_64BIT)
|| ix86_cmodel == CM_LARGE || ix86_cmodel == CM_LARGE_PIC)
not_a_num = CONST0_RTX (SFmode);
else
{
- not_a_num = gen_lowpart (SFmode, GEN_INT (0x7fc00000));
+ REAL_VALUE_TYPE r;
+
+ real_nan (&r, "", 1, SFmode);
+ not_a_num = CONST_DOUBLE_FROM_REAL_VALUE (r, SFmode);
not_a_num = force_const_mem (SFmode, not_a_num);
}
max_uid = get_max_uid ();
stack_regs_mentioned_data = VEC_alloc (char, heap, max_uid + 1);
memset (VEC_address (char, stack_regs_mentioned_data),
- 0, sizeof (char) * max_uid + 1);
+ 0, sizeof (char) * (max_uid + 1));
convert_regs ();
#endif
}
+struct rtl_opt_pass pass_stack_regs =
+{
+ {
+ RTL_PASS,
+ NULL, /* name */
+ gate_handle_stack_regs, /* gate */
+ NULL, /* execute */
+ NULL, /* sub */
+ NULL, /* next */
+ 0, /* static_pass_number */
+ TV_REG_STACK, /* tv_id */
+ 0, /* properties_required */
+ 0, /* properties_provided */
+ 0, /* properties_destroyed */
+ 0, /* todo_flags_start */
+ 0 /* todo_flags_finish */
+ }
+};
+
/* Convert register usage from flat register file usage to a stack
register file. */
static unsigned int
rest_of_handle_stack_regs (void)
{
#ifdef STACK_REGS
- if (reg_to_stack () && optimize)
- {
- regstack_completed = 1;
- if (cleanup_cfg (CLEANUP_EXPENSIVE | CLEANUP_POST_REGSTACK
- | (flag_crossjumping ? CLEANUP_CROSSJUMP : 0))
- && (flag_reorder_blocks || flag_reorder_blocks_and_partition))
- {
- reorder_basic_blocks (0);
- cleanup_cfg (CLEANUP_EXPENSIVE | CLEANUP_POST_REGSTACK);
- }
- }
- else
- regstack_completed = 1;
+ reg_to_stack ();
+ regstack_completed = 1;
#endif
return 0;
}
-struct tree_opt_pass pass_stack_regs =
+struct rtl_opt_pass pass_stack_regs_run =
{
+ {
+ RTL_PASS,
"stack", /* name */
- gate_handle_stack_regs, /* gate */
+ NULL, /* gate */
rest_of_handle_stack_regs, /* execute */
NULL, /* sub */
NULL, /* next */
0, /* properties_provided */
0, /* properties_destroyed */
0, /* todo_flags_start */
+ TODO_df_finish | TODO_verify_rtl_sharing |
TODO_dump_func |
- TODO_ggc_collect, /* todo_flags_finish */
- 'k' /* letter */
+ TODO_ggc_collect /* todo_flags_finish */
+ }
};
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