/* Subroutines used by or related to instruction recognition.
Copyright (C) 1987, 1988, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998
- 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
+ 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
This file is part of GCC.
#include "config.h"
#include "system.h"
+#include "coretypes.h"
+#include "tm.h"
#include "rtl.h"
#include "tm_p.h"
#include "insn-config.h"
#endif
#endif
-static void validate_replace_rtx_1 PARAMS ((rtx *, rtx, rtx, rtx));
-static rtx *find_single_use_1 PARAMS ((rtx, rtx *));
-static void validate_replace_src_1 PARAMS ((rtx *, void *));
-static rtx split_insn PARAMS ((rtx));
+static void validate_replace_rtx_1 (rtx *, rtx, rtx, rtx);
+static rtx *find_single_use_1 (rtx, rtx *);
+static void validate_replace_src_1 (rtx *, void *);
+static rtx split_insn (rtx);
/* Nonzero means allow operands to be volatile.
This should be 0 if you are generating rtl, such as if you are calling
int reload_completed;
+/* Nonzero after thread_prologue_and_epilogue_insns has run. */
+int epilogue_completed;
+
/* Initialize data used by the function `recog'.
This must be called once in the compilation of a function
before any insn recognition may be done in the function. */
void
-init_recog_no_volatile ()
+init_recog_no_volatile (void)
{
volatile_ok = 0;
}
void
-init_recog ()
+init_recog (void)
{
volatile_ok = 1;
}
through this one. (The only exception is in combine.c.) */
int
-recog_memoized_1 (insn)
- rtx insn;
+recog_memoized_1 (rtx insn)
{
if (INSN_CODE (insn) < 0)
INSN_CODE (insn) = recog (PATTERN (insn), insn, 0);
and that the operands mentioned in it are legitimate. */
int
-check_asm_operands (x)
- rtx x;
+check_asm_operands (rtx x)
{
int noperands;
rtx *operands;
if (noperands == 0)
return 1;
- operands = (rtx *) alloca (noperands * sizeof (rtx));
- constraints = (const char **) alloca (noperands * sizeof (char *));
+ operands = alloca (noperands * sizeof (rtx));
+ constraints = alloca (noperands * sizeof (char *));
decode_asm_operands (x, operands, NULL, constraints, NULL);
c = constraints[c[0] - '0'];
if (! asm_operand_ok (operands[i], c))
- return 0;
+ return 0;
}
return 1;
an INSN, CALL_INSN, or JUMP_INSN, the insn will be re-recognized with
the change in place.
- IN_GROUP is non-zero if this is part of a group of changes that must be
+ IN_GROUP is nonzero if this is part of a group of changes that must be
performed as a group. In that case, the changes will be stored. The
function `apply_change_group' will validate and apply the changes.
Otherwise, perform the change and return 1. */
int
-validate_change (object, loc, new, in_group)
- rtx object;
- rtx *loc;
- rtx new;
- int in_group;
+validate_change (rtx object, rtx *loc, rtx new, int in_group)
{
rtx old = *loc;
else
changes_allocated *= 2;
- changes =
- (change_t*) xrealloc (changes,
- sizeof (change_t) * changes_allocated);
+ changes = xrealloc (changes, sizeof (change_t) * changes_allocated);
}
-
+
changes[num_changes].object = object;
changes[num_changes].loc = loc;
changes[num_changes].old = old;
were valid; i.e. whether INSN can still be recognized. */
int
-insn_invalid_p (insn)
- rtx insn;
+insn_invalid_p (rtx insn)
{
rtx pat = PATTERN (insn);
int num_clobbers = 0;
? &num_clobbers : 0);
int is_asm = icode < 0 && asm_noperands (PATTERN (insn)) >= 0;
-
+
/* If this is an asm and the operand aren't legal, then fail. Likewise if
this is not an asm and the insn wasn't recognized. */
if ((is_asm && ! check_asm_operands (PATTERN (insn)))
return 0;
}
+/* Return number of changes made and not validated yet. */
+int
+num_changes_pending (void)
+{
+ return num_changes;
+}
+
/* Apply a group of changes previously issued with `validate_change'.
Return 1 if all changes are valid, zero otherwise. */
int
-apply_change_group ()
+apply_change_group (void)
{
int i;
rtx last_validated = NULL_RTX;
{
rtx object = changes[i].object;
- /* if there is no object to test or if it is the same as the one we
+ /* If there is no object to test or if it is the same as the one we
already tested, ignore it. */
if (object == 0 || object == last_validated)
continue;
int j;
newpat
- = gen_rtx_PARALLEL (VOIDmode,
+ = gen_rtx_PARALLEL (VOIDmode,
rtvec_alloc (XVECLEN (pat, 0) - 1));
for (j = 0; j < XVECLEN (newpat, 0); j++)
XVECEXP (newpat, 0, j) = XVECEXP (pat, 0, j);
for (i = 0; i < num_changes; i++)
if (changes[i].object
&& INSN_P (changes[i].object)
- && basic_block_for_insn
- && ((unsigned int)INSN_UID (changes[i].object)
- < basic_block_for_insn->num_elements)
&& (bb = BLOCK_FOR_INSN (changes[i].object)))
- bb->flags |= BB_DIRTY;
+ bb->flags |= BB_DIRTY;
num_changes = 0;
return 1;
/* Return the number of changes so far in the current group. */
int
-num_validated_changes ()
+num_validated_changes (void)
{
return num_changes;
}
/* Retract the changes numbered NUM and up. */
void
-cancel_changes (num)
- int num;
+cancel_changes (int num)
{
int i;
validate_change passing OBJECT. */
static void
-validate_replace_rtx_1 (loc, from, to, object)
- rtx *loc;
- rtx from, to, object;
+validate_replace_rtx_1 (rtx *loc, rtx from, rtx to, rtx object)
{
int i, j;
const char *fmt;
{
case PLUS:
/* If we have a PLUS whose second operand is now a CONST_INT, use
- plus_constant to try to simplify it.
+ simplify_gen_binary to try to simplify it.
??? We may want later to remove this, once simplification is
separated from this function. */
- if (GET_CODE (XEXP (x, 1)) == CONST_INT)
+ if (GET_CODE (XEXP (x, 1)) == CONST_INT && XEXP (x, 1) == to)
validate_change (object, loc,
simplify_gen_binary
(PLUS, GET_MODE (x), XEXP (x, 0), XEXP (x, 1)), 1);
if INSN is still valid. */
int
-validate_replace_rtx_subexp (from, to, insn, loc)
- rtx from, to, insn, *loc;
+validate_replace_rtx_subexp (rtx from, rtx to, rtx insn, rtx *loc)
{
validate_replace_rtx_1 (loc, from, to, insn);
return apply_change_group ();
changes have been made, validate by seeing if INSN is still valid. */
int
-validate_replace_rtx (from, to, insn)
- rtx from, to, insn;
+validate_replace_rtx (rtx from, rtx to, rtx insn)
{
validate_replace_rtx_1 (&PATTERN (insn), from, to, insn);
return apply_change_group ();
/* Try replacing every occurrence of FROM in INSN with TO. */
void
-validate_replace_rtx_group (from, to, insn)
- rtx from, to, insn;
+validate_replace_rtx_group (rtx from, rtx to, rtx insn)
{
validate_replace_rtx_1 (&PATTERN (insn), from, to, insn);
}
};
static void
-validate_replace_src_1 (x, data)
- rtx *x;
- void *data;
+validate_replace_src_1 (rtx *x, void *data)
{
struct validate_replace_src_data *d
= (struct validate_replace_src_data *) data;
}
/* Try replacing every occurrence of FROM in INSN with TO, avoiding
- SET_DESTs. After all changes have been made, validate by seeing if
- INSN is still valid. */
+ SET_DESTs. */
-int
-validate_replace_src (from, to, insn)
- rtx from, to, insn;
+void
+validate_replace_src_group (rtx from, rtx to, rtx insn)
{
struct validate_replace_src_data d;
d.to = to;
d.insn = insn;
note_uses (&PATTERN (insn), validate_replace_src_1, &d);
+}
+
+/* Same as validate_replace_src_group, but validate by seeing if
+ INSN is still valid. */
+int
+validate_replace_src (rtx from, rtx to, rtx insn)
+{
+ validate_replace_src_group (from, to, insn);
return apply_change_group ();
}
\f
EQ and NE tests do not count. */
int
-next_insn_tests_no_inequality (insn)
- rtx insn;
+next_insn_tests_no_inequality (rtx insn)
{
rtx next = next_cc0_user (insn);
|| GET_CODE (next) == CALL_INSN)
&& ! inequality_comparisons_p (PATTERN (next)));
}
-
-#if 0 /* This is useless since the insn that sets the cc's
- must be followed immediately by the use of them. */
-/* Return 1 if the CC value set up by INSN is not used. */
-
-int
-next_insns_test_no_inequality (insn)
- rtx insn;
-{
- rtx next = NEXT_INSN (insn);
-
- for (; next != 0; next = NEXT_INSN (next))
- {
- if (GET_CODE (next) == CODE_LABEL
- || GET_CODE (next) == BARRIER)
- return 1;
- if (GET_CODE (next) == NOTE)
- continue;
- if (inequality_comparisons_p (PATTERN (next)))
- return 0;
- if (sets_cc0_p (PATTERN (next)) == 1)
- return 1;
- if (! reg_mentioned_p (cc0_rtx, PATTERN (next)))
- return 1;
- }
- return 1;
-}
-#endif
#endif
\f
/* This is used by find_single_use to locate an rtx that contains exactly one
DEST that are being used to totally replace it are not counted. */
static rtx *
-find_single_use_1 (dest, loc)
- rtx dest;
- rtx *loc;
+find_single_use_1 (rtx dest, rtx *loc)
{
rtx x = *loc;
enum rtx_code code = GET_CODE (x);
case MEM:
case SUBREG:
return find_single_use_1 (dest, &XEXP (x, 0));
-
+
default:
break;
}
sequel. If so, return a pointer to the innermost rtx expression in which
it is used.
- If PLOC is non-zero, *PLOC is set to the insn containing the single use.
+ If PLOC is nonzero, *PLOC is set to the insn containing the single use.
This routine will return usually zero either before flow is called (because
there will be no LOG_LINKS notes) or after reload (because the REG_DEAD
and last insn referencing DEST. */
rtx *
-find_single_use (dest, insn, ploc)
- rtx dest;
- rtx insn;
- rtx *ploc;
+find_single_use (rtx dest, rtx insn, rtx *ploc)
{
rtx next;
rtx *result;
class NO_REGS, see the comment for `register_operand'. */
int
-general_operand (op, mode)
- rtx op;
- enum machine_mode mode;
+general_operand (rtx op, enum machine_mode mode)
{
enum rtx_code code = GET_CODE (op);
return 0;
if (GET_CODE (op) == CONST_INT
+ && mode != VOIDmode
&& trunc_int_for_mode (INTVAL (op), mode) != INTVAL (op))
return 0;
if (code == SUBREG)
{
+ rtx sub = SUBREG_REG (op);
+
#ifdef INSN_SCHEDULING
/* On machines that have insn scheduling, we want all memory
reference to be explicit, so outlaw paradoxical SUBREGs. */
- if (GET_CODE (SUBREG_REG (op)) == MEM
- && GET_MODE_SIZE (mode) > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op))))
+ if (GET_CODE (sub) == MEM
+ && GET_MODE_SIZE (mode) > GET_MODE_SIZE (GET_MODE (sub)))
return 0;
#endif
/* Avoid memories with nonzero SUBREG_BYTE, as offsetting the memory
may result in incorrect reference. We should simplify all valid
subregs of MEM anyway. But allow this after reload because we
- might be called from cleanup_subreg_operands.
+ might be called from cleanup_subreg_operands.
??? This is a kludge. */
if (!reload_completed && SUBREG_BYTE (op) != 0
- && GET_CODE (SUBREG_REG (op)) == MEM)
- return 0;
+ && GET_CODE (sub) == MEM)
+ return 0;
- op = SUBREG_REG (op);
+ /* FLOAT_MODE subregs can't be paradoxical. Combine will occasionally
+ create such rtl, and we must reject it. */
+ if (GET_MODE_CLASS (GET_MODE (op)) == MODE_FLOAT
+ && GET_MODE_SIZE (GET_MODE (op)) > GET_MODE_SIZE (GET_MODE (sub)))
+ return 0;
+
+ op = sub;
code = GET_CODE (op);
}
expressions in the machine description. */
int
-address_operand (op, mode)
- rtx op;
- enum machine_mode mode;
+address_operand (rtx op, enum machine_mode mode)
{
return memory_address_p (mode, op);
}
it is most consistent to keep this function from accepting them. */
int
-register_operand (op, mode)
- rtx op;
- enum machine_mode mode;
+register_operand (rtx op, enum machine_mode mode)
{
if (GET_MODE (op) != mode && mode != VOIDmode)
return 0;
if (GET_CODE (op) == SUBREG)
{
+ rtx sub = SUBREG_REG (op);
+
/* Before reload, we can allow (SUBREG (MEM...)) as a register operand
because it is guaranteed to be reloaded into one.
Just make sure the MEM is valid in itself.
(Ideally, (SUBREG (MEM)...) should not exist after reload,
but currently it does result from (SUBREG (REG)...) where the
reg went on the stack.) */
- if (! reload_completed && GET_CODE (SUBREG_REG (op)) == MEM)
+ if (! reload_completed && GET_CODE (sub) == MEM)
return general_operand (op, mode);
-#ifdef CLASS_CANNOT_CHANGE_MODE
- if (GET_CODE (SUBREG_REG (op)) == REG
- && REGNO (SUBREG_REG (op)) < FIRST_PSEUDO_REGISTER
- && (TEST_HARD_REG_BIT
- (reg_class_contents[(int) CLASS_CANNOT_CHANGE_MODE],
- REGNO (SUBREG_REG (op))))
- && CLASS_CANNOT_CHANGE_MODE_P (mode, GET_MODE (SUBREG_REG (op)))
- && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op))) != MODE_COMPLEX_INT
- && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op))) != MODE_COMPLEX_FLOAT)
+#ifdef CANNOT_CHANGE_MODE_CLASS
+ if (GET_CODE (sub) == REG
+ && REGNO (sub) < FIRST_PSEUDO_REGISTER
+ && REG_CANNOT_CHANGE_MODE_P (REGNO (sub), GET_MODE (sub), mode)
+ && GET_MODE_CLASS (GET_MODE (sub)) != MODE_COMPLEX_INT
+ && GET_MODE_CLASS (GET_MODE (sub)) != MODE_COMPLEX_FLOAT)
return 0;
#endif
- op = SUBREG_REG (op);
+ /* FLOAT_MODE subregs can't be paradoxical. Combine will occasionally
+ create such rtl, and we must reject it. */
+ if (GET_MODE_CLASS (GET_MODE (op)) == MODE_FLOAT
+ && GET_MODE_SIZE (GET_MODE (op)) > GET_MODE_SIZE (GET_MODE (sub)))
+ return 0;
+
+ op = sub;
}
/* If we have an ADDRESSOF, consider it valid since it will be
/* Return 1 for a register in Pmode; ignore the tested mode. */
int
-pmode_register_operand (op, mode)
- rtx op;
- enum machine_mode mode ATTRIBUTE_UNUSED;
+pmode_register_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
{
return register_operand (op, Pmode);
}
or a hard register. */
int
-scratch_operand (op, mode)
- rtx op;
- enum machine_mode mode;
+scratch_operand (rtx op, enum machine_mode mode)
{
if (GET_MODE (op) != mode && mode != VOIDmode)
return 0;
expressions in the machine description. */
int
-immediate_operand (op, mode)
- rtx op;
- enum machine_mode mode;
+immediate_operand (rtx op, enum machine_mode mode)
{
/* Don't accept CONST_INT or anything similar
if the caller wants something floating. */
return 0;
if (GET_CODE (op) == CONST_INT
+ && mode != VOIDmode
&& trunc_int_for_mode (INTVAL (op), mode) != INTVAL (op))
return 0;
/* Returns 1 if OP is an operand that is a CONST_INT. */
int
-const_int_operand (op, mode)
- rtx op;
- enum machine_mode mode;
+const_int_operand (rtx op, enum machine_mode mode)
{
if (GET_CODE (op) != CONST_INT)
return 0;
floating-point number. */
int
-const_double_operand (op, mode)
- rtx op;
- enum machine_mode mode;
+const_double_operand (rtx op, enum machine_mode mode)
{
/* Don't accept CONST_INT or anything similar
if the caller wants something floating. */
/* Return 1 if OP is a general operand that is not an immediate operand. */
int
-nonimmediate_operand (op, mode)
- rtx op;
- enum machine_mode mode;
+nonimmediate_operand (rtx op, enum machine_mode mode)
{
return (general_operand (op, mode) && ! CONSTANT_P (op));
}
/* Return 1 if OP is a register reference or immediate value of mode MODE. */
int
-nonmemory_operand (op, mode)
- rtx op;
- enum machine_mode mode;
+nonmemory_operand (rtx op, enum machine_mode mode)
{
if (CONSTANT_P (op))
{
return 0;
if (GET_CODE (op) == CONST_INT
+ && mode != VOIDmode
&& trunc_int_for_mode (INTVAL (op), mode) != INTVAL (op))
return 0;
expressions in the machine description. */
int
-push_operand (op, mode)
- rtx op;
- enum machine_mode mode;
+push_operand (rtx op, enum machine_mode mode)
{
unsigned int rounded_size = GET_MODE_SIZE (mode);
#ifdef STACK_GROWS_DOWNWARD
|| INTVAL (XEXP (XEXP (op, 1), 1)) != - (int) rounded_size
#else
- || INTVAL (XEXP (XEXP (op, 1), 1)) != rounded_size
+ || INTVAL (XEXP (XEXP (op, 1), 1)) != (int) rounded_size
#endif
)
return 0;
expressions in the machine description. */
int
-pop_operand (op, mode)
- rtx op;
- enum machine_mode mode;
+pop_operand (rtx op, enum machine_mode mode)
{
if (GET_CODE (op) != MEM)
return 0;
/* Return 1 if ADDR is a valid memory address for mode MODE. */
int
-memory_address_p (mode, addr)
- enum machine_mode mode ATTRIBUTE_UNUSED;
- rtx addr;
+memory_address_p (enum machine_mode mode ATTRIBUTE_UNUSED, rtx addr)
{
if (GET_CODE (addr) == ADDRESSOF)
return 1;
-
+
GO_IF_LEGITIMATE_ADDRESS (mode, addr, win);
return 0;
expressions in the machine description. */
int
-memory_operand (op, mode)
- rtx op;
- enum machine_mode mode;
+memory_operand (rtx op, enum machine_mode mode)
{
rtx inner;
that is, a memory reference whose address is a general_operand. */
int
-indirect_operand (op, mode)
- rtx op;
- enum machine_mode mode;
+indirect_operand (rtx op, enum machine_mode mode)
{
/* Before reload, a SUBREG isn't in memory (see memory_operand, above). */
if (! reload_completed
MATCH_OPERATOR to recognize all the branch insns. */
int
-comparison_operator (op, mode)
- rtx op;
- enum machine_mode mode;
+comparison_operator (rtx op, enum machine_mode mode)
{
return ((mode == VOIDmode || GET_MODE (op) == mode)
&& GET_RTX_CLASS (GET_CODE (op)) == '<');
Otherwise return -1. */
int
-asm_noperands (body)
- rtx body;
+asm_noperands (rtx body)
{
switch (GET_CODE (body))
{
we don't store that info. */
const char *
-decode_asm_operands (body, operands, operand_locs, constraints, modes)
- rtx body;
- rtx *operands;
- rtx **operand_locs;
- const char **constraints;
- enum machine_mode *modes;
+decode_asm_operands (rtx body, rtx *operands, rtx **operand_locs,
+ const char **constraints, enum machine_mode *modes)
{
int i;
int noperands;
{
if (GET_CODE (XVECEXP (body, 0, i)) == CLOBBER)
break; /* Past last SET */
-
+
if (operands)
operands[i] = SET_DEST (XVECEXP (body, 0, i));
if (operand_locs)
return template;
}
-/* Check if an asm_operand matches it's constraints.
+/* Check if an asm_operand matches it's constraints.
Return > 0 if ok, = 0 if bad, < 0 if inconclusive. */
int
-asm_operand_ok (op, constraint)
- rtx op;
- const char *constraint;
+asm_operand_ok (rtx op, const char *constraint)
{
int result = 0;
while (*constraint)
{
- char c = *constraint++;
+ char c = *constraint;
+ int len;
switch (c)
{
+ case ',':
+ constraint++;
+ continue;
case '=':
case '+':
case '*':
case '%':
- case '?':
case '!':
case '#':
case '&':
- case ',':
+ case '?':
break;
case '0': case '1': case '2': case '3': case '4':
proper matching constraint, but we can't actually fail
the check if they didn't. Indicate that results are
inconclusive. */
- while (ISDIGIT (*constraint))
+ do
constraint++;
- result = -1;
- break;
+ while (ISDIGIT (*constraint));
+ if (! result)
+ result = -1;
+ continue;
case 'p':
if (address_operand (op, VOIDmode))
- return 1;
+ result = 1;
break;
case 'm':
case 'V': /* non-offsettable */
if (memory_operand (op, VOIDmode))
- return 1;
+ result = 1;
break;
case 'o': /* offsettable */
if (offsettable_nonstrict_memref_p (op))
- return 1;
+ result = 1;
break;
case '<':
if (GET_CODE (op) == MEM
&& (1
|| GET_CODE (XEXP (op, 0)) == PRE_DEC
- || GET_CODE (XEXP (op, 0)) == POST_DEC))
- return 1;
+ || GET_CODE (XEXP (op, 0)) == POST_DEC))
+ result = 1;
break;
case '>':
if (GET_CODE (op) == MEM
&& (1
|| GET_CODE (XEXP (op, 0)) == PRE_INC
- || GET_CODE (XEXP (op, 0)) == POST_INC))
- return 1;
+ || GET_CODE (XEXP (op, 0)) == POST_INC))
+ result = 1;
break;
case 'E':
case 'F':
- if (GET_CODE (op) == CONST_DOUBLE)
- return 1;
+ if (GET_CODE (op) == CONST_DOUBLE
+ || (GET_CODE (op) == CONST_VECTOR
+ && GET_MODE_CLASS (GET_MODE (op)) == MODE_VECTOR_FLOAT))
+ result = 1;
break;
case 'G':
if (GET_CODE (op) == CONST_DOUBLE
- && CONST_DOUBLE_OK_FOR_LETTER_P (op, 'G'))
- return 1;
+ && CONST_DOUBLE_OK_FOR_CONSTRAINT_P (op, 'G', constraint))
+ result = 1;
break;
case 'H':
if (GET_CODE (op) == CONST_DOUBLE
- && CONST_DOUBLE_OK_FOR_LETTER_P (op, 'H'))
- return 1;
+ && CONST_DOUBLE_OK_FOR_CONSTRAINT_P (op, 'H', constraint))
+ result = 1;
break;
case 's':
&& (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op))
#endif
)
- return 1;
+ result = 1;
break;
case 'n':
if (GET_CODE (op) == CONST_INT
|| (GET_CODE (op) == CONST_DOUBLE
&& GET_MODE (op) == VOIDmode))
- return 1;
+ result = 1;
break;
case 'I':
if (GET_CODE (op) == CONST_INT
- && CONST_OK_FOR_LETTER_P (INTVAL (op), 'I'))
- return 1;
+ && CONST_OK_FOR_CONSTRAINT_P (INTVAL (op), 'I', constraint))
+ result = 1;
break;
case 'J':
if (GET_CODE (op) == CONST_INT
- && CONST_OK_FOR_LETTER_P (INTVAL (op), 'J'))
- return 1;
+ && CONST_OK_FOR_CONSTRAINT_P (INTVAL (op), 'J', constraint))
+ result = 1;
break;
case 'K':
if (GET_CODE (op) == CONST_INT
- && CONST_OK_FOR_LETTER_P (INTVAL (op), 'K'))
- return 1;
+ && CONST_OK_FOR_CONSTRAINT_P (INTVAL (op), 'K', constraint))
+ result = 1;
break;
case 'L':
if (GET_CODE (op) == CONST_INT
- && CONST_OK_FOR_LETTER_P (INTVAL (op), 'L'))
- return 1;
+ && CONST_OK_FOR_CONSTRAINT_P (INTVAL (op), 'L', constraint))
+ result = 1;
break;
case 'M':
if (GET_CODE (op) == CONST_INT
- && CONST_OK_FOR_LETTER_P (INTVAL (op), 'M'))
- return 1;
+ && CONST_OK_FOR_CONSTRAINT_P (INTVAL (op), 'M', constraint))
+ result = 1;
break;
case 'N':
if (GET_CODE (op) == CONST_INT
- && CONST_OK_FOR_LETTER_P (INTVAL (op), 'N'))
- return 1;
+ && CONST_OK_FOR_CONSTRAINT_P (INTVAL (op), 'N', constraint))
+ result = 1;
break;
case 'O':
if (GET_CODE (op) == CONST_INT
- && CONST_OK_FOR_LETTER_P (INTVAL (op), 'O'))
- return 1;
+ && CONST_OK_FOR_CONSTRAINT_P (INTVAL (op), 'O', constraint))
+ result = 1;
break;
case 'P':
if (GET_CODE (op) == CONST_INT
- && CONST_OK_FOR_LETTER_P (INTVAL (op), 'P'))
- return 1;
+ && CONST_OK_FOR_CONSTRAINT_P (INTVAL (op), 'P', constraint))
+ result = 1;
break;
case 'X':
- return 1;
+ result = 1;
case 'g':
if (general_operand (op, VOIDmode))
- return 1;
+ result = 1;
break;
default:
/* For all other letters, we first check for a register class,
otherwise it is an EXTRA_CONSTRAINT. */
- if (REG_CLASS_FROM_LETTER (c) != NO_REGS)
+ if (REG_CLASS_FROM_CONSTRAINT (c, constraint) != NO_REGS)
{
case 'r':
if (GET_MODE (op) == BLKmode)
break;
if (register_operand (op, VOIDmode))
- return 1;
+ result = 1;
+ }
+#ifdef EXTRA_CONSTRAINT_STR
+ if (EXTRA_CONSTRAINT_STR (op, c, constraint))
+ result = 1;
+ if (EXTRA_MEMORY_CONSTRAINT (c, constraint))
+ {
+ /* Every memory operand can be reloaded to fit. */
+ if (memory_operand (op, VOIDmode))
+ result = 1;
+ }
+ if (EXTRA_ADDRESS_CONSTRAINT (c, constraint))
+ {
+ /* Every address operand can be reloaded to fit. */
+ if (address_operand (op, VOIDmode))
+ result = 1;
}
-#ifdef EXTRA_CONSTRAINT
- if (EXTRA_CONSTRAINT (op, c))
- return 1;
#endif
break;
}
+ len = CONSTRAINT_LEN (c, constraint);
+ do
+ constraint++;
+ while (--len && *constraint);
+ if (len)
+ return 0;
}
return result;
Otherwise, return a null pointer. */
rtx *
-find_constant_term_loc (p)
- rtx *p;
+find_constant_term_loc (rtx *p)
{
rtx *tem;
enum rtx_code code = GET_CODE (*p);
don't use it before reload. */
int
-offsettable_memref_p (op)
- rtx op;
+offsettable_memref_p (rtx op)
{
return ((GET_CODE (op) == MEM)
&& offsettable_address_p (1, GET_MODE (op), XEXP (op, 0)));
consider pseudo-regs valid as index or base regs. */
int
-offsettable_nonstrict_memref_p (op)
- rtx op;
+offsettable_nonstrict_memref_p (rtx op)
{
return ((GET_CODE (op) == MEM)
&& offsettable_address_p (0, GET_MODE (op), XEXP (op, 0)));
for the sake of use in reload.c. */
int
-offsettable_address_p (strictp, mode, y)
- int strictp;
- enum machine_mode mode;
- rtx y;
+offsettable_address_p (int strictp, enum machine_mode mode, rtx y)
{
enum rtx_code ycode = GET_CODE (y);
rtx z;
rtx y1 = y;
rtx *y2;
- int (*addressp) PARAMS ((enum machine_mode, rtx)) =
+ int (*addressp) (enum machine_mode, rtx) =
(strictp ? strict_memory_address_p : memory_address_p);
unsigned int mode_sz = GET_MODE_SIZE (mode);
of the specified mode. We assume that if Y and Y+c are
valid addresses then so is Y+d for all 0<d<c. adjust_address will
go inside a LO_SUM here, so we do so as well. */
- if (GET_CODE (y) == LO_SUM)
+ if (GET_CODE (y) == LO_SUM
+ && mode != BLKmode
+ && mode_sz <= GET_MODE_ALIGNMENT (mode) / BITS_PER_UNIT)
z = gen_rtx_LO_SUM (GET_MODE (y), XEXP (y, 0),
plus_constant (XEXP (y, 1), mode_sz - 1));
else
because the amount of the increment depends on the mode. */
int
-mode_dependent_address_p (addr)
- rtx addr ATTRIBUTE_UNUSED; /* Maybe used in GO_IF_MODE_DEPENDENT_ADDRESS. */
+mode_dependent_address_p (rtx addr ATTRIBUTE_UNUSED /* Maybe used in GO_IF_MODE_DEPENDENT_ADDRESS. */)
{
GO_IF_MODE_DEPENDENT_ADDRESS (addr, win);
return 0;
win: ATTRIBUTE_UNUSED_LABEL
return 1;
}
-
-/* Return 1 if OP is a general operand
- other than a memory ref with a mode dependent address. */
-
-int
-mode_independent_operand (op, mode)
- enum machine_mode mode;
- rtx op;
-{
- rtx addr;
-
- if (! general_operand (op, mode))
- return 0;
-
- if (GET_CODE (op) != MEM)
- return 1;
-
- addr = XEXP (op, 0);
- GO_IF_MODE_DEPENDENT_ADDRESS (addr, lose);
- return 1;
- /* Label `lose' might (not) be used via GO_IF_MODE_DEPENDENT_ADDRESS. */
- lose: ATTRIBUTE_UNUSED_LABEL
- return 0;
-}
\f
/* Like extract_insn, but save insn extracted and don't extract again, when
called again for the same insn expecting that recog_data still contain the
valid information. This is used primary by gen_attr infrastructure that
often does extract insn again and again. */
void
-extract_insn_cached (insn)
- rtx insn;
+extract_insn_cached (rtx insn)
{
if (recog_data.insn == insn && INSN_CODE (insn) >= 0)
return;
/* Do cached extract_insn, constrain_operand and complain about failures.
Used by insn_attrtab. */
void
-extract_constrain_insn_cached (insn)
- rtx insn;
+extract_constrain_insn_cached (rtx insn)
{
extract_insn_cached (insn);
if (which_alternative == -1
}
/* Do cached constrain_operand and complain about failures. */
int
-constrain_operands_cached (strict)
- int strict;
+constrain_operands_cached (int strict)
{
if (which_alternative == -1)
return constrain_operands (strict);
/* Analyze INSN and fill in recog_data. */
void
-extract_insn (insn)
- rtx insn;
+extract_insn (rtx insn)
{
int i;
int icode;
information from the constraint strings into a more usable form.
The collected data is stored in recog_op_alt. */
void
-preprocess_constraints ()
+preprocess_constraints (void)
{
int i;
for (;;)
{
- char c = *p++;
+ char c = *p;
if (c == '#')
do
- c = *p++;
+ c = *++p;
while (c != ',' && c != '\0');
if (c == ',' || c == '\0')
- break;
+ {
+ p++;
+ break;
+ }
switch (c)
{
break;
case '&':
op_alt[j].earlyclobber = 1;
- break;
+ break;
case '0': case '1': case '2': case '3': case '4':
case '5': case '6': case '7': case '8': case '9':
{
char *end;
- op_alt[j].matches = strtoul (p - 1, &end, 10);
+ op_alt[j].matches = strtoul (p, &end, 10);
recog_op_alt[op_alt[j].matches][j].matched = i;
p = end;
}
- break;
+ continue;
case 'm':
op_alt[j].memory_ok = 1;
break;
default:
- op_alt[j].class = reg_class_subunion[(int) op_alt[j].class][(int) REG_CLASS_FROM_LETTER ((unsigned char) c)];
+ if (EXTRA_MEMORY_CONSTRAINT (c, p))
+ {
+ op_alt[j].memory_ok = 1;
+ break;
+ }
+ if (EXTRA_ADDRESS_CONSTRAINT (c, p))
+ {
+ op_alt[j].is_address = 1;
+ op_alt[j].class
+ = (reg_class_subunion
+ [(int) op_alt[j].class]
+ [(int) MODE_BASE_REG_CLASS (VOIDmode)]);
+ break;
+ }
+
+ op_alt[j].class
+ = (reg_class_subunion
+ [(int) op_alt[j].class]
+ [(int) REG_CLASS_FROM_CONSTRAINT ((unsigned char) c, p)]);
break;
}
+ p += CONSTRAINT_LEN (c, p);
}
}
}
}
-
+
/* Check the operands of an insn against the insn's operand constraints
and return 1 if they are valid.
The information about the insn's operands, constraints, operand modes
alternative of constraints was matched: 0 for the first alternative,
1 for the next, etc.
- In addition, when two operands are match
+ In addition, when two operands are required to match
and it happens that the output operand is (reg) while the
input operand is --(reg) or ++(reg) (a pre-inc or pre-dec),
make the output operand look like the input.
This is used in final, just before printing the assembler code and by
the routines that determine an insn's attribute.
- If STRICT is a positive non-zero value, it means that we have been
+ If STRICT is a positive nonzero value, it means that we have been
called after reload has been completed. In that case, we must
do all checks strictly. If it is zero, it means that we have been called
before reload has completed. In that case, we first try to see if we can
};
int
-constrain_operands (strict)
- int strict;
+constrain_operands (int strict)
{
const char *constraints[MAX_RECOG_OPERANDS];
int matching_operands[MAX_RECOG_OPERANDS];
int offset = 0;
int win = 0;
int val;
+ int len;
earlyclobber[opno] = 0;
if (*p == 0 || *p == ',')
win = 1;
- while (*p && (c = *p++) != ',')
- switch (c)
+ do
+ switch (c = *p, len = CONSTRAINT_LEN (c, p), c)
{
+ case '\0':
+ len = 0;
+ break;
+ case ',':
+ c = '\0';
+ break;
+
case '?': case '!': case '*': case '%':
case '=': case '+':
break;
case '#':
/* Ignore rest of this alternative as far as
constraint checking is concerned. */
- while (*p && *p != ',')
+ do
p++;
+ while (*p && *p != ',');
+ len = 0;
break;
case '&':
char *end;
int match;
- match = strtoul (p - 1, &end, 10);
+ match = strtoul (p, &end, 10);
p = end;
if (strict < 0)
funny_match[funny_match_index++].other = match;
}
}
+ len = 0;
break;
case 'p':
case 'E':
case 'F':
- if (GET_CODE (op) == CONST_DOUBLE)
+ if (GET_CODE (op) == CONST_DOUBLE
+ || (GET_CODE (op) == CONST_VECTOR
+ && GET_MODE_CLASS (GET_MODE (op)) == MODE_VECTOR_FLOAT))
win = 1;
break;
case 'G':
case 'H':
if (GET_CODE (op) == CONST_DOUBLE
- && CONST_DOUBLE_OK_FOR_LETTER_P (op, c))
+ && CONST_DOUBLE_OK_FOR_CONSTRAINT_P (op, c, p))
win = 1;
break;
case 'O':
case 'P':
if (GET_CODE (op) == CONST_INT
- && CONST_OK_FOR_LETTER_P (INTVAL (op), c))
+ && CONST_OK_FOR_CONSTRAINT_P (INTVAL (op), c, p))
win = 1;
break;
{
enum reg_class class;
- class = (c == 'r' ? GENERAL_REGS : REG_CLASS_FROM_LETTER (c));
+ class = (c == 'r'
+ ? GENERAL_REGS : REG_CLASS_FROM_CONSTRAINT (c, p));
if (class != NO_REGS)
{
if (strict < 0
&& reg_fits_class_p (op, class, offset, mode)))
win = 1;
}
-#ifdef EXTRA_CONSTRAINT
- else if (EXTRA_CONSTRAINT (op, c))
+#ifdef EXTRA_CONSTRAINT_STR
+ else if (EXTRA_CONSTRAINT_STR (op, c, p))
win = 1;
+
+ if (EXTRA_MEMORY_CONSTRAINT (c, p))
+ {
+ /* Every memory operand can be reloaded to fit. */
+ if (strict < 0 && GET_CODE (op) == MEM)
+ win = 1;
+
+ /* Before reload, accept what reload can turn into mem. */
+ if (strict < 0 && CONSTANT_P (op))
+ win = 1;
+
+ /* During reload, accept a pseudo */
+ if (reload_in_progress && GET_CODE (op) == REG
+ && REGNO (op) >= FIRST_PSEUDO_REGISTER)
+ win = 1;
+ }
+ if (EXTRA_ADDRESS_CONSTRAINT (c, p))
+ {
+ /* Every address operand can be reloaded to fit. */
+ if (strict < 0)
+ win = 1;
+ }
#endif
break;
}
}
+ while (p += len, c);
constraints[opno] = p;
/* If this operand did not win somehow,
If REG occupies multiple hard regs, all of them must be in CLASS. */
int
-reg_fits_class_p (operand, class, offset, mode)
- rtx operand;
- enum reg_class class;
- int offset;
- enum machine_mode mode;
+reg_fits_class_p (rtx operand, enum reg_class class, int offset,
+ enum machine_mode mode)
{
int regno = REGNO (operand);
if (regno < FIRST_PSEUDO_REGISTER
/* Split single instruction. Helper function for split_all_insns.
Return last insn in the sequence if successful, or NULL if unsuccessful. */
static rtx
-split_insn (insn)
- rtx insn;
+split_insn (rtx insn)
{
rtx set;
if (!INSN_P (insn))
NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
/* ??? Coddle to md files that generate subregs in post-
- reload splitters instead of computing the proper
+ reload splitters instead of computing the proper
hard register. */
if (reload_completed && first != last)
{
/* Split all insns in the function. If UPD_LIFE, update life info after. */
void
-split_all_insns (upd_life)
- int upd_life;
+split_all_insns (int upd_life)
{
sbitmap blocks;
- int changed;
- int i;
+ bool changed;
+ basic_block bb;
- blocks = sbitmap_alloc (n_basic_blocks);
+ blocks = sbitmap_alloc (last_basic_block);
sbitmap_zero (blocks);
- changed = 0;
+ changed = false;
- for (i = n_basic_blocks - 1; i >= 0; --i)
+ FOR_EACH_BB_REVERSE (bb)
{
- basic_block bb = BASIC_BLOCK (i);
rtx insn, next;
bool finish = false;
while (GET_CODE (last) == BARRIER)
last = PREV_INSN (last);
- SET_BIT (blocks, i);
- changed = 1;
+ SET_BIT (blocks, bb->index);
+ changed = true;
insn = last;
}
}
if (changed)
{
+ int old_last_basic_block = last_basic_block;
+
find_many_sub_basic_blocks (blocks);
+
+ if (old_last_basic_block != last_basic_block && upd_life)
+ blocks = sbitmap_resize (blocks, last_basic_block, 1);
}
if (changed && upd_life)
- {
- count_or_remove_death_notes (blocks, 1);
- update_life_info (blocks, UPDATE_LIFE_LOCAL, PROP_DEATH_NOTES);
- }
+ update_life_info (blocks, UPDATE_LIFE_GLOBAL_RM_NOTES,
+ PROP_DEATH_NOTES | PROP_REG_INFO);
+
#ifdef ENABLE_CHECKING
verify_flow_info ();
#endif
sbitmap_free (blocks);
}
-/* Same as split_all_insns, but do not expect CFG to be available.
- Used by machine depedent reorg passes. */
+/* Same as split_all_insns, but do not expect CFG to be available.
+ Used by machine dependent reorg passes. */
void
-split_all_insns_noflow ()
+split_all_insns_noflow (void)
{
rtx next, insn;
in a multi-insn pattern. */
rtx
-peep2_next_insn (n)
- int n;
+peep2_next_insn (int n)
{
if (n >= MAX_INSNS_PER_PEEP2 + 1)
abort ();
after `current'. */
int
-peep2_regno_dead_p (ofs, regno)
- int ofs;
- int regno;
+peep2_regno_dead_p (int ofs, int regno)
{
if (ofs >= MAX_INSNS_PER_PEEP2 + 1)
abort ();
/* Similarly for a REG. */
int
-peep2_reg_dead_p (ofs, reg)
- int ofs;
- rtx reg;
+peep2_reg_dead_p (int ofs, rtx reg)
{
int regno, n;
returned. */
rtx
-peep2_find_free_register (from, to, class_str, mode, reg_set)
- int from, to;
- const char *class_str;
- enum machine_mode mode;
- HARD_REG_SET *reg_set;
+peep2_find_free_register (int from, int to, const char *class_str,
+ enum machine_mode mode, HARD_REG_SET *reg_set)
{
static int search_ofs;
enum reg_class class;
}
class = (class_str[0] == 'r' ? GENERAL_REGS
- : REG_CLASS_FROM_LETTER (class_str[0]));
+ : REG_CLASS_FROM_CONSTRAINT (class_str[0], class_str));
for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
{
/* Perform the peephole2 optimization pass. */
void
-peephole2_optimize (dump_file)
- FILE *dump_file ATTRIBUTE_UNUSED;
+peephole2_optimize (FILE *dump_file ATTRIBUTE_UNUSED)
{
regset_head rs_heads[MAX_INSNS_PER_PEEP2 + 2];
rtx insn, prev;
regset live;
- int i, b;
+ int i;
+ basic_block bb;
#ifdef HAVE_conditional_execution
sbitmap blocks;
- int changed;
+ bool changed;
#endif
+ bool do_cleanup_cfg = false;
+ bool do_rebuild_jump_labels = false;
/* Initialize the regsets we're going to use. */
for (i = 0; i < MAX_INSNS_PER_PEEP2 + 1; ++i)
live = INITIALIZE_REG_SET (rs_heads[i]);
#ifdef HAVE_conditional_execution
- blocks = sbitmap_alloc (n_basic_blocks);
+ blocks = sbitmap_alloc (last_basic_block);
sbitmap_zero (blocks);
- changed = 0;
+ changed = false;
#else
count_or_remove_death_notes (NULL, 1);
#endif
- for (b = n_basic_blocks - 1; b >= 0; --b)
+ FOR_EACH_BB_REVERSE (bb)
{
- basic_block bb = BASIC_BLOCK (b);
struct propagate_block_info *pbi;
/* Indicate that all slots except the last holds invalid data. */
prev = PREV_INSN (insn);
if (INSN_P (insn))
{
- rtx try;
+ rtx try, before_try, x;
int match_len;
rtx note;
+ bool was_call = false;
/* Record this insn. */
if (--peep2_current < 0)
cfg-related call notes. */
for (i = 0; i <= match_len; ++i)
{
- int j, k;
+ int j;
rtx old_insn, new_insn, note;
j = i + peep2_current;
old_insn = peep2_insn_data[j].insn;
if (GET_CODE (old_insn) != CALL_INSN)
continue;
+ was_call = true;
- new_insn = NULL_RTX;
- if (GET_CODE (try) == SEQUENCE)
- for (k = XVECLEN (try, 0) - 1; k >= 0; k--)
- {
- rtx x = XVECEXP (try, 0, k);
- if (GET_CODE (x) == CALL_INSN)
- {
- new_insn = x;
- break;
- }
- }
- else if (GET_CODE (try) == CALL_INSN)
- new_insn = try;
- if (! new_insn)
+ new_insn = try;
+ while (new_insn != NULL_RTX)
+ {
+ if (GET_CODE (new_insn) == CALL_INSN)
+ break;
+ new_insn = NEXT_INSN (new_insn);
+ }
+
+ if (new_insn == NULL_RTX)
abort ();
CALL_INSN_FUNCTION_USAGE (new_insn)
if (i >= MAX_INSNS_PER_PEEP2 + 1)
i -= MAX_INSNS_PER_PEEP2 + 1;
+ note = find_reg_note (peep2_insn_data[i].insn,
+ REG_EH_REGION, NULL_RTX);
+
/* Replace the old sequence with the new. */
- try = emit_insn_after (try, peep2_insn_data[i].insn);
+ try = emit_insn_after_setloc (try, peep2_insn_data[i].insn,
+ INSN_LOCATOR (peep2_insn_data[i].insn));
+ before_try = PREV_INSN (insn);
delete_insn_chain (insn, peep2_insn_data[i].insn);
/* Re-insert the EH_REGION notes. */
- if (try == bb->end
- && (note = find_reg_note (peep2_insn_data[i].insn,
- REG_EH_REGION, NULL_RTX)))
+ if (note || (was_call && nonlocal_goto_handler_labels))
{
- rtx x;
- for (x = NEXT_INSN (peep2_insn_data[i].insn);
- x != NEXT_INSN (try); x = NEXT_INSN (x))
+ edge eh_edge;
+
+ for (eh_edge = bb->succ; eh_edge
+ ; eh_edge = eh_edge->succ_next)
+ if (eh_edge->flags & (EDGE_EH | EDGE_ABNORMAL_CALL))
+ break;
+
+ for (x = try ; x != before_try ; x = PREV_INSN (x))
if (GET_CODE (x) == CALL_INSN
|| (flag_non_call_exceptions
- && may_trap_p (PATTERN (x))))
- REG_NOTES (x)
- = gen_rtx_EXPR_LIST (REG_EH_REGION,
- XEXP (note, 0),
- REG_NOTES (x));
+ && may_trap_p (PATTERN (x))
+ && !find_reg_note (x, REG_EH_REGION, NULL)))
+ {
+ if (note)
+ REG_NOTES (x)
+ = gen_rtx_EXPR_LIST (REG_EH_REGION,
+ XEXP (note, 0),
+ REG_NOTES (x));
+
+ if (x != bb->end && eh_edge)
+ {
+ edge nfte, nehe;
+ int flags;
+
+ nfte = split_block (bb, x);
+ flags = (eh_edge->flags
+ & (EDGE_EH | EDGE_ABNORMAL));
+ if (GET_CODE (x) == CALL_INSN)
+ flags |= EDGE_ABNORMAL_CALL;
+ nehe = make_edge (nfte->src, eh_edge->dest,
+ flags);
+
+ nehe->probability = eh_edge->probability;
+ nfte->probability
+ = REG_BR_PROB_BASE - nehe->probability;
+
+ do_cleanup_cfg |= purge_dead_edges (nfte->dest);
+#ifdef HAVE_conditional_execution
+ SET_BIT (blocks, nfte->dest->index);
+ changed = true;
+#endif
+ bb = nfte->src;
+ eh_edge = nehe;
+ }
+ }
+
+ /* Converting possibly trapping insn to non-trapping is
+ possible. Zap dummy outgoing edges. */
+ do_cleanup_cfg |= purge_dead_edges (bb);
}
- /* Converting possibly trapping insn to non-trapping is
- possible. Zap dummy outgoing edges. */
- if (try == bb->end)
- purge_dead_edges (bb);
#ifdef HAVE_conditional_execution
/* With conditional execution, we cannot back up the
death data structures are not so self-contained.
So record that we've made a modification to this
block and update life information at the end. */
- SET_BIT (blocks, b);
- changed = 1;
+ SET_BIT (blocks, bb->index);
+ changed = true;
for (i = 0; i < MAX_INSNS_PER_PEEP2 + 1; ++i)
peep2_insn_data[i].insn = NULL_RTX;
COPY_REG_SET (live, peep2_insn_data[i].live_before);
/* Update life information for the new sequence. */
+ x = try;
do
{
- if (INSN_P (try))
+ if (INSN_P (x))
{
if (--i < 0)
i = MAX_INSNS_PER_PEEP2;
- peep2_insn_data[i].insn = try;
- propagate_one_insn (pbi, try);
+ peep2_insn_data[i].insn = x;
+ propagate_one_insn (pbi, x);
COPY_REG_SET (peep2_insn_data[i].live_before, live);
}
- try = PREV_INSN (try);
+ x = PREV_INSN (x);
}
- while (try != prev);
+ while (x != prev);
/* ??? Should verify that LIVE now matches what we
had before the new sequence. */
peep2_current = i;
#endif
+
+ /* If we generated a jump instruction, it won't have
+ JUMP_LABEL set. Recompute after we're done. */
+ for (x = try; x != before_try; x = PREV_INSN (x))
+ if (GET_CODE (x) == JUMP_INSN)
+ {
+ do_rebuild_jump_labels = true;
+ break;
+ }
}
}
FREE_REG_SET (peep2_insn_data[i].live_before);
FREE_REG_SET (live);
+ if (do_rebuild_jump_labels)
+ rebuild_jump_labels (get_insns ());
+
+ /* If we eliminated EH edges, we may be able to merge blocks. Further,
+ we've changed global life since exception handlers are no longer
+ reachable. */
+ if (do_cleanup_cfg)
+ {
+ cleanup_cfg (0);
+ update_life_info (0, UPDATE_LIFE_GLOBAL_RM_NOTES, PROP_DEATH_NOTES);
+ }
#ifdef HAVE_conditional_execution
- count_or_remove_death_notes (blocks, 1);
- update_life_info (blocks, UPDATE_LIFE_LOCAL, PROP_DEATH_NOTES);
+ else
+ {
+ count_or_remove_death_notes (blocks, 1);
+ update_life_info (blocks, UPDATE_LIFE_LOCAL, PROP_DEATH_NOTES);
+ }
sbitmap_free (blocks);
#endif
}
#endif /* HAVE_peephole2 */
+
+/* Common predicates for use with define_bypass. */
+
+/* True if the dependency between OUT_INSN and IN_INSN is on the store
+ data not the address operand(s) of the store. IN_INSN must be
+ single_set. OUT_INSN must be either a single_set or a PARALLEL with
+ SETs inside. */
+
+int
+store_data_bypass_p (rtx out_insn, rtx in_insn)
+{
+ rtx out_set, in_set;
+
+ in_set = single_set (in_insn);
+ if (! in_set)
+ abort ();
+
+ if (GET_CODE (SET_DEST (in_set)) != MEM)
+ return false;
+
+ out_set = single_set (out_insn);
+ if (out_set)
+ {
+ if (reg_mentioned_p (SET_DEST (out_set), SET_DEST (in_set)))
+ return false;
+ }
+ else
+ {
+ rtx out_pat;
+ int i;
+
+ out_pat = PATTERN (out_insn);
+ if (GET_CODE (out_pat) != PARALLEL)
+ abort ();
+
+ for (i = 0; i < XVECLEN (out_pat, 0); i++)
+ {
+ rtx exp = XVECEXP (out_pat, 0, i);
+
+ if (GET_CODE (exp) == CLOBBER)
+ continue;
+
+ if (GET_CODE (exp) != SET)
+ abort ();
+
+ if (reg_mentioned_p (SET_DEST (exp), SET_DEST (in_set)))
+ return false;
+ }
+ }
+
+ return true;
+}
+
+/* True if the dependency between OUT_INSN and IN_INSN is in the IF_THEN_ELSE
+ condition, and not the THEN or ELSE branch. OUT_INSN may be either a single
+ or multiple set; IN_INSN should be single_set for truth, but for convenience
+ of insn categorization may be any JUMP or CALL insn. */
+
+int
+if_test_bypass_p (rtx out_insn, rtx in_insn)
+{
+ rtx out_set, in_set;
+
+ in_set = single_set (in_insn);
+ if (! in_set)
+ {
+ if (GET_CODE (in_insn) == JUMP_INSN || GET_CODE (in_insn) == CALL_INSN)
+ return false;
+ abort ();
+ }
+
+ if (GET_CODE (SET_SRC (in_set)) != IF_THEN_ELSE)
+ return false;
+ in_set = SET_SRC (in_set);
+
+ out_set = single_set (out_insn);
+ if (out_set)
+ {
+ if (reg_mentioned_p (SET_DEST (out_set), XEXP (in_set, 1))
+ || reg_mentioned_p (SET_DEST (out_set), XEXP (in_set, 2)))
+ return false;
+ }
+ else
+ {
+ rtx out_pat;
+ int i;
+
+ out_pat = PATTERN (out_insn);
+ if (GET_CODE (out_pat) != PARALLEL)
+ abort ();
+
+ for (i = 0; i < XVECLEN (out_pat, 0); i++)
+ {
+ rtx exp = XVECEXP (out_pat, 0, i);
+
+ if (GET_CODE (exp) == CLOBBER)
+ continue;
+
+ if (GET_CODE (exp) != SET)
+ abort ();
+
+ if (reg_mentioned_p (SET_DEST (out_set), XEXP (in_set, 1))
+ || reg_mentioned_p (SET_DEST (out_set), XEXP (in_set, 2)))
+ return false;
+ }
+ }
+
+ return true;
+}
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