extern enum insn_code movcc_gen_code[NUM_MACHINE_MODES];
#endif
+/* Indexed by the machine mode, gives the insn code for vector conditional
+ operation. */
+
+extern enum insn_code vcond_gen_code[NUM_MACHINE_MODES];
+extern enum insn_code vcondu_gen_code[NUM_MACHINE_MODES];
+
/* This array records the insn_code of insns to perform block moves. */
extern enum insn_code movmem_optab[NUM_MACHINE_MODES];
/* Generate code for a FIX_EXPR. */
extern void expand_fix (rtx, rtx, int);
+/* Return tree if target supports vector operations for COND_EXPR. */
+bool expand_vec_cond_expr_p (tree, enum machine_mode);
+
+/* Generate code for VEC_COND_EXPR. */
+extern rtx expand_vec_cond_expr (tree, rtx);
+
#endif /* GCC_OPTABS_H */