/* Allocate registers within a basic block, for GNU compiler.
- Copyright (C) 1987, 88, 91, 93-98, 1999 Free Software Foundation, Inc.
+ Copyright (C) 1987, 1988, 1991, 1993, 1994, 1995, 1996, 1997, 1998,
+ 1999, 2000 Free Software Foundation, Inc.
This file is part of GNU CC.
the Free Software Foundation, 59 Temple Place - Suite 330,
Boston, MA 02111-1307, USA. */
-
/* Allocation of hard register numbers to pseudo registers is done in
two passes. In this pass we consider only regs that are born and
die once within one basic block. We do this one basic block at a
Tying is represented with "quantity numbers".
A non-tied register is given a new quantity number.
Tied registers have the same quantity number.
-
+
We have provision to exempt registers, even when they are contained
within the block, that can be tied to others that are not contained in it.
This is so that global_alloc could process them both and tie them then.
#include "config.h"
#include "system.h"
#include "rtl.h"
+#include "tm_p.h"
#include "flags.h"
+#include "hard-reg-set.h"
#include "basic-block.h"
#include "regs.h"
-#include "hard-reg-set.h"
+#include "function.h"
#include "insn-config.h"
#include "insn-attr.h"
#include "recog.h"
static int next_qty;
-/* In all the following vectors indexed by quantity number. */
+/* Information we maitain about each quantity. */
+struct qty
+{
+ /* The number of refs to quantity Q. */
-/* Element Q is the hard reg number chosen for quantity Q,
- or -1 if none was found. */
+ int n_refs;
-static short *qty_phys_reg;
+ /* Insn number (counting from head of basic block)
+ where quantity Q was born. -1 if birth has not been recorded. */
-/* We maintain two hard register sets that indicate suggested hard registers
- for each quantity. The first, qty_phys_copy_sugg, contains hard registers
- that are tied to the quantity by a simple copy. The second contains all
- hard registers that are tied to the quantity via an arithmetic operation.
+ int birth;
- The former register set is given priority for allocation. This tends to
- eliminate copy insns. */
+ /* Insn number (counting from head of basic block)
+ where given quantity died. Due to the way tying is done,
+ and the fact that we consider in this pass only regs that die but once,
+ a quantity can die only once. Each quantity's life span
+ is a set of consecutive insns. -1 if death has not been recorded. */
-/* Element Q is a set of hard registers that are suggested for quantity Q by
- copy insns. */
+ int death;
-static HARD_REG_SET *qty_phys_copy_sugg;
+ /* Number of words needed to hold the data in given quantity.
+ This depends on its machine mode. It is used for these purposes:
+ 1. It is used in computing the relative importances of qtys,
+ which determines the order in which we look for regs for them.
+ 2. It is used in rules that prevent tying several registers of
+ different sizes in a way that is geometrically impossible
+ (see combine_regs). */
-/* Element Q is a set of hard registers that are suggested for quantity Q by
- arithmetic insns. */
+ int size;
-static HARD_REG_SET *qty_phys_sugg;
+ /* Number of times a reg tied to given qty lives across a CALL_INSN. */
-/* Element Q is the number of suggested registers in qty_phys_copy_sugg. */
+ int n_calls_crossed;
-static short *qty_phys_num_copy_sugg;
+ /* The register number of one pseudo register whose reg_qty value is Q.
+ This register should be the head of the chain
+ maintained in reg_next_in_qty. */
-/* Element Q is the number of suggested registers in qty_phys_sugg. */
+ int first_reg;
-static short *qty_phys_num_sugg;
+ /* Reg class contained in (smaller than) the preferred classes of all
+ the pseudo regs that are tied in given quantity.
+ This is the preferred class for allocating that quantity. */
-/* Element Q is the number of refs to quantity Q. */
+ enum reg_class min_class;
-static int *qty_n_refs;
+ /* Register class within which we allocate given qty if we can't get
+ its preferred class. */
-/* Element Q is a reg class contained in (smaller than) the
- preferred classes of all the pseudo regs that are tied in quantity Q.
- This is the preferred class for allocating that quantity. */
+ enum reg_class alternate_class;
-static enum reg_class *qty_min_class;
+ /* This holds the mode of the registers that are tied to given qty,
+ or VOIDmode if registers with differing modes are tied together. */
-/* Insn number (counting from head of basic block)
- where quantity Q was born. -1 if birth has not been recorded. */
+ enum machine_mode mode;
-static int *qty_birth;
+ /* the hard reg number chosen for given quantity,
+ or -1 if none was found. */
-/* Insn number (counting from head of basic block)
- where quantity Q died. Due to the way tying is done,
- and the fact that we consider in this pass only regs that die but once,
- a quantity can die only once. Each quantity's life span
- is a set of consecutive insns. -1 if death has not been recorded. */
+ short phys_reg;
-static int *qty_death;
+ /* Nonzero if this quantity has been used in a SUBREG in some
+ way that is illegal. */
-/* Number of words needed to hold the data in quantity Q.
- This depends on its machine mode. It is used for these purposes:
- 1. It is used in computing the relative importances of qtys,
- which determines the order in which we look for regs for them.
- 2. It is used in rules that prevent tying several registers of
- different sizes in a way that is geometrically impossible
- (see combine_regs). */
+ char changes_mode;
-static int *qty_size;
+};
-/* This holds the mode of the registers that are tied to qty Q,
- or VOIDmode if registers with differing modes are tied together. */
+static struct qty *qty;
-static enum machine_mode *qty_mode;
+/* These fields are kept separately to speedup their clearing. */
-/* Number of times a reg tied to qty Q lives across a CALL_INSN. */
+/* We maintain two hard register sets that indicate suggested hard registers
+ for each quantity. The first, phys_copy_sugg, contains hard registers
+ that are tied to the quantity by a simple copy. The second contains all
+ hard registers that are tied to the quantity via an arithmetic operation.
-static int *qty_n_calls_crossed;
+ The former register set is given priority for allocation. This tends to
+ eliminate copy insns. */
-/* Register class within which we allocate qty Q if we can't get
- its preferred class. */
+/* Element Q is a set of hard registers that are suggested for quantity Q by
+ copy insns. */
-static enum reg_class *qty_alternate_class;
+static HARD_REG_SET *qty_phys_copy_sugg;
-/* Element Q is nonzero if this quantity has been used in a SUBREG
- that changes its size. */
+/* Element Q is a set of hard registers that are suggested for quantity Q by
+ arithmetic insns. */
+
+static HARD_REG_SET *qty_phys_sugg;
+
+/* Element Q is the number of suggested registers in qty_phys_copy_sugg. */
-static char *qty_changes_size;
+static short *qty_phys_num_copy_sugg;
-/* Element Q is the register number of one pseudo register whose
- reg_qty value is Q. This register should be the head of the chain
- maintained in reg_next_in_qty. */
+/* Element Q is the number of suggested registers in qty_phys_sugg. */
-static int *qty_first_reg;
+static short *qty_phys_num_sugg;
/* If (REG N) has been assigned a quantity number, is a register number
of another register assigned the same quantity number, or -1 for the
- end of the chain. qty_first_reg point to the head of this chain. */
+ end of the chain. qty->first_reg point to the head of this chain. */
static int *reg_next_in_qty;
static int this_insn_number;
static rtx this_insn;
-/* Used to communicate changes made by update_equiv_regs to
- memref_referenced_p. reg_equiv_replacement is set for any REG_EQUIV note
- found or created, so that we can keep track of what memory accesses might
- be created later, e.g. by reload. */
-
-static rtx *reg_equiv_replacement;
-
-/* Used for communication between update_equiv_regs and no_equiv. */
-static rtx *reg_equiv_init_insns;
-
-static void alloc_qty PROTO((int, enum machine_mode, int, int));
-static void validate_equiv_mem_from_store PROTO((rtx, rtx));
-static int validate_equiv_mem PROTO((rtx, rtx, rtx));
-static int contains_replace_regs PROTO((rtx, char *));
-static int memref_referenced_p PROTO((rtx, rtx));
-static int memref_used_between_p PROTO((rtx, rtx, rtx));
-static void update_equiv_regs PROTO((void));
-static void no_equiv PROTO((rtx, rtx));
-static void block_alloc PROTO((int));
-static int qty_sugg_compare PROTO((int, int));
-static int qty_sugg_compare_1 PROTO((const GENERIC_PTR, const GENERIC_PTR));
-static int qty_compare PROTO((int, int));
-static int qty_compare_1 PROTO((const GENERIC_PTR, const GENERIC_PTR));
-static int combine_regs PROTO((rtx, rtx, int, int, rtx, int));
-static int reg_meets_class_p PROTO((int, enum reg_class));
-static void update_qty_class PROTO((int, int));
-static void reg_is_set PROTO((rtx, rtx));
-static void reg_is_born PROTO((rtx, int));
-static void wipe_dead_reg PROTO((rtx, int));
-static int find_free_reg PROTO((enum reg_class, enum machine_mode,
+struct equivalence
+{
+ /* Set when an attempt should be made to replace a register
+ with the associated src entry. */
+
+ char replace;
+
+ /* Set when a REG_EQUIV note is found or created. Use to
+ keep track of what memory accesses might be created later,
+ e.g. by reload. */
+
+ rtx replacement;
+
+ rtx src;
+
+ /* Loop depth is used to recognize equivalences which appear
+ to be present within the same loop (or in an inner loop). */
+
+ int loop_depth;
+
+ /* The list of each instruction which initializes this register. */
+
+ rtx init_insns;
+};
+
+/* reg_equiv[N] (where N is a pseudo reg number) is the equivalence
+ structure for that register. */
+
+static struct equivalence *reg_equiv;
+
+/* Nonzero if we recorded an equivalence for a LABEL_REF. */
+static int recorded_label_ref;
+
+static void alloc_qty PARAMS ((int, enum machine_mode, int, int));
+static void validate_equiv_mem_from_store PARAMS ((rtx, rtx, void *));
+static int validate_equiv_mem PARAMS ((rtx, rtx, rtx));
+static int equiv_init_varies_p PARAMS ((rtx));
+static int equiv_init_movable_p PARAMS ((rtx, int));
+static int contains_replace_regs PARAMS ((rtx));
+static int memref_referenced_p PARAMS ((rtx, rtx));
+static int memref_used_between_p PARAMS ((rtx, rtx, rtx));
+static void update_equiv_regs PARAMS ((void));
+static void no_equiv PARAMS ((rtx, rtx, void *));
+static void block_alloc PARAMS ((int));
+static int qty_sugg_compare PARAMS ((int, int));
+static int qty_sugg_compare_1 PARAMS ((const PTR, const PTR));
+static int qty_compare PARAMS ((int, int));
+static int qty_compare_1 PARAMS ((const PTR, const PTR));
+static int combine_regs PARAMS ((rtx, rtx, int, int, rtx, int));
+static int reg_meets_class_p PARAMS ((int, enum reg_class));
+static void update_qty_class PARAMS ((int, int));
+static void reg_is_set PARAMS ((rtx, rtx, void *));
+static void reg_is_born PARAMS ((rtx, int));
+static void wipe_dead_reg PARAMS ((rtx, int));
+static int find_free_reg PARAMS ((enum reg_class, enum machine_mode,
int, int, int, int, int));
-static void mark_life PROTO((int, enum machine_mode, int));
-static void post_mark_life PROTO((int, enum machine_mode, int, int, int));
-static int no_conflict_p PROTO((rtx, rtx, rtx));
-static int requires_inout PROTO((const char *));
+static void mark_life PARAMS ((int, enum machine_mode, int));
+static void post_mark_life PARAMS ((int, enum machine_mode, int, int, int));
+static int no_conflict_p PARAMS ((rtx, rtx, rtx));
+static int requires_inout PARAMS ((const char *));
\f
/* Allocate a new quantity (new within current basic block)
for register number REGNO which is born at index BIRTH
enum machine_mode mode;
int size, birth;
{
- register int qty = next_qty++;
+ register int qtyno = next_qty++;
- reg_qty[regno] = qty;
+ reg_qty[regno] = qtyno;
reg_offset[regno] = 0;
reg_next_in_qty[regno] = -1;
- qty_first_reg[qty] = regno;
- qty_size[qty] = size;
- qty_mode[qty] = mode;
- qty_birth[qty] = birth;
- qty_n_calls_crossed[qty] = REG_N_CALLS_CROSSED (regno);
- qty_min_class[qty] = reg_preferred_class (regno);
- qty_alternate_class[qty] = reg_alternate_class (regno);
- qty_n_refs[qty] = REG_N_REFS (regno);
- qty_changes_size[qty] = REG_CHANGES_SIZE (regno);
+ qty[qtyno].first_reg = regno;
+ qty[qtyno].size = size;
+ qty[qtyno].mode = mode;
+ qty[qtyno].birth = birth;
+ qty[qtyno].n_calls_crossed = REG_N_CALLS_CROSSED (regno);
+ qty[qtyno].min_class = reg_preferred_class (regno);
+ qty[qtyno].alternate_class = reg_alternate_class (regno);
+ qty[qtyno].n_refs = REG_N_REFS (regno);
+ qty[qtyno].changes_mode = REG_CHANGES_MODE (regno);
}
\f
/* Main entry point of this file. */
-void
+int
local_alloc ()
{
register int b, i;
int max_qty;
+ /* We need to keep track of whether or not we recorded a LABEL_REF so
+ that we know if the jump optimizer needs to be rerun. */
+ recorded_label_ref = 0;
+
/* Leaf functions and non-leaf functions have different needs.
If defined, let the machine say what kind of ordering we
should use. */
See the declarations of these variables, above,
for what they mean. */
- qty_phys_reg = (short *) alloca (max_qty * sizeof (short));
+ qty = (struct qty *) xmalloc (max_qty * sizeof (struct qty));
qty_phys_copy_sugg
- = (HARD_REG_SET *) alloca (max_qty * sizeof (HARD_REG_SET));
- qty_phys_num_copy_sugg = (short *) alloca (max_qty * sizeof (short));
- qty_phys_sugg = (HARD_REG_SET *) alloca (max_qty * sizeof (HARD_REG_SET));
- qty_phys_num_sugg = (short *) alloca (max_qty * sizeof (short));
- qty_birth = (int *) alloca (max_qty * sizeof (int));
- qty_death = (int *) alloca (max_qty * sizeof (int));
- qty_first_reg = (int *) alloca (max_qty * sizeof (int));
- qty_size = (int *) alloca (max_qty * sizeof (int));
- qty_mode
- = (enum machine_mode *) alloca (max_qty * sizeof (enum machine_mode));
- qty_n_calls_crossed = (int *) alloca (max_qty * sizeof (int));
- qty_min_class
- = (enum reg_class *) alloca (max_qty * sizeof (enum reg_class));
- qty_alternate_class
- = (enum reg_class *) alloca (max_qty * sizeof (enum reg_class));
- qty_n_refs = (int *) alloca (max_qty * sizeof (int));
- qty_changes_size = (char *) alloca (max_qty * sizeof (char));
+ = (HARD_REG_SET *) xmalloc (max_qty * sizeof (HARD_REG_SET));
+ qty_phys_num_copy_sugg = (short *) xmalloc (max_qty * sizeof (short));
+ qty_phys_sugg = (HARD_REG_SET *) xmalloc (max_qty * sizeof (HARD_REG_SET));
+ qty_phys_num_sugg = (short *) xmalloc (max_qty * sizeof (short));
reg_qty = (int *) xmalloc (max_regno * sizeof (int));
reg_offset = (char *) xmalloc (max_regno * sizeof (char));
- reg_next_in_qty = (int *) xmalloc(max_regno * sizeof (int));
+ reg_next_in_qty = (int *) xmalloc (max_regno * sizeof (int));
- /* Allocate the reg_renumber array */
+ /* Allocate the reg_renumber array. */
allocate_reg_info (max_regno, FALSE, TRUE);
/* Determine which pseudo-registers can be allocated by local-alloc.
In general, these are the registers used only in a single block and
- which only die once. However, if a register's preferred class has only
- a few entries, don't allocate this register here unless it is preferred
- or nothing since retry_global_alloc won't be able to move it to
- GENERAL_REGS if a reload register of this class is needed.
+ which only die once.
We need not be concerned with which block actually uses the register
since we will never see it outside that block. */
for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
{
- if (REG_BASIC_BLOCK (i) >= 0 && REG_N_DEATHS (i) == 1
- && (reg_alternate_class (i) == NO_REGS
- || ! CLASS_LIKELY_SPILLED_P (reg_preferred_class (i))))
+ if (REG_BASIC_BLOCK (i) >= 0 && REG_N_DEATHS (i) == 1)
reg_qty[i] = -2;
else
reg_qty[i] = -1;
else
{
#define CLEAR(vector) \
- bzero ((char *) (vector), (sizeof (*(vector))) * next_qty);
+ memset ((char *) (vector), 0, (sizeof (*(vector))) * next_qty);
CLEAR (qty_phys_copy_sugg);
CLEAR (qty_phys_num_copy_sugg);
next_qty = 0;
block_alloc (b);
-#ifdef USE_C_ALLOCA
- alloca (0);
-#endif
}
+ free (qty);
+ free (qty_phys_copy_sugg);
+ free (qty_phys_num_copy_sugg);
+ free (qty_phys_sugg);
+ free (qty_phys_num_sugg);
+
free (reg_qty);
free (reg_offset);
free (reg_next_in_qty);
+
+ return recorded_label_ref;
}
\f
-/* Depth of loops we are in while in update_equiv_regs. */
-static int loop_depth;
-
/* Used for communication between the following two functions: contains
a MEM that we wish to ensure remains unchanged. */
static rtx equiv_mem;
Called via note_stores. */
static void
-validate_equiv_mem_from_store (dest, set)
+validate_equiv_mem_from_store (dest, set, data)
rtx dest;
rtx set ATTRIBUTE_UNUSED;
+ void *data ATTRIBUTE_UNUSED;
{
if ((GET_CODE (dest) == REG
&& reg_overlap_mentioned_p (dest, equiv_mem))
for (insn = start; insn && ! equiv_mem_modified; insn = NEXT_INSN (insn))
{
- if (GET_RTX_CLASS (GET_CODE (insn)) != 'i')
+ if (! INSN_P (insn))
continue;
if (find_reg_note (insn, REG_DEAD, reg))
&& ! CONST_CALL_P (insn))
return 0;
- note_stores (PATTERN (insn), validate_equiv_mem_from_store);
+ note_stores (PATTERN (insn), validate_equiv_mem_from_store, NULL);
/* If a register mentioned in MEMREF is modified via an
auto-increment, we lose the equivalence. Do the same if one
return 0;
}
-/* TRUE if X uses any registers for which reg_equiv_replace is true. */
+/* Returns zero if X is known to be invariant. */
static int
-contains_replace_regs (x, reg_equiv_replace)
+equiv_init_varies_p (x)
rtx x;
- char *reg_equiv_replace;
+{
+ register RTX_CODE code = GET_CODE (x);
+ register int i;
+ register const char *fmt;
+
+ switch (code)
+ {
+ case MEM:
+ return ! RTX_UNCHANGING_P (x) || equiv_init_varies_p (XEXP (x, 0));
+
+ case QUEUED:
+ return 1;
+
+ case CONST:
+ case CONST_INT:
+ case CONST_DOUBLE:
+ case SYMBOL_REF:
+ case LABEL_REF:
+ return 0;
+
+ case REG:
+ return reg_equiv[REGNO (x)].replace == 0 && rtx_varies_p (x, 0);
+
+ case ASM_OPERANDS:
+ if (MEM_VOLATILE_P (x))
+ return 1;
+
+ /* FALLTHROUGH */
+
+ default:
+ break;
+ }
+
+ fmt = GET_RTX_FORMAT (code);
+ for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
+ if (fmt[i] == 'e')
+ {
+ if (equiv_init_varies_p (XEXP (x, i)))
+ return 1;
+ }
+ else if (fmt[i] == 'E')
+ {
+ int j;
+ for (j = 0; j < XVECLEN (x, i); j++)
+ if (equiv_init_varies_p (XVECEXP (x, i, j)))
+ return 1;
+ }
+
+ return 0;
+}
+
+/* Returns non-zero if X (used to initialize register REGNO) is movable.
+ X is only movable if the registers it uses have equivalent initializations
+ which appear to be within the same loop (or in an inner loop) and movable
+ or if they are not candidates for local_alloc and don't vary. */
+
+static int
+equiv_init_movable_p (x, regno)
+ rtx x;
+ int regno;
{
int i, j;
- char *fmt;
+ const char *fmt;
+ enum rtx_code code = GET_CODE (x);
+
+ switch (code)
+ {
+ case SET:
+ return equiv_init_movable_p (SET_SRC (x), regno);
+
+ case CC0:
+ case CLOBBER:
+ return 0;
+
+ case PRE_INC:
+ case PRE_DEC:
+ case POST_INC:
+ case POST_DEC:
+ case PRE_MODIFY:
+ case POST_MODIFY:
+ return 0;
+
+ case REG:
+ return (reg_equiv[REGNO (x)].loop_depth >= reg_equiv[regno].loop_depth
+ && reg_equiv[REGNO (x)].replace)
+ || (REG_BASIC_BLOCK (REGNO (x)) < 0 && ! rtx_varies_p (x, 0));
+
+ case UNSPEC_VOLATILE:
+ return 0;
+
+ case ASM_OPERANDS:
+ if (MEM_VOLATILE_P (x))
+ return 0;
+
+ /* FALLTHROUGH */
+
+ default:
+ break;
+ }
+
+ fmt = GET_RTX_FORMAT (code);
+ for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
+ switch (fmt[i])
+ {
+ case 'e':
+ if (! equiv_init_movable_p (XEXP (x, i), regno))
+ return 0;
+ break;
+ case 'E':
+ for (j = XVECLEN (x, i) - 1; j >= 0; j--)
+ if (! equiv_init_movable_p (XVECEXP (x, i, j), regno))
+ return 0;
+ break;
+ }
+
+ return 1;
+}
+
+/* TRUE if X uses any registers for which reg_equiv[REGNO].replace is true. */
+
+static int
+contains_replace_regs (x)
+ rtx x;
+{
+ int i, j;
+ const char *fmt;
enum rtx_code code = GET_CODE (x);
switch (code)
return 0;
case REG:
- return reg_equiv_replace[REGNO (x)];
+ return reg_equiv[REGNO (x)].replace;
default:
break;
switch (fmt[i])
{
case 'e':
- if (contains_replace_regs (XEXP (x, i), reg_equiv_replace))
+ if (contains_replace_regs (XEXP (x, i)))
return 1;
break;
case 'E':
for (j = XVECLEN (x, i) - 1; j >= 0; j--)
- if (contains_replace_regs (XVECEXP (x, i, j), reg_equiv_replace))
+ if (contains_replace_regs (XVECEXP (x, i, j)))
return 1;
break;
}
rtx memref;
{
int i, j;
- char *fmt;
+ const char *fmt;
enum rtx_code code = GET_CODE (x);
switch (code)
return 0;
case REG:
- return (reg_equiv_replacement[REGNO (x)]
+ return (reg_equiv[REGNO (x)].replacement
&& memref_referenced_p (memref,
- reg_equiv_replacement[REGNO (x)]));
+ reg_equiv[REGNO (x)].replacement));
case MEM:
if (true_dependence (memref, VOIDmode, x, rtx_varies_p))
return 1;
return memref_referenced_p (memref, SET_SRC (x));
-
+
default:
break;
}
for (insn = NEXT_INSN (start); insn != NEXT_INSN (end);
insn = NEXT_INSN (insn))
- if (GET_RTX_CLASS (GET_CODE (insn)) == 'i'
- && memref_referenced_p (memref, PATTERN (insn)))
+ if (INSN_P (insn) && memref_referenced_p (memref, PATTERN (insn)))
return 1;
return 0;
static void
update_equiv_regs ()
{
- /* Set when an attempt should be made to replace a register with the
- associated reg_equiv_replacement entry at the end of this function. */
- char *reg_equiv_replace
- = (char *) alloca (max_regno * sizeof *reg_equiv_replace);
rtx insn;
- int block, depth;
-
- reg_equiv_init_insns = (rtx *) alloca (max_regno * sizeof (rtx));
- reg_equiv_replacement = (rtx *) alloca (max_regno * sizeof (rtx));
+ int block;
+ int loop_depth;
+ regset_head cleared_regs;
+ int clear_regnos = 0;
- bzero ((char *) reg_equiv_init_insns, max_regno * sizeof (rtx));
- bzero ((char *) reg_equiv_replacement, max_regno * sizeof (rtx));
- bzero ((char *) reg_equiv_replace, max_regno * sizeof *reg_equiv_replace);
+ reg_equiv = (struct equivalence *) xcalloc (max_regno, sizeof *reg_equiv);
+ INIT_REG_SET (&cleared_regs);
init_alias_analysis ();
- loop_depth = 1;
-
/* Scan the insns and find which registers have equivalences. Do this
in a separate scan of the insns because (due to -fcse-follow-jumps)
a register can be set below its use. */
+ loop_depth = 0;
for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
{
rtx note;
if (GET_CODE (insn) == NOTE)
{
if (NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_BEG)
- loop_depth++;
+ ++loop_depth;
else if (NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_END)
- loop_depth--;
+ {
+ if (! loop_depth)
+ abort ();
+ --loop_depth;
+ }
}
- if (GET_RTX_CLASS (GET_CODE (insn)) != 'i')
+ if (! INSN_P (insn))
continue;
for (note = REG_NOTES (insn); note; note = XEXP (note, 1))
if (REG_NOTE_KIND (note) == REG_INC)
- no_equiv (XEXP (note, 0), note);
+ no_equiv (XEXP (note, 0), note, NULL);
set = single_set (insn);
only mark all destinations as having no known equivalence. */
if (set == 0)
{
- note_stores (PATTERN (insn), no_equiv);
+ note_stores (PATTERN (insn), no_equiv, NULL);
continue;
}
else if (GET_CODE (PATTERN (insn)) == PARALLEL)
{
rtx part = XVECEXP (PATTERN (insn), 0, i);
if (part != set)
- note_stores (part, no_equiv);
+ note_stores (part, no_equiv, NULL);
}
}
Don't add a REG_EQUIV note if the insn already has one. The existing
REG_EQUIV is likely more useful than the one we are adding.
- If one of the regs in the address is marked as reg_equiv_replace,
- then we can't add this REG_EQUIV note. The reg_equiv_replace
+ If one of the regs in the address has reg_equiv[REGNO].replace set,
+ then we can't add this REG_EQUIV note. The reg_equiv[REGNO].replace
optimization may move the set of this register immediately before
- insn, which puts it after reg_equiv_init_insns[regno], and hence
+ insn, which puts it after reg_equiv[REGNO].init_insns, and hence
the mention in the REG_EQUIV note would be to an uninitialized
pseudo. */
/* ????? This test isn't good enough; we might see a MEM with a use of
a pseudo register before we see its setting insn that will cause
- reg_equiv_replace for that pseudo to be set.
+ reg_equiv[].replace for that pseudo to be set.
Equivalences to MEMs should be made in another pass, after the
- reg_equiv_replace information has been gathered. */
+ reg_equiv[].replace information has been gathered. */
if (GET_CODE (dest) == MEM && GET_CODE (src) == REG
&& (regno = REGNO (src)) >= FIRST_PSEUDO_REGISTER
&& REG_BASIC_BLOCK (regno) >= 0
&& REG_N_SETS (regno) == 1
- && reg_equiv_init_insns[regno] != 0
- && reg_equiv_init_insns[regno] != const0_rtx
- && ! find_reg_note (insn, REG_EQUIV, NULL_RTX)
- && ! contains_replace_regs (XEXP (dest, 0), reg_equiv_replace))
+ && reg_equiv[regno].init_insns != 0
+ && reg_equiv[regno].init_insns != const0_rtx
+ && ! find_reg_note (XEXP (reg_equiv[regno].init_insns, 0),
+ REG_EQUIV, NULL_RTX)
+ && ! contains_replace_regs (XEXP (dest, 0)))
{
- rtx init_insn = XEXP (reg_equiv_init_insns[regno], 0);
+ rtx init_insn = XEXP (reg_equiv[regno].init_insns, 0);
if (validate_equiv_mem (init_insn, src, dest)
&& ! memref_used_between_p (dest, init_insn, insn))
REG_NOTES (init_insn)
if (GET_CODE (dest) != REG
|| (regno = REGNO (dest)) < FIRST_PSEUDO_REGISTER
- || reg_equiv_init_insns[regno] == const0_rtx
+ || reg_equiv[regno].init_insns == const0_rtx
|| (CLASS_LIKELY_SPILLED_P (reg_preferred_class (regno))
&& GET_CODE (src) == MEM))
{
/* This might be seting a SUBREG of a pseudo, a pseudo that is
also set somewhere else to a constant. */
- note_stores (set, no_equiv);
- continue;
- }
- /* Don't handle the equivalence if the source is in a register
- class that's likely to be spilled. */
- if (GET_CODE (src) == REG
- && REGNO (src) >= FIRST_PSEUDO_REGISTER
- && CLASS_LIKELY_SPILLED_P (reg_preferred_class (REGNO (src))))
- {
- no_equiv (dest, set);
+ note_stores (set, no_equiv, NULL);
continue;
}
note = find_reg_note (insn, REG_EQUAL, NULL_RTX);
+ /* cse sometimes generates function invariants, but doesn't put a
+ REG_EQUAL note on the insn. Since this note would be redundant,
+ there's no point creating it earlier than here. */
+ if (! note && ! rtx_varies_p (src, 0))
+ REG_NOTES (insn)
+ = note = gen_rtx_EXPR_LIST (REG_EQUAL, src, REG_NOTES (insn));
+
+ /* Don't bother considering a REG_EQUAL note containing an EXPR_LIST
+ since it represents a function call */
+ if (note && GET_CODE (XEXP (note, 0)) == EXPR_LIST)
+ note = NULL_RTX;
+
if (REG_N_SETS (regno) != 1
&& (! note
- || ! function_invariant_p (XEXP (note, 0))
- || (reg_equiv_replacement[regno]
+ || rtx_varies_p (XEXP (note, 0), 0)
+ || (reg_equiv[regno].replacement
&& ! rtx_equal_p (XEXP (note, 0),
- reg_equiv_replacement[regno]))))
+ reg_equiv[regno].replacement))))
{
- no_equiv (dest, set);
+ no_equiv (dest, set, NULL);
continue;
}
/* Record this insn as initializing this register. */
- reg_equiv_init_insns[regno]
- = gen_rtx_INSN_LIST (VOIDmode, insn, reg_equiv_init_insns[regno]);
+ reg_equiv[regno].init_insns
+ = gen_rtx_INSN_LIST (VOIDmode, insn, reg_equiv[regno].init_insns);
/* If this register is known to be equal to a constant, record that
it is always equivalent to the constant. */
- if (note && function_invariant_p (XEXP (note, 0)))
+ if (note && ! rtx_varies_p (XEXP (note, 0), 0))
PUT_MODE (note, (enum machine_mode) REG_EQUIV);
/* If this insn introduces a "constant" register, decrease the priority
a register used only in one basic block from a MEM. If so, and the
MEM remains unchanged for the life of the register, add a REG_EQUIV
note. */
-
+
note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
if (note == 0 && REG_BASIC_BLOCK (regno) >= 0
{
int regno = REGNO (dest);
- reg_equiv_replacement[regno] = XEXP (note, 0);
+ /* Record whether or not we created a REG_EQUIV note for a LABEL_REF.
+ We might end up substituting the LABEL_REF for uses of the
+ pseudo here or later. That kind of transformation may turn an
+ indirect jump into a direct jump, in which case we must rerun the
+ jump optimizer to ensure that the JUMP_LABEL fields are valid. */
+ if (GET_CODE (XEXP (note, 0)) == LABEL_REF
+ || (GET_CODE (XEXP (note, 0)) == CONST
+ && GET_CODE (XEXP (XEXP (note, 0), 0)) == PLUS
+ && (GET_CODE (XEXP (XEXP (XEXP (note, 0), 0), 0))
+ == LABEL_REF)))
+ recorded_label_ref = 1;
+
+ reg_equiv[regno].replacement = XEXP (note, 0);
+ reg_equiv[regno].src = src;
+ reg_equiv[regno].loop_depth = loop_depth;
/* Don't mess with things live during setjmp. */
if (REG_LIVE_LENGTH (regno) >= 0)
/* If the register is referenced exactly twice, meaning it is
set once and used once, indicate that the reference may be
- replaced by the equivalence we computed above. If the
- register is only used in one basic block, this can't succeed
- or combine would have done it.
+ replaced by the equivalence we computed above. Do this
+ even if the register is only used in one block so that
+ dependencies can be handled where the last register is
+ used in a different block (i.e. HIGH / LO_SUM sequences)
+ and to reduce the number of registers alive across calls.
It would be nice to use "loop_depth * 2" in the compare
below. Unfortunately, LOOP_DEPTH need not be constant within
memory and then used exactly once, not in a loop. */
if (REG_N_REFS (regno) == 2
- && REG_BASIC_BLOCK (regno) < 0
- && rtx_equal_p (XEXP (note, 0), SET_SRC (set)))
- reg_equiv_replace[regno] = 1;
+ && (rtx_equal_p (XEXP (note, 0), src)
+ || ! equiv_init_varies_p (src))
+ && GET_CODE (insn) == INSN
+ && equiv_init_movable_p (PATTERN (insn), regno))
+ reg_equiv[regno].replace = 1;
}
}
}
registers only used that once. If so, see if we can replace the
reference with the equivalent from. If we can, delete the
initializing reference and this register will go away. If we
- can't replace the reference, and the instruction is not in a
- loop, then move the register initialization just before the use,
- so that they are in the same basic block. */
- block = -1;
- depth = 0;
- for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
+ can't replace the reference, and the initialzing reference is
+ within the same loop (or in an inner loop), then move the register
+ initialization just before the use, so that they are in the same
+ basic block.
+
+ Skip this optimization if loop_depth isn't initially zero since
+ that indicates a mismatch between loop begin and loop end notes
+ (i.e. gcc.dg/noncompile/920721-2.c). */
+ block = n_basic_blocks - 1;
+ for (insn = (loop_depth == 0) ? get_last_insn () : NULL_RTX;
+ insn; insn = PREV_INSN (insn))
{
rtx link;
- /* Keep track of which basic block we are in. */
- if (block + 1 < n_basic_blocks
- && BLOCK_HEAD (block + 1) == insn)
- ++block;
-
- if (GET_RTX_CLASS (GET_CODE (insn)) != 'i')
+ if (! INSN_P (insn))
{
if (GET_CODE (insn) == NOTE)
{
- if (NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_BEG)
- ++depth;
- else if (NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_END)
+ if (NOTE_INSN_BASIC_BLOCK_P (insn))
+ block = NOTE_BASIC_BLOCK (insn)->index - 1;
+ else if (NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_BEG)
{
- --depth;
- if (depth < 0)
+ if (! loop_depth)
abort ();
+ --loop_depth;
}
+ else if (NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_END)
+ ++loop_depth;
}
continue;
int regno = REGNO (XEXP (link, 0));
rtx equiv_insn;
- if (! reg_equiv_replace[regno])
+ if (! reg_equiv[regno].replace
+ || reg_equiv[regno].loop_depth < loop_depth)
continue;
- /* reg_equiv_replace[REGNO] gets set only when
+ /* reg_equiv[REGNO].replace gets set only when
REG_N_REFS[REGNO] is 2, i.e. the register is set
once and used once. (If it were only set, but not used,
- flow would have deleted the setting insns.) Hence
- there can only be one insn in reg_equiv_init_insns. */
- equiv_insn = XEXP (reg_equiv_init_insns[regno], 0);
-
- if (validate_replace_rtx (regno_reg_rtx[regno],
- reg_equiv_replacement[regno], insn))
+ flow would have deleted the setting insns.) Hence
+ there can only be one insn in reg_equiv[REGNO].init_insns. */
+ if (reg_equiv[regno].init_insns == NULL_RTX
+ || XEXP (reg_equiv[regno].init_insns, 1) != NULL_RTX)
+ abort ();
+ equiv_insn = XEXP (reg_equiv[regno].init_insns, 0);
+
+ if (asm_noperands (PATTERN (equiv_insn)) < 0
+ && validate_replace_rtx (regno_reg_rtx[regno],
+ reg_equiv[regno].src, insn))
{
+ rtx equiv_link;
+ rtx last_link;
+ rtx note;
+
+ /* Find the last note. */
+ for (last_link = link; XEXP (last_link, 1);
+ last_link = XEXP (last_link, 1))
+ ;
+
+ /* Append the REG_DEAD notes from equiv_insn. */
+ equiv_link = REG_NOTES (equiv_insn);
+ while (equiv_link)
+ {
+ note = equiv_link;
+ equiv_link = XEXP (equiv_link, 1);
+ if (REG_NOTE_KIND (note) == REG_DEAD)
+ {
+ remove_note (equiv_insn, note);
+ XEXP (last_link, 1) = note;
+ XEXP (note, 1) = NULL_RTX;
+ last_link = note;
+ }
+ }
+
remove_death (regno, insn);
REG_N_REFS (regno) = 0;
PUT_CODE (equiv_insn, NOTE);
NOTE_LINE_NUMBER (equiv_insn) = NOTE_INSN_DELETED;
NOTE_SOURCE_FILE (equiv_insn) = 0;
+
+ reg_equiv[regno].init_insns
+ = XEXP (reg_equiv[regno].init_insns, 1);
}
- /* If we aren't in a loop, and there are no calls in
- INSN or in the initialization of the register, then
- move the initialization of the register to just
- before INSN. Update the flow information. */
- else if (depth == 0
- && GET_CODE (equiv_insn) == INSN
- && GET_CODE (insn) == INSN
- && REG_BASIC_BLOCK (regno) < 0)
+ /* Move the initialization of the register to just before
+ INSN. Update the flow information. */
+ else if (PREV_INSN (insn) != equiv_insn)
{
- int l;
+ rtx new_insn;
- emit_insn_before (copy_rtx (PATTERN (equiv_insn)), insn);
+ new_insn = emit_insn_before (PATTERN (equiv_insn), insn);
REG_NOTES (PREV_INSN (insn)) = REG_NOTES (equiv_insn);
+ REG_NOTES (equiv_insn) = 0;
PUT_CODE (equiv_insn, NOTE);
NOTE_LINE_NUMBER (equiv_insn) = NOTE_INSN_DELETED;
NOTE_SOURCE_FILE (equiv_insn) = 0;
- REG_NOTES (equiv_insn) = 0;
- if (block < 0)
- REG_BASIC_BLOCK (regno) = 0;
- else
- REG_BASIC_BLOCK (regno) = block;
+ XEXP (reg_equiv[regno].init_insns, 0) = new_insn;
+
+ REG_BASIC_BLOCK (regno) = block >= 0 ? block : 0;
REG_N_CALLS_CROSSED (regno) = 0;
REG_LIVE_LENGTH (regno) = 2;
if (block >= 0 && insn == BLOCK_HEAD (block))
BLOCK_HEAD (block) = PREV_INSN (insn);
- for (l = 0; l < n_basic_blocks; l++)
- CLEAR_REGNO_REG_SET (BASIC_BLOCK (l)->global_live_at_start,
- regno);
+ /* Remember to clear REGNO from all basic block's live
+ info. */
+ SET_REGNO_REG_SET (&cleared_regs, regno);
+ clear_regnos++;
}
}
}
}
+
+ /* Clear all dead REGNOs from all basic block's live info. */
+ if (clear_regnos)
+ {
+ int j, l;
+ if (clear_regnos > 8)
+ {
+ for (l = 0; l < n_basic_blocks; l++)
+ {
+ AND_COMPL_REG_SET (BASIC_BLOCK (l)->global_live_at_start,
+ &cleared_regs);
+ AND_COMPL_REG_SET (BASIC_BLOCK (l)->global_live_at_end,
+ &cleared_regs);
+ }
+ }
+ else
+ EXECUTE_IF_SET_IN_REG_SET (&cleared_regs, 0, j,
+ {
+ for (l = 0; l < n_basic_blocks; l++)
+ {
+ CLEAR_REGNO_REG_SET (BASIC_BLOCK (l)->global_live_at_start, j);
+ CLEAR_REGNO_REG_SET (BASIC_BLOCK (l)->global_live_at_end, j);
+ }
+ });
+ }
+
+ /* Clean up. */
+ end_alias_analysis ();
+ CLEAR_REG_SET (&cleared_regs);
+ free (reg_equiv);
}
/* Mark REG as having no known equivalence.
assignment - a SET, CLOBBER or REG_INC note. It is currently not used,
but needs to be there because this function is called from note_stores. */
static void
-no_equiv (reg, store)
+no_equiv (reg, store, data)
rtx reg, store ATTRIBUTE_UNUSED;
+ void *data ATTRIBUTE_UNUSED;
{
int regno;
rtx list;
if (GET_CODE (reg) != REG)
return;
regno = REGNO (reg);
- list = reg_equiv_init_insns[regno];
+ list = reg_equiv[regno].init_insns;
if (list == const0_rtx)
return;
for (; list; list = XEXP (list, 1))
rtx insn = XEXP (list, 0);
remove_note (insn, find_reg_note (insn, REG_EQUIV, NULL_RTX));
}
- reg_equiv_init_insns[regno] = const0_rtx;
- reg_equiv_replacement[regno] = NULL_RTX;
+ reg_equiv[regno].init_insns = const0_rtx;
+ reg_equiv[regno].replacement = NULL_RTX;
}
\f
/* Allocate hard regs to the pseudo regs used only within block number B.
/* +2 to leave room for a post_mark_life at the last insn and for
the birth of a CLOBBER in the first insn. */
- regs_live_at = (HARD_REG_SET *) alloca ((2 * insn_count + 2)
- * sizeof (HARD_REG_SET));
- bzero ((char *) regs_live_at, (2 * insn_count + 2) * sizeof (HARD_REG_SET));
+ regs_live_at = (HARD_REG_SET *) xcalloc ((2 * insn_count + 2),
+ sizeof (HARD_REG_SET));
/* Initialize table of hardware registers currently live. */
insn = BLOCK_HEAD (b);
while (1)
{
- register rtx body = PATTERN (insn);
-
if (GET_CODE (insn) != NOTE)
insn_number++;
- if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
+ if (INSN_P (insn))
{
register rtx link, set;
register int win = 0;
- register rtx r0, r1;
+ register rtx r0, r1 = NULL_RTX;
int combined_regno = -1;
int i;
If tying is done, WIN is set nonzero. */
- if (1
-#ifdef REGISTER_CONSTRAINTS
- && recog_n_operands > 1
- && recog_constraints[0][0] == '='
- && recog_constraints[0][1] != '&'
-#else
- && GET_CODE (PATTERN (insn)) == SET
- && rtx_equal_p (SET_DEST (PATTERN (insn)), recog_operand[0])
-#endif
- )
+ if (optimize
+ && recog_data.n_operands > 1
+ && recog_data.constraints[0][0] == '='
+ && recog_data.constraints[0][1] != '&')
{
-#ifdef REGISTER_CONSTRAINTS
/* If non-negative, is an operand that must match operand 0. */
int must_match_0 = -1;
/* Counts number of alternatives that require a match with
operand 0. */
int n_matching_alts = 0;
- for (i = 1; i < recog_n_operands; i++)
+ for (i = 1; i < recog_data.n_operands; i++)
{
- const char *p = recog_constraints[i];
+ const char *p = recog_data.constraints[i];
int this_match = (requires_inout (p));
n_matching_alts += this_match;
- if (this_match == recog_n_alternatives)
+ if (this_match == recog_data.n_alternatives)
must_match_0 = i;
}
-#endif
- r0 = recog_operand[0];
- for (i = 1; i < recog_n_operands; i++)
+ r0 = recog_data.operand[0];
+ for (i = 1; i < recog_data.n_operands; i++)
{
-#ifdef REGISTER_CONSTRAINTS
/* Skip this operand if we found an operand that
must match operand 0 and this operand isn't it
and can't be made to be it by commutativity. */
if (must_match_0 >= 0 && i != must_match_0
&& ! (i == must_match_0 + 1
- && recog_constraints[i-1][0] == '%')
+ && recog_data.constraints[i-1][0] == '%')
&& ! (i == must_match_0 - 1
- && recog_constraints[i][0] == '%'))
+ && recog_data.constraints[i][0] == '%'))
continue;
/* Likewise if each alternative has some operand that
- must match operand zero. In that case, skip any
+ must match operand zero. In that case, skip any
operand that doesn't list operand 0 since we know that
the operand always conflicts with operand 0. We
ignore commutatity in this case to keep things simple. */
- if (n_matching_alts == recog_n_alternatives
- && 0 == requires_inout (recog_constraints[i]))
+ if (n_matching_alts == recog_data.n_alternatives
+ && 0 == requires_inout (recog_data.constraints[i]))
continue;
-#endif
- r1 = recog_operand[i];
+ r1 = recog_data.operand[i];
/* If the operand is an address, find a register in it.
There may be more than one register, but we only try one
of them. */
- if (
-#ifdef REGISTER_CONSTRAINTS
- recog_constraints[i][0] == 'p'
-#else
- recog_operand_address_p[i]
-#endif
- )
+ if (recog_data.constraints[i][0] == 'p')
while (GET_CODE (r1) == PLUS || GET_CODE (r1) == MULT)
r1 = XEXP (r1, 0);
can only be in the same register as the output, give
priority to an equivalence found from that insn. */
int may_save_copy
- = ((SET_DEST (body) == r0 && SET_SRC (body) == r1)
-#ifdef REGISTER_CONSTRAINTS
- || (r1 == recog_operand[i] && must_match_0 >= 0)
-#endif
- );
-
+ = (r1 == recog_data.operand[i] && must_match_0 >= 0);
+
if (GET_CODE (r1) == REG || GET_CODE (r1) == SUBREG)
win = combine_regs (r1, r0, may_save_copy,
insn_number, insn, 0);
destination register won't have had a quantity number
assigned, since that would prevent combining. */
- if (GET_CODE (PATTERN (insn)) == CLOBBER
+ if (optimize
+ && GET_CODE (PATTERN (insn)) == CLOBBER
&& (r0 = XEXP (PATTERN (insn), 0),
GET_CODE (r0) == REG)
&& (link = find_reg_note (insn, REG_LIBCALL, NULL_RTX)) != 0
for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
if (REG_NOTE_KIND (link) == REG_DEAD
&& GET_CODE (XEXP (link, 0)) == REG
- && combined_regno != REGNO (XEXP (link, 0))
- && (no_conflict_combined_regno != REGNO (XEXP (link, 0))
- || ! find_reg_note (insn, REG_NO_CONFLICT, XEXP (link, 0))))
+ && combined_regno != (int) REGNO (XEXP (link, 0))
+ && (no_conflict_combined_regno != (int) REGNO (XEXP (link, 0))
+ || ! find_reg_note (insn, REG_NO_CONFLICT,
+ XEXP (link, 0))))
wipe_dead_reg (XEXP (link, 0), 0);
/* Allocate qty numbers for all registers local to this block
that are born (set) in this instruction.
A pseudo that already has a qty is not changed. */
- note_stores (PATTERN (insn), reg_is_set);
+ note_stores (PATTERN (insn), reg_is_set, NULL);
/* If anything is set in this insn and then unused, mark it as dying
after this insn, so it will conflict with our outputs. This
&& GET_CODE (XEXP (link, 0)) == REG)
wipe_dead_reg (XEXP (link, 0), 1);
- /* If this is an insn that has a REG_RETVAL note pointing at a
+ /* If this is an insn that has a REG_RETVAL note pointing at a
CLOBBER insn, we have reached the end of a REG_NO_CONFLICT
block, so clear any register number that combined within it. */
if ((note = find_reg_note (insn, REG_RETVAL, NULL_RTX)) != 0
/* Now every register that is local to this basic block
should have been given a quantity, or else -1 meaning ignore it.
- Every quantity should have a known birth and death.
+ Every quantity should have a known birth and death.
Order the qtys so we assign them registers in order of the
number of suggested registers they need so we allocate those with
the most restrictive needs first. */
- qty_order = (int *) alloca (next_qty * sizeof (int));
+ qty_order = (int *) xmalloc (next_qty * sizeof (int));
for (i = 0; i < next_qty; i++)
qty_order[i] = i;
{
q = qty_order[i];
if (qty_phys_num_sugg[q] != 0 || qty_phys_num_copy_sugg[q] != 0)
- qty_phys_reg[q] = find_free_reg (qty_min_class[q], qty_mode[q], q,
- 0, 1, qty_birth[q], qty_death[q]);
+ qty[q].phys_reg = find_free_reg (qty[q].min_class, qty[q].mode, q,
+ 0, 1, qty[q].birth, qty[q].death);
else
- qty_phys_reg[q] = -1;
+ qty[q].phys_reg = -1;
}
- /* Order the qtys so we assign them registers in order of
- decreasing length of life. Normally call qsort, but if we
+ /* Order the qtys so we assign them registers in order of
+ decreasing length of life. Normally call qsort, but if we
have only a very small number of quantities, sort them ourselves. */
for (i = 0; i < next_qty; i++)
for (i = 0; i < next_qty; i++)
{
q = qty_order[i];
- if (qty_phys_reg[q] < 0)
+ if (qty[q].phys_reg < 0)
{
#ifdef INSN_SCHEDULING
/* These values represent the adjusted lifetime of a qty so
The purpose behind extending the lifetime of this qty is to
discourage the register allocator from creating false
dependencies.
-
+
The adjustment value is choosen to indicate that this qty
conflicts with all the qtys in the instructions immediately
before and after the lifetime of this qty.
If allocation using the extended lifetime fails we will try
again with the qty's unadjusted lifetime. */
- int fake_birth = MAX (0, qty_birth[q] - 2 + qty_birth[q] % 2);
+ int fake_birth = MAX (0, qty[q].birth - 2 + qty[q].birth % 2);
int fake_death = MIN (insn_number * 2 + 1,
- qty_death[q] + 2 - qty_death[q] % 2);
+ qty[q].death + 2 - qty[q].death % 2);
#endif
if (N_REG_CLASSES > 1)
&& !optimize_size
&& !SMALL_REGISTER_CLASSES)
{
-
- qty_phys_reg[q] = find_free_reg (qty_min_class[q],
- qty_mode[q], q, 0, 0,
+ qty[q].phys_reg = find_free_reg (qty[q].min_class,
+ qty[q].mode, q, 0, 0,
fake_birth, fake_death);
- if (qty_phys_reg[q] >= 0)
+ if (qty[q].phys_reg >= 0)
continue;
}
#endif
- qty_phys_reg[q] = find_free_reg (qty_min_class[q],
- qty_mode[q], q, 0, 0,
- qty_birth[q], qty_death[q]);
- if (qty_phys_reg[q] >= 0)
+ qty[q].phys_reg = find_free_reg (qty[q].min_class,
+ qty[q].mode, q, 0, 0,
+ qty[q].birth, qty[q].death);
+ if (qty[q].phys_reg >= 0)
continue;
}
if (flag_schedule_insns_after_reload
&& !optimize_size
&& !SMALL_REGISTER_CLASSES
- && qty_alternate_class[q] != NO_REGS)
- qty_phys_reg[q] = find_free_reg (qty_alternate_class[q],
- qty_mode[q], q, 0, 0,
+ && qty[q].alternate_class != NO_REGS)
+ qty[q].phys_reg = find_free_reg (qty[q].alternate_class,
+ qty[q].mode, q, 0, 0,
fake_birth, fake_death);
#endif
- if (qty_alternate_class[q] != NO_REGS)
- qty_phys_reg[q] = find_free_reg (qty_alternate_class[q],
- qty_mode[q], q, 0, 0,
- qty_birth[q], qty_death[q]);
+ if (qty[q].alternate_class != NO_REGS)
+ qty[q].phys_reg = find_free_reg (qty[q].alternate_class,
+ qty[q].mode, q, 0, 0,
+ qty[q].birth, qty[q].death);
}
}
to the pseudo regs belonging to the qtys. */
for (q = 0; q < next_qty; q++)
- if (qty_phys_reg[q] >= 0)
+ if (qty[q].phys_reg >= 0)
{
- for (i = qty_first_reg[q]; i >= 0; i = reg_next_in_qty[i])
- reg_renumber[i] = qty_phys_reg[q] + reg_offset[i];
+ for (i = qty[q].first_reg; i >= 0; i = reg_next_in_qty[i])
+ reg_renumber[i] = qty[q].phys_reg + reg_offset[i];
}
+
+ /* Clean up. */
+ free (regs_live_at);
+ free (qty_order);
}
\f
/* Compare two quantities' priority for getting real registers.
QTY_CMP_PRI is also used by qty_sugg_compare. */
#define QTY_CMP_PRI(q) \
- ((int) (((double) (floor_log2 (qty_n_refs[q]) * qty_n_refs[q] * qty_size[q]) \
- / (qty_death[q] - qty_birth[q])) * 10000))
+ ((int) (((double) (floor_log2 (qty[q].n_refs) * qty[q].n_refs * qty[q].size) \
+ / (qty[q].death - qty[q].birth)) * 10000))
static int
qty_compare (q1, q2)
static int
qty_compare_1 (q1p, q2p)
- const GENERIC_PTR q1p;
- const GENERIC_PTR q2p;
+ const PTR q1p;
+ const PTR q2p;
{
- register int q1 = *(int *)q1p, q2 = *(int *)q2p;
+ register int q1 = *(const int *) q1p, q2 = *(const int *) q2p;
register int tem = QTY_CMP_PRI (q2) - QTY_CMP_PRI (q1);
if (tem != 0)
if (tem != 0)
return tem;
-
+
return QTY_CMP_PRI (q2) - QTY_CMP_PRI (q1);
}
static int
qty_sugg_compare_1 (q1p, q2p)
- const GENERIC_PTR q1p;
- const GENERIC_PTR q2p;
+ const PTR q1p;
+ const PTR q2p;
{
- register int q1 = *(int *)q1p, q2 = *(int *)q2p;
+ register int q1 = *(const int *) q1p, q2 = *(const int *) q2p;
register int tem = QTY_CMP_SUGG (q1) - QTY_CMP_SUGG (q2);
if (tem != 0)
MAY_SAVE_COPYCOPY is non-zero if this insn is simply copying USEDREG to
SETREG or if the input and output must share a register.
In that case, we record a hard reg suggestion in QTY_PHYS_COPY_SUGG.
-
+
There are elaborate checks for the validity of combining. */
-
static int
combine_regs (usedreg, setreg, may_save_copy, insn_number, insn, already_dead)
rtx usedreg, setreg;
/* Do not combine with a smaller already-assigned object
if that smaller object is already combined with something bigger. */
|| (ssize > usize && ureg >= FIRST_PSEUDO_REGISTER
- && usize < qty_size[reg_qty[ureg]])
+ && usize < qty[reg_qty[ureg]].size)
/* Can't combine if SREG is not a register we can allocate. */
|| (sreg >= FIRST_PSEUDO_REGISTER && reg_qty[sreg] == -1)
/* Don't combine with a pseudo mentioned in a REG_NO_CONFLICT note.
|| ureg == sreg
/* Don't try to connect two different hardware registers. */
|| (ureg < FIRST_PSEUDO_REGISTER && sreg < FIRST_PSEUDO_REGISTER)
- /* Don't use a hard reg that might be spilled. */
- || (ureg < FIRST_PSEUDO_REGISTER
- && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (ureg)))
- || (sreg < FIRST_PSEUDO_REGISTER
- && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (sreg)))
/* Don't connect two different machine modes if they have different
implications as to which registers may be used. */
|| !MODES_TIEABLE_P (GET_MODE (usedreg), GET_MODE (setreg)))
are compatible. */
if ((already_dead || find_regno_note (insn, REG_DEAD, ureg))
- && reg_meets_class_p (sreg, qty_min_class[reg_qty[ureg]]))
+ && reg_meets_class_p (sreg, qty[reg_qty[ureg]].min_class))
{
/* Add SREG to UREG's quantity. */
sqty = reg_qty[ureg];
reg_qty[sreg] = sqty;
reg_offset[sreg] = reg_offset[ureg] + offset;
- reg_next_in_qty[sreg] = qty_first_reg[sqty];
- qty_first_reg[sqty] = sreg;
+ reg_next_in_qty[sreg] = qty[sqty].first_reg;
+ qty[sqty].first_reg = sreg;
- /* If SREG's reg class is smaller, set qty_min_class[SQTY]. */
+ /* If SREG's reg class is smaller, set qty[SQTY].min_class. */
update_qty_class (sqty, sreg);
/* Update info about quantity SQTY. */
- qty_n_calls_crossed[sqty] += REG_N_CALLS_CROSSED (sreg);
- qty_n_refs[sqty] += REG_N_REFS (sreg);
+ qty[sqty].n_calls_crossed += REG_N_CALLS_CROSSED (sreg);
+ qty[sqty].n_refs += REG_N_REFS (sreg);
if (usize < ssize)
{
register int i;
- for (i = qty_first_reg[sqty]; i >= 0; i = reg_next_in_qty[i])
+ for (i = qty[sqty].first_reg; i >= 0; i = reg_next_in_qty[i])
reg_offset[i] -= offset;
- qty_size[sqty] = ssize;
- qty_mode[sqty] = GET_MODE (setreg);
+ qty[sqty].size = ssize;
+ qty[sqty].mode = GET_MODE (setreg);
}
}
else
|| reg_class_subset_p (class, rclass));
}
-/* Update the class of QTY assuming that REG is being tied to it. */
+/* Update the class of QTYNO assuming that REG is being tied to it. */
static void
-update_qty_class (qty, reg)
- int qty;
+update_qty_class (qtyno, reg)
+ int qtyno;
int reg;
{
enum reg_class rclass = reg_preferred_class (reg);
- if (reg_class_subset_p (rclass, qty_min_class[qty]))
- qty_min_class[qty] = rclass;
+ if (reg_class_subset_p (rclass, qty[qtyno].min_class))
+ qty[qtyno].min_class = rclass;
rclass = reg_alternate_class (reg);
- if (reg_class_subset_p (rclass, qty_alternate_class[qty]))
- qty_alternate_class[qty] = rclass;
+ if (reg_class_subset_p (rclass, qty[qtyno].alternate_class))
+ qty[qtyno].alternate_class = rclass;
- if (REG_CHANGES_SIZE (reg))
- qty_changes_size[qty] = 1;
+ if (REG_CHANGES_MODE (reg))
+ qty[qtyno].changes_mode = 1;
}
\f
/* Handle something which alters the value of an rtx REG.
carry info from `block_alloc'. */
static void
-reg_is_set (reg, setter)
+reg_is_set (reg, setter, data)
rtx reg;
rtx setter;
+ void *data ATTRIBUTE_UNUSED;
{
/* Note that note_stores will only pass us a SUBREG if it is a SUBREG of
a hard register. These may actually not exist any more. */
int birth;
{
register int regno;
-
+
if (GET_CODE (reg) == SUBREG)
regno = REGNO (SUBREG_REG (reg)) + SUBREG_WORD (reg);
else
/* If this register has a quantity number, show that it isn't dead. */
if (reg_qty[regno] >= 0)
- qty_death[reg_qty[regno]] = -1;
+ qty[reg_qty[regno]].death = -1;
}
}
/* If this insn has multiple results,
and the dead reg is used in one of the results,
extend its life to after this insn,
- so it won't get allocated together with any other result of this insn.
+ so it won't get allocated together with any other result of this insn.
It is unsafe to use !single_set here since it will ignore an unused
output. Just because an output is unused does not mean the compiler
not to happen). */
if (output_p)
post_mark_life (regno, GET_MODE (reg), 1,
- 2 * this_insn_number, 2 * this_insn_number+ 1);
+ 2 * this_insn_number, 2 * this_insn_number + 1);
}
else if (reg_qty[regno] >= 0)
- qty_death[reg_qty[regno]] = 2 * this_insn_number + output_p;
+ qty[reg_qty[regno]].death = 2 * this_insn_number + output_p;
}
\f
/* Find a block of SIZE words of hard regs in reg_class CLASS
(but actually we test only the first of the block for holding MODE)
and still free between insn BORN_INDEX and insn DEAD_INDEX,
and return the number of the first of them.
- Return -1 if such a block cannot be found.
- If QTY crosses calls, insist on a register preserved by calls,
+ Return -1 if such a block cannot be found.
+ If QTYNO crosses calls, insist on a register preserved by calls,
unless ACCEPT_CALL_CLOBBERED is nonzero.
If JUST_TRY_SUGGESTED is non-zero, only try to see if the suggested
register is available. If not, return -1. */
static int
-find_free_reg (class, mode, qty, accept_call_clobbered, just_try_suggested,
+find_free_reg (class, mode, qtyno, accept_call_clobbered, just_try_suggested,
born_index, dead_index)
enum reg_class class;
enum machine_mode mode;
- int qty;
+ int qtyno;
int accept_call_clobbered;
int just_try_suggested;
int born_index, dead_index;
{
register int i, ins;
#ifdef HARD_REG_SET
- register /* Declare it register if it's a scalar. */
+ /* Declare it register if it's a scalar. */
+ register
#endif
HARD_REG_SET used, first_used;
#ifdef ELIMINABLE_REGS
/* Don't let a pseudo live in a reg across a function call
if we might get a nonlocal goto. */
if (current_function_has_nonlocal_label
- && qty_n_calls_crossed[qty] > 0)
+ && qty[qtyno].n_calls_crossed > 0)
return -1;
if (accept_call_clobbered)
COPY_HARD_REG_SET (used, call_fixed_reg_set);
- else if (qty_n_calls_crossed[qty] == 0)
+ else if (qty[qtyno].n_calls_crossed == 0)
COPY_HARD_REG_SET (used, fixed_reg_set);
else
COPY_HARD_REG_SET (used, call_used_reg_set);
This is true of any register that can be eliminated. */
#ifdef ELIMINABLE_REGS
- for (i = 0; i < (int)(sizeof eliminables / sizeof eliminables[0]); i++)
+ for (i = 0; i < (int) ARRAY_SIZE (eliminables); i++)
SET_HARD_REG_BIT (used, eliminables[i].from);
#if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
/* If FRAME_POINTER_REGNUM is not a real register, then protect the one
SET_HARD_REG_BIT (used, FRAME_POINTER_REGNUM);
#endif
-#ifdef CLASS_CANNOT_CHANGE_SIZE
- if (qty_changes_size[qty])
+#ifdef CLASS_CANNOT_CHANGE_MODE
+ if (qty[qtyno].changes_mode)
IOR_HARD_REG_SET (used,
- reg_class_contents[(int) CLASS_CANNOT_CHANGE_SIZE]);
+ reg_class_contents[(int) CLASS_CANNOT_CHANGE_MODE]);
#endif
/* Normally, the registers that can be used for the first register in
if (just_try_suggested)
{
- if (qty_phys_num_copy_sugg[qty] != 0)
- IOR_COMPL_HARD_REG_SET (first_used, qty_phys_copy_sugg[qty]);
+ if (qty_phys_num_copy_sugg[qtyno] != 0)
+ IOR_COMPL_HARD_REG_SET (first_used, qty_phys_copy_sugg[qtyno]);
else
- IOR_COMPL_HARD_REG_SET (first_used, qty_phys_sugg[qty]);
+ IOR_COMPL_HARD_REG_SET (first_used, qty_phys_sugg[qtyno]);
}
/* If all registers are excluded, we can't do anything. */
#endif
if (! TEST_HARD_REG_BIT (first_used, regno)
&& HARD_REGNO_MODE_OK (regno, mode)
- && (qty_n_calls_crossed[qty] == 0
+ && (qty[qtyno].n_calls_crossed == 0
|| accept_call_clobbered
|| ! HARD_REGNO_CALL_PART_CLOBBERED (regno, mode)))
{
return regno;
}
#ifndef REG_ALLOC_ORDER
- i += j; /* Skip starting points we know will lose */
+ /* Skip starting points we know will lose. */
+ i += j;
#endif
}
}
fail:
-
/* If we are just trying suggested register, we have just tried copy-
suggested registers, and there are arithmetic-suggested registers,
try them. */
-
+
/* If it would be profitable to allocate a call-clobbered register
and save and restore it around calls, do that. */
- if (just_try_suggested && qty_phys_num_copy_sugg[qty] != 0
- && qty_phys_num_sugg[qty] != 0)
+ if (just_try_suggested && qty_phys_num_copy_sugg[qtyno] != 0
+ && qty_phys_num_sugg[qtyno] != 0)
{
/* Don't try the copy-suggested regs again. */
- qty_phys_num_copy_sugg[qty] = 0;
- return find_free_reg (class, mode, qty, accept_call_clobbered, 1,
+ qty_phys_num_copy_sugg[qtyno] = 0;
+ return find_free_reg (class, mode, qtyno, accept_call_clobbered, 1,
born_index, dead_index);
}
if (! accept_call_clobbered
&& flag_caller_saves
&& ! just_try_suggested
- && qty_n_calls_crossed[qty] != 0
- && CALLER_SAVE_PROFITABLE (qty_n_refs[qty], qty_n_calls_crossed[qty]))
+ && qty[qtyno].n_calls_crossed != 0
+ && CALLER_SAVE_PROFITABLE (qty[qtyno].n_refs,
+ qty[qtyno].n_calls_crossed))
{
- i = find_free_reg (class, mode, qty, 1, 0, born_index, dead_index);
+ i = find_free_reg (class, mode, qtyno, 1, 0, born_index, dead_index);
if (i >= 0)
caller_save_needed = 1;
return i;
{
register int j = HARD_REGNO_NREGS (regno, mode);
#ifdef HARD_REG_SET
- register /* Declare it register if it's a scalar. */
+ /* Declare it register if it's a scalar. */
+ register
#endif
HARD_REG_SET this_reg;
static int
no_conflict_p (insn, r0, r1)
- rtx insn, r0, r1;
+ rtx insn, r0 ATTRIBUTE_UNUSED, r1;
{
int ok = 0;
rtx note = find_reg_note (insn, REG_LIBCALL, NULL_RTX);
last = XEXP (note, 0);
for (p = NEXT_INSN (insn); p && p != last; p = NEXT_INSN (p))
- if (GET_RTX_CLASS (GET_CODE (p)) == 'i')
+ if (INSN_P (p))
{
if (find_reg_note (p, REG_DEAD, r1))
ok = 1;
if (! find_reg_note (p, REG_NO_CONFLICT, r1))
return 0;
}
-
+
return ok;
}
\f
-#ifdef REGISTER_CONSTRAINTS
-
/* Return the number of alternatives for which the constraint string P
indicates that the operand must be equal to operand 0 and that no register
is acceptable. */
static int
requires_inout (p)
- const char *p;
+ const char *p;
{
char c;
int found_zero = 0;
case '=': case '+': case '?':
case '#': case '&': case '!':
case '*': case '%':
- case '1': case '2': case '3': case '4':
+ case '1': case '2': case '3': case '4': case '5':
+ case '6': case '7': case '8': case '9':
case 'm': case '<': case '>': case 'V': case 'o':
case 'E': case 'F': case 'G': case 'H':
case 's': case 'i': case 'n':
case 'I': case 'J': case 'K': case 'L':
case 'M': case 'N': case 'O': case 'P':
-#ifdef EXTRA_CONSTRAINT
- case 'Q': case 'R': case 'S': case 'T': case 'U':
-#endif
case 'X':
/* These don't say anything we care about. */
break;
found_zero = 1;
break;
+ default:
+ if (REG_CLASS_FROM_LETTER (c) == NO_REGS)
+ break;
+ /* FALLTHRU */
case 'p':
case 'g': case 'r':
- default:
reg_allowed = 1;
break;
}
return num_matching_alts;
}
-#endif /* REGISTER_CONSTRAINTS */
\f
void
dump_local_alloc (file)
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