/* Allocate registers within a basic block, for GNU compiler.
Copyright (C) 1987, 1988, 1991, 1993, 1994, 1995, 1996, 1997, 1998,
- 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
+ 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
+ Free Software Foundation, Inc.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License as published by the Free
-Software Foundation; either version 2, or (at your option) any later
+Software Foundation; either version 3, or (at your option) any later
version.
GCC is distributed in the hope that it will be useful, but WITHOUT ANY
for more details.
You should have received a copy of the GNU General Public License
-along with GCC; see the file COPYING. If not, write to the Free
-Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-02111-1307, USA. */
+along with GCC; see the file COPYING3. If not see
+<http://www.gnu.org/licenses/>. */
/* Allocation of hard register numbers to pseudo registers is done in
two passes. In this pass we consider only regs that are born and
#include "config.h"
#include "system.h"
+#include "coretypes.h"
+#include "tm.h"
+#include "hard-reg-set.h"
#include "rtl.h"
#include "tm_p.h"
#include "flags.h"
-#include "hard-reg-set.h"
-#include "basic-block.h"
#include "regs.h"
#include "function.h"
#include "insn-config.h"
#include "toplev.h"
#include "except.h"
#include "integrate.h"
+#include "reload.h"
+#include "ggc.h"
+#include "timevar.h"
+#include "tree-pass.h"
+#include "df.h"
+#include "dbgcnt.h"
+
\f
/* Next quantity number available for allocation. */
/* Number of words needed to hold the data in given quantity.
This depends on its machine mode. It is used for these purposes:
- 1. It is used in computing the relative importances of qtys,
+ 1. It is used in computing the relative importance of qtys,
which determines the order in which we look for regs for them.
2. It is used in rules that prevent tying several registers of
different sizes in a way that is geometrically impossible
int n_calls_crossed;
+ /* Number of times a reg tied to given qty lives across a CALL_INSN. */
+
+ int freq_calls_crossed;
+
+ /* Number of times a reg tied to given qty lives across a CALL_INSN
+ that might throw. */
+
+ int n_throwing_calls_crossed;
+
/* The register number of one pseudo register whose reg_qty value is Q.
This register should be the head of the chain
maintained in reg_next_in_qty. */
or -1 if none was found. */
short phys_reg;
-
- /* Nonzero if this quantity has been used in a SUBREG in some
- way that is illegal. */
-
- char changes_mode;
-
};
static struct qty *qty;
/* The list of each instruction which initializes this register. */
rtx init_insns;
+
+ /* Nonzero if this had a preexisting REG_EQUIV note. */
+
+ int is_arg_equivalence;
};
/* reg_equiv[N] (where N is a pseudo reg number) is the equivalence
/* Nonzero if we recorded an equivalence for a LABEL_REF. */
static int recorded_label_ref;
-static void alloc_qty PARAMS ((int, enum machine_mode, int, int));
-static void validate_equiv_mem_from_store PARAMS ((rtx, rtx, void *));
-static int validate_equiv_mem PARAMS ((rtx, rtx, rtx));
-static int equiv_init_varies_p PARAMS ((rtx));
-static int equiv_init_movable_p PARAMS ((rtx, int));
-static int contains_replace_regs PARAMS ((rtx));
-static int memref_referenced_p PARAMS ((rtx, rtx));
-static int memref_used_between_p PARAMS ((rtx, rtx, rtx));
-static void update_equiv_regs PARAMS ((void));
-static void no_equiv PARAMS ((rtx, rtx, void *));
-static void block_alloc PARAMS ((int));
-static int qty_sugg_compare PARAMS ((int, int));
-static int qty_sugg_compare_1 PARAMS ((const PTR, const PTR));
-static int qty_compare PARAMS ((int, int));
-static int qty_compare_1 PARAMS ((const PTR, const PTR));
-static int combine_regs PARAMS ((rtx, rtx, int, int, rtx, int));
-static int reg_meets_class_p PARAMS ((int, enum reg_class));
-static void update_qty_class PARAMS ((int, int));
-static void reg_is_set PARAMS ((rtx, rtx, void *));
-static void reg_is_born PARAMS ((rtx, int));
-static void wipe_dead_reg PARAMS ((rtx, int));
-static int find_free_reg PARAMS ((enum reg_class, enum machine_mode,
- int, int, int, int, int));
-static void mark_life PARAMS ((int, enum machine_mode, int));
-static void post_mark_life PARAMS ((int, enum machine_mode, int, int, int));
-static int no_conflict_p PARAMS ((rtx, rtx, rtx));
-static int requires_inout PARAMS ((const char *));
+static void alloc_qty (int, enum machine_mode, int, int);
+static void validate_equiv_mem_from_store (rtx, const_rtx, void *);
+static int validate_equiv_mem (rtx, rtx, rtx);
+static int equiv_init_varies_p (rtx);
+static int equiv_init_movable_p (rtx, int);
+static int contains_replace_regs (rtx);
+static int memref_referenced_p (rtx, rtx);
+static int memref_used_between_p (rtx, rtx, rtx);
+static void update_equiv_regs (void);
+static void no_equiv (rtx, const_rtx, void *);
+static void block_alloc (int);
+static int qty_sugg_compare (int, int);
+static int qty_sugg_compare_1 (const void *, const void *);
+static int qty_compare (int, int);
+static int qty_compare_1 (const void *, const void *);
+static int combine_regs (rtx, rtx, int, int, rtx);
+static int reg_meets_class_p (int, enum reg_class);
+static void update_qty_class (int, int);
+static void reg_is_set (rtx, const_rtx, void *);
+static void reg_is_born (rtx, int);
+static void wipe_dead_reg (rtx, int);
+static int find_free_reg (enum reg_class, enum machine_mode, int, int, int,
+ int, int);
+static void mark_life (int, enum machine_mode, int);
+static void post_mark_life (int, enum machine_mode, int, int, int);
+static int requires_inout (const char *);
\f
/* Allocate a new quantity (new within current basic block)
for register number REGNO which is born at index BIRTH
within the block. MODE and SIZE are info on reg REGNO. */
static void
-alloc_qty (regno, mode, size, birth)
- int regno;
- enum machine_mode mode;
- int size, birth;
+alloc_qty (int regno, enum machine_mode mode, int size, int birth)
{
int qtyno = next_qty++;
qty[qtyno].mode = mode;
qty[qtyno].birth = birth;
qty[qtyno].n_calls_crossed = REG_N_CALLS_CROSSED (regno);
+ qty[qtyno].freq_calls_crossed = REG_FREQ_CALLS_CROSSED (regno);
+ qty[qtyno].n_throwing_calls_crossed = REG_N_THROWING_CALLS_CROSSED (regno);
qty[qtyno].min_class = reg_preferred_class (regno);
qty[qtyno].alternate_class = reg_alternate_class (regno);
qty[qtyno].n_refs = REG_N_REFS (regno);
qty[qtyno].freq = REG_FREQ (regno);
- qty[qtyno].changes_mode = REG_CHANGES_MODE (regno);
}
\f
/* Main entry point of this file. */
-int
-local_alloc ()
+static int
+local_alloc (void)
{
int i;
int max_qty;
/* Promote REG_EQUAL notes to REG_EQUIV notes and adjust status of affected
registers. */
- if (optimize)
- update_equiv_regs ();
+ update_equiv_regs ();
/* This sets the maximum number of quantities we can have. Quantity
numbers start at zero and we can have one for each pseudo. */
See the declarations of these variables, above,
for what they mean. */
- qty = (struct qty *) xmalloc (max_qty * sizeof (struct qty));
- qty_phys_copy_sugg
- = (HARD_REG_SET *) xmalloc (max_qty * sizeof (HARD_REG_SET));
- qty_phys_num_copy_sugg = (short *) xmalloc (max_qty * sizeof (short));
- qty_phys_sugg = (HARD_REG_SET *) xmalloc (max_qty * sizeof (HARD_REG_SET));
- qty_phys_num_sugg = (short *) xmalloc (max_qty * sizeof (short));
+ qty = XNEWVEC (struct qty, max_qty);
+ qty_phys_copy_sugg = XNEWVEC (HARD_REG_SET, max_qty);
+ qty_phys_num_copy_sugg = XNEWVEC (short, max_qty);
+ qty_phys_sugg = XNEWVEC (HARD_REG_SET, max_qty);
+ qty_phys_num_sugg = XNEWVEC (short, max_qty);
- reg_qty = (int *) xmalloc (max_regno * sizeof (int));
- reg_offset = (char *) xmalloc (max_regno * sizeof (char));
- reg_next_in_qty = (int *) xmalloc (max_regno * sizeof (int));
+ reg_qty = XNEWVEC (int, max_regno);
+ reg_offset = XNEWVEC (char, max_regno);
+ reg_next_in_qty = XNEWVEC (int, max_regno);
/* Determine which pseudo-registers can be allocated by local-alloc.
In general, these are the registers used only in a single block and
for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
{
- if (REG_BASIC_BLOCK (i) >= 0 && REG_N_DEATHS (i) == 1)
+ if (REG_BASIC_BLOCK (i) >= NUM_FIXED_BLOCKS && REG_N_DEATHS (i) == 1)
reg_qty[i] = -2;
else
reg_qty[i] = -1;
else
{
#define CLEAR(vector) \
- memset ((char *) (vector), 0, (sizeof (*(vector))) * next_qty);
+ memset ((vector), 0, (sizeof (*(vector))) * next_qty);
CLEAR (qty_phys_copy_sugg);
CLEAR (qty_phys_num_copy_sugg);
Called via note_stores. */
static void
-validate_equiv_mem_from_store (dest, set, data)
- rtx dest;
- rtx set ATTRIBUTE_UNUSED;
- void *data ATTRIBUTE_UNUSED;
+validate_equiv_mem_from_store (rtx dest, const_rtx set ATTRIBUTE_UNUSED,
+ void *data ATTRIBUTE_UNUSED)
{
- if ((GET_CODE (dest) == REG
+ if ((REG_P (dest)
&& reg_overlap_mentioned_p (dest, equiv_mem))
- || (GET_CODE (dest) == MEM
+ || (MEM_P (dest)
&& true_dependence (dest, VOIDmode, equiv_mem, rtx_varies_p)))
equiv_mem_modified = 1;
}
Return 1 if MEMREF remains valid. */
static int
-validate_equiv_mem (start, reg, memref)
- rtx start;
- rtx reg;
- rtx memref;
+validate_equiv_mem (rtx start, rtx reg, rtx memref)
{
rtx insn;
rtx note;
if (find_reg_note (insn, REG_DEAD, reg))
return 1;
- if (GET_CODE (insn) == CALL_INSN && ! RTX_UNCHANGING_P (memref)
- && ! CONST_OR_PURE_CALL_P (insn))
+ if (CALL_P (insn) && ! MEM_READONLY_P (memref)
+ && ! RTL_CONST_OR_PURE_CALL_P (insn))
return 0;
note_stores (PATTERN (insn), validate_equiv_mem_from_store, NULL);
for (note = REG_NOTES (insn); note; note = XEXP (note, 1))
if ((REG_NOTE_KIND (note) == REG_INC
|| REG_NOTE_KIND (note) == REG_DEAD)
- && GET_CODE (XEXP (note, 0)) == REG
+ && REG_P (XEXP (note, 0))
&& reg_overlap_mentioned_p (XEXP (note, 0), memref))
return 0;
}
/* Returns zero if X is known to be invariant. */
static int
-equiv_init_varies_p (x)
- rtx x;
+equiv_init_varies_p (rtx x)
{
RTX_CODE code = GET_CODE (x);
int i;
switch (code)
{
case MEM:
- return ! RTX_UNCHANGING_P (x) || equiv_init_varies_p (XEXP (x, 0));
-
- case QUEUED:
- return 1;
+ return !MEM_READONLY_P (x) || equiv_init_varies_p (XEXP (x, 0));
case CONST:
case CONST_INT:
case CONST_DOUBLE:
+ case CONST_FIXED:
case CONST_VECTOR:
case SYMBOL_REF:
case LABEL_REF:
if (MEM_VOLATILE_P (x))
return 1;
- /* FALLTHROUGH */
+ /* Fall through. */
default:
break;
return 0;
}
-/* Returns non-zero if X (used to initialize register REGNO) is movable.
+/* Returns nonzero if X (used to initialize register REGNO) is movable.
X is only movable if the registers it uses have equivalent initializations
which appear to be within the same loop (or in an inner loop) and movable
or if they are not candidates for local_alloc and don't vary. */
static int
-equiv_init_movable_p (x, regno)
- rtx x;
- int regno;
+equiv_init_movable_p (rtx x, int regno)
{
int i, j;
const char *fmt;
case REG:
return (reg_equiv[REGNO (x)].loop_depth >= reg_equiv[regno].loop_depth
&& reg_equiv[REGNO (x)].replace)
- || (REG_BASIC_BLOCK (REGNO (x)) < 0 && ! rtx_varies_p (x, 0));
+ || (REG_BASIC_BLOCK (REGNO (x)) < NUM_FIXED_BLOCKS && ! rtx_varies_p (x, 0));
case UNSPEC_VOLATILE:
return 0;
if (MEM_VOLATILE_P (x))
return 0;
- /* FALLTHROUGH */
+ /* Fall through. */
default:
break;
/* TRUE if X uses any registers for which reg_equiv[REGNO].replace is true. */
static int
-contains_replace_regs (x)
- rtx x;
+contains_replace_regs (rtx x)
{
int i, j;
const char *fmt;
case LABEL_REF:
case SYMBOL_REF:
case CONST_DOUBLE:
+ case CONST_FIXED:
case CONST_VECTOR:
case PC:
case CC0:
to MEMREF. */
static int
-memref_referenced_p (memref, x)
- rtx x;
- rtx memref;
+memref_referenced_p (rtx memref, rtx x)
{
int i, j;
const char *fmt;
case LABEL_REF:
case SYMBOL_REF:
case CONST_DOUBLE:
+ case CONST_FIXED:
case CONST_VECTOR:
case PC:
case CC0:
case SET:
/* If we are setting a MEM, it doesn't count (its address does), but any
other SET_DEST that has a MEM in it is referencing the MEM. */
- if (GET_CODE (SET_DEST (x)) == MEM)
+ if (MEM_P (SET_DEST (x)))
{
if (memref_referenced_p (memref, XEXP (SET_DEST (x), 0)))
return 1;
that would be affected by a store to MEMREF. */
static int
-memref_used_between_p (memref, start, end)
- rtx memref;
- rtx start;
- rtx end;
+memref_used_between_p (rtx memref, rtx start, rtx end)
{
rtx insn;
for (insn = NEXT_INSN (start); insn != NEXT_INSN (end);
insn = NEXT_INSN (insn))
- if (INSN_P (insn) && memref_referenced_p (memref, PATTERN (insn)))
- return 1;
+ {
+ if (!INSN_P (insn))
+ continue;
+
+ if (memref_referenced_p (memref, PATTERN (insn)))
+ return 1;
+
+ /* Nonconst functions may access memory. */
+ if (CALL_P (insn) && (! RTL_CONST_CALL_P (insn)))
+ return 1;
+ }
return 0;
}
\f
-/* Return nonzero if the rtx X is invariant over the current function. */
-/* ??? Actually, the places this is used in reload expect exactly what
- is tested here, and not everything that is function invariant. In
- particular, the frame pointer and arg pointer are special cased;
- pic_offset_table_rtx is not, and this will cause aborts when we
- go to spill these things to memory. */
-
-int
-function_invariant_p (x)
- rtx x;
-{
- if (CONSTANT_P (x))
- return 1;
- if (x == frame_pointer_rtx || x == arg_pointer_rtx)
- return 1;
- if (GET_CODE (x) == PLUS
- && (XEXP (x, 0) == frame_pointer_rtx || XEXP (x, 0) == arg_pointer_rtx)
- && CONSTANT_P (XEXP (x, 1)))
- return 1;
- return 0;
-}
-
/* Find registers that are equivalent to a single value throughout the
compilation (either because they can be referenced in memory or are set once
from a single constant). Lower their priority for a register.
If such a register is only referenced once, try substituting its value
into the using insn. If it succeeds, we can eliminate the register
- completely. */
+ completely.
+
+ Initialize the REG_EQUIV_INIT array of initializing insns. */
static void
-update_equiv_regs ()
+update_equiv_regs (void)
{
rtx insn;
basic_block bb;
int loop_depth;
- regset_head cleared_regs;
- int clear_regnos = 0;
-
- reg_equiv = (struct equivalence *) xcalloc (max_regno, sizeof *reg_equiv);
- INIT_REG_SET (&cleared_regs);
+ bitmap cleared_regs;
+
+ reg_equiv = XCNEWVEC (struct equivalence, max_regno);
+ reg_equiv_init = ggc_alloc_cleared (max_regno * sizeof (rtx));
+ reg_equiv_init_size = max_regno;
init_alias_analysis ();
{
loop_depth = bb->loop_depth;
- for (insn = bb->head; insn != NEXT_INSN (bb->end); insn = NEXT_INSN (insn))
+ for (insn = BB_HEAD (bb);
+ insn != NEXT_INSN (BB_END (bb));
+ insn = NEXT_INSN (insn))
{
rtx note;
rtx set;
dest = SET_DEST (set);
src = SET_SRC (set);
- /* If this sets a MEM to the contents of a REG that is only used
- in a single basic block, see if the register is always equivalent
- to that memory location and if moving the store from INSN to the
- insn that set REG is safe. If so, put a REG_EQUIV note on the
- initializing insn.
-
- Don't add a REG_EQUIV note if the insn already has one. The existing
- REG_EQUIV is likely more useful than the one we are adding.
-
- If one of the regs in the address has reg_equiv[REGNO].replace set,
- then we can't add this REG_EQUIV note. The reg_equiv[REGNO].replace
- optimization may move the set of this register immediately before
- insn, which puts it after reg_equiv[REGNO].init_insns, and hence
- the mention in the REG_EQUIV note would be to an uninitialized
- pseudo. */
- /* ????? This test isn't good enough; we might see a MEM with a use of
- a pseudo register before we see its setting insn that will cause
- reg_equiv[].replace for that pseudo to be set.
- Equivalences to MEMs should be made in another pass, after the
- reg_equiv[].replace information has been gathered. */
-
- if (GET_CODE (dest) == MEM && GET_CODE (src) == REG
- && (regno = REGNO (src)) >= FIRST_PSEUDO_REGISTER
- && REG_BASIC_BLOCK (regno) >= 0
- && REG_N_SETS (regno) == 1
- && reg_equiv[regno].init_insns != 0
- && reg_equiv[regno].init_insns != const0_rtx
- && ! find_reg_note (XEXP (reg_equiv[regno].init_insns, 0),
- REG_EQUIV, NULL_RTX)
- && ! contains_replace_regs (XEXP (dest, 0)))
+ /* See if this is setting up the equivalence between an argument
+ register and its stack slot. */
+ note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
+ if (note)
{
- rtx init_insn = XEXP (reg_equiv[regno].init_insns, 0);
- if (validate_equiv_mem (init_insn, src, dest)
- && ! memref_used_between_p (dest, init_insn, insn))
- REG_NOTES (init_insn)
- = gen_rtx_EXPR_LIST (REG_EQUIV, dest, REG_NOTES (init_insn));
+ gcc_assert (REG_P (dest));
+ regno = REGNO (dest);
+
+ /* Note that we don't want to clear reg_equiv_init even if there
+ are multiple sets of this register. */
+ reg_equiv[regno].is_arg_equivalence = 1;
+
+ /* Record for reload that this is an equivalencing insn. */
+ if (rtx_equal_p (src, XEXP (note, 0)))
+ reg_equiv_init[regno]
+ = gen_rtx_INSN_LIST (VOIDmode, insn, reg_equiv_init[regno]);
+
+ /* Continue normally in case this is a candidate for
+ replacements. */
}
+ if (!optimize)
+ continue;
+
/* We only handle the case of a pseudo register being set
once, or always to the same value. */
/* ??? The mn10200 port breaks if we add equivalences for
preferred class of a pseudo depends on all instructions that set
or use it. */
- if (GET_CODE (dest) != REG
+ if (!REG_P (dest)
|| (regno = REGNO (dest)) < FIRST_PSEUDO_REGISTER
|| reg_equiv[regno].init_insns == const0_rtx
|| (CLASS_LIKELY_SPILLED_P (reg_preferred_class (regno))
- && GET_CODE (src) == MEM))
+ && MEM_P (src) && ! reg_equiv[regno].is_arg_equivalence))
{
- /* This might be seting a SUBREG of a pseudo, a pseudo that is
+ /* This might be setting a SUBREG of a pseudo, a pseudo that is
also set somewhere else to a constant. */
note_stores (set, no_equiv, NULL);
continue;
REG_EQUAL note on the insn. Since this note would be redundant,
there's no point creating it earlier than here. */
if (! note && ! rtx_varies_p (src, 0))
- note = set_unique_reg_note (insn, REG_EQUAL, src);
+ note = set_unique_reg_note (insn, REG_EQUAL, copy_rtx (src));
/* Don't bother considering a REG_EQUAL note containing an EXPR_LIST
since it represents a function call */
if (note && GET_CODE (XEXP (note, 0)) == EXPR_LIST)
note = NULL_RTX;
- if (REG_N_SETS (regno) != 1
+ if (DF_REG_DEF_COUNT (regno) != 1
&& (! note
|| rtx_varies_p (XEXP (note, 0), 0)
|| (reg_equiv[regno].replacement
/* If this register is known to be equal to a constant, record that
it is always equivalent to the constant. */
- if (note && ! rtx_varies_p (XEXP (note, 0), 0))
- PUT_MODE (note, (enum machine_mode) REG_EQUIV);
+ if (DF_REG_DEF_COUNT (regno) == 1
+ && note && ! rtx_varies_p (XEXP (note, 0), 0))
+ {
+ rtx note_value = XEXP (note, 0);
+ remove_note (insn, note);
+ set_unique_reg_note (insn, REG_EQUIV, note_value);
+ }
/* If this insn introduces a "constant" register, decrease the priority
of that register. Record this insn if the register is only used once
note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
- if (note == 0 && REG_BASIC_BLOCK (regno) >= 0
- && GET_CODE (SET_SRC (set)) == MEM
+ if (note == 0 && REG_BASIC_BLOCK (regno) >= NUM_FIXED_BLOCKS
+ && MEM_P (SET_SRC (set))
&& validate_equiv_mem (insn, dest, SET_SRC (set)))
- REG_NOTES (insn) = note = gen_rtx_EXPR_LIST (REG_EQUIV, SET_SRC (set),
- REG_NOTES (insn));
+ note = set_unique_reg_note (insn, REG_EQUIV, copy_rtx (SET_SRC (set)));
if (note)
{
int regno = REGNO (dest);
+ rtx x = XEXP (note, 0);
+
+ /* If we haven't done so, record for reload that this is an
+ equivalencing insn. */
+ if (!reg_equiv[regno].is_arg_equivalence)
+ reg_equiv_init[regno]
+ = gen_rtx_INSN_LIST (VOIDmode, insn, reg_equiv_init[regno]);
/* Record whether or not we created a REG_EQUIV note for a LABEL_REF.
We might end up substituting the LABEL_REF for uses of the
pseudo here or later. That kind of transformation may turn an
indirect jump into a direct jump, in which case we must rerun the
jump optimizer to ensure that the JUMP_LABEL fields are valid. */
- if (GET_CODE (XEXP (note, 0)) == LABEL_REF
- || (GET_CODE (XEXP (note, 0)) == CONST
- && GET_CODE (XEXP (XEXP (note, 0), 0)) == PLUS
- && (GET_CODE (XEXP (XEXP (XEXP (note, 0), 0), 0))
- == LABEL_REF)))
+ if (GET_CODE (x) == LABEL_REF
+ || (GET_CODE (x) == CONST
+ && GET_CODE (XEXP (x, 0)) == PLUS
+ && (GET_CODE (XEXP (XEXP (x, 0), 0)) == LABEL_REF)))
recorded_label_ref = 1;
- reg_equiv[regno].replacement = XEXP (note, 0);
+ reg_equiv[regno].replacement = x;
reg_equiv[regno].src_p = &SET_SRC (set);
reg_equiv[regno].loop_depth = loop_depth;
in local-alloc! */
REG_LIVE_LENGTH (regno) *= 2;
-
/* If the register is referenced exactly twice, meaning it is
set once and used once, indicate that the reference may be
replaced by the equivalence we computed above. Do this
and to reduce the number of registers alive across
calls. */
- if (REG_N_REFS (regno) == 2
- && (rtx_equal_p (XEXP (note, 0), src)
- || ! equiv_init_varies_p (src))
- && GET_CODE (insn) == INSN
- && equiv_init_movable_p (PATTERN (insn), regno))
- reg_equiv[regno].replace = 1;
+ if (REG_N_REFS (regno) == 2
+ && (rtx_equal_p (x, src)
+ || ! equiv_init_varies_p (src))
+ && NONJUMP_INSN_P (insn)
+ && equiv_init_movable_p (PATTERN (insn), regno))
+ reg_equiv[regno].replace = 1;
}
}
}
}
+ if (!optimize)
+ goto out;
+
+ /* A second pass, to gather additional equivalences with memory. This needs
+ to be done after we know which registers we are going to replace. */
+
+ for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
+ {
+ rtx set, src, dest;
+ unsigned regno;
+
+ if (! INSN_P (insn))
+ continue;
+
+ set = single_set (insn);
+ if (! set)
+ continue;
+
+ dest = SET_DEST (set);
+ src = SET_SRC (set);
+
+ /* If this sets a MEM to the contents of a REG that is only used
+ in a single basic block, see if the register is always equivalent
+ to that memory location and if moving the store from INSN to the
+ insn that set REG is safe. If so, put a REG_EQUIV note on the
+ initializing insn.
+
+ Don't add a REG_EQUIV note if the insn already has one. The existing
+ REG_EQUIV is likely more useful than the one we are adding.
+
+ If one of the regs in the address has reg_equiv[REGNO].replace set,
+ then we can't add this REG_EQUIV note. The reg_equiv[REGNO].replace
+ optimization may move the set of this register immediately before
+ insn, which puts it after reg_equiv[REGNO].init_insns, and hence
+ the mention in the REG_EQUIV note would be to an uninitialized
+ pseudo. */
+
+ if (MEM_P (dest) && REG_P (src)
+ && (regno = REGNO (src)) >= FIRST_PSEUDO_REGISTER
+ && REG_BASIC_BLOCK (regno) >= NUM_FIXED_BLOCKS
+ && DF_REG_DEF_COUNT (regno) == 1
+ && reg_equiv[regno].init_insns != 0
+ && reg_equiv[regno].init_insns != const0_rtx
+ && ! find_reg_note (XEXP (reg_equiv[regno].init_insns, 0),
+ REG_EQUIV, NULL_RTX)
+ && ! contains_replace_regs (XEXP (dest, 0)))
+ {
+ rtx init_insn = XEXP (reg_equiv[regno].init_insns, 0);
+ if (validate_equiv_mem (init_insn, src, dest)
+ && ! memref_used_between_p (dest, init_insn, insn)
+ /* Attaching a REG_EQUIV note will fail if INIT_INSN has
+ multiple sets. */
+ && set_unique_reg_note (init_insn, REG_EQUIV, copy_rtx (dest)))
+ {
+ /* This insn makes the equivalence, not the one initializing
+ the register. */
+ reg_equiv_init[regno]
+ = gen_rtx_INSN_LIST (VOIDmode, insn, NULL_RTX);
+ df_notes_rescan (init_insn);
+ }
+ }
+ }
+
+ cleared_regs = BITMAP_ALLOC (NULL);
/* Now scan all regs killed in an insn to see if any of them are
registers only used that once. If so, see if we can replace the
- reference with the equivalent from. If we can, delete the
+ reference with the equivalent form. If we can, delete the
initializing reference and this register will go away. If we
- can't replace the reference, and the initialzing reference is
+ can't replace the reference, and the initializing reference is
within the same loop (or in an inner loop), then move the register
initialization just before the use, so that they are in the same
basic block. */
FOR_EACH_BB_REVERSE (bb)
{
loop_depth = bb->loop_depth;
- for (insn = bb->end; insn != PREV_INSN (bb->head); insn = PREV_INSN (insn))
+ for (insn = BB_END (bb);
+ insn != PREV_INSN (BB_HEAD (bb));
+ insn = PREV_INSN (insn))
{
rtx link;
if (! INSN_P (insn))
continue;
+ /* Don't substitute into a non-local goto, this confuses CFG. */
+ if (JUMP_P (insn)
+ && find_reg_note (insn, REG_NON_LOCAL_GOTO, NULL_RTX))
+ continue;
+
for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
{
if (REG_NOTE_KIND (link) == REG_DEAD
once and used once. (If it were only set, but not used,
flow would have deleted the setting insns.) Hence
there can only be one insn in reg_equiv[REGNO].init_insns. */
- if (reg_equiv[regno].init_insns == NULL_RTX
- || XEXP (reg_equiv[regno].init_insns, 1) != NULL_RTX)
- abort ();
+ gcc_assert (reg_equiv[regno].init_insns
+ && !XEXP (reg_equiv[regno].init_insns, 1));
equiv_insn = XEXP (reg_equiv[regno].init_insns, 0);
/* We may not move instructions that can throw, since
}
remove_death (regno, insn);
- REG_N_REFS (regno) = 0;
+ SET_REG_N_REFS (regno, 0);
REG_FREQ (regno) = 0;
delete_insn (equiv_insn);
reg_equiv[regno].init_insns
= XEXP (reg_equiv[regno].init_insns, 1);
+
+ reg_equiv_init[regno] = NULL_RTX;
+ bitmap_set_bit (cleared_regs, regno);
}
/* Move the initialization of the register to just before
INSN. Update the flow information. */
REG_NOTES (new_insn) = REG_NOTES (equiv_insn);
REG_NOTES (equiv_insn) = 0;
- /* Make sure this insn is recognized before reload begins,
- otherwise eliminate_regs_in_insn will abort. */
+ /* Make sure this insn is recognized before
+ reload begins, otherwise
+ eliminate_regs_in_insn will die. */
INSN_CODE (new_insn) = INSN_CODE (equiv_insn);
delete_insn (equiv_insn);
REG_BASIC_BLOCK (regno) = bb->index;
REG_N_CALLS_CROSSED (regno) = 0;
+ REG_FREQ_CALLS_CROSSED (regno) = 0;
+ REG_N_THROWING_CALLS_CROSSED (regno) = 0;
REG_LIVE_LENGTH (regno) = 2;
- if (insn == bb->head)
- bb->head = PREV_INSN (insn);
+ if (insn == BB_HEAD (bb))
+ BB_HEAD (bb) = PREV_INSN (insn);
- /* Remember to clear REGNO from all basic block's live
- info. */
- SET_REGNO_REG_SET (&cleared_regs, regno);
- clear_regnos++;
+ reg_equiv_init[regno]
+ = gen_rtx_INSN_LIST (VOIDmode, new_insn, NULL_RTX);
+ bitmap_set_bit (cleared_regs, regno);
}
}
}
}
}
- /* Clear all dead REGNOs from all basic block's live info. */
- if (clear_regnos)
- {
- int j;
- if (clear_regnos > 8)
- {
- FOR_EACH_BB (bb)
- {
- AND_COMPL_REG_SET (bb->global_live_at_start, &cleared_regs);
- AND_COMPL_REG_SET (bb->global_live_at_end, &cleared_regs);
- }
- }
- else
- EXECUTE_IF_SET_IN_REG_SET (&cleared_regs, 0, j,
- {
- FOR_EACH_BB (bb)
- {
- CLEAR_REGNO_REG_SET (bb->global_live_at_start, j);
- CLEAR_REGNO_REG_SET (bb->global_live_at_end, j);
- }
- });
- }
+ if (!bitmap_empty_p (cleared_regs))
+ FOR_EACH_BB (bb)
+ {
+ bitmap_and_compl_into (DF_LIVE_IN (bb), cleared_regs);
+ bitmap_and_compl_into (DF_LIVE_OUT (bb), cleared_regs);
+ bitmap_and_compl_into (DF_LR_IN (bb), cleared_regs);
+ bitmap_and_compl_into (DF_LR_OUT (bb), cleared_regs);
+ }
+
+ BITMAP_FREE (cleared_regs);
+ out:
/* Clean up. */
+
end_alias_analysis ();
- CLEAR_REG_SET (&cleared_regs);
free (reg_equiv);
}
/* Mark REG as having no known equivalence.
- Some instructions might have been proceessed before and furnished
+ Some instructions might have been processed before and furnished
with REG_EQUIV notes for this register; these notes will have to be
removed.
STORE is the piece of RTL that does the non-constant / conflicting
assignment - a SET, CLOBBER or REG_INC note. It is currently not used,
but needs to be there because this function is called from note_stores. */
static void
-no_equiv (reg, store, data)
- rtx reg, store ATTRIBUTE_UNUSED;
- void *data ATTRIBUTE_UNUSED;
+no_equiv (rtx reg, const_rtx store ATTRIBUTE_UNUSED, void *data ATTRIBUTE_UNUSED)
{
int regno;
rtx list;
- if (GET_CODE (reg) != REG)
+ if (!REG_P (reg))
return;
regno = REGNO (reg);
list = reg_equiv[regno].init_insns;
if (list == const0_rtx)
return;
+ reg_equiv[regno].init_insns = const0_rtx;
+ reg_equiv[regno].replacement = NULL_RTX;
+ /* This doesn't matter for equivalences made for argument registers, we
+ should keep their initialization insns. */
+ if (reg_equiv[regno].is_arg_equivalence)
+ return;
+ reg_equiv_init[regno] = NULL_RTX;
for (; list; list = XEXP (list, 1))
{
rtx insn = XEXP (list, 0);
remove_note (insn, find_reg_note (insn, REG_EQUIV, NULL_RTX));
}
- reg_equiv[regno].init_insns = const0_rtx;
- reg_equiv[regno].replacement = NULL_RTX;
}
\f
/* Allocate hard regs to the pseudo regs used only within block number B.
Only the pseudos that die but once can be handled. */
static void
-block_alloc (b)
- int b;
+block_alloc (int b)
{
int i, q;
rtx insn;
- rtx note, hard_reg;
+ rtx hard_reg;
int insn_number = 0;
int insn_count = 0;
int max_uid = get_max_uid ();
int *qty_order;
- int no_conflict_combined_regno = -1;
+ struct df_ref ** def_rec;
/* Count the instructions in the basic block. */
- insn = BLOCK_END (b);
+ insn = BB_END (BASIC_BLOCK (b));
while (1)
{
- if (GET_CODE (insn) != NOTE)
- if (++insn_count > max_uid)
- abort ();
- if (insn == BLOCK_HEAD (b))
+ if (!NOTE_P (insn))
+ {
+ ++insn_count;
+ gcc_assert (insn_count <= max_uid);
+ }
+ if (insn == BB_HEAD (BASIC_BLOCK (b)))
break;
insn = PREV_INSN (insn);
}
/* +2 to leave room for a post_mark_life at the last insn and for
the birth of a CLOBBER in the first insn. */
- regs_live_at = (HARD_REG_SET *) xcalloc ((2 * insn_count + 2),
- sizeof (HARD_REG_SET));
+ regs_live_at = XCNEWVEC (HARD_REG_SET, 2 * insn_count + 2);
/* Initialize table of hardware registers currently live. */
- REG_SET_TO_HARD_REG_SET (regs_live, BASIC_BLOCK (b)->global_live_at_start);
+ REG_SET_TO_HARD_REG_SET (regs_live, DF_LR_IN (BASIC_BLOCK (b)));
+
+ /* This is conservative, as this would include registers that are
+ artificial-def'ed-but-not-used. However, artificial-defs are
+ rare, and such uninitialized use is rarer still, and the chance
+ of this having any performance impact is even less, while the
+ benefit is not having to compute and keep the TOP set around. */
+ for (def_rec = df_get_artificial_defs (b); *def_rec; def_rec++)
+ {
+ int regno = DF_REF_REGNO (*def_rec);
+ if (regno < FIRST_PSEUDO_REGISTER)
+ SET_HARD_REG_BIT (regs_live, regno);
+ }
/* This loop scans the instructions of the basic block
and assigns quantities to registers.
It computes which registers to tie. */
- insn = BLOCK_HEAD (b);
+ insn = BB_HEAD (BASIC_BLOCK (b));
while (1)
{
- if (GET_CODE (insn) != NOTE)
+ if (!NOTE_P (insn))
insn_number++;
if (INSN_P (insn))
{
- rtx link, set;
+ rtx link;
int win = 0;
rtx r0, r1 = NULL_RTX;
int combined_regno = -1;
must match operand zero. In that case, skip any
operand that doesn't list operand 0 since we know that
the operand always conflicts with operand 0. We
- ignore commutatity in this case to keep things simple. */
+ ignore commutativity in this case to keep things simple. */
if (n_matching_alts == recog_data.n_alternatives
&& 0 == requires_inout (recog_data.constraints[i]))
continue;
/* If the operand is an address, find a register in it.
There may be more than one register, but we only try one
of them. */
- if (recog_data.constraints[i][0] == 'p')
+ if (recog_data.constraints[i][0] == 'p'
+ || EXTRA_ADDRESS_CONSTRAINT (recog_data.constraints[i][0],
+ recog_data.constraints[i]))
while (GET_CODE (r1) == PLUS || GET_CODE (r1) == MULT)
r1 = XEXP (r1, 0);
/* Avoid making a call-saved register unnecessarily
clobbered. */
- hard_reg = get_hard_reg_initial_reg (cfun, r1);
+ hard_reg = get_hard_reg_initial_reg (r1);
if (hard_reg != NULL_RTX)
{
- if (GET_CODE (hard_reg) == REG
- && IN_RANGE (REGNO (hard_reg),
- 0, FIRST_PSEUDO_REGISTER - 1)
- && ! call_used_regs[REGNO (hard_reg)])
+ if (REG_P (hard_reg)
+ && REGNO (hard_reg) < FIRST_PSEUDO_REGISTER
+ && !call_used_regs[REGNO (hard_reg)])
continue;
}
- if (GET_CODE (r0) == REG || GET_CODE (r0) == SUBREG)
+ if (REG_P (r0) || GET_CODE (r0) == SUBREG)
{
/* We have two priorities for hard register preferences.
If we have a move insn or an insn whose first input
int may_save_copy
= (r1 == recog_data.operand[i] && must_match_0 >= 0);
- if (GET_CODE (r1) == REG || GET_CODE (r1) == SUBREG)
+ if (REG_P (r1) || GET_CODE (r1) == SUBREG)
win = combine_regs (r1, r0, may_save_copy,
- insn_number, insn, 0);
+ insn_number, insn);
}
if (win)
break;
}
}
- /* Recognize an insn sequence with an ultimate result
- which can safely overlap one of the inputs.
- The sequence begins with a CLOBBER of its result,
- and ends with an insn that copies the result to itself
- and has a REG_EQUAL note for an equivalent formula.
- That note indicates what the inputs are.
- The result and the input can overlap if each insn in
- the sequence either doesn't mention the input
- or has a REG_NO_CONFLICT note to inhibit the conflict.
-
- We do the combining test at the CLOBBER so that the
- destination register won't have had a quantity number
- assigned, since that would prevent combining. */
-
- if (optimize
- && GET_CODE (PATTERN (insn)) == CLOBBER
- && (r0 = XEXP (PATTERN (insn), 0),
- GET_CODE (r0) == REG)
- && (link = find_reg_note (insn, REG_LIBCALL, NULL_RTX)) != 0
- && XEXP (link, 0) != 0
- && GET_CODE (XEXP (link, 0)) == INSN
- && (set = single_set (XEXP (link, 0))) != 0
- && SET_DEST (set) == r0 && SET_SRC (set) == r0
- && (note = find_reg_note (XEXP (link, 0), REG_EQUAL,
- NULL_RTX)) != 0)
- {
- if (r1 = XEXP (note, 0), GET_CODE (r1) == REG
- /* Check that we have such a sequence. */
- && no_conflict_p (insn, r0, r1))
- win = combine_regs (r1, r0, 1, insn_number, insn, 1);
- else if (GET_RTX_FORMAT (GET_CODE (XEXP (note, 0)))[0] == 'e'
- && (r1 = XEXP (XEXP (note, 0), 0),
- GET_CODE (r1) == REG || GET_CODE (r1) == SUBREG)
- && no_conflict_p (insn, r0, r1))
- win = combine_regs (r1, r0, 0, insn_number, insn, 1);
-
- /* Here we care if the operation to be computed is
- commutative. */
- else if ((GET_CODE (XEXP (note, 0)) == EQ
- || GET_CODE (XEXP (note, 0)) == NE
- || GET_RTX_CLASS (GET_CODE (XEXP (note, 0))) == 'c')
- && (r1 = XEXP (XEXP (note, 0), 1),
- (GET_CODE (r1) == REG || GET_CODE (r1) == SUBREG))
- && no_conflict_p (insn, r0, r1))
- win = combine_regs (r1, r0, 0, insn_number, insn, 1);
-
- /* If we did combine something, show the register number
- in question so that we know to ignore its death. */
- if (win)
- no_conflict_combined_regno = REGNO (r1);
- }
-
/* If registers were just tied, set COMBINED_REGNO
to the number of the register used in this insn
that was tied to the register set in this insn.
combined_regno = REGNO (r1);
}
- /* Mark the death of everything that dies in this instruction,
- except for anything that was just combined. */
+ /* Mark the death of everything that dies in this instruction. */
for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
if (REG_NOTE_KIND (link) == REG_DEAD
- && GET_CODE (XEXP (link, 0)) == REG
- && combined_regno != (int) REGNO (XEXP (link, 0))
- && (no_conflict_combined_regno != (int) REGNO (XEXP (link, 0))
- || ! find_reg_note (insn, REG_NO_CONFLICT,
- XEXP (link, 0))))
+ && REG_P (XEXP (link, 0))
+ && combined_regno != (int) REGNO (XEXP (link, 0)))
wipe_dead_reg (XEXP (link, 0), 0);
/* Allocate qty numbers for all registers local to this block
for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
if (REG_NOTE_KIND (link) == REG_UNUSED
- && GET_CODE (XEXP (link, 0)) == REG)
+ && REG_P (XEXP (link, 0)))
wipe_dead_reg (XEXP (link, 0), 1);
-
- /* If this is an insn that has a REG_RETVAL note pointing at a
- CLOBBER insn, we have reached the end of a REG_NO_CONFLICT
- block, so clear any register number that combined within it. */
- if ((note = find_reg_note (insn, REG_RETVAL, NULL_RTX)) != 0
- && GET_CODE (XEXP (note, 0)) == INSN
- && GET_CODE (PATTERN (XEXP (note, 0))) == CLOBBER)
- no_conflict_combined_regno = -1;
}
/* Set the registers live after INSN_NUMBER. Note that we never
IOR_HARD_REG_SET (regs_live_at[2 * insn_number], regs_live);
IOR_HARD_REG_SET (regs_live_at[2 * insn_number + 1], regs_live);
- if (insn == BLOCK_END (b))
+ if (insn == BB_END (BASIC_BLOCK (b)))
break;
insn = NEXT_INSN (insn);
number of suggested registers they need so we allocate those with
the most restrictive needs first. */
- qty_order = (int *) xmalloc (next_qty * sizeof (int));
+ qty_order = XNEWVEC (int, next_qty);
for (i = 0; i < next_qty; i++)
qty_order[i] = i;
This optimization is only appropriate when we will run
a scheduling pass after reload and we are not optimizing
for code size. */
- if (flag_schedule_insns_after_reload
+ if (flag_schedule_insns_after_reload && dbg_cnt (local_alloc_for_sched)
&& !optimize_size
&& !SMALL_REGISTER_CLASSES)
{
#ifdef INSN_SCHEDULING
/* Similarly, avoid false dependencies. */
- if (flag_schedule_insns_after_reload
+ if (flag_schedule_insns_after_reload && dbg_cnt (local_alloc_for_sched)
&& !optimize_size
&& !SMALL_REGISTER_CLASSES
&& qty[q].alternate_class != NO_REGS)
/ (qty[q].death - qty[q].birth)) * (10000 / REG_FREQ_MAX)))
static int
-qty_compare (q1, q2)
- int q1, q2;
+qty_compare (int q1, int q2)
{
return QTY_CMP_PRI (q2) - QTY_CMP_PRI (q1);
}
static int
-qty_compare_1 (q1p, q2p)
- const PTR q1p;
- const PTR q2p;
+qty_compare_1 (const void *q1p, const void *q2p)
{
int q1 = *(const int *) q1p, q2 = *(const int *) q2p;
int tem = QTY_CMP_PRI (q2) - QTY_CMP_PRI (q1);
: qty_phys_num_sugg[q] * FIRST_PSEUDO_REGISTER)
static int
-qty_sugg_compare (q1, q2)
- int q1, q2;
+qty_sugg_compare (int q1, int q2)
{
int tem = QTY_CMP_SUGG (q1) - QTY_CMP_SUGG (q2);
}
static int
-qty_sugg_compare_1 (q1p, q2p)
- const PTR q1p;
- const PTR q2p;
+qty_sugg_compare_1 (const void *q1p, const void *q2p)
{
int q1 = *(const int *) q1p, q2 = *(const int *) q2p;
int tem = QTY_CMP_SUGG (q1) - QTY_CMP_SUGG (q2);
Combining registers means marking them as having the same quantity
and adjusting the offsets within the quantity if either of
- them is a SUBREG).
+ them is a SUBREG.
We don't actually combine a hard reg with a pseudo; instead
we just record the hard reg as the suggestion for the pseudo's quantity.
If we really combined them, we could lose if the pseudo lives
- across an insn that clobbers the hard reg (eg, movstr).
-
- ALREADY_DEAD is non-zero if USEDREG is known to be dead even though
- there is no REG_DEAD note on INSN. This occurs during the processing
- of REG_NO_CONFLICT blocks.
+ across an insn that clobbers the hard reg (eg, movmem).
- MAY_SAVE_COPYCOPY is non-zero if this insn is simply copying USEDREG to
+ MAY_SAVE_COPY is nonzero if this insn is simply copying USEDREG to
SETREG or if the input and output must share a register.
In that case, we record a hard reg suggestion in QTY_PHYS_COPY_SUGG.
There are elaborate checks for the validity of combining. */
static int
-combine_regs (usedreg, setreg, may_save_copy, insn_number, insn, already_dead)
- rtx usedreg, setreg;
- int may_save_copy;
- int insn_number;
- rtx insn;
- int already_dead;
+combine_regs (rtx usedreg, rtx setreg, int may_save_copy, int insn_number,
+ rtx insn)
{
int ureg, sreg;
int offset = 0;
{
rtx subreg = SUBREG_REG (usedreg);
- if (GET_CODE (subreg) == REG)
+ if (REG_P (subreg))
{
if (GET_MODE_SIZE (GET_MODE (subreg)) > UNITS_PER_WORD)
may_save_copy = 0;
usedreg = subreg;
}
- if (GET_CODE (usedreg) != REG)
+ if (!REG_P (usedreg))
return 0;
ureg = REGNO (usedreg);
if (ureg < FIRST_PSEUDO_REGISTER)
- usize = HARD_REGNO_NREGS (ureg, GET_MODE (usedreg));
+ usize = hard_regno_nregs[ureg][GET_MODE (usedreg)];
else
usize = ((GET_MODE_SIZE (GET_MODE (usedreg))
+ (REGMODE_NATURAL_SIZE (GET_MODE (usedreg)) - 1))
{
rtx subreg = SUBREG_REG (setreg);
- if (GET_CODE (subreg) == REG)
+ if (REG_P (subreg))
{
if (GET_MODE_SIZE (GET_MODE (subreg)) > UNITS_PER_WORD)
may_save_copy = 0;
setreg = subreg;
}
- if (GET_CODE (setreg) != REG)
+ if (!REG_P (setreg))
return 0;
sreg = REGNO (setreg);
if (sreg < FIRST_PSEUDO_REGISTER)
- ssize = HARD_REGNO_NREGS (sreg, GET_MODE (setreg));
+ ssize = hard_regno_nregs[sreg][GET_MODE (setreg)];
else
ssize = ((GET_MODE_SIZE (GET_MODE (setreg))
+ (REGMODE_NATURAL_SIZE (GET_MODE (setreg)) - 1))
&& usize < qty[reg_qty[ureg]].size)
/* Can't combine if SREG is not a register we can allocate. */
|| (sreg >= FIRST_PSEUDO_REGISTER && reg_qty[sreg] == -1)
- /* Don't combine with a pseudo mentioned in a REG_NO_CONFLICT note.
- These have already been taken care of. This probably wouldn't
- combine anyway, but don't take any chances. */
- || (ureg >= FIRST_PSEUDO_REGISTER
- && find_reg_note (insn, REG_NO_CONFLICT, usedreg))
/* Don't tie something to itself. In most cases it would make no
difference, but it would screw up if the reg being tied to itself
also dies in this insn. */
if (reg_qty[sreg] >= -1
/* If we are not going to let any regs live across calls,
don't tie a call-crossing reg to a non-call-crossing reg. */
- || (current_function_has_nonlocal_label
+ || (cfun->has_nonlocal_label
&& ((REG_N_CALLS_CROSSED (ureg) > 0)
!= (REG_N_CALLS_CROSSED (sreg) > 0))))
return 0;
if this is the last use of UREG, provided the classes they want
are compatible. */
- if ((already_dead || find_regno_note (insn, REG_DEAD, ureg))
+ if (find_regno_note (insn, REG_DEAD, ureg)
&& reg_meets_class_p (sreg, qty[reg_qty[ureg]].min_class))
{
/* Add SREG to UREG's quantity. */
/* Update info about quantity SQTY. */
qty[sqty].n_calls_crossed += REG_N_CALLS_CROSSED (sreg);
+ qty[sqty].freq_calls_crossed += REG_FREQ_CALLS_CROSSED (sreg);
+ qty[sqty].n_throwing_calls_crossed
+ += REG_N_THROWING_CALLS_CROSSED (sreg);
qty[sqty].n_refs += REG_N_REFS (sreg);
qty[sqty].freq += REG_FREQ (sreg);
if (usize < ssize)
True if REG's reg class either contains or is contained in CLASS. */
static int
-reg_meets_class_p (reg, class)
- int reg;
- enum reg_class class;
+reg_meets_class_p (int reg, enum reg_class class)
{
enum reg_class rclass = reg_preferred_class (reg);
return (reg_class_subset_p (rclass, class)
/* Update the class of QTYNO assuming that REG is being tied to it. */
static void
-update_qty_class (qtyno, reg)
- int qtyno;
- int reg;
+update_qty_class (int qtyno, int reg)
{
enum reg_class rclass = reg_preferred_class (reg);
if (reg_class_subset_p (rclass, qty[qtyno].min_class))
rclass = reg_alternate_class (reg);
if (reg_class_subset_p (rclass, qty[qtyno].alternate_class))
qty[qtyno].alternate_class = rclass;
-
- if (REG_CHANGES_MODE (reg))
- qty[qtyno].changes_mode = 1;
}
\f
/* Handle something which alters the value of an rtx REG.
carry info from `block_alloc'. */
static void
-reg_is_set (reg, setter, data)
- rtx reg;
- rtx setter;
- void *data ATTRIBUTE_UNUSED;
+reg_is_set (rtx reg, const_rtx setter, void *data ATTRIBUTE_UNUSED)
{
/* Note that note_stores will only pass us a SUBREG if it is a SUBREG of
a hard register. These may actually not exist any more. */
if (GET_CODE (reg) != SUBREG
- && GET_CODE (reg) != REG)
+ && !REG_P (reg))
return;
/* Mark this register as being born. If it is used in a CLOBBER, mark
BIRTH is the index at which this is happening. */
static void
-reg_is_born (reg, birth)
- rtx reg;
- int birth;
+reg_is_born (rtx reg, int birth)
{
int regno;
{
regno = REGNO (SUBREG_REG (reg));
if (regno < FIRST_PSEUDO_REGISTER)
- regno = subreg_hard_regno (reg, 1);
+ regno = subreg_regno (reg);
}
else
regno = REGNO (reg);
}
}
-/* Record the death of REG in the current insn. If OUTPUT_P is non-zero,
+/* Record the death of REG in the current insn. If OUTPUT_P is nonzero,
REG is an output that is dying (i.e., it is never used), otherwise it
is an input (the normal case).
If OUTPUT_P is 1, then we extend the life past the end of this insn. */
static void
-wipe_dead_reg (reg, output_p)
- rtx reg;
- int output_p;
+wipe_dead_reg (rtx reg, int output_p)
{
int regno = REGNO (reg);
{
rtx set = XVECEXP (PATTERN (this_insn), 0, i);
if (GET_CODE (set) == SET
- && GET_CODE (SET_DEST (set)) != REG
+ && !REG_P (SET_DEST (set))
&& !rtx_equal_p (reg, SET_DEST (set))
&& reg_overlap_mentioned_p (reg, SET_DEST (set)))
output_p = 1;
If QTYNO crosses calls, insist on a register preserved by calls,
unless ACCEPT_CALL_CLOBBERED is nonzero.
- If JUST_TRY_SUGGESTED is non-zero, only try to see if the suggested
+ If JUST_TRY_SUGGESTED is nonzero, only try to see if the suggested
register is available. If not, return -1. */
static int
-find_free_reg (class, mode, qtyno, accept_call_clobbered, just_try_suggested,
- born_index, dead_index)
- enum reg_class class;
- enum machine_mode mode;
- int qtyno;
- int accept_call_clobbered;
- int just_try_suggested;
- int born_index, dead_index;
+find_free_reg (enum reg_class class, enum machine_mode mode, int qtyno,
+ int accept_call_clobbered, int just_try_suggested,
+ int born_index, int dead_index)
{
int i, ins;
-#ifdef HARD_REG_SET
- /* Declare it register if it's a scalar. */
- register
-#endif
- HARD_REG_SET used, first_used;
+ HARD_REG_SET first_used, used;
#ifdef ELIMINABLE_REGS
static const struct {const int from, to; } eliminables[] = ELIMINABLE_REGS;
#endif
/* Validate our parameters. */
- if (born_index < 0 || born_index > dead_index)
- abort ();
+ gcc_assert (born_index >= 0 && born_index <= dead_index);
/* Don't let a pseudo live in a reg across a function call
if we might get a nonlocal goto. */
- if (current_function_has_nonlocal_label
+ if (cfun->has_nonlocal_label
&& qty[qtyno].n_calls_crossed > 0)
return -1;
SET_HARD_REG_BIT (used, FRAME_POINTER_REGNUM);
#endif
-#ifdef CLASS_CANNOT_CHANGE_MODE
- if (qty[qtyno].changes_mode)
- IOR_HARD_REG_SET (used,
- reg_class_contents[(int) CLASS_CANNOT_CHANGE_MODE]);
+#ifdef CANNOT_CHANGE_MODE_CLASS
+ cannot_change_mode_set_regs (&used, mode, qty[qtyno].first_reg);
#endif
/* Normally, the registers that can be used for the first register in
IOR_COMPL_HARD_REG_SET (first_used, qty_phys_sugg[qtyno]);
}
- /* If all registers are excluded, we can't do anything. */
- GO_IF_HARD_REG_SUBSET (reg_class_contents[(int) ALL_REGS], first_used, fail);
-
/* If at least one would be suitable, test each hard reg. */
-
- for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
- {
+ if (!hard_reg_set_subset_p (reg_class_contents[(int) ALL_REGS], first_used))
+ for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
+ {
#ifdef REG_ALLOC_ORDER
- int regno = reg_alloc_order[i];
+ int regno = reg_alloc_order[i];
#else
- int regno = i;
+ int regno = i;
#endif
- if (! TEST_HARD_REG_BIT (first_used, regno)
- && HARD_REGNO_MODE_OK (regno, mode)
- && (qty[qtyno].n_calls_crossed == 0
- || accept_call_clobbered
- || ! HARD_REGNO_CALL_PART_CLOBBERED (regno, mode)))
- {
- int j;
- int size1 = HARD_REGNO_NREGS (regno, mode);
- for (j = 1; j < size1 && ! TEST_HARD_REG_BIT (used, regno + j); j++);
- if (j == size1)
- {
- /* Mark that this register is in use between its birth and death
- insns. */
- post_mark_life (regno, mode, 1, born_index, dead_index);
- return regno;
- }
+ if (!TEST_HARD_REG_BIT (first_used, regno)
+ && HARD_REGNO_MODE_OK (regno, mode)
+ && (qty[qtyno].n_calls_crossed == 0
+ || accept_call_clobbered
+ || !HARD_REGNO_CALL_PART_CLOBBERED (regno, mode)))
+ {
+ int j;
+ int size1 = hard_regno_nregs[regno][mode];
+ j = 1;
+ while (j < size1 && !TEST_HARD_REG_BIT (used, regno + j))
+ j++;
+ if (j == size1)
+ {
+ /* Mark that this register is in use between its birth
+ and death insns. */
+ post_mark_life (regno, mode, 1, born_index, dead_index);
+ return regno;
+ }
#ifndef REG_ALLOC_ORDER
- /* Skip starting points we know will lose. */
- i += j;
+ /* Skip starting points we know will lose. */
+ i += j;
#endif
- }
- }
+ }
+ }
- fail:
/* If we are just trying suggested register, we have just tried copy-
suggested registers, and there are arithmetic-suggested registers,
try them. */
/* We need not check to see if the current function has nonlocal
labels because we don't put any pseudos that are live over calls in
- registers in that case. */
+ registers in that case. Avoid putting pseudos crossing calls that
+ might throw into call used registers. */
if (! accept_call_clobbered
&& flag_caller_saves
&& ! just_try_suggested
&& qty[qtyno].n_calls_crossed != 0
- && CALLER_SAVE_PROFITABLE (qty[qtyno].n_refs,
- qty[qtyno].n_calls_crossed))
+ && qty[qtyno].n_throwing_calls_crossed == 0
+ && CALLER_SAVE_PROFITABLE (optimize_size ? qty[qtyno].n_refs : qty[qtyno].freq,
+ optimize_size ? qty[qtyno].n_calls_crossed
+ : qty[qtyno].freq_calls_crossed))
{
i = find_free_reg (class, mode, qtyno, 1, 0, born_index, dead_index);
if (i >= 0)
}
\f
/* Mark that REGNO with machine-mode MODE is live starting from the current
- insn (if LIFE is non-zero) or dead starting at the current insn (if LIFE
+ insn (if LIFE is nonzero) or dead starting at the current insn (if LIFE
is zero). */
static void
-mark_life (regno, mode, life)
- int regno;
- enum machine_mode mode;
- int life;
+mark_life (int regno, enum machine_mode mode, int life)
{
- int j = HARD_REGNO_NREGS (regno, mode);
if (life)
- while (--j >= 0)
- SET_HARD_REG_BIT (regs_live, regno + j);
+ add_to_hard_reg_set (®s_live, mode, regno);
else
- while (--j >= 0)
- CLEAR_HARD_REG_BIT (regs_live, regno + j);
+ remove_from_hard_reg_set (®s_live, mode, regno);
}
/* Mark register number REGNO (with machine-mode MODE) as live (if LIFE
- is non-zero) or dead (if LIFE is zero) from insn number BIRTH (inclusive)
+ is nonzero) or dead (if LIFE is zero) from insn number BIRTH (inclusive)
to insn number DEATH (exclusive). */
static void
-post_mark_life (regno, mode, life, birth, death)
- int regno;
- enum machine_mode mode;
- int life, birth, death;
+post_mark_life (int regno, enum machine_mode mode, int life, int birth,
+ int death)
{
- int j = HARD_REGNO_NREGS (regno, mode);
-#ifdef HARD_REG_SET
- /* Declare it register if it's a scalar. */
- register
-#endif
- HARD_REG_SET this_reg;
+ HARD_REG_SET this_reg;
CLEAR_HARD_REG_SET (this_reg);
- while (--j >= 0)
- SET_HARD_REG_BIT (this_reg, regno + j);
+ add_to_hard_reg_set (&this_reg, mode, regno);
if (life)
while (birth < death)
}
}
\f
-/* INSN is the CLOBBER insn that starts a REG_NO_NOCONFLICT block, R0
- is the register being clobbered, and R1 is a register being used in
- the equivalent expression.
-
- If R1 dies in the block and has a REG_NO_CONFLICT note on every insn
- in which it is used, return 1.
-
- Otherwise, return 0. */
-
-static int
-no_conflict_p (insn, r0, r1)
- rtx insn, r0 ATTRIBUTE_UNUSED, r1;
-{
- int ok = 0;
- rtx note = find_reg_note (insn, REG_LIBCALL, NULL_RTX);
- rtx p, last;
-
- /* If R1 is a hard register, return 0 since we handle this case
- when we scan the insns that actually use it. */
-
- if (note == 0
- || (GET_CODE (r1) == REG && REGNO (r1) < FIRST_PSEUDO_REGISTER)
- || (GET_CODE (r1) == SUBREG && GET_CODE (SUBREG_REG (r1)) == REG
- && REGNO (SUBREG_REG (r1)) < FIRST_PSEUDO_REGISTER))
- return 0;
-
- last = XEXP (note, 0);
-
- for (p = NEXT_INSN (insn); p && p != last; p = NEXT_INSN (p))
- if (INSN_P (p))
- {
- if (find_reg_note (p, REG_DEAD, r1))
- ok = 1;
-
- /* There must be a REG_NO_CONFLICT note on every insn, otherwise
- some earlier optimization pass has inserted instructions into
- the sequence, and it is not safe to perform this optimization.
- Note that emit_no_conflict_block always ensures that this is
- true when these sequences are created. */
- if (! find_reg_note (p, REG_NO_CONFLICT, r1))
- return 0;
- }
-
- return ok;
-}
-\f
/* Return the number of alternatives for which the constraint string P
indicates that the operand must be equal to operand 0 and that no register
is acceptable. */
static int
-requires_inout (p)
- const char *p;
+requires_inout (const char *p)
{
char c;
int found_zero = 0;
int reg_allowed = 0;
int num_matching_alts = 0;
+ int len;
- while ((c = *p++))
- switch (c)
- {
- case '=': case '+': case '?':
- case '#': case '&': case '!':
- case '*': case '%':
- case 'm': case '<': case '>': case 'V': case 'o':
- case 'E': case 'F': case 'G': case 'H':
- case 's': case 'i': case 'n':
- case 'I': case 'J': case 'K': case 'L':
- case 'M': case 'N': case 'O': case 'P':
- case 'X':
- /* These don't say anything we care about. */
- break;
+ for ( ; (c = *p); p += len)
+ {
+ len = CONSTRAINT_LEN (c, p);
+ switch (c)
+ {
+ case '=': case '+': case '?':
+ case '#': case '&': case '!':
+ case '*': case '%':
+ case 'm': case '<': case '>': case 'V': case 'o':
+ case 'E': case 'F': case 'G': case 'H':
+ case 's': case 'i': case 'n':
+ case 'I': case 'J': case 'K': case 'L':
+ case 'M': case 'N': case 'O': case 'P':
+ case 'X':
+ /* These don't say anything we care about. */
+ break;
- case ',':
- if (found_zero && ! reg_allowed)
- num_matching_alts++;
+ case ',':
+ if (found_zero && ! reg_allowed)
+ num_matching_alts++;
- found_zero = reg_allowed = 0;
- break;
+ found_zero = reg_allowed = 0;
+ break;
- case '0':
- found_zero = 1;
- break;
+ case '0':
+ found_zero = 1;
+ break;
- case '1': case '2': case '3': case '4': case '5':
- case '6': case '7': case '8': case '9':
- /* Skip the balance of the matching constraint. */
- while (ISDIGIT (*p))
- p++;
- break;
+ case '1': case '2': case '3': case '4': case '5':
+ case '6': case '7': case '8': case '9':
+ /* Skip the balance of the matching constraint. */
+ do
+ p++;
+ while (ISDIGIT (*p));
+ len = 0;
+ break;
- default:
- if (REG_CLASS_FROM_LETTER (c) == NO_REGS)
+ default:
+ if (REG_CLASS_FROM_CONSTRAINT (c, p) == NO_REGS
+ && !EXTRA_ADDRESS_CONSTRAINT (c, p))
+ break;
+ /* Fall through. */
+ case 'p':
+ case 'g': case 'r':
+ reg_allowed = 1;
break;
- /* FALLTHRU */
- case 'p':
- case 'g': case 'r':
- reg_allowed = 1;
- break;
- }
+ }
+ }
if (found_zero && ! reg_allowed)
num_matching_alts++;
}
\f
void
-dump_local_alloc (file)
- FILE *file;
+dump_local_alloc (FILE *file)
{
int i;
for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
if (reg_renumber[i] != -1)
fprintf (file, ";; Register %d in %d.\n", i, reg_renumber[i]);
}
+
+#ifdef STACK_REGS
+static void
+find_stack_regs (void)
+{
+ bitmap stack_regs = BITMAP_ALLOC (NULL);
+ int i;
+ HARD_REG_SET stack_hard_regs, used;
+ basic_block bb;
+
+ /* Any register that MAY be allocated to a register stack (like the
+ 387) is treated poorly. Each such register is marked as being
+ live everywhere. This keeps the register allocator and the
+ subsequent passes from doing anything useful with these values.
+
+ FIXME: This seems like an incredibly poor idea. */
+
+ CLEAR_HARD_REG_SET (stack_hard_regs);
+ for (i = FIRST_STACK_REG; i <= LAST_STACK_REG; i++)
+ SET_HARD_REG_BIT (stack_hard_regs, i);
+
+ for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
+ {
+ COPY_HARD_REG_SET (used, reg_class_contents[reg_preferred_class (i)]);
+ IOR_HARD_REG_SET (used, reg_class_contents[reg_alternate_class (i)]);
+ AND_HARD_REG_SET (used, stack_hard_regs);
+ if (!hard_reg_set_empty_p (used))
+ bitmap_set_bit (stack_regs, i);
+ }
+
+ if (dump_file)
+ bitmap_print (dump_file, stack_regs, "stack regs:", "\n");
+
+ FOR_EACH_BB (bb)
+ {
+ bitmap_ior_into (DF_LIVE_IN (bb), stack_regs);
+ bitmap_and_into (DF_LIVE_IN (bb), DF_LR_IN (bb));
+ bitmap_ior_into (DF_LIVE_OUT (bb), stack_regs);
+ bitmap_and_into (DF_LIVE_OUT (bb), DF_LR_OUT (bb));
+ }
+ BITMAP_FREE (stack_regs);
+}
+#endif
+
+/* Run old register allocator. Return TRUE if we must exit
+ rest_of_compilation upon return. */
+static unsigned int
+rest_of_handle_local_alloc (void)
+{
+ int rebuild_notes;
+ int max_regno = max_reg_num ();
+
+ df_note_add_problem ();
+
+ if (optimize == 1)
+ {
+ df_live_add_problem ();
+ df_live_set_all_dirty ();
+ }
+#ifdef ENABLE_CHECKING
+ df->changeable_flags |= DF_VERIFY_SCHEDULED;
+#endif
+ df_analyze ();
+#ifdef STACK_REGS
+ if (optimize)
+ find_stack_regs ();
+#endif
+ regstat_init_n_sets_and_refs ();
+ regstat_compute_ri ();
+
+ /* If we are not optimizing, then this is the only place before
+ register allocation where dataflow is done. And that is needed
+ to generate these warnings. */
+ if (warn_clobbered)
+ generate_setjmp_warnings ();
+
+ /* Determine if the current function is a leaf before running reload
+ since this can impact optimizations done by the prologue and
+ epilogue thus changing register elimination offsets. */
+ current_function_is_leaf = leaf_function_p ();
+
+ /* And the reg_equiv_memory_loc array. */
+ VEC_safe_grow (rtx, gc, reg_equiv_memory_loc_vec, max_regno);
+ memset (VEC_address (rtx, reg_equiv_memory_loc_vec), 0,
+ sizeof (rtx) * max_regno);
+ reg_equiv_memory_loc = VEC_address (rtx, reg_equiv_memory_loc_vec);
+
+ allocate_initial_values (reg_equiv_memory_loc);
+
+ regclass (get_insns (), max_regno);
+ rebuild_notes = local_alloc ();
+
+ /* Local allocation may have turned an indirect jump into a direct
+ jump. If so, we must rebuild the JUMP_LABEL fields of jumping
+ instructions. */
+ if (rebuild_notes)
+ {
+ timevar_push (TV_JUMP);
+
+ rebuild_jump_labels (get_insns ());
+ purge_all_dead_edges ();
+ timevar_pop (TV_JUMP);
+ }
+
+ if (dump_file && (dump_flags & TDF_DETAILS))
+ {
+ timevar_push (TV_DUMP);
+ dump_flow_info (dump_file, dump_flags);
+ dump_local_alloc (dump_file);
+ timevar_pop (TV_DUMP);
+ }
+ return 0;
+}
+
+struct rtl_opt_pass pass_local_alloc =
+{
+ {
+ RTL_PASS,
+ "lreg", /* name */
+ NULL, /* gate */
+ rest_of_handle_local_alloc, /* execute */
+ NULL, /* sub */
+ NULL, /* next */
+ 0, /* static_pass_number */
+ TV_LOCAL_ALLOC, /* tv_id */
+ 0, /* properties_required */
+ 0, /* properties_provided */
+ 0, /* properties_destroyed */
+ 0, /* todo_flags_start */
+ TODO_dump_func |
+ TODO_ggc_collect /* todo_flags_finish */
+ }
+};
+
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