/* Integrated Register Allocator (IRA) entry point.
- Copyright (C) 2006, 2007, 2008
+ Copyright (C) 2006, 2007, 2008, 2009
Free Software Foundation, Inc.
Contributed by Vladimir Makarov <vmakarov@redhat.com>.
static void
setup_class_subset_and_memory_move_costs (void)
{
- int cl, cl2;
- enum machine_mode mode;
+ int cl, cl2, mode;
HARD_REG_SET temp_hard_regset2;
for (mode = 0; mode < MAX_MACHINE_MODE; mode++)
if (cl != (int) NO_REGS)
for (mode = 0; mode < MAX_MACHINE_MODE; mode++)
{
- ira_memory_move_cost[mode][cl][0] = MEMORY_MOVE_COST (mode, cl, 0);
- ira_memory_move_cost[mode][cl][1] = MEMORY_MOVE_COST (mode, cl, 1);
+ ira_memory_move_cost[mode][cl][0] =
+ MEMORY_MOVE_COST ((enum machine_mode) mode,
+ (enum reg_class) cl, 0);
+ ira_memory_move_cost[mode][cl][1] =
+ MEMORY_MOVE_COST ((enum machine_mode) mode,
+ (enum reg_class) cl, 1);
/* Costs for NO_REGS are used in cost calculation on the
1st pass when the preferred register classes are not
known yet. In this case we take the best scenario. */
static void
setup_cover_and_important_classes (void)
{
- int i, j, n;
- bool set_p, eq_p;
- enum reg_class cl;
+ int i, j, n, cl;
+ bool set_p;
const enum reg_class *cover_classes;
HARD_REG_SET temp_hard_regset2;
static enum reg_class classes[LIM_REG_CLASSES + 1];
else
{
for (i = 0; (cl = cover_classes[i]) != LIM_REG_CLASSES; i++)
- classes[i] = cl;
+ classes[i] = (enum reg_class) cl;
classes[i] = LIM_REG_CLASSES;
}
{
if (i == NO_REGS)
continue;
-#ifdef CONSTRAINT__LIMIT
+#ifdef CONSTRAINT_NUM_DEFINED_P
for (j = 0; j < CONSTRAINT__LIMIT; j++)
- if ((int) regclass_for_constraint (j) == i)
+ if ((int) REG_CLASS_FOR_CONSTRAINT ((enum constraint_num) j) == i)
break;
if (j < CONSTRAINT__LIMIT)
{
- classes[n++] = i;
+ classes[n++] = (enum reg_class) i;
continue;
}
#endif
break;
}
if (j >= i)
- classes[n++] = i;
+ classes[n++] = (enum reg_class) i;
}
classes[n] = LIM_REG_CLASSES;
}
{
for (j = 0; j < i; j++)
if (flag_ira_algorithm != IRA_ALGORITHM_PRIORITY
- && reg_classes_intersect_p (cl, classes[j]))
+ && reg_classes_intersect_p ((enum reg_class) cl, classes[j]))
gcc_unreachable ();
COPY_HARD_REG_SET (temp_hard_regset, reg_class_contents[cl]);
AND_COMPL_HARD_REG_SET (temp_hard_regset, no_unit_alloc_regs);
if (! hard_reg_set_empty_p (temp_hard_regset))
- ira_reg_class_cover[ira_reg_class_cover_size++] = cl;
+ ira_reg_class_cover[ira_reg_class_cover_size++] = (enum reg_class) cl;
}
ira_important_classes_num = 0;
for (cl = 0; cl < N_REG_CLASSES; cl++)
AND_COMPL_HARD_REG_SET (temp_hard_regset, no_unit_alloc_regs);
if (! hard_reg_set_empty_p (temp_hard_regset))
{
- set_p = eq_p = false;
+ set_p = false;
for (j = 0; j < ira_reg_class_cover_size; j++)
{
COPY_HARD_REG_SET (temp_hard_regset, reg_class_contents[cl]);
COPY_HARD_REG_SET (temp_hard_regset2,
reg_class_contents[ira_reg_class_cover[j]]);
AND_COMPL_HARD_REG_SET (temp_hard_regset2, no_unit_alloc_regs);
- if (cl == ira_reg_class_cover[j])
- {
- eq_p = false;
- set_p = true;
- break;
- }
- else if (hard_reg_set_equal_p (temp_hard_regset,
- temp_hard_regset2))
- eq_p = true;
+ if ((enum reg_class) cl == ira_reg_class_cover[j]
+ || hard_reg_set_equal_p (temp_hard_regset,
+ temp_hard_regset2))
+ break;
else if (hard_reg_set_subset_p (temp_hard_regset,
temp_hard_regset2))
set_p = true;
}
- if (set_p && ! eq_p)
- {
- ira_important_class_nums[cl] = ira_important_classes_num;
- ira_important_classes[ira_important_classes_num++] = cl;
- }
+ if (set_p && j >= ira_reg_class_cover_size)
+ ira_important_classes[ira_important_classes_num++]
+ = (enum reg_class) cl;
}
}
+ for (j = 0; j < ira_reg_class_cover_size; j++)
+ ira_important_classes[ira_important_classes_num++]
+ = ira_reg_class_cover[j];
}
/* Map of all register classes to corresponding cover class containing
static void
setup_class_translate (void)
{
- enum reg_class cl, cover_class, best_class, *cl_ptr;
- enum machine_mode mode;
+ int cl, mode;
+ enum reg_class cover_class, best_class, *cl_ptr;
int i, cost, min_cost, best_cost;
for (cl = 0; cl < N_REG_CLASSES; cl++)
}
}
+/* Order numbers of cover classes in original target cover class
+ array, -1 for non-cover classes. */
+static int cover_class_order[N_REG_CLASSES];
+
+/* The function used to sort the important classes. */
+static int
+comp_reg_classes_func (const void *v1p, const void *v2p)
+{
+ enum reg_class cl1 = *(const enum reg_class *) v1p;
+ enum reg_class cl2 = *(const enum reg_class *) v2p;
+ int diff;
+
+ cl1 = ira_class_translate[cl1];
+ cl2 = ira_class_translate[cl2];
+ if (cl1 != NO_REGS && cl2 != NO_REGS
+ && (diff = cover_class_order[cl1] - cover_class_order[cl2]) != 0)
+ return diff;
+ return (int) cl1 - (int) cl2;
+}
+
+/* Reorder important classes according to the order of their cover
+ classes. Set up array ira_important_class_nums too. */
+static void
+reorder_important_classes (void)
+{
+ int i;
+
+ for (i = 0; i < N_REG_CLASSES; i++)
+ cover_class_order[i] = -1;
+ for (i = 0; i < ira_reg_class_cover_size; i++)
+ cover_class_order[ira_reg_class_cover[i]] = i;
+ qsort (ira_important_classes, ira_important_classes_num,
+ sizeof (enum reg_class), comp_reg_classes_func);
+ for (i = 0; i < ira_important_classes_num; i++)
+ ira_important_class_nums[ira_important_classes[i]] = i;
+}
+
/* The biggest important reg_class inside of intersection of the two
reg_classes (that is calculated taking only hard registers
available for allocation into account). If the both reg_classes
if (cl3 == LIM_REG_CLASSES)
break;
if (reg_class_subset_p (ira_reg_class_intersect[cl1][cl2],
- cl3))
- ira_reg_class_intersect[cl1][cl2] = cl3;
+ (enum reg_class) cl3))
+ ira_reg_class_intersect[cl1][cl2] = (enum reg_class) cl3;
}
ira_reg_class_union[cl1][cl2] = reg_class_subunion[cl1][cl2];
continue;
setup_reg_subclasses ();
setup_cover_and_important_classes ();
setup_class_translate ();
+ reorder_important_classes ();
setup_reg_class_relations ();
}
static void
setup_reg_class_nregs (void)
{
- int m;
- enum reg_class cl;
+ int cl, m;
ira_max_nregs = -1;
for (cl = 0; cl < N_REG_CLASSES; cl++)
for (m = 0; m < MAX_MACHINE_MODE; m++)
{
- ira_reg_class_nregs[cl][m] = CLASS_MAX_NREGS (cl, m);
+ ira_reg_class_nregs[cl][m] = CLASS_MAX_NREGS ((enum reg_class) cl,
+ (enum machine_mode) m);
if (ira_max_nregs < ira_reg_class_nregs[cl][m])
ira_max_nregs = ira_reg_class_nregs[cl][m];
}
for (k = ira_class_hard_regs_num[cl] - 1; k >= 0; k--)
{
hard_regno = ira_class_hard_regs[cl][k];
- if (! HARD_REGNO_MODE_OK (hard_regno, j))
+ if (! HARD_REGNO_MODE_OK (hard_regno, (enum machine_mode) j))
SET_HARD_REG_BIT (prohibited_class_mode_regs[cl][j],
hard_regno);
}
void
ira_init_once (void)
{
- enum machine_mode mode;
+ int mode;
for (mode = 0; mode < MAX_MACHINE_MODE; mode++)
{
static void
free_register_move_costs (void)
{
- enum machine_mode mode;
+ int mode;
for (mode = 0; mode < MAX_MACHINE_MODE; mode++)
{
SET_HARD_REG_SET (ira_prohibited_mode_move_regs[i]);
for (j = 0; j < FIRST_PSEUDO_REGISTER; j++)
{
- if (! HARD_REGNO_MODE_OK (j, i))
+ if (! HARD_REGNO_MODE_OK (j, (enum machine_mode) i))
continue;
SET_REGNO (test_reg1, j);
- PUT_MODE (test_reg1, i);
+ PUT_MODE (test_reg1, (enum machine_mode) i);
SET_REGNO (test_reg2, j);
- PUT_MODE (test_reg2, i);
+ PUT_MODE (test_reg2, (enum machine_mode) i);
INSN_CODE (move_insn) = -1;
recog_memoized (move_insn);
if (INSN_CODE (move_insn) < 0)
/* Set up ELIMINABLE_REGSET, IRA_NO_ALLOC_REGS, and REGS_EVER_LIVE. */
-static void
-setup_eliminable_regset (void)
+void
+ira_setup_eliminable_regset (void)
{
/* Like regs_ever_live, but 1 if a reg is set or clobbered from an
asm. Unlike regs_ever_live, elements of this array corresponding
|| (cfun->calls_alloca && EXIT_IGNORE_STACK)
|| crtl->accesses_prior_frames
|| crtl->stack_realign_needed
- || FRAME_POINTER_REQUIRED);
+ || targetm.frame_pointer_required ());
frame_pointer_needed = need_fp;
for (i = 0; i < (int) ARRAY_SIZE (eliminables); i++)
{
bool cannot_elim
- = (! CAN_ELIMINATE (eliminables[i].from, eliminables[i].to)
+ = (! targetm.can_eliminate (eliminables[i].from, eliminables[i].to)
|| (eliminables[i].to == STACK_POINTER_REGNUM && need_fp));
if (! regs_asm_clobbered[eliminables[i].from])
old_regno = ORIGINAL_REGNO (regno_reg_rtx[i]);
ira_assert (i != old_regno);
setup_reg_classes (i, reg_preferred_class (old_regno),
- reg_alternate_class (old_regno));
+ reg_alternate_class (old_regno),
+ reg_cover_class (old_regno));
if (internal_flag_ira_verbose > 2 && ira_dump_file != NULL)
fprintf (ira_dump_file,
" New r%d: setting preferred %s, alternative %s\n",
resize_reg_info ();
for (i = old_size; i < size; i++)
- {
- reg_renumber[i] = -1;
- setup_reg_classes (i, GENERAL_REGS, ALL_REGS);
- }
+ setup_reg_classes (i, GENERAL_REGS, ALL_REGS, GENERAL_REGS);
}
/* Return TRUE if there is too high register pressure in the function.
struct equivalence
{
- /* Set when an attempt should be made to replace a register
- with the associated src_p entry. */
- char replace;
/* Set when a REG_EQUIV note is found or created. Use to
keep track of what memory accesses might be created later,
e.g. by reload. */
rtx replacement;
rtx *src_p;
+ /* The list of each instruction which initializes this register. */
+ rtx init_insns;
/* Loop depth is used to recognize equivalences which appear
to be present within the same loop (or in an inner loop). */
int loop_depth;
- /* The list of each instruction which initializes this register. */
- rtx init_insns;
/* Nonzero if this had a preexisting REG_EQUIV note. */
int is_arg_equivalence;
+ /* Set when an attempt should be made to replace a register
+ with the associated src_p entry. */
+ char replace;
};
/* reg_equiv[N] (where N is a pseudo reg number) is the equivalence
for (insn = NEXT_INSN (start); insn != NEXT_INSN (end);
insn = NEXT_INSN (insn))
{
- if (!INSN_P (insn))
+ if (!NONDEBUG_INSN_P (insn))
continue;
if (memref_referenced_p (memref, PATTERN (insn)))
}
/* Move the initialization of the register to just before
INSN. Update the flow information. */
- else if (PREV_INSN (insn) != equiv_insn)
+ else if (prev_nondebug_insn (insn) != equiv_insn)
{
rtx new_insn;
CLEAR_REG_SET (live_relevant_regs);
memset (live_subregs_used, 0, max_regno * sizeof (int));
- EXECUTE_IF_SET_IN_BITMAP (df_get_live_out (bb), 0, i, bi)
+ EXECUTE_IF_SET_IN_BITMAP (DF_LR_OUT (bb), 0, i, bi)
{
if (i >= FIRST_PSEUDO_REGISTER)
break;
bitmap_set_bit (live_relevant_regs, i);
}
- EXECUTE_IF_SET_IN_BITMAP (df_get_live_out (bb),
+ EXECUTE_IF_SET_IN_BITMAP (DF_LR_OUT (bb),
FIRST_PSEUDO_REGISTER, i, bi)
{
if (pseudo_for_reload_consideration_p (i))
}
max_regno_before_ira = allocated_reg_info_size = max_reg_num ();
- allocate_reg_info ();
- setup_eliminable_regset ();
+ resize_reg_info ();
+ ira_setup_eliminable_regset ();
ira_overall_cost = ira_reg_cost = ira_mem_cost = 0;
ira_load_cost = ira_store_cost = ira_shuffle_cost = 0;
NULL, /* sub */
NULL, /* next */
0, /* static_pass_number */
- 0, /* tv_id */
+ TV_NONE, /* tv_id */
0, /* properties_required */
0, /* properties_provided */
0, /* properties_destroyed */
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