/* Integrated Register Allocator (IRA) entry point.
- Copyright (C) 2006, 2007, 2008, 2009, 2010
+ Copyright (C) 2006, 2007, 2008, 2009, 2010, 2011, 2012
Free Software Foundation, Inc.
Contributed by Vladimir Makarov <vmakarov@redhat.com>.
the other regions. Therefore data structure representing a
region is called loop_tree_node.
- o *Cover class* is a register class belonging to a set of
- non-intersecting register classes containing all of the
- hard-registers available for register allocation. The set of
- all cover classes for a target is defined in the corresponding
- machine-description file according some criteria. Such notion
- is needed because Chaitin-Briggs algorithm works on
- non-intersected register classes.
+ o *Allocno class* is a register class used for allocation of
+ given allocno. It means that only hard register of given
+ register class can be assigned to given allocno. In reality,
+ even smaller subset of (*profitable*) hard registers can be
+ assigned. In rare cases, the subset can be even smaller
+ because our modification of Chaitin-Briggs algorithm requires
+ that sets of hard registers can be assigned to allocnos forms a
+ forest, i.e. the sets can be ordered in a way where any
+ previous set is not intersected with given set or is a superset
+ of given set.
+
+ o *Pressure class* is a register class belonging to a set of
+ register classes containing all of the hard-registers available
+ for register allocation. The set of all pressure classes for a
+ target is defined in the corresponding machine-description file
+ according some criteria. Register pressure is calculated only
+ for pressure classes and it affects some IRA decisions as
+ forming allocation regions.
o *Allocno* represents the live range of a pseudo-register in a
region. Besides the obvious attributes like the corresponding
- pseudo-register number, cover class, conflicting allocnos and
+ pseudo-register number, allocno class, conflicting allocnos and
conflicting hard-registers, there are a few allocno attributes
which are important for understanding the allocation algorithm:
- - *Live ranges*. This is a list of ranges of *program
- points* where the allocno lives. Program points represent
- places where a pseudo can be born or become dead (there are
+ - *Live ranges*. This is a list of ranges of *program points*
+ where the allocno lives. Program points represent places
+ where a pseudo can be born or become dead (there are
approximately two times more program points than the insns)
and they are represented by integers starting with 0. The
- live ranges are used to find conflicts between allocnos of
- different cover classes. They also play very important role
- for the transformation of the IRA internal representation of
- several regions into a one region representation. The later is
- used during the reload pass work because each allocno
- represents all of the corresponding pseudo-registers.
+ live ranges are used to find conflicts between allocnos.
+ They also play very important role for the transformation of
+ the IRA internal representation of several regions into a one
+ region representation. The later is used during the reload
+ pass work because each allocno represents all of the
+ corresponding pseudo-registers.
- *Hard-register costs*. This is a vector of size equal to the
- number of available hard-registers of the allocno's cover
- class. The cost of a callee-clobbered hard-register for an
- allocno is increased by the cost of save/restore code around
- the calls through the given allocno's life. If the allocno
- is a move instruction operand and another operand is a
- hard-register of the allocno's cover class, the cost of the
- hard-register is decreased by the move cost.
+ number of available hard-registers of the allocno class. The
+ cost of a callee-clobbered hard-register for an allocno is
+ increased by the cost of save/restore code around the calls
+ through the given allocno's life. If the allocno is a move
+ instruction operand and another operand is a hard-register of
+ the allocno class, the cost of the hard-register is decreased
+ by the move cost.
When an allocno is assigned, the hard-register with minimal
full cost is used. Initially, a hard-register's full cost is
* First, IRA builds regions and creates allocnos (file
ira-build.c) and initializes most of their attributes.
- * Then IRA finds a cover class for each allocno and calculates
- its initial (non-accumulated) cost of memory and each
- hard-register of its cover class (file ira-cost.c).
+ * Then IRA finds an allocno class for each allocno and
+ calculates its initial (non-accumulated) cost of memory and
+ each hard-register of its allocno class (file ira-cost.c).
* IRA creates live ranges of each allocno, calulates register
- pressure for each cover class in each region, sets up
+ pressure for each pressure class in each region, sets up
conflict hard registers for each allocno and info about calls
the allocno lives through (file ira-lives.c).
* IRA creates all caps (file ira-build.c).
- * Having live-ranges of allocnos and their cover classes, IRA
- creates conflicting allocnos of the same cover class for each
- allocno. Conflicting allocnos are stored as a bit vector or
- array of pointers to the conflicting allocnos whatever is
- more profitable (file ira-conflicts.c). At this point IRA
- creates allocno copies.
+ * Having live-ranges of allocnos and their classes, IRA creates
+ conflicting allocnos for each allocno. Conflicting allocnos
+ are stored as a bit vector or array of pointers to the
+ conflicting allocnos whatever is more profitable (file
+ ira-conflicts.c). At this point IRA creates allocno copies.
o Coloring. Now IRA has all necessary info to start graph coloring
process. It is done in each region on top-down traverse of the
region tree (file ira-color.c). There are following subpasses:
+ * Finding profitable hard registers of corresponding allocno
+ class for each allocno. For example, only callee-saved hard
+ registers are frequently profitable for allocnos living
+ through colors. If the profitable hard register set of
+ allocno does not form a tree based on subset relation, we use
+ some approximation to form the tree. This approximation is
+ used to figure out trivial colorability of allocnos. The
+ approximation is a pretty rare case.
+
* Putting allocnos onto the coloring stack. IRA uses Briggs
optimistic coloring which is a major improvement over
Chaitin's coloring. Therefore IRA does not spill allocnos at
this point. There is some freedom in the order of putting
allocnos on the stack which can affect the final result of
- the allocation. IRA uses some heuristics to improve the order.
+ the allocation. IRA uses some heuristics to improve the
+ order.
+
+ We also use a modification of Chaitin-Briggs algorithm which
+ works for intersected register classes of allocnos. To
+ figure out trivial colorability of allocnos, the mentioned
+ above tree of hard register sets is used. To get an idea how
+ the algorithm works in i386 example, let us consider an
+ allocno to which any general hard register can be assigned.
+ If the allocno conflicts with eight allocnos to which only
+ EAX register can be assigned, given allocno is still
+ trivially colorable because all conflicting allocnos might be
+ assigned only to EAX and all other general hard registers are
+ still free.
+
+ To get an idea of the used trivial colorability criterion, it
+ is also useful to read article "Graph-Coloring Register
+ Allocation for Irregular Architectures" by Michael D. Smith
+ and Glen Holloway. Major difference between the article
+ approach and approach used in IRA is that Smith's approach
+ takes register classes only from machine description and IRA
+ calculate register classes from intermediate code too
+ (e.g. an explicit usage of hard registers in RTL code for
+ parameter passing can result in creation of additional
+ register classes which contain or exclude the hard
+ registers). That makes IRA approach useful for improving
+ coloring even for architectures with regular register files
+ and in fact some benchmarking shows the improvement for
+ regular class architectures is even bigger than for irregular
+ ones. Another difference is that Smith's approach chooses
+ intersection of classes of all insn operands in which a given
+ pseudo occurs. IRA can use bigger classes if it is still
+ more profitable than memory usage.
* Popping the allocnos from the stack and assigning them hard
registers. If IRA can not assign a hard register to an
hard-register for the allocno and cost of usage of the
hard-register for allocnos conflicting with given allocno.
+ * Chaitin-Briggs coloring assigns as many pseudos as possible
+ to hard registers. After coloringh we try to improve
+ allocation with cost point of view. We improve the
+ allocation by spilling some allocnos and assigning the freed
+ hard registers to other allocnos if it decreases the overall
+ allocation cost.
+
* After allono assigning in the region, IRA modifies the hard
register and memory costs for the corresponding allocnos in
the subregions to reflect the cost of possible loads, stores,
When default regional allocation algorithm is used
(-fira-algorithm=mixed), IRA just propagates the assignment
for allocnos if the register pressure in the region for the
- corresponding cover class is less than number of available
- hard registers for given cover class.
+ corresponding pressure class is less than number of available
+ hard registers for given pressure class.
o Spill/restore code moving. When IRA performs an allocation
by traversing regions in top-down order, it does not know what
practice, so there is no real need for a better time complexity
algorithm.
- o Code change. After coloring, two allocnos representing the same
- pseudo-register outside and inside a region respectively may be
- assigned to different locations (hard-registers or memory). In
- this case IRA creates and uses a new pseudo-register inside the
- region and adds code to move allocno values on the region's
- borders. This is done during top-down traversal of the regions
- (file ira-emit.c). In some complicated cases IRA can create a
- new allocno to move allocno values (e.g. when a swap of values
- stored in two hard-registers is needed). At this stage, the
- new allocno is marked as spilled. IRA still creates the
- pseudo-register and the moves on the region borders even when
- both allocnos were assigned to the same hard-register. If the
- reload pass spills a pseudo-register for some reason, the
- effect will be smaller because another allocno will still be in
- the hard-register. In most cases, this is better then spilling
- both allocnos. If reload does not change the allocation
- for the two pseudo-registers, the trivial move will be removed
- by post-reload optimizations. IRA does not generate moves for
+ o Code change. After coloring, two allocnos representing the
+ same pseudo-register outside and inside a region respectively
+ may be assigned to different locations (hard-registers or
+ memory). In this case IRA creates and uses a new
+ pseudo-register inside the region and adds code to move allocno
+ values on the region's borders. This is done during top-down
+ traversal of the regions (file ira-emit.c). In some
+ complicated cases IRA can create a new allocno to move allocno
+ values (e.g. when a swap of values stored in two hard-registers
+ is needed). At this stage, the new allocno is marked as
+ spilled. IRA still creates the pseudo-register and the moves
+ on the region borders even when both allocnos were assigned to
+ the same hard-register. If the reload pass spills a
+ pseudo-register for some reason, the effect will be smaller
+ because another allocno will still be in the hard-register. In
+ most cases, this is better then spilling both allocnos. If
+ reload does not change the allocation for the two
+ pseudo-registers, the trivial move will be removed by
+ post-reload optimizations. IRA does not generate moves for
allocnos assigned to the same hard register when the default
regional allocation algorithm is used and the register pressure
- in the region for the corresponding allocno cover class is less
- than number of available hard registers for given cover class.
+ in the region for the corresponding pressure class is less than
+ number of available hard registers for given pressure class.
IRA also does some optimizations to remove redundant stores and
to reduce code duplication on the region borders.
o Guei-Yuan Lueh, Thomas Gross, and Ali-Reza Adl-Tabatabai. Global
Register Allocation Based on Graph Fusion.
+ o Michael D. Smith and Glenn Holloway. Graph-Coloring Register
+ Allocation for Irregular Architectures
+
o Vladimir Makarov. The Integrated Register Allocator for GCC.
o Vladimir Makarov. The top-down register allocator for irregular
#include "integrate.h"
#include "ggc.h"
#include "ira-int.h"
+#include "dce.h"
struct target_ira default_target_ira;
stack slots used in current function so far. */
struct ira_spilled_reg_stack_slot *ira_spilled_reg_stack_slots;
-/* Correspondingly overall cost of the allocation, cost of the
- allocnos assigned to hard-registers, cost of the allocnos assigned
- to memory, cost of loads, stores and register move insns generated
- for pseudo-register live range splitting (see ira-emit.c). */
-int ira_overall_cost;
+/* Correspondingly overall cost of the allocation, overall cost before
+ reload, cost of the allocnos assigned to hard-registers, cost of
+ the allocnos assigned to memory, cost of loads, stores and register
+ move insns generated for pseudo-register live range splitting (see
+ ira-emit.c). */
+int ira_overall_cost, overall_cost_before;
int ira_reg_cost, ira_mem_cost;
int ira_load_cost, ira_store_cost, ira_shuffle_cost;
int ira_move_loops_num, ira_additional_jumps_num;
CLEAR_HARD_REG_SET (processed_hard_reg_set);
for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
{
- ira_non_ordered_class_hard_regs[cl][0] = -1;
- ira_class_hard_reg_index[cl][0] = -1;
+ ira_non_ordered_class_hard_regs[cl][i] = -1;
+ ira_class_hard_reg_index[cl][i] = -1;
}
for (n = 0, i = 0; i < FIRST_PSEUDO_REGISTER; i++)
{
\f
-/* Set up IRA_MEMORY_MOVE_COST, IRA_REGISTER_MOVE_COST. */
+#define alloc_reg_class_subclasses \
+ (this_target_ira_int->x_alloc_reg_class_subclasses)
+
+/* Initialize the table of subclasses of each reg class. */
+static void
+setup_reg_subclasses (void)
+{
+ int i, j;
+ HARD_REG_SET temp_hard_regset2;
+
+ for (i = 0; i < N_REG_CLASSES; i++)
+ for (j = 0; j < N_REG_CLASSES; j++)
+ alloc_reg_class_subclasses[i][j] = LIM_REG_CLASSES;
+
+ for (i = 0; i < N_REG_CLASSES; i++)
+ {
+ if (i == (int) NO_REGS)
+ continue;
+
+ COPY_HARD_REG_SET (temp_hard_regset, reg_class_contents[i]);
+ AND_COMPL_HARD_REG_SET (temp_hard_regset, no_unit_alloc_regs);
+ if (hard_reg_set_empty_p (temp_hard_regset))
+ continue;
+ for (j = 0; j < N_REG_CLASSES; j++)
+ if (i != j)
+ {
+ enum reg_class *p;
+
+ COPY_HARD_REG_SET (temp_hard_regset2, reg_class_contents[j]);
+ AND_COMPL_HARD_REG_SET (temp_hard_regset2, no_unit_alloc_regs);
+ if (! hard_reg_set_subset_p (temp_hard_regset,
+ temp_hard_regset2))
+ continue;
+ p = &alloc_reg_class_subclasses[j][0];
+ while (*p != LIM_REG_CLASSES) p++;
+ *p = (enum reg_class) i;
+ }
+ }
+}
+
+\f
+
+/* Set up IRA_MEMORY_MOVE_COST and IRA_MAX_MEMORY_MOVE_COST. */
static void
setup_class_subset_and_memory_move_costs (void)
{
- int cl, cl2, mode;
+ int cl, cl2, mode, cost;
HARD_REG_SET temp_hard_regset2;
for (mode = 0; mode < MAX_MACHINE_MODE; mode++)
if (cl != (int) NO_REGS)
for (mode = 0; mode < MAX_MACHINE_MODE; mode++)
{
- ira_memory_move_cost[mode][cl][0] =
- memory_move_cost ((enum machine_mode) mode,
- (enum reg_class) cl, false);
- ira_memory_move_cost[mode][cl][1] =
- memory_move_cost ((enum machine_mode) mode,
- (enum reg_class) cl, true);
+ ira_max_memory_move_cost[mode][cl][0]
+ = ira_memory_move_cost[mode][cl][0]
+ = memory_move_cost ((enum machine_mode) mode,
+ (reg_class_t) cl, false);
+ ira_max_memory_move_cost[mode][cl][1]
+ = ira_memory_move_cost[mode][cl][1]
+ = memory_move_cost ((enum machine_mode) mode,
+ (reg_class_t) cl, true);
/* Costs for NO_REGS are used in cost calculation on the
1st pass when the preferred register classes are not
known yet. In this case we take the best scenario. */
if (ira_memory_move_cost[mode][NO_REGS][0]
> ira_memory_move_cost[mode][cl][0])
- ira_memory_move_cost[mode][NO_REGS][0]
+ ira_max_memory_move_cost[mode][NO_REGS][0]
+ = ira_memory_move_cost[mode][NO_REGS][0]
= ira_memory_move_cost[mode][cl][0];
if (ira_memory_move_cost[mode][NO_REGS][1]
> ira_memory_move_cost[mode][cl][1])
- ira_memory_move_cost[mode][NO_REGS][1]
+ ira_max_memory_move_cost[mode][NO_REGS][1]
+ = ira_memory_move_cost[mode][NO_REGS][1]
= ira_memory_move_cost[mode][cl][1];
}
- for (cl2 = (int) N_REG_CLASSES - 1; cl2 >= 0; cl2--)
- {
- COPY_HARD_REG_SET (temp_hard_regset, reg_class_contents[cl]);
- AND_COMPL_HARD_REG_SET (temp_hard_regset, no_unit_alloc_regs);
- COPY_HARD_REG_SET (temp_hard_regset2, reg_class_contents[cl2]);
- AND_COMPL_HARD_REG_SET (temp_hard_regset2, no_unit_alloc_regs);
- ira_class_subset_p[cl][cl2]
- = hard_reg_set_subset_p (temp_hard_regset, temp_hard_regset2);
- }
}
+ for (cl = (int) N_REG_CLASSES - 1; cl >= 0; cl--)
+ for (cl2 = (int) N_REG_CLASSES - 1; cl2 >= 0; cl2--)
+ {
+ COPY_HARD_REG_SET (temp_hard_regset, reg_class_contents[cl]);
+ AND_COMPL_HARD_REG_SET (temp_hard_regset, no_unit_alloc_regs);
+ COPY_HARD_REG_SET (temp_hard_regset2, reg_class_contents[cl2]);
+ AND_COMPL_HARD_REG_SET (temp_hard_regset2, no_unit_alloc_regs);
+ ira_class_subset_p[cl][cl2]
+ = hard_reg_set_subset_p (temp_hard_regset, temp_hard_regset2);
+ if (! hard_reg_set_empty_p (temp_hard_regset2)
+ && hard_reg_set_subset_p (reg_class_contents[cl2],
+ reg_class_contents[cl]))
+ for (mode = 0; mode < MAX_MACHINE_MODE; mode++)
+ {
+ cost = ira_memory_move_cost[mode][cl2][0];
+ if (cost > ira_max_memory_move_cost[mode][cl][0])
+ ira_max_memory_move_cost[mode][cl][0] = cost;
+ cost = ira_memory_move_cost[mode][cl2][1];
+ if (cost > ira_max_memory_move_cost[mode][cl][1])
+ ira_max_memory_move_cost[mode][cl][1] = cost;
+ }
+ }
+ for (cl = (int) N_REG_CLASSES - 1; cl >= 0; cl--)
+ for (mode = 0; mode < MAX_MACHINE_MODE; mode++)
+ {
+ ira_memory_move_cost[mode][cl][0]
+ = ira_max_memory_move_cost[mode][cl][0];
+ ira_memory_move_cost[mode][cl][1]
+ = ira_max_memory_move_cost[mode][cl][1];
+ }
+ setup_reg_subclasses ();
}
\f
return res;
}
-/* Reallocate memory PTR of size LEN for IRA data. */
-void *
-ira_reallocate (void *ptr, size_t len)
-{
- void *res;
-
-#ifndef IRA_NO_OBSTACK
- res = obstack_alloc (&ira_obstack, len);
-#else
- res = xrealloc (ptr, len);
-#endif
- return res;
-}
-
/* Free memory ADDR allocated for IRA data. */
void
ira_free (void *addr ATTRIBUTE_UNUSED)
if ((bb = ALLOCNO_LOOP_TREE_NODE (a)->bb) != NULL)
fprintf (f, "b%-3d", bb->index);
else
- fprintf (f, "l%-3d", ALLOCNO_LOOP_TREE_NODE (a)->loop->num);
+ fprintf (f, "l%-3d", ALLOCNO_LOOP_TREE_NODE (a)->loop_num);
if (ALLOCNO_HARD_REGNO (a) >= 0)
fprintf (f, " %3d", ALLOCNO_HARD_REGNO (a));
else
}
\f
-#define alloc_reg_class_subclasses \
- (this_target_ira_int->x_alloc_reg_class_subclasses)
-/* Initialize the table of subclasses of each reg class. */
+/* Set up ira_stack_reg_pressure_class which is the biggest pressure
+ register class containing stack registers or NO_REGS if there are
+ no stack registers. To find this class, we iterate through all
+ register pressure classes and choose the first register pressure
+ class containing all the stack registers and having the biggest
+ size. */
static void
-setup_reg_subclasses (void)
+setup_stack_reg_pressure_class (void)
+{
+ ira_stack_reg_pressure_class = NO_REGS;
+#ifdef STACK_REGS
+ {
+ int i, best, size;
+ enum reg_class cl;
+ HARD_REG_SET temp_hard_regset2;
+
+ CLEAR_HARD_REG_SET (temp_hard_regset);
+ for (i = FIRST_STACK_REG; i <= LAST_STACK_REG; i++)
+ SET_HARD_REG_BIT (temp_hard_regset, i);
+ best = 0;
+ for (i = 0; i < ira_pressure_classes_num; i++)
+ {
+ cl = ira_pressure_classes[i];
+ COPY_HARD_REG_SET (temp_hard_regset2, temp_hard_regset);
+ AND_HARD_REG_SET (temp_hard_regset2, reg_class_contents[cl]);
+ size = hard_reg_set_size (temp_hard_regset2);
+ if (best < size)
+ {
+ best = size;
+ ira_stack_reg_pressure_class = cl;
+ }
+ }
+ }
+#endif
+}
+
+/* Find pressure classes which are register classes for which we
+ calculate register pressure in IRA, register pressure sensitive
+ insn scheduling, and register pressure sensitive loop invariant
+ motion.
+
+ To make register pressure calculation easy, we always use
+ non-intersected register pressure classes. A move of hard
+ registers from one register pressure class is not more expensive
+ than load and store of the hard registers. Most likely an allocno
+ class will be a subset of a register pressure class and in many
+ cases a register pressure class. That makes usage of register
+ pressure classes a good approximation to find a high register
+ pressure. */
+static void
+setup_pressure_classes (void)
{
- int i, j;
+ int cost, i, n, curr;
+ int cl, cl2;
+ enum reg_class pressure_classes[N_REG_CLASSES];
+ int m;
HARD_REG_SET temp_hard_regset2;
+ bool insert_p;
- for (i = 0; i < N_REG_CLASSES; i++)
- for (j = 0; j < N_REG_CLASSES; j++)
- alloc_reg_class_subclasses[i][j] = LIM_REG_CLASSES;
-
- for (i = 0; i < N_REG_CLASSES; i++)
+ n = 0;
+ for (cl = 0; cl < N_REG_CLASSES; cl++)
{
- if (i == (int) NO_REGS)
+ if (ira_available_class_regs[cl] == 0)
continue;
-
- COPY_HARD_REG_SET (temp_hard_regset, reg_class_contents[i]);
+ if (ira_available_class_regs[cl] != 1
+ /* A register class without subclasses may contain a few
+ hard registers and movement between them is costly
+ (e.g. SPARC FPCC registers). We still should consider it
+ as a candidate for a pressure class. */
+ && alloc_reg_class_subclasses[cl][0] != LIM_REG_CLASSES)
+ {
+ /* Check that the moves between any hard registers of the
+ current class are not more expensive for a legal mode
+ than load/store of the hard registers of the current
+ class. Such class is a potential candidate to be a
+ register pressure class. */
+ for (m = 0; m < NUM_MACHINE_MODES; m++)
+ {
+ COPY_HARD_REG_SET (temp_hard_regset, reg_class_contents[cl]);
+ AND_COMPL_HARD_REG_SET (temp_hard_regset, no_unit_alloc_regs);
+ AND_COMPL_HARD_REG_SET (temp_hard_regset,
+ ira_prohibited_class_mode_regs[cl][m]);
+ if (hard_reg_set_empty_p (temp_hard_regset))
+ continue;
+ ira_init_register_move_cost_if_necessary ((enum machine_mode) m);
+ cost = ira_register_move_cost[m][cl][cl];
+ if (cost <= ira_max_memory_move_cost[m][cl][1]
+ || cost <= ira_max_memory_move_cost[m][cl][0])
+ break;
+ }
+ if (m >= NUM_MACHINE_MODES)
+ continue;
+ }
+ curr = 0;
+ insert_p = true;
+ COPY_HARD_REG_SET (temp_hard_regset, reg_class_contents[cl]);
AND_COMPL_HARD_REG_SET (temp_hard_regset, no_unit_alloc_regs);
- if (hard_reg_set_empty_p (temp_hard_regset))
- continue;
- for (j = 0; j < N_REG_CLASSES; j++)
- if (i != j)
- {
- enum reg_class *p;
-
- COPY_HARD_REG_SET (temp_hard_regset2, reg_class_contents[j]);
- AND_COMPL_HARD_REG_SET (temp_hard_regset2, no_unit_alloc_regs);
- if (! hard_reg_set_subset_p (temp_hard_regset,
- temp_hard_regset2))
+ /* Remove so far added pressure classes which are subset of the
+ current candidate class. Prefer GENERAL_REGS as a pressure
+ register class to another class containing the same
+ allocatable hard registers. We do this because machine
+ dependent cost hooks might give wrong costs for the latter
+ class but always give the right cost for the former class
+ (GENERAL_REGS). */
+ for (i = 0; i < n; i++)
+ {
+ cl2 = pressure_classes[i];
+ COPY_HARD_REG_SET (temp_hard_regset2, reg_class_contents[cl2]);
+ AND_COMPL_HARD_REG_SET (temp_hard_regset2, no_unit_alloc_regs);
+ if (hard_reg_set_subset_p (temp_hard_regset, temp_hard_regset2)
+ && (! hard_reg_set_equal_p (temp_hard_regset, temp_hard_regset2)
+ || cl2 == (int) GENERAL_REGS))
+ {
+ pressure_classes[curr++] = (enum reg_class) cl2;
+ insert_p = false;
continue;
- p = &alloc_reg_class_subclasses[j][0];
- while (*p != LIM_REG_CLASSES) p++;
- *p = (enum reg_class) i;
+ }
+ if (hard_reg_set_subset_p (temp_hard_regset2, temp_hard_regset)
+ && (! hard_reg_set_equal_p (temp_hard_regset2, temp_hard_regset)
+ || cl == (int) GENERAL_REGS))
+ continue;
+ if (hard_reg_set_equal_p (temp_hard_regset2, temp_hard_regset))
+ insert_p = false;
+ pressure_classes[curr++] = (enum reg_class) cl2;
+ }
+ /* If the current candidate is a subset of a so far added
+ pressure class, don't add it to the list of the pressure
+ classes. */
+ if (insert_p)
+ pressure_classes[curr++] = (enum reg_class) cl;
+ n = curr;
+ }
+#ifdef ENABLE_IRA_CHECKING
+ {
+ HARD_REG_SET ignore_hard_regs;
+
+ /* Check pressure classes correctness: here we check that hard
+ registers from all register pressure classes contains all hard
+ registers available for the allocation. */
+ CLEAR_HARD_REG_SET (temp_hard_regset);
+ CLEAR_HARD_REG_SET (temp_hard_regset2);
+ COPY_HARD_REG_SET (ignore_hard_regs, no_unit_alloc_regs);
+ for (cl = 0; cl < LIM_REG_CLASSES; cl++)
+ {
+ /* For some targets (like MIPS with MD_REGS), there are some
+ classes with hard registers available for allocation but
+ not able to hold value of any mode. */
+ for (m = 0; m < NUM_MACHINE_MODES; m++)
+ if (contains_reg_of_mode[cl][m])
+ break;
+ if (m >= NUM_MACHINE_MODES)
+ {
+ IOR_HARD_REG_SET (ignore_hard_regs, reg_class_contents[cl]);
+ continue;
}
+ for (i = 0; i < n; i++)
+ if ((int) pressure_classes[i] == cl)
+ break;
+ IOR_HARD_REG_SET (temp_hard_regset2, reg_class_contents[cl]);
+ if (i < n)
+ IOR_HARD_REG_SET (temp_hard_regset, reg_class_contents[cl]);
+ }
+ for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
+ /* Some targets (like SPARC with ICC reg) have alocatable regs
+ for which no reg class is defined. */
+ if (REGNO_REG_CLASS (i) == NO_REGS)
+ SET_HARD_REG_BIT (ignore_hard_regs, i);
+ AND_COMPL_HARD_REG_SET (temp_hard_regset, ignore_hard_regs);
+ AND_COMPL_HARD_REG_SET (temp_hard_regset2, ignore_hard_regs);
+ ira_assert (hard_reg_set_subset_p (temp_hard_regset2, temp_hard_regset));
+ }
+#endif
+ ira_pressure_classes_num = 0;
+ for (i = 0; i < n; i++)
+ {
+ cl = (int) pressure_classes[i];
+ ira_reg_pressure_class_p[cl] = true;
+ ira_pressure_classes[ira_pressure_classes_num++] = (enum reg_class) cl;
}
-}
-
-\f
-
-/* Set the four global variables defined above. */
+ setup_stack_reg_pressure_class ();
+}
+
+/* Set up IRA_ALLOCNO_CLASSES, IRA_ALLOCNO_CLASSES_NUM,
+ IRA_IMPORTANT_CLASSES, and IRA_IMPORTANT_CLASSES_NUM.
+
+ Target may have many subtargets and not all target hard regiters can
+ be used for allocation, e.g. x86 port in 32-bit mode can not use
+ hard registers introduced in x86-64 like r8-r15). Some classes
+ might have the same allocatable hard registers, e.g. INDEX_REGS
+ and GENERAL_REGS in x86 port in 32-bit mode. To decrease different
+ calculations efforts we introduce allocno classes which contain
+ unique non-empty sets of allocatable hard-registers.
+
+ Pseudo class cost calculation in ira-costs.c is very expensive.
+ Therefore we are trying to decrease number of classes involved in
+ such calculation. Register classes used in the cost calculation
+ are called important classes. They are allocno classes and other
+ non-empty classes whose allocatable hard register sets are inside
+ of an allocno class hard register set. From the first sight, it
+ looks like that they are just allocno classes. It is not true. In
+ example of x86-port in 32-bit mode, allocno classes will contain
+ GENERAL_REGS but not LEGACY_REGS (because allocatable hard
+ registers are the same for the both classes). The important
+ classes will contain GENERAL_REGS and LEGACY_REGS. It is done
+ because a machine description insn constraint may refers for
+ LEGACY_REGS and code in ira-costs.c is mostly base on investigation
+ of the insn constraints. */
static void
-setup_cover_and_important_classes (void)
+setup_allocno_and_important_classes (void)
{
int i, j, n, cl;
bool set_p;
- const reg_class_t *cover_classes;
HARD_REG_SET temp_hard_regset2;
static enum reg_class classes[LIM_REG_CLASSES + 1];
- if (targetm.ira_cover_classes == NULL)
- cover_classes = NULL;
- else
- cover_classes = targetm.ira_cover_classes ();
- if (cover_classes == NULL)
- ira_assert (flag_ira_algorithm == IRA_ALGORITHM_PRIORITY);
- else
- {
- for (i = 0; (cl = cover_classes[i]) != LIM_REG_CLASSES; i++)
- classes[i] = (enum reg_class) cl;
- classes[i] = LIM_REG_CLASSES;
- }
-
- if (flag_ira_algorithm == IRA_ALGORITHM_PRIORITY)
+ n = 0;
+ /* Collect classes which contain unique sets of allocatable hard
+ registers. Prefer GENERAL_REGS to other classes containing the
+ same set of hard registers. */
+ for (i = 0; i < LIM_REG_CLASSES; i++)
{
- n = 0;
- for (i = 0; i <= LIM_REG_CLASSES; i++)
+ COPY_HARD_REG_SET (temp_hard_regset, reg_class_contents[i]);
+ AND_COMPL_HARD_REG_SET (temp_hard_regset, no_unit_alloc_regs);
+ for (j = 0; j < n; j++)
{
- if (i == NO_REGS)
- continue;
-#ifdef CONSTRAINT_NUM_DEFINED_P
- for (j = 0; j < CONSTRAINT__LIMIT; j++)
- if ((int) REG_CLASS_FOR_CONSTRAINT ((enum constraint_num) j) == i)
- break;
- if (j < CONSTRAINT__LIMIT)
- {
- classes[n++] = (enum reg_class) i;
- continue;
- }
-#endif
- COPY_HARD_REG_SET (temp_hard_regset, reg_class_contents[i]);
- AND_COMPL_HARD_REG_SET (temp_hard_regset, no_unit_alloc_regs);
- for (j = 0; j < LIM_REG_CLASSES; j++)
- {
- if (i == j)
- continue;
- COPY_HARD_REG_SET (temp_hard_regset2, reg_class_contents[j]);
- AND_COMPL_HARD_REG_SET (temp_hard_regset2,
- no_unit_alloc_regs);
- if (hard_reg_set_equal_p (temp_hard_regset,
- temp_hard_regset2))
- break;
- }
- if (j >= i)
- classes[n++] = (enum reg_class) i;
+ cl = classes[j];
+ COPY_HARD_REG_SET (temp_hard_regset2, reg_class_contents[cl]);
+ AND_COMPL_HARD_REG_SET (temp_hard_regset2,
+ no_unit_alloc_regs);
+ if (hard_reg_set_equal_p (temp_hard_regset,
+ temp_hard_regset2))
+ break;
}
- classes[n] = LIM_REG_CLASSES;
+ if (j >= n)
+ classes[n++] = (enum reg_class) i;
+ else if (i == GENERAL_REGS)
+ /* Prefer general regs. For i386 example, it means that
+ we prefer GENERAL_REGS over INDEX_REGS or LEGACY_REGS
+ (all of them consists of the same available hard
+ registers). */
+ classes[j] = (enum reg_class) i;
}
+ classes[n] = LIM_REG_CLASSES;
- ira_reg_class_cover_size = 0;
+ /* Set up classes which can be used for allocnos as classes
+ conatining non-empty unique sets of allocatable hard
+ registers. */
+ ira_allocno_classes_num = 0;
for (i = 0; (cl = classes[i]) != LIM_REG_CLASSES; i++)
{
- for (j = 0; j < i; j++)
- if (flag_ira_algorithm != IRA_ALGORITHM_PRIORITY
- && reg_classes_intersect_p ((enum reg_class) cl, classes[j]))
- gcc_unreachable ();
COPY_HARD_REG_SET (temp_hard_regset, reg_class_contents[cl]);
AND_COMPL_HARD_REG_SET (temp_hard_regset, no_unit_alloc_regs);
- if (! hard_reg_set_empty_p (temp_hard_regset))
- ira_reg_class_cover[ira_reg_class_cover_size++] = (enum reg_class) cl;
+ if (hard_reg_set_empty_p (temp_hard_regset))
+ continue;
+ ira_allocno_classes[ira_allocno_classes_num++] = (enum reg_class) cl;
}
ira_important_classes_num = 0;
+ /* Add non-allocno classes containing to non-empty set of
+ allocatable hard regs. */
for (cl = 0; cl < N_REG_CLASSES; cl++)
{
COPY_HARD_REG_SET (temp_hard_regset, reg_class_contents[cl]);
if (! hard_reg_set_empty_p (temp_hard_regset))
{
set_p = false;
- for (j = 0; j < ira_reg_class_cover_size; j++)
+ for (j = 0; j < ira_allocno_classes_num; j++)
{
- COPY_HARD_REG_SET (temp_hard_regset, reg_class_contents[cl]);
- AND_COMPL_HARD_REG_SET (temp_hard_regset, no_unit_alloc_regs);
COPY_HARD_REG_SET (temp_hard_regset2,
- reg_class_contents[ira_reg_class_cover[j]]);
+ reg_class_contents[ira_allocno_classes[j]]);
AND_COMPL_HARD_REG_SET (temp_hard_regset2, no_unit_alloc_regs);
- if ((enum reg_class) cl == ira_reg_class_cover[j]
- || hard_reg_set_equal_p (temp_hard_regset,
- temp_hard_regset2))
+ if ((enum reg_class) cl == ira_allocno_classes[j])
break;
else if (hard_reg_set_subset_p (temp_hard_regset,
temp_hard_regset2))
set_p = true;
}
- if (set_p && j >= ira_reg_class_cover_size)
+ if (set_p && j >= ira_allocno_classes_num)
ira_important_classes[ira_important_classes_num++]
= (enum reg_class) cl;
}
}
- for (j = 0; j < ira_reg_class_cover_size; j++)
+ /* Now add allocno classes to the important classes. */
+ for (j = 0; j < ira_allocno_classes_num; j++)
ira_important_classes[ira_important_classes_num++]
- = ira_reg_class_cover[j];
-}
-
-/* Set up array IRA_CLASS_TRANSLATE. */
+ = ira_allocno_classes[j];
+ for (cl = 0; cl < N_REG_CLASSES; cl++)
+ {
+ ira_reg_allocno_class_p[cl] = false;
+ ira_reg_pressure_class_p[cl] = false;
+ }
+ for (j = 0; j < ira_allocno_classes_num; j++)
+ ira_reg_allocno_class_p[ira_allocno_classes[j]] = true;
+ setup_pressure_classes ();
+}
+
+/* Setup translation in CLASS_TRANSLATE of all classes into a class
+ given by array CLASSES of length CLASSES_NUM. The function is used
+ make translation any reg class to an allocno class or to an
+ pressure class. This translation is necessary for some
+ calculations when we can use only allocno or pressure classes and
+ such translation represents an approximate representation of all
+ classes.
+
+ The translation in case when allocatable hard register set of a
+ given class is subset of allocatable hard register set of a class
+ in CLASSES is pretty simple. We use smallest classes from CLASSES
+ containing a given class. If allocatable hard register set of a
+ given class is not a subset of any corresponding set of a class
+ from CLASSES, we use the cheapest (with load/store point of view)
+ class from CLASSES whose set intersects with given class set */
static void
-setup_class_translate (void)
+setup_class_translate_array (enum reg_class *class_translate,
+ int classes_num, enum reg_class *classes)
{
int cl, mode;
- enum reg_class cover_class, best_class, *cl_ptr;
+ enum reg_class aclass, best_class, *cl_ptr;
int i, cost, min_cost, best_cost;
for (cl = 0; cl < N_REG_CLASSES; cl++)
- ira_class_translate[cl] = NO_REGS;
+ class_translate[cl] = NO_REGS;
- if (flag_ira_algorithm == IRA_ALGORITHM_PRIORITY)
- for (cl = 0; cl < LIM_REG_CLASSES; cl++)
- {
- COPY_HARD_REG_SET (temp_hard_regset, reg_class_contents[cl]);
- AND_COMPL_HARD_REG_SET (temp_hard_regset, no_unit_alloc_regs);
- for (i = 0; i < ira_reg_class_cover_size; i++)
- {
- HARD_REG_SET temp_hard_regset2;
-
- cover_class = ira_reg_class_cover[i];
- COPY_HARD_REG_SET (temp_hard_regset2,
- reg_class_contents[cover_class]);
- AND_COMPL_HARD_REG_SET (temp_hard_regset2, no_unit_alloc_regs);
- if (hard_reg_set_equal_p (temp_hard_regset, temp_hard_regset2))
- ira_class_translate[cl] = cover_class;
- }
- }
- for (i = 0; i < ira_reg_class_cover_size; i++)
+ for (i = 0; i < classes_num; i++)
{
- cover_class = ira_reg_class_cover[i];
- if (flag_ira_algorithm != IRA_ALGORITHM_PRIORITY)
- for (cl_ptr = &alloc_reg_class_subclasses[cover_class][0];
- (cl = *cl_ptr) != LIM_REG_CLASSES;
- cl_ptr++)
- {
- if (ira_class_translate[cl] == NO_REGS)
- ira_class_translate[cl] = cover_class;
-#ifdef ENABLE_IRA_CHECKING
- else
- {
- COPY_HARD_REG_SET (temp_hard_regset, reg_class_contents[cl]);
- AND_COMPL_HARD_REG_SET (temp_hard_regset, no_unit_alloc_regs);
- if (! hard_reg_set_empty_p (temp_hard_regset))
- gcc_unreachable ();
- }
-#endif
- }
- ira_class_translate[cover_class] = cover_class;
+ aclass = classes[i];
+ for (cl_ptr = &alloc_reg_class_subclasses[aclass][0];
+ (cl = *cl_ptr) != LIM_REG_CLASSES;
+ cl_ptr++)
+ if (class_translate[cl] == NO_REGS)
+ class_translate[cl] = aclass;
+ class_translate[aclass] = aclass;
}
- /* For classes which are not fully covered by a cover class (in
- other words covered by more one cover class), use the cheapest
- cover class. */
+ /* For classes which are not fully covered by one of given classes
+ (in other words covered by more one given class), use the
+ cheapest class. */
for (cl = 0; cl < N_REG_CLASSES; cl++)
{
- if (cl == NO_REGS || ira_class_translate[cl] != NO_REGS)
+ if (cl == NO_REGS || class_translate[cl] != NO_REGS)
continue;
best_class = NO_REGS;
best_cost = INT_MAX;
- for (i = 0; i < ira_reg_class_cover_size; i++)
+ for (i = 0; i < classes_num; i++)
{
- cover_class = ira_reg_class_cover[i];
+ aclass = classes[i];
COPY_HARD_REG_SET (temp_hard_regset,
- reg_class_contents[cover_class]);
+ reg_class_contents[aclass]);
AND_HARD_REG_SET (temp_hard_regset, reg_class_contents[cl]);
AND_COMPL_HARD_REG_SET (temp_hard_regset, no_unit_alloc_regs);
if (! hard_reg_set_empty_p (temp_hard_regset))
}
if (best_class == NO_REGS || best_cost > min_cost)
{
- best_class = cover_class;
+ best_class = aclass;
best_cost = min_cost;
}
}
}
- ira_class_translate[cl] = best_class;
+ class_translate[cl] = best_class;
}
}
-/* Order numbers of cover classes in original target cover class
- array, -1 for non-cover classes. This is only live during
- reorder_important_classes. */
-static int cover_class_order[N_REG_CLASSES];
+/* Set up array IRA_ALLOCNO_CLASS_TRANSLATE and
+ IRA_PRESSURE_CLASS_TRANSLATE. */
+static void
+setup_class_translate (void)
+{
+ setup_class_translate_array (ira_allocno_class_translate,
+ ira_allocno_classes_num, ira_allocno_classes);
+ setup_class_translate_array (ira_pressure_class_translate,
+ ira_pressure_classes_num, ira_pressure_classes);
+}
+
+/* Order numbers of allocno classes in original target allocno class
+ array, -1 for non-allocno classes. */
+static int allocno_class_order[N_REG_CLASSES];
/* The function used to sort the important classes. */
static int
{
enum reg_class cl1 = *(const enum reg_class *) v1p;
enum reg_class cl2 = *(const enum reg_class *) v2p;
+ enum reg_class tcl1, tcl2;
int diff;
- cl1 = ira_class_translate[cl1];
- cl2 = ira_class_translate[cl2];
- if (cl1 != NO_REGS && cl2 != NO_REGS
- && (diff = cover_class_order[cl1] - cover_class_order[cl2]) != 0)
+ tcl1 = ira_allocno_class_translate[cl1];
+ tcl2 = ira_allocno_class_translate[cl2];
+ if (tcl1 != NO_REGS && tcl2 != NO_REGS
+ && (diff = allocno_class_order[tcl1] - allocno_class_order[tcl2]) != 0)
return diff;
return (int) cl1 - (int) cl2;
}
-/* Reorder important classes according to the order of their cover
- classes. */
+/* For correct work of function setup_reg_class_relation we need to
+ reorder important classes according to the order of their allocno
+ classes. It places important classes containing the same
+ allocatable hard register set adjacent to each other and allocno
+ class with the allocatable hard register set right after the other
+ important classes with the same set.
+
+ In example from comments of function
+ setup_allocno_and_important_classes, it places LEGACY_REGS and
+ GENERAL_REGS close to each other and GENERAL_REGS is after
+ LEGACY_REGS. */
static void
reorder_important_classes (void)
{
int i;
for (i = 0; i < N_REG_CLASSES; i++)
- cover_class_order[i] = -1;
- for (i = 0; i < ira_reg_class_cover_size; i++)
- cover_class_order[ira_reg_class_cover[i]] = i;
+ allocno_class_order[i] = -1;
+ for (i = 0; i < ira_allocno_classes_num; i++)
+ allocno_class_order[ira_allocno_classes[i]] = i;
qsort (ira_important_classes, ira_important_classes_num,
sizeof (enum reg_class), comp_reg_classes_func);
+ for (i = 0; i < ira_important_classes_num; i++)
+ ira_important_class_nums[ira_important_classes[i]] = i;
}
-/* Set up the above reg class relations. */
+/* Set up IRA_REG_CLASS_SUBUNION, IRA_REG_CLASS_SUPERUNION,
+ IRA_REG_CLASS_SUPER_CLASSES, IRA_REG_CLASSES_INTERSECT, and
+ IRA_REG_CLASSES_INTERSECT_P. For the meaning of the relations,
+ please see corresponding comments in ira-int.h. */
static void
setup_reg_class_relations (void)
{
if (hard_reg_set_empty_p (temp_hard_regset)
&& hard_reg_set_empty_p (temp_set2))
{
+ /* The both classes have no allocatable hard registers
+ -- take all class hard registers into account and use
+ reg_class_subunion and reg_class_superunion. */
for (i = 0;; i++)
{
cl3 = reg_class_subclasses[cl1][i];
(enum reg_class) cl3))
ira_reg_class_intersect[cl1][cl2] = (enum reg_class) cl3;
}
- ira_reg_class_union[cl1][cl2] = reg_class_subunion[cl1][cl2];
+ ira_reg_class_subunion[cl1][cl2] = reg_class_subunion[cl1][cl2];
+ ira_reg_class_superunion[cl1][cl2] = reg_class_superunion[cl1][cl2];
continue;
}
ira_reg_classes_intersect_p[cl1][cl2]
if (important_class_p[cl1] && important_class_p[cl2]
&& hard_reg_set_subset_p (temp_hard_regset, temp_set2))
{
+ /* CL1 and CL2 are important classes and CL1 allocatable
+ hard register set is inside of CL2 allocatable hard
+ registers -- make CL1 a superset of CL2. */
enum reg_class *p;
p = &ira_reg_class_super_classes[cl1][0];
*p++ = (enum reg_class) cl2;
*p = LIM_REG_CLASSES;
}
- ira_reg_class_union[cl1][cl2] = NO_REGS;
+ ira_reg_class_subunion[cl1][cl2] = NO_REGS;
+ ira_reg_class_superunion[cl1][cl2] = NO_REGS;
COPY_HARD_REG_SET (intersection_set, reg_class_contents[cl1]);
AND_HARD_REG_SET (intersection_set, reg_class_contents[cl2]);
AND_COMPL_HARD_REG_SET (intersection_set, no_unit_alloc_regs);
AND_COMPL_HARD_REG_SET (temp_hard_regset, no_unit_alloc_regs);
if (hard_reg_set_subset_p (temp_hard_regset, intersection_set))
{
+ /* CL3 allocatable hard register set is inside of
+ intersection of allocatable hard register sets
+ of CL1 and CL2. */
COPY_HARD_REG_SET
(temp_set2,
reg_class_contents[(int)
ira_reg_class_intersect[cl1][cl2]]);
AND_COMPL_HARD_REG_SET (temp_set2, no_unit_alloc_regs);
if (! hard_reg_set_subset_p (temp_hard_regset, temp_set2)
- /* Ignore unavailable hard registers and prefer
- smallest class for debugging purposes. */
+ /* If the allocatable hard register sets are the
+ same, prefer GENERAL_REGS or the smallest
+ class for debugging purposes. */
|| (hard_reg_set_equal_p (temp_hard_regset, temp_set2)
- && hard_reg_set_subset_p
- (reg_class_contents[cl3],
- reg_class_contents
- [(int) ira_reg_class_intersect[cl1][cl2]])))
+ && (cl3 == GENERAL_REGS
+ || (ira_reg_class_intersect[cl1][cl2] != GENERAL_REGS
+ && hard_reg_set_subset_p
+ (reg_class_contents[cl3],
+ reg_class_contents
+ [(int) ira_reg_class_intersect[cl1][cl2]])))))
ira_reg_class_intersect[cl1][cl2] = (enum reg_class) cl3;
}
if (hard_reg_set_subset_p (temp_hard_regset, union_set))
{
+ /* CL3 allocatbale hard register set is inside of
+ union of allocatable hard register sets of CL1
+ and CL2. */
COPY_HARD_REG_SET
(temp_set2,
- reg_class_contents[(int) ira_reg_class_union[cl1][cl2]]);
+ reg_class_contents[(int) ira_reg_class_subunion[cl1][cl2]]);
AND_COMPL_HARD_REG_SET (temp_set2, no_unit_alloc_regs);
- if (ira_reg_class_union[cl1][cl2] == NO_REGS
+ if (ira_reg_class_subunion[cl1][cl2] == NO_REGS
|| (hard_reg_set_subset_p (temp_set2, temp_hard_regset)
+
+ && (! hard_reg_set_equal_p (temp_set2,
+ temp_hard_regset)
+ || cl3 == GENERAL_REGS
+ /* If the allocatable hard register sets are the
+ same, prefer GENERAL_REGS or the smallest
+ class for debugging purposes. */
+ || (ira_reg_class_subunion[cl1][cl2] != GENERAL_REGS
+ && hard_reg_set_subset_p
+ (reg_class_contents[cl3],
+ reg_class_contents
+ [(int) ira_reg_class_subunion[cl1][cl2]])))))
+ ira_reg_class_subunion[cl1][cl2] = (enum reg_class) cl3;
+ }
+ if (hard_reg_set_subset_p (union_set, temp_hard_regset))
+ {
+ /* CL3 allocatable hard register set contains union
+ of allocatable hard register sets of CL1 and
+ CL2. */
+ COPY_HARD_REG_SET
+ (temp_set2,
+ reg_class_contents[(int) ira_reg_class_superunion[cl1][cl2]]);
+ AND_COMPL_HARD_REG_SET (temp_set2, no_unit_alloc_regs);
+ if (ira_reg_class_superunion[cl1][cl2] == NO_REGS
+ || (hard_reg_set_subset_p (temp_hard_regset, temp_set2)
&& (! hard_reg_set_equal_p (temp_set2,
temp_hard_regset)
- /* Ignore unavailable hard registers and
- prefer smallest class for debugging
- purposes. */
- || hard_reg_set_subset_p
- (reg_class_contents[cl3],
- reg_class_contents
- [(int) ira_reg_class_union[cl1][cl2]]))))
- ira_reg_class_union[cl1][cl2] = (enum reg_class) cl3;
+ || cl3 == GENERAL_REGS
+ /* If the allocatable hard register sets are the
+ same, prefer GENERAL_REGS or the smallest
+ class for debugging purposes. */
+ || (ira_reg_class_superunion[cl1][cl2] != GENERAL_REGS
+ && hard_reg_set_subset_p
+ (reg_class_contents[cl3],
+ reg_class_contents
+ [(int) ira_reg_class_superunion[cl1][cl2]])))))
+ ira_reg_class_superunion[cl1][cl2] = (enum reg_class) cl3;
}
}
}
}
}
-/* Output all cover classes and the translation map into file F. */
+/* Output all possible allocno classes and the translation map into
+ file F. */
static void
-print_class_cover (FILE *f)
-{
+print_classes (FILE *f, bool pressure_p)
+{
+ int classes_num = (pressure_p
+ ? ira_pressure_classes_num : ira_allocno_classes_num);
+ enum reg_class *classes = (pressure_p
+ ? ira_pressure_classes : ira_allocno_classes);
+ enum reg_class *class_translate = (pressure_p
+ ? ira_pressure_class_translate
+ : ira_allocno_class_translate);
static const char *const reg_class_names[] = REG_CLASS_NAMES;
int i;
- fprintf (f, "Class cover:\n");
- for (i = 0; i < ira_reg_class_cover_size; i++)
- fprintf (f, " %s", reg_class_names[ira_reg_class_cover[i]]);
+ fprintf (f, "%s classes:\n", pressure_p ? "Pressure" : "Allocno");
+ for (i = 0; i < classes_num; i++)
+ fprintf (f, " %s", reg_class_names[classes[i]]);
fprintf (f, "\nClass translation:\n");
for (i = 0; i < N_REG_CLASSES; i++)
fprintf (f, " %s -> %s\n", reg_class_names[i],
- reg_class_names[ira_class_translate[i]]);
+ reg_class_names[class_translate[i]]);
}
-/* Output all cover classes and the translation map into
- stderr. */
+/* Output all possible allocno and translation classes and the
+ translation maps into stderr. */
void
-ira_debug_class_cover (void)
+ira_debug_allocno_classes (void)
{
- print_class_cover (stderr);
+ print_classes (stderr, false);
+ print_classes (stderr, true);
}
-/* Set up different arrays concerning class subsets, cover and
+/* Set up different arrays concerning class subsets, allocno and
important classes. */
static void
-find_reg_class_closure (void)
+find_reg_classes (void)
{
- setup_reg_subclasses ();
- setup_cover_and_important_classes ();
+ setup_allocno_and_important_classes ();
setup_class_translate ();
reorder_important_classes ();
setup_reg_class_relations ();
/* Set up the array above. */
static void
-setup_hard_regno_cover_class (void)
+setup_hard_regno_aclass (void)
{
- int i, j;
- enum reg_class cl;
+ int i;
for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
{
- ira_hard_regno_cover_class[i] = NO_REGS;
- for (j = 0; j < ira_reg_class_cover_size; j++)
- {
- cl = ira_reg_class_cover[j];
- if (ira_class_hard_reg_index[cl][i] >= 0)
- {
- ira_hard_regno_cover_class[i] = cl;
- break;
- }
- }
-
+#if 1
+ ira_hard_regno_allocno_class[i]
+ = (TEST_HARD_REG_BIT (no_unit_alloc_regs, i)
+ ? NO_REGS
+ : ira_allocno_class_translate[REGNO_REG_CLASS (i)]);
+#else
+ int j;
+ enum reg_class cl;
+ ira_hard_regno_allocno_class[i] = NO_REGS;
+ for (j = 0; j < ira_allocno_classes_num; j++)
+ {
+ cl = ira_allocno_classes[j];
+ if (ira_class_hard_reg_index[cl][i] >= 0)
+ {
+ ira_hard_regno_allocno_class[i] = cl;
+ break;
+ }
+ }
+#endif
}
}
\f
-/* Form IRA_REG_CLASS_NREGS map. */
+/* Form IRA_REG_CLASS_MAX_NREGS and IRA_REG_CLASS_MIN_NREGS maps. */
static void
setup_reg_class_nregs (void)
{
- int cl, m;
+ int i, cl, cl2, m;
- for (cl = 0; cl < N_REG_CLASSES; cl++)
- for (m = 0; m < MAX_MACHINE_MODE; m++)
- ira_reg_class_nregs[cl][m] = CLASS_MAX_NREGS ((enum reg_class) cl,
- (enum machine_mode) m);
+ for (m = 0; m < MAX_MACHINE_MODE; m++)
+ {
+ for (cl = 0; cl < N_REG_CLASSES; cl++)
+ ira_reg_class_max_nregs[cl][m]
+ = ira_reg_class_min_nregs[cl][m]
+ = targetm.class_max_nregs ((reg_class_t) cl, (enum machine_mode) m);
+ for (cl = 0; cl < N_REG_CLASSES; cl++)
+ for (i = 0;
+ (cl2 = alloc_reg_class_subclasses[cl][i]) != LIM_REG_CLASSES;
+ i++)
+ if (ira_reg_class_min_nregs[cl2][m]
+ < ira_reg_class_min_nregs[cl][m])
+ ira_reg_class_min_nregs[cl][m] = ira_reg_class_min_nregs[cl2][m];
+ }
}
\f
-/* Set up PROHIBITED_CLASS_MODE_REGS. */
+/* Set up IRA_PROHIBITED_CLASS_MODE_REGS. */
static void
setup_prohibited_class_mode_regs (void)
{
- int i, j, k, hard_regno;
- enum reg_class cl;
+ int j, k, hard_regno, cl;
- for (i = 0; i < ira_reg_class_cover_size; i++)
+ for (cl = (int) N_REG_CLASSES - 1; cl >= 0; cl--)
{
- cl = ira_reg_class_cover[i];
for (j = 0; j < NUM_MACHINE_MODES; j++)
{
- CLEAR_HARD_REG_SET (prohibited_class_mode_regs[cl][j]);
+ CLEAR_HARD_REG_SET (ira_prohibited_class_mode_regs[cl][j]);
for (k = ira_class_hard_regs_num[cl] - 1; k >= 0; k--)
{
hard_regno = ira_class_hard_regs[cl][k];
if (! HARD_REGNO_MODE_OK (hard_regno, (enum machine_mode) j))
- SET_HARD_REG_BIT (prohibited_class_mode_regs[cl][j],
+ SET_HARD_REG_BIT (ira_prohibited_class_mode_regs[cl][j],
hard_regno);
}
}
}
}
+/* Clarify IRA_PROHIBITED_CLASS_MODE_REGS by excluding hard registers
+ spanning from one register pressure class to another one. It is
+ called after defining the pressure classes. */
+static void
+clarify_prohibited_class_mode_regs (void)
+{
+ int j, k, hard_regno, cl, pclass, nregs;
+
+ for (cl = (int) N_REG_CLASSES - 1; cl >= 0; cl--)
+ for (j = 0; j < NUM_MACHINE_MODES; j++)
+ for (k = ira_class_hard_regs_num[cl] - 1; k >= 0; k--)
+ {
+ hard_regno = ira_class_hard_regs[cl][k];
+ if (TEST_HARD_REG_BIT (ira_prohibited_class_mode_regs[cl][j], hard_regno))
+ continue;
+ nregs = hard_regno_nregs[hard_regno][j];
+ if (hard_regno + nregs > FIRST_PSEUDO_REGISTER)
+ {
+ SET_HARD_REG_BIT (ira_prohibited_class_mode_regs[cl][j],
+ hard_regno);
+ continue;
+ }
+ pclass = ira_pressure_class_translate[REGNO_REG_CLASS (hard_regno)];
+ for (nregs-- ;nregs >= 0; nregs--)
+ if (((enum reg_class) pclass
+ != ira_pressure_class_translate[REGNO_REG_CLASS
+ (hard_regno + nregs)]))
+ {
+ SET_HARD_REG_BIT (ira_prohibited_class_mode_regs[cl][j],
+ hard_regno);
+ break;
+ }
+ }
+}
+
\f
/* Allocate and initialize IRA_REGISTER_MOVE_COST,
- IRA_MAY_MOVE_IN_COST, and IRA_MAY_MOVE_OUT_COST for MODE if it is
- not done yet. */
+ IRA_MAX_REGISTER_MOVE_COST, IRA_MAY_MOVE_IN_COST,
+ IRA_MAY_MOVE_OUT_COST, IRA_MAX_MAY_MOVE_IN_COST, and
+ IRA_MAX_MAY_MOVE_OUT_COST for MODE if it is not done yet. */
void
ira_init_register_move_cost (enum machine_mode mode)
{
- int cl1, cl2;
+ int cl1, cl2, cl3;
ira_assert (ira_register_move_cost[mode] == NULL
+ && ira_max_register_move_cost[mode] == NULL
&& ira_may_move_in_cost[mode] == NULL
- && ira_may_move_out_cost[mode] == NULL);
+ && ira_may_move_out_cost[mode] == NULL
+ && ira_max_may_move_in_cost[mode] == NULL
+ && ira_max_may_move_out_cost[mode] == NULL);
if (move_cost[mode] == NULL)
init_move_cost (mode);
ira_register_move_cost[mode] = move_cost[mode];
/* Don't use ira_allocate because the tables exist out of scope of a
IRA call. */
+ ira_max_register_move_cost[mode]
+ = (move_table *) xmalloc (sizeof (move_table) * N_REG_CLASSES);
+ memcpy (ira_max_register_move_cost[mode], ira_register_move_cost[mode],
+ sizeof (move_table) * N_REG_CLASSES);
+ for (cl1 = 0; cl1 < N_REG_CLASSES; cl1++)
+ {
+ /* Some subclasses are to small to have enough registers to hold
+ a value of MODE. Just ignore them. */
+ if (ira_reg_class_max_nregs[cl1][mode] > ira_available_class_regs[cl1])
+ continue;
+ COPY_HARD_REG_SET (temp_hard_regset, reg_class_contents[cl1]);
+ AND_COMPL_HARD_REG_SET (temp_hard_regset, no_unit_alloc_regs);
+ if (hard_reg_set_empty_p (temp_hard_regset))
+ continue;
+ for (cl2 = 0; cl2 < N_REG_CLASSES; cl2++)
+ if (hard_reg_set_subset_p (reg_class_contents[cl1],
+ reg_class_contents[cl2]))
+ for (cl3 = 0; cl3 < N_REG_CLASSES; cl3++)
+ {
+ if (ira_max_register_move_cost[mode][cl2][cl3]
+ < ira_register_move_cost[mode][cl1][cl3])
+ ira_max_register_move_cost[mode][cl2][cl3]
+ = ira_register_move_cost[mode][cl1][cl3];
+ if (ira_max_register_move_cost[mode][cl3][cl2]
+ < ira_register_move_cost[mode][cl3][cl1])
+ ira_max_register_move_cost[mode][cl3][cl2]
+ = ira_register_move_cost[mode][cl3][cl1];
+ }
+ }
ira_may_move_in_cost[mode]
= (move_table *) xmalloc (sizeof (move_table) * N_REG_CLASSES);
memcpy (ira_may_move_in_cost[mode], may_move_in_cost[mode],
= (move_table *) xmalloc (sizeof (move_table) * N_REG_CLASSES);
memcpy (ira_may_move_out_cost[mode], may_move_out_cost[mode],
sizeof (move_table) * N_REG_CLASSES);
+ ira_max_may_move_in_cost[mode]
+ = (move_table *) xmalloc (sizeof (move_table) * N_REG_CLASSES);
+ memcpy (ira_max_may_move_in_cost[mode], ira_max_register_move_cost[mode],
+ sizeof (move_table) * N_REG_CLASSES);
+ ira_max_may_move_out_cost[mode]
+ = (move_table *) xmalloc (sizeof (move_table) * N_REG_CLASSES);
+ memcpy (ira_max_may_move_out_cost[mode], ira_max_register_move_cost[mode],
+ sizeof (move_table) * N_REG_CLASSES);
for (cl1 = 0; cl1 < N_REG_CLASSES; cl1++)
{
for (cl2 = 0; cl2 < N_REG_CLASSES; cl2++)
{
+ COPY_HARD_REG_SET (temp_hard_regset, reg_class_contents[cl2]);
+ AND_COMPL_HARD_REG_SET (temp_hard_regset, no_unit_alloc_regs);
+ if (hard_reg_set_empty_p (temp_hard_regset))
+ continue;
if (ira_class_subset_p[cl1][cl2])
ira_may_move_in_cost[mode][cl1][cl2] = 0;
if (ira_class_subset_p[cl2][cl1])
ira_may_move_out_cost[mode][cl1][cl2] = 0;
+ if (ira_class_subset_p[cl1][cl2])
+ ira_max_may_move_in_cost[mode][cl1][cl2] = 0;
+ if (ira_class_subset_p[cl2][cl1])
+ ira_max_may_move_out_cost[mode][cl1][cl2] = 0;
+ ira_register_move_cost[mode][cl1][cl2]
+ = ira_max_register_move_cost[mode][cl1][cl2];
+ ira_may_move_in_cost[mode][cl1][cl2]
+ = ira_max_may_move_in_cost[mode][cl1][cl2];
+ ira_may_move_out_cost[mode][cl1][cl2]
+ = ira_max_may_move_out_cost[mode][cl1][cl2];
}
}
}
for (mode = 0; mode < MAX_MACHINE_MODE; mode++)
{
ira_register_move_cost[mode] = NULL;
+ ira_max_register_move_cost[mode] = NULL;
ira_may_move_in_cost[mode] = NULL;
ira_may_move_out_cost[mode] = NULL;
+ ira_max_may_move_in_cost[mode] = NULL;
+ ira_max_may_move_out_cost[mode] = NULL;
}
ira_init_costs_once ();
}
-/* Free ira_register_move_cost, ira_may_move_in_cost, and
- ira_may_move_out_cost for each mode. */
+/* Free ira_max_register_move_cost, ira_may_move_in_cost,
+ ira_may_move_out_cost, ira_max_may_move_in_cost, and
+ ira_max_may_move_out_cost for each mode. */
static void
free_register_move_costs (void)
{
for (mode = 0; mode < MAX_MACHINE_MODE; mode++)
{
- if (ira_may_move_in_cost[mode] != NULL)
- free (ira_may_move_in_cost[mode]);
- if (ira_may_move_out_cost[mode] != NULL)
- free (ira_may_move_out_cost[mode]);
+ free (ira_max_register_move_cost[mode]);
+ free (ira_may_move_in_cost[mode]);
+ free (ira_may_move_out_cost[mode]);
+ free (ira_max_may_move_in_cost[mode]);
+ free (ira_max_may_move_out_cost[mode]);
ira_register_move_cost[mode] = NULL;
+ ira_max_register_move_cost[mode] = NULL;
ira_may_move_in_cost[mode] = NULL;
ira_may_move_out_cost[mode] = NULL;
+ ira_max_may_move_in_cost[mode] = NULL;
+ ira_max_may_move_out_cost[mode] = NULL;
}
}
setup_reg_mode_hard_regset ();
setup_alloc_regs (flag_omit_frame_pointer != 0);
setup_class_subset_and_memory_move_costs ();
- find_reg_class_closure ();
- setup_hard_regno_cover_class ();
setup_reg_class_nregs ();
setup_prohibited_class_mode_regs ();
+ find_reg_classes ();
+ clarify_prohibited_class_mode_regs ();
+ setup_hard_regno_aclass ();
ira_init_costs ();
}
|| ira_bad_reload_regno_1 (regno, out));
}
-/* Function specific hard registers that can not be used for the
- register allocation. */
-HARD_REG_SET ira_no_alloc_regs;
-
/* Return TRUE if *LOC contains an asm. */
static int
insn_contains_asm_1 (rtx *loc, void *data ATTRIBUTE_UNUSED)
{
df_ref def = *def_rec;
unsigned int dregno = DF_REF_REGNO (def);
- if (dregno < FIRST_PSEUDO_REGISTER)
- {
- unsigned int i;
- enum machine_mode mode = GET_MODE (DF_REF_REAL_REG (def));
- unsigned int end = dregno
- + hard_regno_nregs[dregno][mode] - 1;
-
- for (i = dregno; i <= end; ++i)
- SET_HARD_REG_BIT(crtl->asm_clobbers, i);
- }
+ if (HARD_REGISTER_NUM_P (dregno))
+ add_to_hard_reg_set (&crtl->asm_clobbers,
+ GET_MODE (DF_REF_REAL_REG (def)),
+ dregno);
}
}
}
static void
find_reg_equiv_invariant_const (void)
{
- int i;
+ unsigned int i;
bool invariant_p;
rtx list, insn, note, constant, x;
- for (i = FIRST_PSEUDO_REGISTER; i < reg_equiv_init_size; i++)
+ for (i = FIRST_PSEUDO_REGISTER; i < VEC_length (reg_equivs_t, reg_equivs); i++)
{
constant = NULL_RTX;
invariant_p = false;
- for (list = reg_equiv_init[i]; list != NULL_RTX; list = XEXP (list, 1))
+ for (list = reg_equiv_init (i); list != NULL_RTX; list = XEXP (list, 1))
{
insn = XEXP (list, 0);
note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
ALLOCNO_ASSIGNED_P (a) = true;
ira_free_allocno_updated_costs (a);
hard_regno = ALLOCNO_HARD_REGNO (a);
- regno = (int) REGNO (ALLOCNO_REG (a));
+ regno = ALLOCNO_REGNO (a);
reg_renumber[regno] = (hard_regno < 0 ? -1 : hard_regno);
- if (hard_regno >= 0 && ALLOCNO_CALLS_CROSSED_NUM (a) != 0
- && ! ira_hard_reg_not_in_set_p (hard_regno, ALLOCNO_MODE (a),
- call_used_reg_set))
+ if (hard_regno >= 0)
{
- ira_assert (!optimize || flag_caller_saves
- || regno >= ira_reg_equiv_len
- || ira_reg_equiv_const[regno]
- || ira_reg_equiv_invariant_p[regno]);
- caller_save_needed = 1;
+ int i, nwords;
+ enum reg_class pclass;
+ ira_object_t obj;
+
+ pclass = ira_pressure_class_translate[REGNO_REG_CLASS (hard_regno)];
+ nwords = ALLOCNO_NUM_OBJECTS (a);
+ for (i = 0; i < nwords; i++)
+ {
+ obj = ALLOCNO_OBJECT (a, i);
+ IOR_COMPL_HARD_REG_SET (OBJECT_TOTAL_CONFLICT_HARD_REGS (obj),
+ reg_class_contents[pclass]);
+ }
+ if (ALLOCNO_CALLS_CROSSED_NUM (a) != 0
+ && ira_hard_reg_set_intersection_p (hard_regno, ALLOCNO_MODE (a),
+ call_used_reg_set))
+ {
+ ira_assert (!optimize || flag_caller_saves
+ || regno >= ira_reg_equiv_len
+ || ira_reg_equiv_const[regno]
+ || ira_reg_equiv_invariant_p[regno]);
+ caller_save_needed = 1;
+ }
}
}
}
allocnos because the cost info and info about intersected
calls are incorrect for them. */
ALLOCNO_ASSIGNED_P (a) = (hard_regno >= 0
- || ALLOCNO_MEM_OPTIMIZED_DEST_P (a)
+ || ALLOCNO_EMIT_DATA (a)->mem_optimized_dest_p
|| (ALLOCNO_MEMORY_COST (a)
- - ALLOCNO_COVER_CLASS_COST (a)) < 0);
- ira_assert (hard_regno < 0
- || ! ira_hard_reg_not_in_set_p (hard_regno, ALLOCNO_MODE (a),
- reg_class_contents
- [ALLOCNO_COVER_CLASS (a)]));
+ - ALLOCNO_CLASS_COST (a)) < 0);
+ ira_assert
+ (hard_regno < 0
+ || ira_hard_reg_in_set_p (hard_regno, ALLOCNO_MODE (a),
+ reg_class_contents[ALLOCNO_CLASS (a)]));
}
}
{
hard_regno = ALLOCNO_HARD_REGNO (a);
ira_assert (hard_regno < 0
- || ! ira_hard_reg_not_in_set_p
- (hard_regno, ALLOCNO_MODE (a),
- reg_class_contents[ALLOCNO_COVER_CLASS (a)]));
+ || (ira_hard_reg_in_set_p
+ (hard_regno, ALLOCNO_MODE (a),
+ reg_class_contents[ALLOCNO_CLASS (a)])));
if (hard_regno < 0)
{
cost = ALLOCNO_MEMORY_COST (a);
{
cost = (ALLOCNO_HARD_REG_COSTS (a)
[ira_class_hard_reg_index
- [ALLOCNO_COVER_CLASS (a)][hard_regno]]);
+ [ALLOCNO_CLASS (a)][hard_regno]]);
ira_reg_cost += cost;
}
else
{
- cost = ALLOCNO_COVER_CLASS_COST (a);
+ cost = ALLOCNO_CLASS_COST (a);
ira_reg_cost += cost;
}
ira_overall_cost += cost;
int this_regno = hard_regno;
if (n > 1)
{
- if (WORDS_BIG_ENDIAN)
+ if (REG_WORDS_BIG_ENDIAN)
this_regno += n - i - 1;
else
this_regno += i;
if (ALLOCNO_NUM_OBJECTS (conflict_a) > 1
&& conflict_nregs == ALLOCNO_NUM_OBJECTS (conflict_a))
{
- if (WORDS_BIG_ENDIAN)
+ if (REG_WORDS_BIG_ENDIAN)
conflict_hard_regno += (ALLOCNO_NUM_OBJECTS (conflict_a)
- OBJECT_SUBWORD (conflict_obj) - 1);
else
static void
fix_reg_equiv_init (void)
{
- int max_regno = max_reg_num ();
- int i, new_regno;
+ unsigned int max_regno = max_reg_num ();
+ int i, new_regno, max;
rtx x, prev, next, insn, set;
- if (reg_equiv_init_size < max_regno)
+ if (VEC_length (reg_equivs_t, reg_equivs) < max_regno)
{
- reg_equiv_init = GGC_RESIZEVEC (rtx, reg_equiv_init, max_regno);
- while (reg_equiv_init_size < max_regno)
- reg_equiv_init[reg_equiv_init_size++] = NULL_RTX;
- for (i = FIRST_PSEUDO_REGISTER; i < reg_equiv_init_size; i++)
- for (prev = NULL_RTX, x = reg_equiv_init[i]; x != NULL_RTX; x = next)
+ max = VEC_length (reg_equivs_t, reg_equivs);
+ grow_reg_equivs ();
+ for (i = FIRST_PSEUDO_REGISTER; i < max; i++)
+ for (prev = NULL_RTX, x = reg_equiv_init (i);
+ x != NULL_RTX;
+ x = next)
{
next = XEXP (x, 1);
insn = XEXP (x, 0);
else
{
if (prev == NULL_RTX)
- reg_equiv_init[i] = next;
+ reg_equiv_init (i) = next;
else
XEXP (prev, 1) = next;
- XEXP (x, 1) = reg_equiv_init[new_regno];
- reg_equiv_init[new_regno] = x;
+ XEXP (x, 1) = reg_equiv_init (new_regno);
+ reg_equiv_init (new_regno) = x;
}
}
}
ira_assert (i != old_regno);
setup_reg_classes (i, reg_preferred_class (old_regno),
reg_alternate_class (old_regno),
- reg_cover_class (old_regno));
+ reg_allocno_class (old_regno));
if (internal_flag_ira_verbose > 2 && ira_dump_file != NULL)
fprintf (ira_dump_file,
" New r%d: setting preferred %s, alternative %s\n",
too_high_register_pressure_p (void)
{
int i;
- enum reg_class cover_class;
+ enum reg_class pclass;
- for (i = 0; i < ira_reg_class_cover_size; i++)
+ for (i = 0; i < ira_pressure_classes_num; i++)
{
- cover_class = ira_reg_class_cover[i];
- if (ira_loop_tree_root->reg_pressure[cover_class] > 10000)
+ pclass = ira_pressure_classes[i];
+ if (ira_loop_tree_root->reg_pressure[pclass] > 10000)
return true;
}
return false;
if ((REG_P (dest)
&& reg_overlap_mentioned_p (dest, equiv_mem))
|| (MEM_P (dest)
- && true_dependence (dest, VOIDmode, equiv_mem, rtx_varies_p)))
+ && true_dependence (dest, VOIDmode, equiv_mem)))
equiv_mem_modified = 1;
}
if (find_reg_note (insn, REG_DEAD, reg))
return 1;
- if (CALL_P (insn) && ! MEM_READONLY_P (memref)
- && ! RTL_CONST_OR_PURE_CALL_P (insn))
+ /* This used to ignore readonly memory and const/pure calls. The problem
+ is the equivalent form may reference a pseudo which gets assigned a
+ call clobbered hard reg. When we later replace REG with its
+ equivalent form, the value in the call-clobbered reg has been
+ changed and all hell breaks loose. */
+ if (CALL_P (insn))
return 0;
note_stores (PATTERN (insn), validate_equiv_mem_from_store, NULL);
return 0;
case REG:
- return (reg_equiv[REGNO (x)].loop_depth >= reg_equiv[regno].loop_depth
- && reg_equiv[REGNO (x)].replace)
- || (REG_BASIC_BLOCK (REGNO (x)) < NUM_FIXED_BLOCKS && ! rtx_varies_p (x, 0));
+ return ((reg_equiv[REGNO (x)].loop_depth >= reg_equiv[regno].loop_depth
+ && reg_equiv[REGNO (x)].replace)
+ || (REG_BASIC_BLOCK (REGNO (x)) < NUM_FIXED_BLOCKS
+ && ! rtx_varies_p (x, 0)));
case UNSPEC_VOLATILE:
return 0;
return 1;
}
-/* TRUE if X uses any registers for which reg_equiv[REGNO].replace is true. */
+/* TRUE if X uses any registers for which reg_equiv[REGNO].replace is
+ true. */
static int
contains_replace_regs (rtx x)
{
reg_equiv[REGNO (x)].replacement));
case MEM:
- if (true_dependence (memref, VOIDmode, x, rtx_varies_p))
+ if (true_dependence (memref, VOIDmode, x))
return 1;
break;
assignment - a SET, CLOBBER or REG_INC note. It is currently not used,
but needs to be there because this function is called from note_stores. */
static void
-no_equiv (rtx reg, const_rtx store ATTRIBUTE_UNUSED, void *data ATTRIBUTE_UNUSED)
+no_equiv (rtx reg, const_rtx store ATTRIBUTE_UNUSED,
+ void *data ATTRIBUTE_UNUSED)
{
int regno;
rtx list;
should keep their initialization insns. */
if (reg_equiv[regno].is_arg_equivalence)
return;
- reg_equiv_init[regno] = NULL_RTX;
+ reg_equiv_init (regno) = NULL_RTX;
for (; list; list = XEXP (list, 1))
{
rtx insn = XEXP (list, 0);
static int recorded_label_ref;
/* Find registers that are equivalent to a single value throughout the
- compilation (either because they can be referenced in memory or are set once
- from a single constant). Lower their priority for a register.
+ compilation (either because they can be referenced in memory or are
+ set once from a single constant). Lower their priority for a
+ register.
- If such a register is only referenced once, try substituting its value
- into the using insn. If it succeeds, we can eliminate the register
- completely.
+ If such a register is only referenced once, try substituting its
+ value into the using insn. If it succeeds, we can eliminate the
+ register completely.
Initialize the REG_EQUIV_INIT array of initializing insns.
recorded_label_ref = 0;
reg_equiv = XCNEWVEC (struct equivalence, max_regno);
- reg_equiv_init = ggc_alloc_cleared_vec_rtx (max_regno);
- reg_equiv_init_size = max_regno;
+ grow_reg_equivs ();
init_alias_analysis ();
/* Record for reload that this is an equivalencing insn. */
if (rtx_equal_p (src, XEXP (note, 0)))
- reg_equiv_init[regno]
- = gen_rtx_INSN_LIST (VOIDmode, insn, reg_equiv_init[regno]);
+ reg_equiv_init (regno)
+ = gen_rtx_INSN_LIST (VOIDmode, insn, reg_equiv_init (regno));
/* Continue normally in case this is a candidate for
replacements. */
/* If we haven't done so, record for reload that this is an
equivalencing insn. */
if (!reg_equiv[regno].is_arg_equivalence)
- reg_equiv_init[regno]
- = gen_rtx_INSN_LIST (VOIDmode, insn, reg_equiv_init[regno]);
+ reg_equiv_init (regno)
+ = gen_rtx_INSN_LIST (VOIDmode, insn, reg_equiv_init (regno));
/* Record whether or not we created a REG_EQUIV note for a LABEL_REF.
We might end up substituting the LABEL_REF for uses of the
{
/* This insn makes the equivalence, not the one initializing
the register. */
- reg_equiv_init[regno]
+ reg_equiv_init (regno)
= gen_rtx_INSN_LIST (VOIDmode, insn, NULL_RTX);
df_notes_rescan (init_insn);
}
rtx equiv_insn;
if (! reg_equiv[regno].replace
- || reg_equiv[regno].loop_depth < loop_depth)
+ || reg_equiv[regno].loop_depth < loop_depth
+ /* There is no sense to move insns if we did
+ register pressure-sensitive scheduling was
+ done because it will not improve allocation
+ but worsen insn schedule with a big
+ probability. */
+ || (flag_sched_pressure && flag_schedule_insns))
continue;
/* reg_equiv[REGNO].replace gets set only when
reg_equiv[regno].init_insns
= XEXP (reg_equiv[regno].init_insns, 1);
- reg_equiv_init[regno] = NULL_RTX;
+ reg_equiv_init (regno) = NULL_RTX;
bitmap_set_bit (cleared_regs, regno);
}
/* Move the initialization of the register to just before
if (insn == BB_HEAD (bb))
BB_HEAD (bb) = PREV_INSN (insn);
- reg_equiv_init[regno]
+ reg_equiv_init (regno)
= gen_rtx_INSN_LIST (VOIDmode, new_insn, NULL_RTX);
bitmap_set_bit (cleared_regs, regno);
}
}
for (i = 0; i < (unsigned int) max_regno; i++)
- if (live_subregs[i])
- free (live_subregs[i]);
+ free (live_subregs[i]);
reload_insn_chain = c;
*p = NULL;
if (dump_file)
print_insn_chains (dump_file);
}
-\f
-/* Allocate memory for reg_equiv_memory_loc. */
-static void
-init_reg_equiv_memory_loc (void)
-{
- max_regno = max_reg_num ();
- /* And the reg_equiv_memory_loc array. */
- VEC_safe_grow (rtx, gc, reg_equiv_memory_loc_vec, max_regno);
- memset (VEC_address (rtx, reg_equiv_memory_loc_vec), 0,
- sizeof (rtx) * max_regno);
- reg_equiv_memory_loc = VEC_address (rtx, reg_equiv_memory_loc_vec);
-}
+\f
/* All natural loops. */
struct loops ira_loops;
mode or when the conflict table is too big. */
bool ira_conflicts_p;
+/* Saved between IRA and reload. */
+static int saved_flag_ira_share_spill_slots;
+
/* This is the main entry of IRA. */
static void
ira (FILE *f)
{
- int overall_cost_before, allocated_reg_info_size;
+ int allocated_reg_info_size;
bool loops_p;
int max_regno_before_ira, ira_max_point_before_emit;
int rebuild_p;
- int saved_flag_ira_share_spill_slots;
- basic_block bb;
-
- timevar_push (TV_IRA);
if (flag_caller_saves)
init_caller_save ();
{
timevar_push (TV_JUMP);
rebuild_jump_labels (get_insns ());
- purge_all_dead_edges ();
+ if (purge_all_dead_edges ())
+ delete_unreachable_blocks ();
timevar_pop (TV_JUMP);
}
}
ira_move_loops_num = ira_additional_jumps_num = 0;
ira_assert (current_loops == NULL);
- flow_loops_find (&ira_loops);
- record_loop_exits ();
- current_loops = &ira_loops;
-
- init_reg_equiv_memory_loc ();
+ if (flag_ira_region == IRA_REGION_ALL || flag_ira_region == IRA_REGION_MIXED)
+ {
+ flow_loops_find (&ira_loops);
+ record_loop_exits ();
+ current_loops = &ira_loops;
+ }
if (internal_flag_ira_verbose > 0 && ira_dump_file != NULL)
fprintf (ira_dump_file, "Building IRA IR\n");
- loops_p = ira_build (optimize
- && (flag_ira_region == IRA_REGION_ALL
- || flag_ira_region == IRA_REGION_MIXED));
+ loops_p = ira_build ();
ira_assert (ira_conflicts_p || !loops_p);
ira_max_point_before_emit = ira_max_point;
+ ira_initiate_emit_data ();
+
ira_emit (loops_p);
if (ira_conflicts_p)
}
}
+ ira_finish_emit_data ();
+
setup_reg_renumber ();
calculate_allocation_cost ();
check_allocation ();
#endif
- delete_trivially_dead_insns (get_insns (), max_reg_num ());
-
- init_reg_equiv_memory_loc ();
+ if (delete_trivially_dead_insns (get_insns (), max_reg_num ()))
+ df_analyze ();
if (max_regno != max_regno_before_ira)
{
regstat_compute_ri ();
}
- allocate_initial_values (reg_equiv_memory_loc);
-
overall_cost_before = ira_overall_cost;
- if (ira_conflicts_p)
+ if (! ira_conflicts_p)
+ grow_reg_equivs ();
+ else
{
fix_reg_equiv_init ();
memset (ira_spilled_reg_stack_slots, 0,
max_regno * sizeof (struct ira_spilled_reg_stack_slot));
}
+ allocate_initial_values (reg_equivs);
+}
- timevar_pop (TV_IRA);
+static void
+do_reload (void)
+{
+ basic_block bb;
+ bool need_dce;
+
+ if (flag_ira_verbose < 10)
+ ira_dump_file = dump_file;
- timevar_push (TV_RELOAD);
df_set_flags (DF_NO_INSN_RESCAN);
build_insn_chain ();
- reload_completed = !reload (get_insns (), ira_conflicts_p);
-
- finish_subregs_of_mode ();
-
- timevar_pop (TV_RELOAD);
+ need_dce = reload (get_insns (), ira_conflicts_p);
timevar_push (TV_IRA);
ira_free (ira_spilled_reg_stack_slots);
ira_finish_assign ();
-
}
if (internal_flag_ira_verbose > 0 && ira_dump_file != NULL
&& overall_cost_before != ira_overall_cost)
flag_ira_share_spill_slots = saved_flag_ira_share_spill_slots;
- flow_loops_free (&ira_loops);
- free_dominance_info (CDI_DOMINATORS);
+ if (current_loops != NULL)
+ {
+ flow_loops_free (&ira_loops);
+ free_dominance_info (CDI_DOMINATORS);
+ }
FOR_ALL_BB (bb)
bb->loop_father = NULL;
current_loops = NULL;
#endif
/* The code after the reload has changed so much that at this point
- we might as well just rescan everything. Not that
+ we might as well just rescan everything. Note that
df_rescan_all_insns is not going to help here because it does not
touch the artificial uses and defs. */
df_finish_pass (true);
if (optimize)
df_analyze ();
+ if (need_dce && optimize)
+ run_fast_dce ();
+
timevar_pop (TV_IRA);
}
-
\f
-
-static bool
-gate_ira (void)
-{
- return true;
-}
-
/* Run the integrated register allocator. */
static unsigned int
rest_of_handle_ira (void)
{
RTL_PASS,
"ira", /* name */
- gate_ira, /* gate */
+ NULL, /* gate */
rest_of_handle_ira, /* execute */
NULL, /* sub */
NULL, /* next */
0, /* static_pass_number */
- TV_NONE, /* tv_id */
+ TV_IRA, /* tv_id */
+ 0, /* properties_required */
+ 0, /* properties_provided */
+ 0, /* properties_destroyed */
+ 0, /* todo_flags_start */
+ TODO_dump_func /* todo_flags_finish */
+ }
+};
+
+static unsigned int
+rest_of_handle_reload (void)
+{
+ do_reload ();
+ return 0;
+}
+
+struct rtl_opt_pass pass_reload =
+{
+ {
+ RTL_PASS,
+ "reload", /* name */
+ NULL, /* gate */
+ rest_of_handle_reload, /* execute */
+ NULL, /* sub */
+ NULL, /* next */
+ 0, /* static_pass_number */
+ TV_RELOAD, /* tv_id */
0, /* properties_required */
0, /* properties_provided */
0, /* properties_destroyed */
0, /* todo_flags_start */
- TODO_dump_func |
- TODO_ggc_collect /* todo_flags_finish */
+ TODO_dump_func | TODO_ggc_collect /* todo_flags_finish */
}
};
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