#include "insn-config.h"
#include "recog.h"
#include "diagnostic-core.h"
-#include "toplev.h"
#include "params.h"
#include "df.h"
#include "sbitmap.h"
register pressure excess. Excess pressure for a register class at
some point means that there are more allocnos of given register
class living at the point than number of hard-registers of the
- class available for the allocation. It is defined only for cover
- classes. */
+ class available for the allocation. It is defined only for
+ pressure classes. */
static int high_pressure_start_point[N_REG_CLASSES];
/* Objects live at current point in the scan. */
EXECUTE_IF_SET_IN_SPARSESET (objects_live, i)
{
ira_object_t obj = ira_object_id_map[i];
+
SET_HARD_REG_BIT (OBJECT_CONFLICT_HARD_REGS (obj), regno);
SET_HARD_REG_BIT (OBJECT_TOTAL_CONFLICT_HARD_REGS (obj), regno);
}
{
ira_allocno_t a = OBJECT_ALLOCNO (obj);
int start, i;
- enum reg_class cover_class, cl;
+ enum reg_class aclass, pclass, cl;
live_range_t p;
- cover_class = ALLOCNO_COVER_CLASS (a);
+ aclass = ALLOCNO_CLASS (a);
+ pclass = ira_pressure_class_translate[aclass];
for (i = 0;
- (cl = ira_reg_class_super_classes[cover_class][i]) != LIM_REG_CLASSES;
+ (cl = ira_reg_class_super_classes[pclass][i]) != LIM_REG_CLASSES;
i++)
{
+ if (! ira_reg_pressure_class_p[cl])
+ continue;
if (high_pressure_start_point[cl] < 0)
continue;
p = OBJECT_LIVE_RANGES (obj);
update_allocno_pressure_excess_length (obj);
}
-/* The current register pressures for each cover class for the current
+/* The current register pressures for each pressure class for the current
basic block. */
static int curr_reg_pressure[N_REG_CLASSES];
-/* Record that register pressure for COVER_CLASS increased by N
- registers. Update the current register pressure, maximal register
- pressure for the current BB and the start point of the register
- pressure excess. */
+/* Record that register pressure for PCLASS increased by N registers.
+ Update the current register pressure, maximal register pressure for
+ the current BB and the start point of the register pressure
+ excess. */
static void
-inc_register_pressure (enum reg_class cover_class, int n)
+inc_register_pressure (enum reg_class pclass, int n)
{
int i;
enum reg_class cl;
for (i = 0;
- (cl = ira_reg_class_super_classes[cover_class][i]) != LIM_REG_CLASSES;
+ (cl = ira_reg_class_super_classes[pclass][i]) != LIM_REG_CLASSES;
i++)
{
+ if (! ira_reg_pressure_class_p[cl])
+ continue;
curr_reg_pressure[cl] += n;
if (high_pressure_start_point[cl] < 0
&& (curr_reg_pressure[cl] > ira_available_class_regs[cl]))
}
}
-/* Record that register pressure for COVER_CLASS has decreased by
- NREGS registers; update current register pressure, start point of
- the register pressure excess, and register pressure excess length
- for living allocnos. */
+/* Record that register pressure for PCLASS has decreased by NREGS
+ registers; update current register pressure, start point of the
+ register pressure excess, and register pressure excess length for
+ living allocnos. */
static void
-dec_register_pressure (enum reg_class cover_class, int nregs)
+dec_register_pressure (enum reg_class pclass, int nregs)
{
int i;
unsigned int j;
bool set_p = false;
for (i = 0;
- (cl = ira_reg_class_super_classes[cover_class][i]) != LIM_REG_CLASSES;
+ (cl = ira_reg_class_super_classes[pclass][i]) != LIM_REG_CLASSES;
i++)
{
+ if (! ira_reg_pressure_class_p[cl])
+ continue;
curr_reg_pressure[cl] -= nregs;
ira_assert (curr_reg_pressure[cl] >= 0);
if (high_pressure_start_point[cl] >= 0
EXECUTE_IF_SET_IN_SPARSESET (objects_live, j)
update_allocno_pressure_excess_length (ira_object_id_map[j]);
for (i = 0;
- (cl = ira_reg_class_super_classes[cover_class][i])
- != LIM_REG_CLASSES;
+ (cl = ira_reg_class_super_classes[pclass][i]) != LIM_REG_CLASSES;
i++)
- if (high_pressure_start_point[cl] >= 0
- && curr_reg_pressure[cl] <= ira_available_class_regs[cl])
- high_pressure_start_point[cl] = -1;
+ {
+ if (! ira_reg_pressure_class_p[cl])
+ continue;
+ if (high_pressure_start_point[cl] >= 0
+ && curr_reg_pressure[cl] <= ira_available_class_regs[cl])
+ high_pressure_start_point[cl] = -1;
+ }
}
}
mark_pseudo_regno_live (int regno)
{
ira_allocno_t a = ira_curr_regno_allocno_map[regno];
+ enum reg_class pclass;
int i, n, nregs;
- enum reg_class cl;
if (a == NULL)
return;
allocno_saved_at_call[ALLOCNO_NUM (a)] = 0;
n = ALLOCNO_NUM_OBJECTS (a);
- cl = ALLOCNO_COVER_CLASS (a);
- nregs = ira_reg_class_nregs[cl][ALLOCNO_MODE (a)];
+ pclass = ira_pressure_class_translate[ALLOCNO_CLASS (a)];
+ nregs = ira_reg_class_max_nregs[ALLOCNO_CLASS (a)][ALLOCNO_MODE (a)];
if (n > 1)
{
/* We track every subobject separately. */
for (i = 0; i < n; i++)
{
ira_object_t obj = ALLOCNO_OBJECT (a, i);
+
if (sparseset_bit_p (objects_live, OBJECT_CONFLICT_ID (obj)))
continue;
- inc_register_pressure (cl, nregs);
+ inc_register_pressure (pclass, nregs);
make_object_born (obj);
}
}
mark_pseudo_regno_subword_live (int regno, int subword)
{
ira_allocno_t a = ira_curr_regno_allocno_map[regno];
- int n, nregs;
- enum reg_class cl;
+ int n;
+ enum reg_class pclass;
ira_object_t obj;
if (a == NULL)
return;
}
- cl = ALLOCNO_COVER_CLASS (a);
- nregs = ira_reg_class_nregs[cl][ALLOCNO_MODE (a)];
- gcc_assert (nregs == n);
+ pclass = ira_pressure_class_translate[ALLOCNO_CLASS (a)];
+ gcc_assert
+ (n == ira_reg_class_max_nregs[ALLOCNO_CLASS (a)][ALLOCNO_MODE (a)]);
obj = ALLOCNO_OBJECT (a, subword);
if (sparseset_bit_p (objects_live, OBJECT_CONFLICT_ID (obj)))
return;
- inc_register_pressure (cl, nregs);
+ inc_register_pressure (pclass, 1);
make_object_born (obj);
}
if (! TEST_HARD_REG_BIT (ira_no_alloc_regs, regno))
{
int last = regno + hard_regno_nregs[regno][GET_MODE (reg)];
+ enum reg_class aclass, pclass;
while (regno < last)
{
if (! TEST_HARD_REG_BIT (hard_regs_live, regno)
&& ! TEST_HARD_REG_BIT (eliminable_regset, regno))
{
- enum reg_class cover_class = ira_hard_regno_cover_class[regno];
- inc_register_pressure (cover_class, 1);
+ aclass = ira_hard_regno_allocno_class[regno];
+ pclass = ira_pressure_class_translate[aclass];
+ inc_register_pressure (pclass, 1);
make_hard_regno_born (regno);
}
regno++;
}
}
+/* Mark a pseudo, or one of its subwords, as live. REGNO is the pseudo's
+ register number; ORIG_REG is the access in the insn, which may be a
+ subreg. */
+static void
+mark_pseudo_reg_live (rtx orig_reg, unsigned regno)
+{
+ if (df_read_modify_subreg_p (orig_reg))
+ {
+ mark_pseudo_regno_subword_live (regno,
+ subreg_lowpart_p (orig_reg) ? 0 : 1);
+ }
+ else
+ mark_pseudo_regno_live (regno);
+}
+
/* Mark the register referenced by use or def REF as live. */
static void
mark_ref_live (df_ref ref)
reg = SUBREG_REG (reg);
if (REGNO (reg) >= FIRST_PSEUDO_REGISTER)
- {
- if (df_read_modify_subreg_p (orig_reg))
- {
- mark_pseudo_regno_subword_live (REGNO (reg),
- subreg_lowpart_p (orig_reg) ? 0 : 1);
- }
- else
- mark_pseudo_regno_live (REGNO (reg));
- }
+ mark_pseudo_reg_live (orig_reg, REGNO (reg));
else
mark_hard_reg_live (reg);
}
allocno_saved_at_call[ALLOCNO_NUM (a)] = 0;
n = ALLOCNO_NUM_OBJECTS (a);
- cl = ALLOCNO_COVER_CLASS (a);
- nregs = ira_reg_class_nregs[cl][ALLOCNO_MODE (a)];
+ cl = ira_pressure_class_translate[ALLOCNO_CLASS (a)];
+ nregs = ira_reg_class_max_nregs[ALLOCNO_CLASS (a)][ALLOCNO_MODE (a)];
if (n > 1)
{
/* We track every subobject separately. */
mark_pseudo_regno_subword_dead (int regno, int subword)
{
ira_allocno_t a = ira_curr_regno_allocno_map[regno];
- int n, nregs;
+ int n;
enum reg_class cl;
ira_object_t obj;
/* The allocno as a whole doesn't die in this case. */
return;
- cl = ALLOCNO_COVER_CLASS (a);
- nregs = ira_reg_class_nregs[cl][ALLOCNO_MODE (a)];
- gcc_assert (nregs == n);
+ cl = ira_pressure_class_translate[ALLOCNO_CLASS (a)];
+ gcc_assert
+ (n == ira_reg_class_max_nregs[ALLOCNO_CLASS (a)][ALLOCNO_MODE (a)]);
obj = ALLOCNO_OBJECT (a, subword);
if (!sparseset_bit_p (objects_live, OBJECT_CONFLICT_ID (obj)))
if (! TEST_HARD_REG_BIT (ira_no_alloc_regs, regno))
{
int last = regno + hard_regno_nregs[regno][GET_MODE (reg)];
+ enum reg_class aclass, pclass;
while (regno < last)
{
if (TEST_HARD_REG_BIT (hard_regs_live, regno))
{
- enum reg_class cover_class = ira_hard_regno_cover_class[regno];
- dec_register_pressure (cover_class, 1);
+ aclass = ira_hard_regno_allocno_class[regno];
+ pclass = ira_pressure_class_translate[aclass];
+ dec_register_pressure (pclass, 1);
make_hard_regno_dead (regno);
}
regno++;
}
}
+/* Mark a pseudo, or one of its subwords, as dead. REGNO is the pseudo's
+ register number; ORIG_REG is the access in the insn, which may be a
+ subreg. */
+static void
+mark_pseudo_reg_dead (rtx orig_reg, unsigned regno)
+{
+ if (df_read_modify_subreg_p (orig_reg))
+ {
+ mark_pseudo_regno_subword_dead (regno,
+ subreg_lowpart_p (orig_reg) ? 0 : 1);
+ }
+ else
+ mark_pseudo_regno_dead (regno);
+}
+
/* Mark the register referenced by definition DEF as dead, if the
definition is a total one. */
static void
return;
if (REGNO (reg) >= FIRST_PSEUDO_REGISTER)
- {
- if (df_read_modify_subreg_p (orig_reg))
- {
- mark_pseudo_regno_subword_dead (REGNO (reg),
- subreg_lowpart_p (orig_reg) ? 0 : 1);
- }
- else
- mark_pseudo_regno_dead (REGNO (reg));
- }
+ mark_pseudo_reg_dead (orig_reg, REGNO (reg));
else
mark_hard_reg_dead (reg);
}
-/* Make pseudo REG conflicting with pseudo DREG, if the 1st pseudo
- class is intersected with class CL. Advance the current program
- point before making the conflict if ADVANCE_P. Return TRUE if we
- will need to advance the current program point. */
+/* If REG is a pseudo or a subreg of it, and the class of its allocno
+ intersects CL, make a conflict with pseudo DREG. ORIG_DREG is the
+ rtx actually accessed, it may be indentical to DREG or a subreg of it.
+ Advance the current program point before making the conflict if
+ ADVANCE_P. Return TRUE if we will need to advance the current
+ program point. */
static bool
-make_pseudo_conflict (rtx reg, enum reg_class cl, rtx dreg, bool advance_p)
+make_pseudo_conflict (rtx reg, enum reg_class cl, rtx dreg, rtx orig_dreg,
+ bool advance_p)
{
+ rtx orig_reg = reg;
ira_allocno_t a;
if (GET_CODE (reg) == SUBREG)
return advance_p;
a = ira_curr_regno_allocno_map[REGNO (reg)];
- if (! reg_classes_intersect_p (cl, ALLOCNO_COVER_CLASS (a)))
+ if (! reg_classes_intersect_p (cl, ALLOCNO_CLASS (a)))
return advance_p;
if (advance_p)
curr_point++;
- mark_pseudo_regno_live (REGNO (reg));
- mark_pseudo_regno_live (REGNO (dreg));
- mark_pseudo_regno_dead (REGNO (reg));
- mark_pseudo_regno_dead (REGNO (dreg));
+ mark_pseudo_reg_live (orig_reg, REGNO (reg));
+ mark_pseudo_reg_live (orig_dreg, REGNO (dreg));
+ mark_pseudo_reg_dead (orig_reg, REGNO (reg));
+ mark_pseudo_reg_dead (orig_dreg, REGNO (dreg));
return false;
}
/* Check and make if necessary conflicts for pseudo DREG of class
DEF_CL of the current insn with input operand USE of class USE_CL.
- Advance the current program point before making the conflict if
- ADVANCE_P. Return TRUE if we will need to advance the current
- program point. */
+ ORIG_DREG is the rtx actually accessed, it may be indentical to
+ DREG or a subreg of it. Advance the current program point before
+ making the conflict if ADVANCE_P. Return TRUE if we will need to
+ advance the current program point. */
static bool
-check_and_make_def_use_conflict (rtx dreg, enum reg_class def_cl,
- int use, enum reg_class use_cl,
- bool advance_p)
+check_and_make_def_use_conflict (rtx dreg, rtx orig_dreg,
+ enum reg_class def_cl, int use,
+ enum reg_class use_cl, bool advance_p)
{
if (! reg_classes_intersect_p (def_cl, use_cl))
return advance_p;
advance_p = make_pseudo_conflict (recog_data.operand[use],
- use_cl, dreg, advance_p);
+ use_cl, dreg, orig_dreg, advance_p);
+
/* Reload may end up swapping commutative operands, so you
have to take both orderings into account. The
constraints for the two operands can be completely
&& recog_data.constraints[use][0] == '%')
advance_p
= make_pseudo_conflict (recog_data.operand[use + 1],
- use_cl, dreg, advance_p);
+ use_cl, dreg, orig_dreg, advance_p);
if (use >= 1
&& recog_data.constraints[use - 1][0] == '%')
advance_p
= make_pseudo_conflict (recog_data.operand[use - 1],
- use_cl, dreg, advance_p);
+ use_cl, dreg, orig_dreg, advance_p);
return advance_p;
}
enum reg_class use_cl, acl;
bool advance_p;
rtx dreg = recog_data.operand[def];
+ rtx orig_dreg = dreg;
if (def_cl == NO_REGS)
return;
return;
a = ira_curr_regno_allocno_map[REGNO (dreg)];
- acl = ALLOCNO_COVER_CLASS (a);
+ acl = ALLOCNO_CLASS (a);
if (! reg_classes_intersect_p (acl, def_cl))
return;
if (alt1 < recog_data.n_alternatives)
continue;
- advance_p = check_and_make_def_use_conflict (dreg, def_cl, use,
- use_cl, advance_p);
+ advance_p = check_and_make_def_use_conflict (dreg, orig_dreg, def_cl,
+ use, use_cl, advance_p);
if ((use_match = recog_op_alt[use][alt].matches) >= 0)
{
use_cl = ALL_REGS;
else
use_cl = recog_op_alt[use_match][alt].cl;
- advance_p = check_and_make_def_use_conflict (dreg, def_cl, use,
- use_cl, advance_p);
+ advance_p = check_and_make_def_use_conflict (dreg, orig_dreg, def_cl,
+ use, use_cl, advance_p);
}
}
}
static enum reg_class
single_reg_class (const char *constraints, rtx op, rtx equiv_const)
{
- int ignore_p;
+ int curr_alt, c;
+ bool ignore_p;
enum reg_class cl, next_cl;
- int c;
cl = NO_REGS;
- for (ignore_p = false;
+ for (ignore_p = false, curr_alt = 0;
(c = *constraints);
constraints += CONSTRAINT_LEN (c, constraints))
- if (c == '#')
+ if (c == '#' || !recog_data.alternative_enabled_p[curr_alt])
ignore_p = true;
else if (c == ',')
- ignore_p = false;
+ {
+ curr_alt++;
+ ignore_p = false;
+ }
else if (! ignore_p)
switch (c)
{
: REG_CLASS_FROM_CONSTRAINT (c, constraints));
if ((cl != NO_REGS && next_cl != cl)
|| (ira_available_class_regs[next_cl]
- > ira_reg_class_nregs[next_cl][GET_MODE (op)]))
+ > ira_reg_class_max_nregs[next_cl][GET_MODE (op)]))
return NO_REGS;
cl = next_cl;
break;
if ((cl != NO_REGS && next_cl != cl)
|| next_cl == NO_REGS
|| (ira_available_class_regs[next_cl]
- > ira_reg_class_nregs[next_cl][GET_MODE (op)]))
+ > ira_reg_class_max_nregs[next_cl][GET_MODE (op)]))
return NO_REGS;
cl = next_cl;
break;
void
ira_implicitly_set_insn_hard_regs (HARD_REG_SET *set)
{
- int i, c, regno = 0;
+ int i, curr_alt, c, regno = 0;
bool ignore_p;
enum reg_class cl;
rtx op;
mode = (GET_CODE (op) == SCRATCH
? GET_MODE (op) : PSEUDO_REGNO_MODE (regno));
cl = NO_REGS;
- for (ignore_p = false; (c = *p); p += CONSTRAINT_LEN (c, p))
- if (c == '#')
+ for (ignore_p = false, curr_alt = 0;
+ (c = *p);
+ p += CONSTRAINT_LEN (c, p))
+ if (c == '#' || !recog_data.alternative_enabled_p[curr_alt])
ignore_p = true;
else if (c == ',')
- ignore_p = false;
+ {
+ curr_alt++;
+ ignore_p = false;
+ }
else if (! ignore_p)
switch (c)
{
regs in this class are fixed. */
&& ira_available_class_regs[cl] != 0
&& (ira_available_class_regs[cl]
- <= ira_reg_class_nregs[cl][mode]))
+ <= ira_reg_class_max_nregs[cl][mode]))
IOR_HARD_REG_SET (*set, reg_class_contents[cl]);
break;
}
if (REG_P (operand)
&& (regno = REGNO (operand)) >= FIRST_PSEUDO_REGISTER)
{
- enum reg_class cover_class;
+ enum reg_class aclass;
operand_a = ira_curr_regno_allocno_map[regno];
- cover_class = ALLOCNO_COVER_CLASS (operand_a);
- if (ira_class_subset_p[cl][cover_class]
+ aclass = ALLOCNO_CLASS (operand_a);
+ if (ira_class_subset_p[cl][aclass]
&& ira_class_hard_regs_num[cl] != 0)
{
/* View the desired allocation of OPERAND as:
offset = subreg_lowpart_offset (ymode, xmode);
yregno = simplify_subreg_regno (xregno, xmode, offset, ymode);
if (yregno >= 0
- && ira_class_hard_reg_index[cover_class][yregno] >= 0)
+ && ira_class_hard_reg_index[aclass][yregno] >= 0)
{
int cost;
ira_allocate_and_set_costs
(&ALLOCNO_CONFLICT_HARD_REG_COSTS (operand_a),
- cover_class, 0);
- cost
- = (freq
- * (in_p
- ? ira_get_register_move_cost (xmode, cover_class, cl)
- : ira_get_register_move_cost (xmode, cl,
- cover_class)));
+ aclass, 0);
+ ira_init_register_move_cost_if_necessary (xmode);
+ cost = freq * (in_p
+ ? ira_register_move_cost[xmode][aclass][cl]
+ : ira_register_move_cost[xmode][cl][aclass]);
ALLOCNO_CONFLICT_HARD_REG_COSTS (operand_a)
- [ira_class_hard_reg_index[cover_class][yregno]] -= cost;
+ [ira_class_hard_reg_index[aclass][yregno]] -= cost;
}
}
}
bb = loop_tree_node->bb;
if (bb != NULL)
{
- for (i = 0; i < ira_reg_class_cover_size; i++)
+ for (i = 0; i < ira_pressure_classes_num; i++)
{
- curr_reg_pressure[ira_reg_class_cover[i]] = 0;
- high_pressure_start_point[ira_reg_class_cover[i]] = -1;
+ curr_reg_pressure[ira_pressure_classes[i]] = 0;
+ high_pressure_start_point[ira_pressure_classes[i]] = -1;
}
curr_bb_node = loop_tree_node;
reg_live_out = DF_LR_OUT (bb);
for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
if (TEST_HARD_REG_BIT (hard_regs_live, i))
{
- enum reg_class cover_class, cl;
+ enum reg_class aclass, pclass, cl;
- cover_class = ira_class_translate[REGNO_REG_CLASS (i)];
+ aclass = ira_allocno_class_translate[REGNO_REG_CLASS (i)];
+ pclass = ira_pressure_class_translate[aclass];
for (j = 0;
- (cl = ira_reg_class_super_classes[cover_class][j])
+ (cl = ira_reg_class_super_classes[pclass][j])
!= LIM_REG_CLASSES;
j++)
{
+ if (! ira_reg_pressure_class_p[cl])
+ continue;
curr_reg_pressure[cl]++;
if (curr_bb_node->reg_pressure[cl] < curr_reg_pressure[cl])
curr_bb_node->reg_pressure[cl] = curr_reg_pressure[cl];
EXECUTE_IF_SET_IN_SPARSESET (objects_live, px)
{
ira_allocno_t a = OBJECT_ALLOCNO (ira_object_id_map[px]);
+
ALLOCNO_NO_STACK_REG_P (a) = true;
ALLOCNO_TOTAL_NO_STACK_REG_P (a) = true;
}
}
/* Propagate register pressure to upper loop tree nodes: */
if (loop_tree_node != ira_loop_tree_root)
- for (i = 0; i < ira_reg_class_cover_size; i++)
+ for (i = 0; i < ira_pressure_classes_num; i++)
{
- enum reg_class cover_class;
+ enum reg_class pclass;
- cover_class = ira_reg_class_cover[i];
- if (loop_tree_node->reg_pressure[cover_class]
- > loop_tree_node->parent->reg_pressure[cover_class])
- loop_tree_node->parent->reg_pressure[cover_class]
- = loop_tree_node->reg_pressure[cover_class];
+ pclass = ira_pressure_classes[i];
+ if (loop_tree_node->reg_pressure[pclass]
+ > loop_tree_node->parent->reg_pressure[pclass])
+ loop_tree_node->parent->reg_pressure[pclass]
+ = loop_tree_node->reg_pressure[pclass];
}
}
{
int n = ALLOCNO_NUM_OBJECTS (a);
int i;
+
for (i = 0; i < n; i++)
{
fprintf (f, " a%d(r%d", ALLOCNO_NUM (a), ALLOCNO_REGNO (a));
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