PR c++/44127

[pf3gnuchains/gcc-fork.git] / gcc / ira-lives.c

diff --git a/gcc/ira-lives.c b/gcc/ira-lives.c
index ac69e22..7ced1a7 100644 (file)
--- a/gcc/ira-lives.c
+++ b/gcc/ira-lives.c
@@ -1,5 +1,5 @@
 /* IRA processing allocno lives to build allocno live ranges.
-   Copyright (C) 2006, 2007, 2008, 2009
+   Copyright (C) 2006, 2007, 2008, 2009, 2010
    Free Software Foundation, Inc.
    Contributed by Vladimir Makarov <vmakarov@redhat.com>.
 
@@ -499,6 +499,8 @@ check_and_make_def_conflict (int alt, int def, enum reg_class def_cl)
 
   for (use = 0; use < recog_data.n_operands; use++)
     {
+      int alt1;
+
       if (use == def || recog_data.operand_type[use] == OP_OUT)
        continue;
 
@@ -507,6 +509,22 @@ check_and_make_def_conflict (int alt, int def, enum reg_class def_cl)
       else
        use_cl = recog_op_alt[use][alt].cl;
 
+      /* If there's any alternative that allows USE to match DEF, do not
+        record a conflict.  If that causes us to create an invalid
+        instruction due to the earlyclobber, reload must fix it up.  */         
+      for (alt1 = 0; alt1 < recog_data.n_alternatives; alt1++)
+       if (recog_op_alt[use][alt1].matches == def
+           || (use < recog_data.n_operands - 1
+               && recog_data.constraints[use][0] == '%'
+               && recog_op_alt[use + 1][alt1].matches == def)
+           || (use >= 1
+               && recog_data.constraints[use - 1][0] == '%'
+               && recog_op_alt[use - 1][alt1].matches == def))
+         break;
+
+      if (alt1 < recog_data.n_alternatives)
+       continue;
+
       advance_p = check_and_make_def_use_conflict (dreg, def_cl, use,
                                                   use_cl, advance_p);
 
@@ -787,6 +805,9 @@ ira_implicitly_set_insn_hard_regs (HARD_REG_SET *set)
                        ? GENERAL_REGS
                        : REG_CLASS_FROM_CONSTRAINT (c, p));
                  if (cl != NO_REGS
+                     /* There is no register pressure problem if all of the
+                        regs in this class are fixed.  */
+                     && ira_available_class_regs[cl] != 0
                      && (ira_available_class_regs[cl]
                          <= ira_reg_class_nregs[cl][mode]))
                    IOR_HARD_REG_SET (*set, reg_class_contents[cl]);