#define ALLOCNO_MAX(A) ((A)->max)
#define ALLOCNO_CONFLICT_ID(A) ((A)->conflict_id)
-/* Map regno -> allocnos with given regno (see comments for
+/* Map regno -> allocnos with given regno (see comments for
allocno member `next_regno_allocno'). */
extern ira_allocno_t *ira_regno_allocno_map;
} \
((R)[(unsigned) (_i - _min) / IRA_INT_BITS] \
|= ((IRA_INT_TYPE) 1 << ((unsigned) (_i - _min) % IRA_INT_BITS))); }))
-
+
#define CLEAR_ALLOCNO_SET_BIT(R, I, MIN, MAX) __extension__ \
(({ int _min = (MIN), _max = (MAX), _i = (I); \
{
i->word_num++;
i->bit_num = i->word_num * IRA_INT_BITS;
-
+
/* If we have reached the end, break. */
if (i->bit_num >= i->nel)
return false;
}
-
+
/* Skip bits that are zero. */
for (; (i->word & 1) == 0; i->word >>= 1)
i->bit_num++;
-
+
*n = (int) i->bit_num + i->start_val;
-
+
return true;
}
allocation. */
extern int ira_class_subset_p[N_REG_CLASSES][N_REG_CLASSES];
+/* Array of the number of hard registers of given class which are
+ available for allocation. The order is defined by the the hard
+ register numbers. */
+extern short ira_non_ordered_class_hard_regs[N_REG_CLASSES][FIRST_PSEUDO_REGISTER];
+
/* Index (in ira_class_hard_regs) for given register class and hard
register (in general case a hard register can belong to several
register classes). The index is negative for hard registers
for (; i->word == 0; i->word = ((IRA_INT_TYPE *) i->vec)[i->word_num])
{
i->word_num++;
-
+
/* If we have reached the end, break. */
if (i->word_num * sizeof (IRA_INT_TYPE) >= i->size)
return false;
-
+
i->bit_num = i->word_num * IRA_INT_BITS;
}
-
+
/* Skip bits that are zero. */
for (; (i->word & 1) == 0; i->word >>= 1)
i->bit_num++;
-
+
*a = ira_conflict_id_allocno_map[i->bit_num + i->base_conflict_id];
-
+
return true;
}
}