/* Instruction scheduling pass.
- Copyright (C) 1992, 93-98, 1999 Free Software Foundation, Inc.
+ Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
+ 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010
+ Free Software Foundation, Inc.
Contributed by Michael Tiemann (tiemann@cygnus.com) Enhanced by,
and currently maintained by, Jim Wilson (wilson@cygnus.com)
- This file is part of GNU CC.
+This file is part of GCC.
- GNU CC is free software; you can redistribute it and/or modify it
- under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2, or (at your option)
- any later version.
+GCC is free software; you can redistribute it and/or modify it under
+the terms of the GNU General Public License as published by the Free
+Software Foundation; either version 3, or (at your option) any later
+version.
- GNU CC is distributed in the hope that it will be useful, but
- WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- General Public License for more details.
+GCC is distributed in the hope that it will be useful, but WITHOUT ANY
+WARRANTY; without even the implied warranty of MERCHANTABILITY or
+FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+for more details.
- You should have received a copy of the GNU General Public License
- along with GNU CC; see the file COPYING. If not, write to the Free
- the Free Software Foundation, 59 Temple Place - Suite 330,
- Boston, MA 02111-1307, USA. */
+You should have received a copy of the GNU General Public License
+along with GCC; see the file COPYING3. If not see
+<http://www.gnu.org/licenses/>. */
-
-/* Instruction scheduling pass.
-
- This pass implements list scheduling within basic blocks. It is
- run twice: (1) after flow analysis, but before register allocation,
- and (2) after register allocation.
-
- The first run performs interblock scheduling, moving insns between
- different blocks in the same "region", and the second runs only
- basic block scheduling.
-
- Interblock motions performed are useful motions and speculative
- motions, including speculative loads. Motions requiring code
- duplication are not supported. The identification of motion type
- and the check for validity of speculative motions requires
- construction and analysis of the function's control flow graph.
- The scheduler works as follows:
+/* Instruction scheduling pass. This file, along with sched-deps.c,
+ contains the generic parts. The actual entry point is found for
+ the normal instruction scheduling pass is found in sched-rgn.c.
We compute insn priorities based on data dependencies. Flow
analysis only creates a fraction of the data-dependencies we must
as short as possible. The remaining insns are then scheduled in
remaining slots.
- Function unit conflicts are resolved during forward list scheduling
- by tracking the time when each insn is committed to the schedule
- and from that, the time the function units it uses must be free.
- As insns on the ready list are considered for scheduling, those
- that would result in a blockage of the already committed insns are
- queued until no blockage will result.
-
The following list shows the order in which we want to break ties
among insns in the ready list:
compute_block_backward_dependences ().
Dependencies set up by memory references are treated in exactly the
- same way as other dependencies, by using LOG_LINKS backward
- dependences. LOG_LINKS are translated into INSN_DEPEND forward
- dependences for the purpose of forward list scheduling.
+ same way as other dependencies, by using insn backward dependences
+ INSN_BACK_DEPS. INSN_BACK_DEPS are translated into forward dependences
+ INSN_FORW_DEPS the purpose of forward list scheduling.
Having optimized the critical path, we may have also unduly
extended the lifetimes of some registers. If an operation requires
This pass must update information that subsequent passes expect to
be correct. Namely: reg_n_refs, reg_n_sets, reg_n_deaths,
- reg_n_calls_crossed, and reg_live_length. Also, BLOCK_HEAD,
- BLOCK_END.
+ reg_n_calls_crossed, and reg_live_length. Also, BB_HEAD, BB_END.
The information in the line number notes is carefully retained by
this pass. Notes that refer to the starting and ending of
exception regions are also carefully retained by this pass. All
other NOTE insns are grouped in their same relative order at the
- beginning of basic blocks and regions that have been scheduled.
-
- The main entry point for this pass is schedule_insns(), called for
- each function. The work of the scheduler is organized in three
- levels: (1) function level: insns are subject to splitting,
- control-flow-graph is constructed, regions are computed (after
- reload, each region is of one block), (2) region level: control
- flow graph attributes required for interblock scheduling are
- computed (dominators, reachability, etc.), data dependences and
- priorities are computed, and (3) block level: insns in the block
- are actually scheduled. */
+ beginning of basic blocks and regions that have been scheduled. */
\f
#include "config.h"
#include "system.h"
+#include "coretypes.h"
+#include "tm.h"
#include "toplev.h"
#include "rtl.h"
#include "tm_p.h"
-#include "basic-block.h"
+#include "hard-reg-set.h"
#include "regs.h"
#include "function.h"
-#include "hard-reg-set.h"
#include "flags.h"
#include "insn-config.h"
#include "insn-attr.h"
#include "except.h"
#include "toplev.h"
#include "recog.h"
-
-extern char *reg_known_equiv_p;
-extern rtx *reg_known_value;
+#include "sched-int.h"
+#include "target.h"
+#include "output.h"
+#include "params.h"
+#include "vecprim.h"
+#include "dbgcnt.h"
+#include "cfgloop.h"
+#include "ira.h"
#ifdef INSN_SCHEDULING
-/* target_units bitmask has 1 for each unit in the cpu. It should be
- possible to compute this variable from the machine description.
- But currently it is computed by examining the insn list. Since
- this is only needed for visualization, it seems an acceptable
- solution. (For understanding the mapping of bits to units, see
- definition of function_units[] in "insn-attrtab.c".) */
-
-static int target_units = 0;
-
/* issue_rate is the number of insns that can be scheduled in the same
machine cycle. It can be defined in the config/mach/mach.h file,
otherwise we set it to 1. */
-static int issue_rate;
-
-#ifndef ISSUE_RATE
-#define ISSUE_RATE 1
-#endif
+int issue_rate;
/* sched-verbose controls the amount of debugging output the
- scheduler prints. It is controlled by -fsched-verbose-N:
+ scheduler prints. It is controlled by -fsched-verbose=N:
N>0 and no -DSR : the output is directed to stderr.
N>=10 will direct the printouts to stderr (regardless of -dSR).
N=1: same as -dSR.
N=3: rtl at abort point, control-flow, regions info.
N=5: dependences info. */
-#define MAX_RGN_BLOCKS 10
-#define MAX_RGN_INSNS 100
-
static int sched_verbose_param = 0;
-static int sched_verbose = 0;
-
-/* nr_inter/spec counts interblock/speculative motion for the function. */
-static int nr_inter, nr_spec;
-
+int sched_verbose = 0;
/* Debugging file. All printouts are sent to dump, which is always set,
either to stderr, or to the dump listing file (-dRS). */
-static FILE *dump = 0;
+FILE *sched_dump = 0;
/* fix_sched_param() is called from toplev.c upon detection
- of the -fsched-***-N options. */
+ of the -fsched-verbose=N option. */
void
-fix_sched_param (param, val)
- const char *param, *val;
+fix_sched_param (const char *param, const char *val)
{
if (!strcmp (param, "verbose"))
sched_verbose_param = atoi (val);
else
- warning ("fix_sched_param: unknown param: %s", param);
+ warning (0, "fix_sched_param: unknown param: %s", param);
}
-/* Describe state of dependencies used during sched_analyze phase. */
-struct deps
-{
- /* The *_insns and *_mems are paired lists. Each pending memory operation
- will have a pointer to the MEM rtx on one list and a pointer to the
- containing insn on the other list in the same place in the list. */
-
- /* We can't use add_dependence like the old code did, because a single insn
- may have multiple memory accesses, and hence needs to be on the list
- once for each memory access. Add_dependence won't let you add an insn
- to a list more than once. */
-
- /* An INSN_LIST containing all insns with pending read operations. */
- rtx pending_read_insns;
-
- /* An EXPR_LIST containing all MEM rtx's which are pending reads. */
- rtx pending_read_mems;
-
- /* An INSN_LIST containing all insns with pending write operations. */
- rtx pending_write_insns;
-
- /* An EXPR_LIST containing all MEM rtx's which are pending writes. */
- rtx pending_write_mems;
-
- /* Indicates the combined length of the two pending lists. We must prevent
- these lists from ever growing too large since the number of dependencies
- produced is at least O(N*N), and execution time is at least O(4*N*N), as
- a function of the length of these pending lists. */
- int pending_lists_length;
-
- /* The last insn upon which all memory references must depend.
- This is an insn which flushed the pending lists, creating a dependency
- between it and all previously pending memory references. This creates
- a barrier (or a checkpoint) which no memory reference is allowed to cross.
-
- This includes all non constant CALL_INSNs. When we do interprocedural
- alias analysis, this restriction can be relaxed.
- This may also be an INSN that writes memory if the pending lists grow
- too large. */
- rtx last_pending_memory_flush;
-
- /* The last function call we have seen. All hard regs, and, of course,
- the last function call, must depend on this. */
- rtx last_function_call;
-
- /* The LOG_LINKS field of this is a list of insns which use a pseudo register
- that does not already cross a call. We create dependencies between each
- of those insn and the next call insn, to ensure that they won't cross a call
- after scheduling is done. */
- rtx sched_before_next_call;
-
- /* Element N is the next insn that sets (hard or pseudo) register
- N within the current basic block; or zero, if there is no
- such insn. Needed for new registers which may be introduced
- by splitting insns. */
- rtx *reg_last_uses;
- rtx *reg_last_sets;
- rtx *reg_last_clobbers;
-};
-
-static regset reg_pending_sets;
-static regset reg_pending_clobbers;
-static int reg_pending_sets_all;
-
-/* To speed up the test for duplicate dependency links we keep a record
- of true dependencies created by add_dependence when the average number
- of instructions in a basic block is very large.
-
- Studies have shown that there is typically around 5 instructions between
- branches for typical C code. So we can make a guess that the average
- basic block is approximately 5 instructions long; we will choose 100X
- the average size as a very large basic block.
-
- Each insn has an associated bitmap for its dependencies. Each bitmap
- has enough entries to represent a dependency on any other insn in the
- insn chain. */
-static sbitmap *true_dependency_cache;
-
-/* Indexed by INSN_UID, the collection of all data associated with
- a single instruction. */
-
-struct haifa_insn_data
-{
- /* A list of insns which depend on the instruction. Unlike LOG_LINKS,
- it represents forward dependancies. */
- rtx depend;
+/* This is a placeholder for the scheduler parameters common
+ to all schedulers. */
+struct common_sched_info_def *common_sched_info;
- /* The line number note in effect for each insn. For line number
- notes, this indicates whether the note may be reused. */
- rtx line_note;
+#define INSN_TICK(INSN) (HID (INSN)->tick)
+#define INTER_TICK(INSN) (HID (INSN)->inter_tick)
- /* Logical uid gives the original ordering of the insns. */
- int luid;
-
- /* A priority for each insn. */
- int priority;
+/* If INSN_TICK of an instruction is equal to INVALID_TICK,
+ then it should be recalculated from scratch. */
+#define INVALID_TICK (-(max_insn_queue_index + 1))
+/* The minimal value of the INSN_TICK of an instruction. */
+#define MIN_TICK (-max_insn_queue_index)
- /* The number of incoming edges in the forward dependency graph.
- As scheduling proceds, counts are decreased. An insn moves to
- the ready queue when its counter reaches zero. */
- int dep_count;
+/* Issue points are used to distinguish between instructions in max_issue ().
+ For now, all instructions are equally good. */
+#define ISSUE_POINTS(INSN) 1
- /* An encoding of the blockage range function. Both unit and range
- are coded. */
- unsigned int blockage;
-
- /* Number of instructions referring to this insn. */
- int ref_count;
+/* List of important notes we must keep around. This is a pointer to the
+ last element in the list. */
+rtx note_list;
- /* The minimum clock tick at which the insn becomes ready. This is
- used to note timing constraints for the insns in the pending list. */
- int tick;
+static struct spec_info_def spec_info_var;
+/* Description of the speculative part of the scheduling.
+ If NULL - no speculation. */
+spec_info_t spec_info = NULL;
- short cost;
+/* True, if recovery block was added during scheduling of current block.
+ Used to determine, if we need to fix INSN_TICKs. */
+static bool haifa_recovery_bb_recently_added_p;
- /* An encoding of the function units used. */
- short units;
+/* True, if recovery block was added during this scheduling pass.
+ Used to determine if we should have empty memory pools of dependencies
+ after finishing current region. */
+bool haifa_recovery_bb_ever_added_p;
- /* This weight is an estimation of the insn's contribution to
- register pressure. */
- short reg_weight;
+/* Counters of different types of speculative instructions. */
+static int nr_begin_data, nr_be_in_data, nr_begin_control, nr_be_in_control;
- /* Some insns (e.g. call) are not allowed to move across blocks. */
- unsigned int cant_move : 1;
+/* Array used in {unlink, restore}_bb_notes. */
+static rtx *bb_header = 0;
- /* Set if there's DEF-USE dependance between some speculatively
- moved load insn and this one. */
- unsigned int fed_by_spec_load : 1;
- unsigned int is_load_insn : 1;
-};
+/* Basic block after which recovery blocks will be created. */
+static basic_block before_recovery;
-static struct haifa_insn_data *h_i_d;
-
-#define INSN_DEPEND(INSN) (h_i_d[INSN_UID (INSN)].depend)
-#define INSN_LUID(INSN) (h_i_d[INSN_UID (INSN)].luid)
-#define INSN_PRIORITY(INSN) (h_i_d[INSN_UID (INSN)].priority)
-#define INSN_DEP_COUNT(INSN) (h_i_d[INSN_UID (INSN)].dep_count)
-#define INSN_COST(INSN) (h_i_d[INSN_UID (INSN)].cost)
-#define INSN_UNIT(INSN) (h_i_d[INSN_UID (INSN)].units)
-#define INSN_REG_WEIGHT(INSN) (h_i_d[INSN_UID (INSN)].reg_weight)
-
-#define INSN_BLOCKAGE(INSN) (h_i_d[INSN_UID (INSN)].blockage)
-#define UNIT_BITS 5
-#define BLOCKAGE_MASK ((1 << BLOCKAGE_BITS) - 1)
-#define ENCODE_BLOCKAGE(U, R) \
- (((U) << BLOCKAGE_BITS \
- | MIN_BLOCKAGE_COST (R)) << BLOCKAGE_BITS \
- | MAX_BLOCKAGE_COST (R))
-#define UNIT_BLOCKED(B) ((B) >> (2 * BLOCKAGE_BITS))
-#define BLOCKAGE_RANGE(B) \
- (((((B) >> BLOCKAGE_BITS) & BLOCKAGE_MASK) << (HOST_BITS_PER_INT / 2)) \
- | ((B) & BLOCKAGE_MASK))
-
-/* Encodings of the `<name>_unit_blockage_range' function. */
-#define MIN_BLOCKAGE_COST(R) ((R) >> (HOST_BITS_PER_INT / 2))
-#define MAX_BLOCKAGE_COST(R) ((R) & ((1 << (HOST_BITS_PER_INT / 2)) - 1))
-
-#define DONE_PRIORITY -1
-#define MAX_PRIORITY 0x7fffffff
-#define TAIL_PRIORITY 0x7ffffffe
-#define LAUNCH_PRIORITY 0x7f000001
-#define DONE_PRIORITY_P(INSN) (INSN_PRIORITY (INSN) < 0)
-#define LOW_PRIORITY_P(INSN) ((INSN_PRIORITY (INSN) & 0x7f000000) == 0)
-
-#define INSN_REF_COUNT(INSN) (h_i_d[INSN_UID (INSN)].ref_count)
-#define LINE_NOTE(INSN) (h_i_d[INSN_UID (INSN)].line_note)
-#define INSN_TICK(INSN) (h_i_d[INSN_UID (INSN)].tick)
-#define CANT_MOVE(insn) (h_i_d[INSN_UID (insn)].cant_move)
-#define FED_BY_SPEC_LOAD(insn) (h_i_d[INSN_UID (insn)].fed_by_spec_load)
-#define IS_LOAD_INSN(insn) (h_i_d[INSN_UID (insn)].is_load_insn)
-
-/* Vector indexed by basic block number giving the starting line-number
- for each basic block. */
-static rtx *line_note_head;
+/* Basic block just before the EXIT_BLOCK and after recovery, if we have
+ created it. */
+basic_block after_recovery;
-/* List of important notes we must keep around. This is a pointer to the
- last element in the list. */
-static rtx note_list;
+/* FALSE if we add bb to another region, so we don't need to initialize it. */
+bool adding_bb_to_current_region_p = true;
/* Queues, etc. */
"Pending" list have their dependencies satisfied and move to either
the "Ready" list or the "Queued" set depending on whether
sufficient time has passed to make them ready. As time passes,
- insns move from the "Queued" set to the "Ready" list. Insns may
- move from the "Ready" list to the "Queued" set if they are blocked
- due to a function unit conflict.
+ insns move from the "Queued" set to the "Ready" list.
- The "Pending" list (P) are the insns in the INSN_DEPEND of the unscheduled
- insns, i.e., those that are ready, queued, and pending.
+ The "Pending" list (P) are the insns in the INSN_FORW_DEPS of the
+ unscheduled insns, i.e., those that are ready, queued, and pending.
The "Queued" set (Q) is implemented by the variable `insn_queue'.
The "Ready" list (R) is implemented by the variables `ready' and
`n_ready'.
The transition (R->S) is implemented in the scheduling loop in
`schedule_block' when the best insn to schedule is chosen.
- The transition (R->Q) is implemented in `queue_insn' when an
- insn is found to have a function unit conflict with the already
- committed insns.
The transitions (P->R and P->Q) are implemented in `schedule_insn' as
insns move from the ready list to the scheduled list.
The transition (Q->R) is implemented in 'queue_to_insn' as time
passes or stalls are introduced. */
/* Implement a circular buffer to delay instructions until sufficient
- time has passed. INSN_QUEUE_SIZE is a power of two larger than
- MAX_BLOCKAGE and MAX_READY_COST computed by genattr.c. This is the
- longest time an isnsn may be queued. */
-static rtx insn_queue[INSN_QUEUE_SIZE];
+ time has passed. For the new pipeline description interface,
+ MAX_INSN_QUEUE_INDEX is a power of two minus one which is not less
+ than maximal time of instruction execution computed by genattr.c on
+ the base maximal time of functional unit reservations and getting a
+ result. This is the longest time an insn may be queued. */
+
+static rtx *insn_queue;
static int q_ptr = 0;
static int q_size = 0;
-#define NEXT_Q(X) (((X)+1) & (INSN_QUEUE_SIZE-1))
-#define NEXT_Q_AFTER(X, C) (((X)+C) & (INSN_QUEUE_SIZE-1))
-
-/* Forward declarations. */
-static void add_dependence PROTO ((rtx, rtx, enum reg_note));
-#ifdef HAVE_cc0
-static void remove_dependence PROTO ((rtx, rtx));
-#endif
-static rtx find_insn_list PROTO ((rtx, rtx));
-static int insn_unit PROTO ((rtx));
-static unsigned int blockage_range PROTO ((int, rtx));
-static void clear_units PROTO ((void));
-static int actual_hazard_this_instance PROTO ((int, int, rtx, int, int));
-static void schedule_unit PROTO ((int, rtx, int));
-static int actual_hazard PROTO ((int, rtx, int, int));
-static int potential_hazard PROTO ((int, rtx, int));
-static int insn_cost PROTO ((rtx, rtx, rtx));
-static int priority PROTO ((rtx));
-static void free_pending_lists PROTO ((void));
-static void add_insn_mem_dependence PROTO ((struct deps *, rtx *, rtx *, rtx,
- rtx));
-static void flush_pending_lists PROTO ((struct deps *, rtx, int));
-static void sched_analyze_1 PROTO ((struct deps *, rtx, rtx));
-static void sched_analyze_2 PROTO ((struct deps *, rtx, rtx));
-static void sched_analyze_insn PROTO ((struct deps *, rtx, rtx, rtx));
-static void sched_analyze PROTO ((struct deps *, rtx, rtx));
-static int rank_for_schedule PROTO ((const PTR, const PTR));
-static void swap_sort PROTO ((rtx *, int));
-static void queue_insn PROTO ((rtx, int));
-static int schedule_insn PROTO ((rtx, rtx *, int, int));
-static void find_insn_reg_weight PROTO ((int));
-static int schedule_block PROTO ((int, int));
-static char *safe_concat PROTO ((char *, char *, const char *));
-static int insn_issue_delay PROTO ((rtx));
-static void adjust_priority PROTO ((rtx));
-
-/* Control flow graph edges are kept in circular lists. */
-typedef struct
- {
- int from_block;
- int to_block;
- int next_in;
- int next_out;
- }
-haifa_edge;
-static haifa_edge *edge_table;
-
-#define NEXT_IN(edge) (edge_table[edge].next_in)
-#define NEXT_OUT(edge) (edge_table[edge].next_out)
-#define FROM_BLOCK(edge) (edge_table[edge].from_block)
-#define TO_BLOCK(edge) (edge_table[edge].to_block)
-
-/* Number of edges in the control flow graph. (In fact, larger than
- that by 1, since edge 0 is unused.) */
-static int nr_edges;
-
-/* Circular list of incoming/outgoing edges of a block. */
-static int *in_edges;
-static int *out_edges;
-
-#define IN_EDGES(block) (in_edges[block])
-#define OUT_EDGES(block) (out_edges[block])
-
-
-
-static int is_cfg_nonregular PROTO ((void));
-static int build_control_flow PROTO ((struct edge_list *));
-static void new_edge PROTO ((int, int));
-
-
-/* A region is the main entity for interblock scheduling: insns
- are allowed to move between blocks in the same region, along
- control flow graph edges, in the 'up' direction. */
-typedef struct
- {
- int rgn_nr_blocks; /* Number of blocks in region. */
- int rgn_blocks; /* cblocks in the region (actually index in rgn_bb_table). */
- }
-region;
-
-/* Number of regions in the procedure. */
-static int nr_regions;
-
-/* Table of region descriptions. */
-static region *rgn_table;
+#define NEXT_Q(X) (((X)+1) & max_insn_queue_index)
+#define NEXT_Q_AFTER(X, C) (((X)+C) & max_insn_queue_index)
-/* Array of lists of regions' blocks. */
-static int *rgn_bb_table;
+#define QUEUE_SCHEDULED (-3)
+#define QUEUE_NOWHERE (-2)
+#define QUEUE_READY (-1)
+/* QUEUE_SCHEDULED - INSN is scheduled.
+ QUEUE_NOWHERE - INSN isn't scheduled yet and is neither in
+ queue or ready list.
+ QUEUE_READY - INSN is in ready list.
+ N >= 0 - INSN queued for X [where NEXT_Q_AFTER (q_ptr, X) == N] cycles. */
-/* Topological order of blocks in the region (if b2 is reachable from
- b1, block_to_bb[b2] > block_to_bb[b1]). Note: A basic block is
- always referred to by either block or b, while its topological
- order name (in the region) is refered to by bb. */
-static int *block_to_bb;
+#define QUEUE_INDEX(INSN) (HID (INSN)->queue_index)
-/* The number of the region containing a block. */
-static int *containing_rgn;
+/* The following variable value refers for all current and future
+ reservations of the processor units. */
+state_t curr_state;
-#define RGN_NR_BLOCKS(rgn) (rgn_table[rgn].rgn_nr_blocks)
-#define RGN_BLOCKS(rgn) (rgn_table[rgn].rgn_blocks)
-#define BLOCK_TO_BB(block) (block_to_bb[block])
-#define CONTAINING_RGN(block) (containing_rgn[block])
+/* The following variable value is size of memory representing all
+ current and future reservations of the processor units. */
+size_t dfa_state_size;
-void debug_regions PROTO ((void));
-static void find_single_block_region PROTO ((void));
-static void find_rgns PROTO ((struct edge_list *, sbitmap *));
-static int too_large PROTO ((int, int *, int *));
+/* The following array is used to find the best insn from ready when
+ the automaton pipeline interface is used. */
+char *ready_try = NULL;
-extern void debug_live PROTO ((int, int));
+/* The ready list. */
+struct ready_list ready = {NULL, 0, 0, 0, 0};
-/* Blocks of the current region being scheduled. */
-static int current_nr_blocks;
-static int current_blocks;
+/* The pointer to the ready list (to be removed). */
+static struct ready_list *readyp = &ready;
-/* The mapping from bb to block. */
-#define BB_TO_BLOCK(bb) (rgn_bb_table[current_blocks + (bb)])
-
-
-/* Bit vectors and bitset operations are needed for computations on
- the control flow graph. */
+/* Scheduling clock. */
+static int clock_var;
-typedef unsigned HOST_WIDE_INT *bitset;
-typedef struct
- {
- int *first_member; /* Pointer to the list start in bitlst_table. */
- int nr_members; /* The number of members of the bit list. */
- }
-bitlst;
+static int may_trap_exp (const_rtx, int);
-static int bitlst_table_last;
-static int bitlst_table_size;
-static int *bitlst_table;
+/* Nonzero iff the address is comprised from at most 1 register. */
+#define CONST_BASED_ADDRESS_P(x) \
+ (REG_P (x) \
+ || ((GET_CODE (x) == PLUS || GET_CODE (x) == MINUS \
+ || (GET_CODE (x) == LO_SUM)) \
+ && (CONSTANT_P (XEXP (x, 0)) \
+ || CONSTANT_P (XEXP (x, 1)))))
-static char bitset_member PROTO ((bitset, int, int));
-static void extract_bitlst PROTO ((bitset, int, bitlst *));
+/* Returns a class that insn with GET_DEST(insn)=x may belong to,
+ as found by analyzing insn's expression. */
-/* Target info declarations.
+\f
+static int haifa_luid_for_non_insn (rtx x);
- The block currently being scheduled is referred to as the "target" block,
- while other blocks in the region from which insns can be moved to the
- target are called "source" blocks. The candidate structure holds info
- about such sources: are they valid? Speculative? Etc. */
-typedef bitlst bblst;
-typedef struct
+/* Haifa version of sched_info hooks common to all headers. */
+const struct common_sched_info_def haifa_common_sched_info =
{
- char is_valid;
- char is_speculative;
- int src_prob;
- bblst split_bbs;
- bblst update_bbs;
- }
-candidate;
-
-static candidate *candidate_table;
-
-/* A speculative motion requires checking live information on the path
- from 'source' to 'target'. The split blocks are those to be checked.
- After a speculative motion, live information should be modified in
- the 'update' blocks.
+ NULL, /* fix_recovery_cfg */
+ NULL, /* add_block */
+ NULL, /* estimate_number_of_insns */
+ haifa_luid_for_non_insn, /* luid_for_non_insn */
+ SCHED_PASS_UNKNOWN /* sched_pass_id */
+ };
- Lists of split and update blocks for each candidate of the current
- target are in array bblst_table. */
-static int *bblst_table, bblst_size, bblst_last;
+const struct sched_scan_info_def *sched_scan_info;
-#define IS_VALID(src) ( candidate_table[src].is_valid )
-#define IS_SPECULATIVE(src) ( candidate_table[src].is_speculative )
-#define SRC_PROB(src) ( candidate_table[src].src_prob )
+/* Mapping from instruction UID to its Logical UID. */
+VEC (int, heap) *sched_luids = NULL;
-/* The bb being currently scheduled. */
-static int target_bb;
+/* Next LUID to assign to an instruction. */
+int sched_max_luid = 1;
-/* List of edges. */
-typedef bitlst edgelst;
+/* Haifa Instruction Data. */
+VEC (haifa_insn_data_def, heap) *h_i_d = NULL;
-/* Target info functions. */
-static void split_edges PROTO ((int, int, edgelst *));
-static void compute_trg_info PROTO ((int));
-void debug_candidate PROTO ((int));
-void debug_candidates PROTO ((int));
+void (* sched_init_only_bb) (basic_block, basic_block);
+/* Split block function. Different schedulers might use different functions
+ to handle their internal data consistent. */
+basic_block (* sched_split_block) (basic_block, rtx);
-/* Bit-set of bbs, where bit 'i' stands for bb 'i'. */
-typedef bitset bbset;
+/* Create empty basic block after the specified block. */
+basic_block (* sched_create_empty_bb) (basic_block);
-/* Number of words of the bbset. */
-static int bbset_size;
-
-/* Dominators array: dom[i] contains the bbset of dominators of
- bb i in the region. */
-static bbset *dom;
-
-/* bb 0 is the only region entry. */
-#define IS_RGN_ENTRY(bb) (!bb)
-
-/* Is bb_src dominated by bb_trg. */
-#define IS_DOMINATED(bb_src, bb_trg) \
-( bitset_member (dom[bb_src], bb_trg, bbset_size) )
-
-/* Probability: Prob[i] is a float in [0, 1] which is the probability
- of bb i relative to the region entry. */
-static float *prob;
-
-/* The probability of bb_src, relative to bb_trg. Note, that while the
- 'prob[bb]' is a float in [0, 1], this macro returns an integer
- in [0, 100]. */
-#define GET_SRC_PROB(bb_src, bb_trg) ((int) (100.0 * (prob[bb_src] / \
- prob[bb_trg])))
-
-/* Bit-set of edges, where bit i stands for edge i. */
-typedef bitset edgeset;
-
-/* Number of edges in the region. */
-static int rgn_nr_edges;
+static int
+may_trap_exp (const_rtx x, int is_store)
+{
+ enum rtx_code code;
-/* Array of size rgn_nr_edges. */
-static int *rgn_edges;
+ if (x == 0)
+ return TRAP_FREE;
+ code = GET_CODE (x);
+ if (is_store)
+ {
+ if (code == MEM && may_trap_p (x))
+ return TRAP_RISKY;
+ else
+ return TRAP_FREE;
+ }
+ if (code == MEM)
+ {
+ /* The insn uses memory: a volatile load. */
+ if (MEM_VOLATILE_P (x))
+ return IRISKY;
+ /* An exception-free load. */
+ if (!may_trap_p (x))
+ return IFREE;
+ /* A load with 1 base register, to be further checked. */
+ if (CONST_BASED_ADDRESS_P (XEXP (x, 0)))
+ return PFREE_CANDIDATE;
+ /* No info on the load, to be further checked. */
+ return PRISKY_CANDIDATE;
+ }
+ else
+ {
+ const char *fmt;
+ int i, insn_class = TRAP_FREE;
-/* Number of words in an edgeset. */
-static int edgeset_size;
+ /* Neither store nor load, check if it may cause a trap. */
+ if (may_trap_p (x))
+ return TRAP_RISKY;
+ /* Recursive step: walk the insn... */
+ fmt = GET_RTX_FORMAT (code);
+ for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
+ {
+ if (fmt[i] == 'e')
+ {
+ int tmp_class = may_trap_exp (XEXP (x, i), is_store);
+ insn_class = WORST_CLASS (insn_class, tmp_class);
+ }
+ else if (fmt[i] == 'E')
+ {
+ int j;
+ for (j = 0; j < XVECLEN (x, i); j++)
+ {
+ int tmp_class = may_trap_exp (XVECEXP (x, i, j), is_store);
+ insn_class = WORST_CLASS (insn_class, tmp_class);
+ if (insn_class == TRAP_RISKY || insn_class == IRISKY)
+ break;
+ }
+ }
+ if (insn_class == TRAP_RISKY || insn_class == IRISKY)
+ break;
+ }
+ return insn_class;
+ }
+}
-/* Mapping from each edge in the graph to its number in the rgn. */
-static int *edge_to_bit;
-#define EDGE_TO_BIT(edge) (edge_to_bit[edge])
+/* Classifies rtx X of an insn for the purpose of verifying that X can be
+ executed speculatively (and consequently the insn can be moved
+ speculatively), by examining X, returning:
+ TRAP_RISKY: store, or risky non-load insn (e.g. division by variable).
+ TRAP_FREE: non-load insn.
+ IFREE: load from a globally safe location.
+ IRISKY: volatile load.
+ PFREE_CANDIDATE, PRISKY_CANDIDATE: load that need to be checked for
+ being either PFREE or PRISKY. */
-/* The split edges of a source bb is different for each target
- bb. In order to compute this efficiently, the 'potential-split edges'
- are computed for each bb prior to scheduling a region. This is actually
- the split edges of each bb relative to the region entry.
+static int
+haifa_classify_rtx (const_rtx x)
+{
+ int tmp_class = TRAP_FREE;
+ int insn_class = TRAP_FREE;
+ enum rtx_code code;
- pot_split[bb] is the set of potential split edges of bb. */
-static edgeset *pot_split;
+ if (GET_CODE (x) == PARALLEL)
+ {
+ int i, len = XVECLEN (x, 0);
-/* For every bb, a set of its ancestor edges. */
-static edgeset *ancestor_edges;
+ for (i = len - 1; i >= 0; i--)
+ {
+ tmp_class = haifa_classify_rtx (XVECEXP (x, 0, i));
+ insn_class = WORST_CLASS (insn_class, tmp_class);
+ if (insn_class == TRAP_RISKY || insn_class == IRISKY)
+ break;
+ }
+ }
+ else
+ {
+ code = GET_CODE (x);
+ switch (code)
+ {
+ case CLOBBER:
+ /* Test if it is a 'store'. */
+ tmp_class = may_trap_exp (XEXP (x, 0), 1);
+ break;
+ case SET:
+ /* Test if it is a store. */
+ tmp_class = may_trap_exp (SET_DEST (x), 1);
+ if (tmp_class == TRAP_RISKY)
+ break;
+ /* Test if it is a load. */
+ tmp_class =
+ WORST_CLASS (tmp_class,
+ may_trap_exp (SET_SRC (x), 0));
+ break;
+ case COND_EXEC:
+ tmp_class = haifa_classify_rtx (COND_EXEC_CODE (x));
+ if (tmp_class == TRAP_RISKY)
+ break;
+ tmp_class = WORST_CLASS (tmp_class,
+ may_trap_exp (COND_EXEC_TEST (x), 0));
+ break;
+ case TRAP_IF:
+ tmp_class = TRAP_RISKY;
+ break;
+ default:;
+ }
+ insn_class = tmp_class;
+ }
-static void compute_dom_prob_ps PROTO ((int));
+ return insn_class;
+}
-#define ABS_VALUE(x) (((x)<0)?(-(x)):(x))
-#define INSN_PROBABILITY(INSN) (SRC_PROB (BLOCK_TO_BB (BLOCK_NUM (INSN))))
-#define IS_SPECULATIVE_INSN(INSN) (IS_SPECULATIVE (BLOCK_TO_BB (BLOCK_NUM (INSN))))
-#define INSN_BB(INSN) (BLOCK_TO_BB (BLOCK_NUM (INSN)))
+int
+haifa_classify_insn (const_rtx insn)
+{
+ return haifa_classify_rtx (PATTERN (insn));
+}
-/* Parameters affecting the decision of rank_for_schedule(). */
-#define MIN_DIFF_PRIORITY 2
-#define MIN_PROBABILITY 40
-#define MIN_PROB_DIFF 10
+/* Forward declarations. */
-/* Speculative scheduling functions. */
-static int check_live_1 PROTO ((int, rtx));
-static void update_live_1 PROTO ((int, rtx));
-static int check_live PROTO ((rtx, int));
-static void update_live PROTO ((rtx, int));
-static void set_spec_fed PROTO ((rtx));
-static int is_pfree PROTO ((rtx, int, int));
-static int find_conditional_protection PROTO ((rtx, int));
-static int is_conditionally_protected PROTO ((rtx, int, int));
-static int may_trap_exp PROTO ((rtx, int));
-static int haifa_classify_insn PROTO ((rtx));
-static int is_prisky PROTO ((rtx, int, int));
-static int is_exception_free PROTO ((rtx, int, int));
+static int priority (rtx);
+static int rank_for_schedule (const void *, const void *);
+static void swap_sort (rtx *, int);
+static void queue_insn (rtx, int);
+static int schedule_insn (rtx);
+static void adjust_priority (rtx);
+static void advance_one_cycle (void);
+static void extend_h_i_d (void);
-static char find_insn_mem_list PROTO ((rtx, rtx, rtx, rtx));
-static void compute_block_forward_dependences PROTO ((int));
-static void add_branch_dependences PROTO ((rtx, rtx));
-static void compute_block_backward_dependences PROTO ((int));
-void debug_dependencies PROTO ((void));
/* Notes handling mechanism:
=========================
Generally, NOTES are saved before scheduling and restored after scheduling.
- The scheduler distinguishes between three types of notes:
+ The scheduler distinguishes between two types of notes:
- (1) LINE_NUMBER notes, generated and used for debugging. Here,
- before scheduling a region, a pointer to the LINE_NUMBER note is
- added to the insn following it (in save_line_notes()), and the note
- is removed (in rm_line_notes() and unlink_line_notes()). After
- scheduling the region, this pointer is used for regeneration of
- the LINE_NUMBER note (in restore_line_notes()).
-
- (2) LOOP_BEGIN, LOOP_END, SETJMP, EHREGION_BEG, EHREGION_END notes:
+ (1) LOOP_BEGIN, LOOP_END, SETJMP, EHREGION_BEG, EHREGION_END notes:
Before scheduling a region, a pointer to the note is added to the insn
that follows or precedes it. (This happens as part of the data dependence
computation). After scheduling an insn, the pointer contained in it is
used for regenerating the corresponding note (in reemit_notes).
- (3) All other notes (e.g. INSN_DELETED): Before scheduling a block,
+ (2) All other notes (e.g. INSN_DELETED): Before scheduling a block,
these notes are put in a list (in rm_other_notes() and
unlink_other_notes ()). After scheduling the block, these notes are
inserted at the beginning of the block (in schedule_block()). */
-static rtx unlink_other_notes PROTO ((rtx, rtx));
-static rtx unlink_line_notes PROTO ((rtx, rtx));
-static void rm_line_notes PROTO ((int));
-static void save_line_notes PROTO ((int));
-static void restore_line_notes PROTO ((int));
-static void rm_redundant_line_notes PROTO ((void));
-static void rm_other_notes PROTO ((rtx, rtx));
-static rtx reemit_notes PROTO ((rtx, rtx));
-
-static void get_block_head_tail PROTO ((int, rtx *, rtx *));
-static void get_bb_head_tail PROTO ((int, rtx *, rtx *));
-
-static int queue_to_ready PROTO ((rtx [], int));
-
-static void debug_ready_list PROTO ((rtx[], int));
-static void init_target_units PROTO ((void));
-static void insn_print_units PROTO ((rtx));
-static int get_visual_tbl_length PROTO ((void));
-static void init_block_visualization PROTO ((void));
-static void print_block_visualization PROTO ((int, const char *));
-static void visualize_scheduled_insns PROTO ((int, int));
-static void visualize_no_unit PROTO ((rtx));
-static void visualize_stall_cycles PROTO ((int, int));
-static void print_exp PROTO ((char *, rtx, int));
-static void print_value PROTO ((char *, rtx, int));
-static void print_pattern PROTO ((char *, rtx, int));
-static void print_insn PROTO ((char *, rtx, int));
-void debug_reg_vector PROTO ((regset));
-
-static rtx move_insn1 PROTO ((rtx, rtx));
-static rtx move_insn PROTO ((rtx, rtx));
-static rtx group_leader PROTO ((rtx));
-static int set_priorities PROTO ((int));
-static void init_deps PROTO ((struct deps *));
-static void schedule_region PROTO ((int));
+static void ready_add (struct ready_list *, rtx, bool);
+static rtx ready_remove_first (struct ready_list *);
+
+static void queue_to_ready (struct ready_list *);
+static int early_queue_to_ready (state_t, struct ready_list *);
+
+static void debug_ready_list (struct ready_list *);
+
+/* The following functions are used to implement multi-pass scheduling
+ on the first cycle. */
+static rtx ready_remove (struct ready_list *, int);
+static void ready_remove_insn (rtx);
+
+static int choose_ready (struct ready_list *, rtx *);
+
+static void fix_inter_tick (rtx, rtx);
+static int fix_tick_ready (rtx);
+static void change_queue_index (rtx, int);
+
+/* The following functions are used to implement scheduling of data/control
+ speculative instructions. */
+
+static void extend_h_i_d (void);
+static void init_h_i_d (rtx);
+static void generate_recovery_code (rtx);
+static void process_insn_forw_deps_be_in_spec (rtx, rtx, ds_t);
+static void begin_speculative_block (rtx);
+static void add_to_speculative_block (rtx);
+static void init_before_recovery (basic_block *);
+static void create_check_block_twin (rtx, bool);
+static void fix_recovery_deps (basic_block);
+static void haifa_change_pattern (rtx, rtx);
+static void dump_new_block_header (int, basic_block, rtx, rtx);
+static void restore_bb_notes (basic_block);
+static void fix_jump_move (rtx);
+static void move_block_after_check (rtx);
+static void move_succs (VEC(edge,gc) **, basic_block);
+static void sched_remove_insn (rtx);
+static void clear_priorities (rtx, rtx_vec_t *);
+static void calc_priorities (rtx_vec_t);
+static void add_jump_dependencies (rtx, rtx);
+#ifdef ENABLE_CHECKING
+static int has_edge_p (VEC(edge,gc) *, int);
+static void check_cfg (rtx, rtx);
+#endif
#endif /* INSN_SCHEDULING */
\f
-#define SIZE_FOR_MODE(X) (GET_MODE_SIZE (GET_MODE (X)))
-
-/* Add ELEM wrapped in an INSN_LIST with reg note kind DEP_TYPE to the
- LOG_LINKS of INSN, if not already there. DEP_TYPE indicates the type
- of dependence that this link represents. */
-
-static void
-add_dependence (insn, elem, dep_type)
- rtx insn;
- rtx elem;
- enum reg_note dep_type;
+/* Point to state used for the current scheduling pass. */
+struct haifa_sched_info *current_sched_info;
+\f
+#ifndef INSN_SCHEDULING
+void
+schedule_insns (void)
{
- rtx link, next;
-
- /* Don't depend an insn on itself. */
- if (insn == elem)
- return;
-
- /* We can get a dependency on deleted insns due to optimizations in
- the register allocation and reloading or due to splitting. Any
- such dependency is useless and can be ignored. */
- if (GET_CODE (elem) == NOTE)
- return;
-
- /* If elem is part of a sequence that must be scheduled together, then
- make the dependence point to the last insn of the sequence.
- When HAVE_cc0, it is possible for NOTEs to exist between users and
- setters of the condition codes, so we must skip past notes here.
- Otherwise, NOTEs are impossible here. */
-
- next = NEXT_INSN (elem);
-
-#ifdef HAVE_cc0
- while (next && GET_CODE (next) == NOTE)
- next = NEXT_INSN (next);
-#endif
-
- if (next && SCHED_GROUP_P (next)
- && GET_CODE (next) != CODE_LABEL)
- {
- /* Notes will never intervene here though, so don't bother checking
- for them. */
- /* We must reject CODE_LABELs, so that we don't get confused by one
- that has LABEL_PRESERVE_P set, which is represented by the same
- bit in the rtl as SCHED_GROUP_P. A CODE_LABEL can never be
- SCHED_GROUP_P. */
- while (NEXT_INSN (next) && SCHED_GROUP_P (NEXT_INSN (next))
- && GET_CODE (NEXT_INSN (next)) != CODE_LABEL)
- next = NEXT_INSN (next);
-
- /* Again, don't depend an insn on itself. */
- if (insn == next)
- return;
-
- /* Make the dependence to NEXT, the last insn of the group, instead
- of the original ELEM. */
- elem = next;
- }
+}
+#else
-#ifdef INSN_SCHEDULING
- /* (This code is guarded by INSN_SCHEDULING, otherwise INSN_BB is undefined.)
- No need for interblock dependences with calls, since
- calls are not moved between blocks. Note: the edge where
- elem is a CALL is still required. */
- if (GET_CODE (insn) == CALL_INSN
- && (INSN_BB (elem) != INSN_BB (insn)))
- return;
+/* Do register pressure sensitive insn scheduling if the flag is set
+ up. */
+bool sched_pressure_p;
+/* Map regno -> its cover class. The map defined only when
+ SCHED_PRESSURE_P is true. */
+enum reg_class *sched_regno_cover_class;
- /* If we already have a true dependency for ELEM, then we do not
- need to do anything. Avoiding the list walk below can cut
- compile times dramatically for some code. */
- if (true_dependency_cache
- && TEST_BIT (true_dependency_cache[INSN_LUID (insn)], INSN_LUID (elem)))
- return;
-#endif
+/* The current register pressure. Only elements corresponding cover
+ classes are defined. */
+static int curr_reg_pressure[N_REG_CLASSES];
- /* Check that we don't already have this dependence. */
- for (link = LOG_LINKS (insn); link; link = XEXP (link, 1))
- if (XEXP (link, 0) == elem)
- {
- /* If this is a more restrictive type of dependence than the existing
- one, then change the existing dependence to this type. */
- if ((int) dep_type < (int) REG_NOTE_KIND (link))
- PUT_REG_NOTE_KIND (link, dep_type);
+/* Saved value of the previous array. */
+static int saved_reg_pressure[N_REG_CLASSES];
-#ifdef INSN_SCHEDULING
- /* If we are adding a true dependency to INSN's LOG_LINKs, then
- note that in the bitmap cache of true dependency information. */
- if ((int)dep_type == 0 && true_dependency_cache)
- SET_BIT (true_dependency_cache[INSN_LUID (insn)], INSN_LUID (elem));
-#endif
- return;
- }
- /* Might want to check one level of transitivity to save conses. */
+/* Register living at given scheduling point. */
+static bitmap curr_reg_live;
- link = alloc_INSN_LIST (elem, LOG_LINKS (insn));
- LOG_LINKS (insn) = link;
+/* Saved value of the previous array. */
+static bitmap saved_reg_live;
- /* Insn dependency, not data dependency. */
- PUT_REG_NOTE_KIND (link, dep_type);
+/* Registers mentioned in the current region. */
+static bitmap region_ref_regs;
-#ifdef INSN_SCHEDULING
- /* If we are adding a true dependency to INSN's LOG_LINKs, then
- note that in the bitmap cache of true dependency information. */
- if ((int)dep_type == 0 && true_dependency_cache)
- SET_BIT (true_dependency_cache[INSN_LUID (insn)], INSN_LUID (elem));
-#endif
+/* Initiate register pressure relative info for scheduling the current
+ region. Currently it is only clearing register mentioned in the
+ current region. */
+void
+sched_init_region_reg_pressure_info (void)
+{
+ bitmap_clear (region_ref_regs);
}
-#ifdef HAVE_cc0
-/* Remove ELEM wrapped in an INSN_LIST from the LOG_LINKS
- of INSN. Abort if not found. */
-
+/* Update current register pressure related info after birth (if
+ BIRTH_P) or death of register REGNO. */
static void
-remove_dependence (insn, elem)
- rtx insn;
- rtx elem;
+mark_regno_birth_or_death (int regno, bool birth_p)
{
- rtx prev, link, next;
- int found = 0;
+ enum reg_class cover_class;
- for (prev = 0, link = LOG_LINKS (insn); link; link = next)
+ cover_class = sched_regno_cover_class[regno];
+ if (regno >= FIRST_PSEUDO_REGISTER)
{
- next = XEXP (link, 1);
- if (XEXP (link, 0) == elem)
+ if (cover_class != NO_REGS)
{
- if (prev)
- XEXP (prev, 1) = next;
+ if (birth_p)
+ {
+ bitmap_set_bit (curr_reg_live, regno);
+ curr_reg_pressure[cover_class]
+ += ira_reg_class_nregs[cover_class][PSEUDO_REGNO_MODE (regno)];
+ }
else
- LOG_LINKS (insn) = next;
-
-#ifdef INSN_SCHEDULING
- /* If we are removing a true dependency from the LOG_LINKS list,
- make sure to remove it from the cache too. */
- if (REG_NOTE_KIND (link) == 0 && true_dependency_cache)
- RESET_BIT (true_dependency_cache[INSN_LUID (insn)],
- INSN_LUID (elem));
-#endif
-
- free_INSN_LIST_node (link);
-
- found = 1;
+ {
+ bitmap_clear_bit (curr_reg_live, regno);
+ curr_reg_pressure[cover_class]
+ -= ira_reg_class_nregs[cover_class][PSEUDO_REGNO_MODE (regno)];
+ }
+ }
+ }
+ else if (cover_class != NO_REGS
+ && ! TEST_HARD_REG_BIT (ira_no_alloc_regs, regno))
+ {
+ if (birth_p)
+ {
+ bitmap_set_bit (curr_reg_live, regno);
+ curr_reg_pressure[cover_class]++;
}
else
- prev = link;
+ {
+ bitmap_clear_bit (curr_reg_live, regno);
+ curr_reg_pressure[cover_class]--;
+ }
}
-
- if (!found)
- abort ();
- return;
}
-#endif /* HAVE_cc0 */
-\f
-#ifndef INSN_SCHEDULING
-void
-schedule_insns (dump_file)
- FILE *dump_file;
+
+/* Initiate current register pressure related info from living
+ registers given by LIVE. */
+static void
+initiate_reg_pressure_info (bitmap live)
{
+ int i;
+ unsigned int j;
+ bitmap_iterator bi;
+
+ for (i = 0; i < ira_reg_class_cover_size; i++)
+ curr_reg_pressure[ira_reg_class_cover[i]] = 0;
+ bitmap_clear (curr_reg_live);
+ EXECUTE_IF_SET_IN_BITMAP (live, 0, j, bi)
+ if (current_nr_blocks == 1 || bitmap_bit_p (region_ref_regs, j))
+ mark_regno_birth_or_death (j, true);
}
-#else
-#ifndef __GNUC__
-#define __inline
-#endif
-
-#ifndef HAIFA_INLINE
-#define HAIFA_INLINE __inline
-#endif
-
-/* Computation of memory dependencies. */
-/* Data structures for the computation of data dependences in a regions. We
- keep one mem_deps structure for every basic block. Before analyzing the
- data dependences for a bb, its variables are initialized as a function of
- the variables of its predecessors. When the analysis for a bb completes,
- we save the contents to the corresponding bb_mem_deps[bb] variable. */
+/* Mark registers in X as mentioned in the current region. */
+static void
+setup_ref_regs (rtx x)
+{
+ int i, j, regno;
+ const RTX_CODE code = GET_CODE (x);
+ const char *fmt;
-static struct deps *bb_deps;
+ if (REG_P (x))
+ {
+ regno = REGNO (x);
+ if (regno >= FIRST_PSEUDO_REGISTER)
+ bitmap_set_bit (region_ref_regs, REGNO (x));
+ else
+ for (i = hard_regno_nregs[regno][GET_MODE (x)] - 1; i >= 0; i--)
+ bitmap_set_bit (region_ref_regs, regno + i);
+ return;
+ }
+ fmt = GET_RTX_FORMAT (code);
+ for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
+ if (fmt[i] == 'e')
+ setup_ref_regs (XEXP (x, i));
+ else if (fmt[i] == 'E')
+ {
+ for (j = 0; j < XVECLEN (x, i); j++)
+ setup_ref_regs (XVECEXP (x, i, j));
+ }
+}
-/* Pointer to the last instruction scheduled. Used by rank_for_schedule,
- so that insns independent of the last scheduled insn will be preferred
- over dependent instructions. */
+/* Initiate current register pressure related info at the start of
+ basic block BB. */
+static void
+initiate_bb_reg_pressure_info (basic_block bb)
+{
+ unsigned int i;
+ rtx insn;
-static rtx last_scheduled_insn;
+ if (current_nr_blocks > 1)
+ FOR_BB_INSNS (bb, insn)
+ if (INSN_P (insn))
+ setup_ref_regs (PATTERN (insn));
+ initiate_reg_pressure_info (df_get_live_in (bb));
+#ifdef EH_RETURN_DATA_REGNO
+ if (bb_has_eh_pred (bb))
+ for (i = 0; ; ++i)
+ {
+ unsigned int regno = EH_RETURN_DATA_REGNO (i);
-/* Functions for construction of the control flow graph. */
+ if (regno == INVALID_REGNUM)
+ break;
+ if (! bitmap_bit_p (df_get_live_in (bb), regno))
+ mark_regno_birth_or_death (regno, true);
+ }
+#endif
+}
-/* Return 1 if control flow graph should not be constructed, 0 otherwise.
+/* Save current register pressure related info. */
+static void
+save_reg_pressure (void)
+{
+ int i;
- We decide not to build the control flow graph if there is possibly more
- than one entry to the function, if computed branches exist, of if we
- have nonlocal gotos. */
+ for (i = 0; i < ira_reg_class_cover_size; i++)
+ saved_reg_pressure[ira_reg_class_cover[i]]
+ = curr_reg_pressure[ira_reg_class_cover[i]];
+ bitmap_copy (saved_reg_live, curr_reg_live);
+}
-static int
-is_cfg_nonregular ()
+/* Restore saved register pressure related info. */
+static void
+restore_reg_pressure (void)
{
- int b;
- rtx insn;
- RTX_CODE code;
-
- /* If we have a label that could be the target of a nonlocal goto, then
- the cfg is not well structured. */
- if (nonlocal_goto_handler_labels)
- return 1;
-
- /* If we have any forced labels, then the cfg is not well structured. */
- if (forced_labels)
- return 1;
-
- /* If this function has a computed jump, then we consider the cfg
- not well structured. */
- if (current_function_has_computed_jump)
- return 1;
-
- /* If we have exception handlers, then we consider the cfg not well
- structured. ?!? We should be able to handle this now that flow.c
- computes an accurate cfg for EH. */
- if (exception_handler_labels)
- return 1;
-
- /* If we have non-jumping insns which refer to labels, then we consider
- the cfg not well structured. */
- /* Check for labels referred to other thn by jumps. */
- for (b = 0; b < n_basic_blocks; b++)
- for (insn = BLOCK_HEAD (b);; insn = NEXT_INSN (insn))
- {
- code = GET_CODE (insn);
- if (GET_RTX_CLASS (code) == 'i')
- {
- rtx note;
+ int i;
- for (note = REG_NOTES (insn); note; note = XEXP (note, 1))
- if (REG_NOTE_KIND (note) == REG_LABEL)
- return 1;
- }
+ for (i = 0; i < ira_reg_class_cover_size; i++)
+ curr_reg_pressure[ira_reg_class_cover[i]]
+ = saved_reg_pressure[ira_reg_class_cover[i]];
+ bitmap_copy (curr_reg_live, saved_reg_live);
+}
- if (insn == BLOCK_END (b))
- break;
- }
+/* Return TRUE if the register is dying after its USE. */
+static bool
+dying_use_p (struct reg_use_data *use)
+{
+ struct reg_use_data *next;
- /* All the tests passed. Consider the cfg well structured. */
- return 0;
+ for (next = use->next_regno_use; next != use; next = next->next_regno_use)
+ if (NONDEBUG_INSN_P (next->insn)
+ && QUEUE_INDEX (next->insn) != QUEUE_SCHEDULED)
+ return false;
+ return true;
}
-/* Build the control flow graph and set nr_edges.
+/* Print info about the current register pressure and its excess for
+ each cover class. */
+static void
+print_curr_reg_pressure (void)
+{
+ int i;
+ enum reg_class cl;
- Instead of trying to build a cfg ourselves, we rely on flow to
- do it for us. Stamp out useless code (and bug) duplication.
+ fprintf (sched_dump, ";;\t");
+ for (i = 0; i < ira_reg_class_cover_size; i++)
+ {
+ cl = ira_reg_class_cover[i];
+ gcc_assert (curr_reg_pressure[cl] >= 0);
+ fprintf (sched_dump, " %s:%d(%d)", reg_class_names[cl],
+ curr_reg_pressure[cl],
+ curr_reg_pressure[cl] - ira_available_class_regs[cl]);
+ }
+ fprintf (sched_dump, "\n");
+}
- Return nonzero if an irregularity in the cfg is found which would
- prevent cross block scheduling. */
+/* Pointer to the last instruction scheduled. Used by rank_for_schedule,
+ so that insns independent of the last scheduled insn will be preferred
+ over dependent instructions. */
-static int
-build_control_flow (edge_list)
- struct edge_list *edge_list;
-{
- int i, unreachable, num_edges;
+static rtx last_scheduled_insn;
- /* This already accounts for entry/exit edges. */
- num_edges = NUM_EDGES (edge_list);
+/* Cached cost of the instruction. Use below function to get cost of the
+ insn. -1 here means that the field is not initialized. */
+#define INSN_COST(INSN) (HID (INSN)->cost)
- /* Unreachable loops with more than one basic block are detected
- during the DFS traversal in find_rgns.
+/* Compute cost of executing INSN.
+ This is the number of cycles between instruction issue and
+ instruction results. */
+int
+insn_cost (rtx insn)
+{
+ int cost;
- Unreachable loops with a single block are detected here. This
- test is redundant with the one in find_rgns, but it's much
- cheaper to go ahead and catch the trivial case here. */
- unreachable = 0;
- for (i = 0; i < n_basic_blocks; i++)
+ if (sel_sched_p ())
{
- basic_block b = BASIC_BLOCK (i);
+ if (recog_memoized (insn) < 0)
+ return 0;
+
+ cost = insn_default_latency (insn);
+ if (cost < 0)
+ cost = 0;
- if (b->pred == NULL
- || (b->pred->src == b
- && b->pred->pred_next == NULL))
- unreachable = 1;
+ return cost;
}
- /* ??? We can kill these soon. */
- in_edges = (int *) xcalloc (n_basic_blocks, sizeof (int));
- out_edges = (int *) xcalloc (n_basic_blocks, sizeof (int));
- edge_table = (haifa_edge *) xcalloc (num_edges, sizeof (haifa_edge));
+ cost = INSN_COST (insn);
- nr_edges = 0;
- for (i = 0; i < num_edges; i++)
+ if (cost < 0)
{
- edge e = INDEX_EDGE (edge_list, i);
+ /* A USE insn, or something else we don't need to
+ understand. We can't pass these directly to
+ result_ready_cost or insn_default_latency because it will
+ trigger a fatal error for unrecognizable insns. */
+ if (recog_memoized (insn) < 0)
+ {
+ INSN_COST (insn) = 0;
+ return 0;
+ }
+ else
+ {
+ cost = insn_default_latency (insn);
+ if (cost < 0)
+ cost = 0;
- if (e->dest != EXIT_BLOCK_PTR
- && e->src != ENTRY_BLOCK_PTR)
- new_edge (e->src->index, e->dest->index);
+ INSN_COST (insn) = cost;
+ }
}
- /* Increment by 1, since edge 0 is unused. */
- nr_edges++;
-
- return unreachable;
+ return cost;
}
+/* Compute cost of dependence LINK.
+ This is the number of cycles between instruction issue and
+ instruction results.
+ ??? We also use this function to call recog_memoized on all insns. */
+int
+dep_cost_1 (dep_t link, dw_t dw)
+{
+ rtx insn = DEP_PRO (link);
+ rtx used = DEP_CON (link);
+ int cost;
+
+ /* A USE insn should never require the value used to be computed.
+ This allows the computation of a function's result and parameter
+ values to overlap the return and call. We don't care about the
+ the dependence cost when only decreasing register pressure. */
+ if (recog_memoized (used) < 0)
+ {
+ cost = 0;
+ recog_memoized (insn);
+ }
+ else
+ {
+ enum reg_note dep_type = DEP_TYPE (link);
-/* Record an edge in the control flow graph from SOURCE to TARGET.
+ cost = insn_cost (insn);
- In theory, this is redundant with the s_succs computed above, but
- we have not converted all of haifa to use information from the
- integer lists. */
+ if (INSN_CODE (insn) >= 0)
+ {
+ if (dep_type == REG_DEP_ANTI)
+ cost = 0;
+ else if (dep_type == REG_DEP_OUTPUT)
+ {
+ cost = (insn_default_latency (insn)
+ - insn_default_latency (used));
+ if (cost <= 0)
+ cost = 1;
+ }
+ else if (bypass_p (insn))
+ cost = insn_latency (insn, used);
+ }
-static void
-new_edge (source, target)
- int source, target;
-{
- int e, next_edge;
- int curr_edge, fst_edge;
- /* Check for duplicates. */
- fst_edge = curr_edge = OUT_EDGES (source);
- while (curr_edge)
- {
- if (FROM_BLOCK (curr_edge) == source
- && TO_BLOCK (curr_edge) == target)
+ if (targetm.sched.adjust_cost_2)
+ cost = targetm.sched.adjust_cost_2 (used, (int) dep_type, insn, cost,
+ dw);
+ else if (targetm.sched.adjust_cost != NULL)
{
- return;
- }
+ /* This variable is used for backward compatibility with the
+ targets. */
+ rtx dep_cost_rtx_link = alloc_INSN_LIST (NULL_RTX, NULL_RTX);
- curr_edge = NEXT_OUT (curr_edge);
+ /* Make it self-cycled, so that if some tries to walk over this
+ incomplete list he/she will be caught in an endless loop. */
+ XEXP (dep_cost_rtx_link, 1) = dep_cost_rtx_link;
- if (fst_edge == curr_edge)
- break;
- }
+ /* Targets use only REG_NOTE_KIND of the link. */
+ PUT_REG_NOTE_KIND (dep_cost_rtx_link, DEP_TYPE (link));
- e = ++nr_edges;
+ cost = targetm.sched.adjust_cost (used, dep_cost_rtx_link,
+ insn, cost);
- FROM_BLOCK (e) = source;
- TO_BLOCK (e) = target;
+ free_INSN_LIST_node (dep_cost_rtx_link);
+ }
- if (OUT_EDGES (source))
- {
- next_edge = NEXT_OUT (OUT_EDGES (source));
- NEXT_OUT (OUT_EDGES (source)) = e;
- NEXT_OUT (e) = next_edge;
- }
- else
- {
- OUT_EDGES (source) = e;
- NEXT_OUT (e) = e;
+ if (cost < 0)
+ cost = 0;
}
- if (IN_EDGES (target))
+ return cost;
+}
+
+/* Compute cost of dependence LINK.
+ This is the number of cycles between instruction issue and
+ instruction results. */
+int
+dep_cost (dep_t link)
+{
+ return dep_cost_1 (link, 0);
+}
+
+/* Use this sel-sched.c friendly function in reorder2 instead of increasing
+ INSN_PRIORITY explicitly. */
+void
+increase_insn_priority (rtx insn, int amount)
+{
+ if (!sel_sched_p ())
{
- next_edge = NEXT_IN (IN_EDGES (target));
- NEXT_IN (IN_EDGES (target)) = e;
- NEXT_IN (e) = next_edge;
+ /* We're dealing with haifa-sched.c INSN_PRIORITY. */
+ if (INSN_PRIORITY_KNOWN (insn))
+ INSN_PRIORITY (insn) += amount;
}
else
{
- IN_EDGES (target) = e;
- NEXT_IN (e) = e;
+ /* In sel-sched.c INSN_PRIORITY is not kept up to date.
+ Use EXPR_PRIORITY instead. */
+ sel_add_to_insn_priority (insn, amount);
}
}
-
-/* BITSET macros for operations on the control flow graph. */
-
-/* Compute bitwise union of two bitsets. */
-#define BITSET_UNION(set1, set2, len) \
-do { register bitset tp = set1, sp = set2; \
- register int i; \
- for (i = 0; i < len; i++) \
- *(tp++) |= *(sp++); } while (0)
-
-/* Compute bitwise intersection of two bitsets. */
-#define BITSET_INTER(set1, set2, len) \
-do { register bitset tp = set1, sp = set2; \
- register int i; \
- for (i = 0; i < len; i++) \
- *(tp++) &= *(sp++); } while (0)
-
-/* Compute bitwise difference of two bitsets. */
-#define BITSET_DIFFER(set1, set2, len) \
-do { register bitset tp = set1, sp = set2; \
- register int i; \
- for (i = 0; i < len; i++) \
- *(tp++) &= ~*(sp++); } while (0)
-
-/* Inverts every bit of bitset 'set'. */
-#define BITSET_INVERT(set, len) \
-do { register bitset tmpset = set; \
- register int i; \
- for (i = 0; i < len; i++, tmpset++) \
- *tmpset = ~*tmpset; } while (0)
-
-/* Turn on the index'th bit in bitset set. */
-#define BITSET_ADD(set, index, len) \
-{ \
- if (index >= HOST_BITS_PER_WIDE_INT * len) \
- abort (); \
- else \
- set[index/HOST_BITS_PER_WIDE_INT] |= \
- 1 << (index % HOST_BITS_PER_WIDE_INT); \
+/* Return 'true' if DEP should be included in priority calculations. */
+static bool
+contributes_to_priority_p (dep_t dep)
+{
+ if (DEBUG_INSN_P (DEP_CON (dep))
+ || DEBUG_INSN_P (DEP_PRO (dep)))
+ return false;
+
+ /* Critical path is meaningful in block boundaries only. */
+ if (!current_sched_info->contributes_to_priority (DEP_CON (dep),
+ DEP_PRO (dep)))
+ return false;
+
+ /* If flag COUNT_SPEC_IN_CRITICAL_PATH is set,
+ then speculative instructions will less likely be
+ scheduled. That is because the priority of
+ their producers will increase, and, thus, the
+ producers will more likely be scheduled, thus,
+ resolving the dependence. */
+ if (sched_deps_info->generate_spec_deps
+ && !(spec_info->flags & COUNT_SPEC_IN_CRITICAL_PATH)
+ && (DEP_STATUS (dep) & SPECULATIVE))
+ return false;
+
+ return true;
}
-/* Turn off the index'th bit in set. */
-#define BITSET_REMOVE(set, index, len) \
-{ \
- if (index >= HOST_BITS_PER_WIDE_INT * len) \
- abort (); \
- else \
- set[index/HOST_BITS_PER_WIDE_INT] &= \
- ~(1 << (index%HOST_BITS_PER_WIDE_INT)); \
-}
+/* Compute the number of nondebug forward deps of an insn. */
+static int
+dep_list_size (rtx insn)
+{
+ sd_iterator_def sd_it;
+ dep_t dep;
+ int dbgcount = 0, nodbgcount = 0;
-/* Check if the index'th bit in bitset set is on. */
+ if (!MAY_HAVE_DEBUG_INSNS)
+ return sd_lists_size (insn, SD_LIST_FORW);
-static char
-bitset_member (set, index, len)
- bitset set;
- int index, len;
-{
- if (index >= HOST_BITS_PER_WIDE_INT * len)
- abort ();
- return (set[index / HOST_BITS_PER_WIDE_INT] &
- 1 << (index % HOST_BITS_PER_WIDE_INT)) ? 1 : 0;
-}
+ FOR_EACH_DEP (insn, SD_LIST_FORW, sd_it, dep)
+ {
+ if (DEBUG_INSN_P (DEP_CON (dep)))
+ dbgcount++;
+ else if (!DEBUG_INSN_P (DEP_PRO (dep)))
+ nodbgcount++;
+ }
+ gcc_assert (dbgcount + nodbgcount == sd_lists_size (insn, SD_LIST_FORW));
-/* Translate a bit-set SET to a list BL of the bit-set members. */
+ return nodbgcount;
+}
-static void
-extract_bitlst (set, len, bl)
- bitset set;
- int len;
- bitlst *bl;
+/* Compute the priority number for INSN. */
+static int
+priority (rtx insn)
{
- int i, j, offset;
- unsigned HOST_WIDE_INT word;
-
- /* bblst table space is reused in each call to extract_bitlst. */
- bitlst_table_last = 0;
+ if (! INSN_P (insn))
+ return 0;
- bl->first_member = &bitlst_table[bitlst_table_last];
- bl->nr_members = 0;
+ /* We should not be interested in priority of an already scheduled insn. */
+ gcc_assert (QUEUE_INDEX (insn) != QUEUE_SCHEDULED);
- for (i = 0; i < len; i++)
+ if (!INSN_PRIORITY_KNOWN (insn))
{
- word = set[i];
- offset = i * HOST_BITS_PER_WIDE_INT;
- for (j = 0; word; j++)
+ int this_priority = -1;
+
+ if (dep_list_size (insn) == 0)
+ /* ??? We should set INSN_PRIORITY to insn_cost when and insn has
+ some forward deps but all of them are ignored by
+ contributes_to_priority hook. At the moment we set priority of
+ such insn to 0. */
+ this_priority = insn_cost (insn);
+ else
{
- if (word & 1)
+ rtx prev_first, twin;
+ basic_block rec;
+
+ /* For recovery check instructions we calculate priority slightly
+ different than that of normal instructions. Instead of walking
+ through INSN_FORW_DEPS (check) list, we walk through
+ INSN_FORW_DEPS list of each instruction in the corresponding
+ recovery block. */
+
+ /* Selective scheduling does not define RECOVERY_BLOCK macro. */
+ rec = sel_sched_p () ? NULL : RECOVERY_BLOCK (insn);
+ if (!rec || rec == EXIT_BLOCK_PTR)
{
- bitlst_table[bitlst_table_last++] = offset;
- (bl->nr_members)++;
+ prev_first = PREV_INSN (insn);
+ twin = insn;
+ }
+ else
+ {
+ prev_first = NEXT_INSN (BB_HEAD (rec));
+ twin = PREV_INSN (BB_END (rec));
}
- word >>= 1;
- ++offset;
- }
- }
-}
+ do
+ {
+ sd_iterator_def sd_it;
+ dep_t dep;
+
+ FOR_EACH_DEP (twin, SD_LIST_FORW, sd_it, dep)
+ {
+ rtx next;
+ int next_priority;
+ next = DEP_CON (dep);
-/* Functions for the construction of regions. */
+ if (BLOCK_FOR_INSN (next) != rec)
+ {
+ int cost;
-/* Print the regions, for debugging purposes. Callable from debugger. */
+ if (!contributes_to_priority_p (dep))
+ continue;
-void
-debug_regions ()
-{
- int rgn, bb;
+ if (twin == insn)
+ cost = dep_cost (dep);
+ else
+ {
+ struct _dep _dep1, *dep1 = &_dep1;
- fprintf (dump, "\n;; ------------ REGIONS ----------\n\n");
- for (rgn = 0; rgn < nr_regions; rgn++)
- {
- fprintf (dump, ";;\trgn %d nr_blocks %d:\n", rgn,
- rgn_table[rgn].rgn_nr_blocks);
- fprintf (dump, ";;\tbb/block: ");
+ init_dep (dep1, insn, next, REG_DEP_ANTI);
- for (bb = 0; bb < rgn_table[rgn].rgn_nr_blocks; bb++)
- {
- current_blocks = RGN_BLOCKS (rgn);
+ cost = dep_cost (dep1);
+ }
+
+ next_priority = cost + priority (next);
+
+ if (next_priority > this_priority)
+ this_priority = next_priority;
+ }
+ }
+
+ twin = PREV_INSN (twin);
+ }
+ while (twin != prev_first);
+ }
- if (bb != BLOCK_TO_BB (BB_TO_BLOCK (bb)))
- abort ();
+ if (this_priority < 0)
+ {
+ gcc_assert (this_priority == -1);
- fprintf (dump, " %d/%d ", bb, BB_TO_BLOCK (bb));
+ this_priority = insn_cost (insn);
}
- fprintf (dump, "\n\n");
+ INSN_PRIORITY (insn) = this_priority;
+ INSN_PRIORITY_STATUS (insn) = 1;
}
-}
+ return INSN_PRIORITY (insn);
+}
+\f
+/* Macros and functions for keeping the priority queue sorted, and
+ dealing with queuing and dequeuing of instructions. */
-/* Build a single block region for each basic block in the function.
- This allows for using the same code for interblock and basic block
- scheduling. */
+#define SCHED_SORT(READY, N_READY) \
+do { if ((N_READY) == 2) \
+ swap_sort (READY, N_READY); \
+ else if ((N_READY) > 2) \
+ qsort (READY, N_READY, sizeof (rtx), rank_for_schedule); } \
+while (0)
+/* Setup info about the current register pressure impact of scheduling
+ INSN at the current scheduling point. */
static void
-find_single_block_region ()
+setup_insn_reg_pressure_info (rtx insn)
{
- int i;
-
- for (i = 0; i < n_basic_blocks; i++)
+ int i, change, before, after, hard_regno;
+ int excess_cost_change;
+ enum machine_mode mode;
+ enum reg_class cl;
+ struct reg_pressure_data *pressure_info;
+ int *max_reg_pressure;
+ struct reg_use_data *use;
+ static int death[N_REG_CLASSES];
+
+ excess_cost_change = 0;
+ for (i = 0; i < ira_reg_class_cover_size; i++)
+ death[ira_reg_class_cover[i]] = 0;
+ for (use = INSN_REG_USE_LIST (insn); use != NULL; use = use->next_insn_use)
+ if (dying_use_p (use))
+ {
+ cl = sched_regno_cover_class[use->regno];
+ if (use->regno < FIRST_PSEUDO_REGISTER)
+ death[cl]++;
+ else
+ death[cl] += ira_reg_class_nregs[cl][PSEUDO_REGNO_MODE (use->regno)];
+ }
+ pressure_info = INSN_REG_PRESSURE (insn);
+ max_reg_pressure = INSN_MAX_REG_PRESSURE (insn);
+ gcc_assert (pressure_info != NULL && max_reg_pressure != NULL);
+ for (i = 0; i < ira_reg_class_cover_size; i++)
{
- rgn_bb_table[i] = i;
- RGN_NR_BLOCKS (i) = 1;
- RGN_BLOCKS (i) = i;
- CONTAINING_RGN (i) = i;
- BLOCK_TO_BB (i) = 0;
+ cl = ira_reg_class_cover[i];
+ gcc_assert (curr_reg_pressure[cl] >= 0);
+ change = (int) pressure_info[i].set_increase - death[cl];
+ before = MAX (0, max_reg_pressure[i] - ira_available_class_regs[cl]);
+ after = MAX (0, max_reg_pressure[i] + change
+ - ira_available_class_regs[cl]);
+ hard_regno = ira_class_hard_regs[cl][0];
+ gcc_assert (hard_regno >= 0);
+ mode = reg_raw_mode[hard_regno];
+ excess_cost_change += ((after - before)
+ * (ira_memory_move_cost[mode][cl][0]
+ + ira_memory_move_cost[mode][cl][1]));
}
- nr_regions = n_basic_blocks;
+ INSN_REG_PRESSURE_EXCESS_COST_CHANGE (insn) = excess_cost_change;
}
-
-/* Update number of blocks and the estimate for number of insns
- in the region. Return 1 if the region is "too large" for interblock
- scheduling (compile time considerations), otherwise return 0. */
+/* Returns a positive value if x is preferred; returns a negative value if
+ y is preferred. Should never return 0, since that will make the sort
+ unstable. */
static int
-too_large (block, num_bbs, num_insns)
- int block, *num_bbs, *num_insns;
+rank_for_schedule (const void *x, const void *y)
{
- (*num_bbs)++;
- (*num_insns) += (INSN_LUID (BLOCK_END (block)) -
- INSN_LUID (BLOCK_HEAD (block)));
- if ((*num_bbs > MAX_RGN_BLOCKS) || (*num_insns > MAX_RGN_INSNS))
- return 1;
- else
- return 0;
-}
+ rtx tmp = *(const rtx *) y;
+ rtx tmp2 = *(const rtx *) x;
+ rtx last;
+ int tmp_class, tmp2_class;
+ int val, priority_val, info_val;
+ if (MAY_HAVE_DEBUG_INSNS)
+ {
+ /* Schedule debug insns as early as possible. */
+ if (DEBUG_INSN_P (tmp) && !DEBUG_INSN_P (tmp2))
+ return -1;
+ else if (DEBUG_INSN_P (tmp2))
+ return 1;
+ }
-/* Update_loop_relations(blk, hdr): Check if the loop headed by max_hdr[blk]
- is still an inner loop. Put in max_hdr[blk] the header of the most inner
- loop containing blk. */
-#define UPDATE_LOOP_RELATIONS(blk, hdr) \
-{ \
- if (max_hdr[blk] == -1) \
- max_hdr[blk] = hdr; \
- else if (dfs_nr[max_hdr[blk]] > dfs_nr[hdr]) \
- RESET_BIT (inner, hdr); \
- else if (dfs_nr[max_hdr[blk]] < dfs_nr[hdr]) \
- { \
- RESET_BIT (inner,max_hdr[blk]); \
- max_hdr[blk] = hdr; \
- } \
-}
+ /* The insn in a schedule group should be issued the first. */
+ if (flag_sched_group_heuristic &&
+ SCHED_GROUP_P (tmp) != SCHED_GROUP_P (tmp2))
+ return SCHED_GROUP_P (tmp2) ? 1 : -1;
+ /* Make sure that priority of TMP and TMP2 are initialized. */
+ gcc_assert (INSN_PRIORITY_KNOWN (tmp) && INSN_PRIORITY_KNOWN (tmp2));
-/* Find regions for interblock scheduling.
+ if (sched_pressure_p)
+ {
+ int diff;
+
+ /* Prefer insn whose scheduling results in the smallest register
+ pressure excess. */
+ if ((diff = (INSN_REG_PRESSURE_EXCESS_COST_CHANGE (tmp)
+ + (INSN_TICK (tmp) > clock_var
+ ? INSN_TICK (tmp) - clock_var : 0)
+ - INSN_REG_PRESSURE_EXCESS_COST_CHANGE (tmp2)
+ - (INSN_TICK (tmp2) > clock_var
+ ? INSN_TICK (tmp2) - clock_var : 0))) != 0)
+ return diff;
+ }
- A region for scheduling can be:
- * A loop-free procedure, or
+ if (sched_pressure_p
+ && (INSN_TICK (tmp2) > clock_var || INSN_TICK (tmp) > clock_var))
+ {
+ if (INSN_TICK (tmp) <= clock_var)
+ return -1;
+ else if (INSN_TICK (tmp2) <= clock_var)
+ return 1;
+ else
+ return INSN_TICK (tmp) - INSN_TICK (tmp2);
+ }
+ /* Prefer insn with higher priority. */
+ priority_val = INSN_PRIORITY (tmp2) - INSN_PRIORITY (tmp);
- * A reducible inner loop, or
+ if (flag_sched_critical_path_heuristic && priority_val)
+ return priority_val;
- * A basic block not contained in any other region.
+ /* Prefer speculative insn with greater dependencies weakness. */
+ if (flag_sched_spec_insn_heuristic && spec_info)
+ {
+ ds_t ds1, ds2;
+ dw_t dw1, dw2;
+ int dw;
+ ds1 = TODO_SPEC (tmp) & SPECULATIVE;
+ if (ds1)
+ dw1 = ds_weak (ds1);
+ else
+ dw1 = NO_DEP_WEAK;
- ?!? In theory we could build other regions based on extended basic
- blocks or reverse extended basic blocks. Is it worth the trouble?
+ ds2 = TODO_SPEC (tmp2) & SPECULATIVE;
+ if (ds2)
+ dw2 = ds_weak (ds2);
+ else
+ dw2 = NO_DEP_WEAK;
- Loop blocks that form a region are put into the region's block list
- in topological order.
+ dw = dw2 - dw1;
+ if (dw > (NO_DEP_WEAK / 8) || dw < -(NO_DEP_WEAK / 8))
+ return dw;
+ }
- This procedure stores its results into the following global (ick) variables
+ info_val = (*current_sched_info->rank) (tmp, tmp2);
+ if(flag_sched_rank_heuristic && info_val)
+ return info_val;
- * rgn_nr
- * rgn_table
- * rgn_bb_table
- * block_to_bb
- * containing region
+ if (flag_sched_last_insn_heuristic)
+ {
+ last = last_scheduled_insn;
+ if (DEBUG_INSN_P (last) && last != current_sched_info->prev_head)
+ do
+ last = PREV_INSN (last);
+ while (!NONDEBUG_INSN_P (last)
+ && last != current_sched_info->prev_head);
+ }
- We use dominator relationships to avoid making regions out of non-reducible
- loops.
+ /* Compare insns based on their relation to the last scheduled
+ non-debug insn. */
+ if (flag_sched_last_insn_heuristic && NONDEBUG_INSN_P (last))
+ {
+ dep_t dep1;
+ dep_t dep2;
- This procedure needs to be converted to work on pred/succ lists instead
- of edge tables. That would simplify it somewhat. */
+ /* Classify the instructions into three classes:
+ 1) Data dependent on last schedule insn.
+ 2) Anti/Output dependent on last scheduled insn.
+ 3) Independent of last scheduled insn, or has latency of one.
+ Choose the insn from the highest numbered class if different. */
+ dep1 = sd_find_dep_between (last, tmp, true);
-static void
-find_rgns (edge_list, dom)
- struct edge_list *edge_list;
- sbitmap *dom;
-{
- int *max_hdr, *dfs_nr, *stack, *degree;
- char no_loops = 1;
- int node, child, loop_head, i, head, tail;
- int count = 0, sp, idx = 0, current_edge = out_edges[0];
- int num_bbs, num_insns, unreachable;
- int too_large_failure;
+ if (dep1 == NULL || dep_cost (dep1) == 1)
+ tmp_class = 3;
+ else if (/* Data dependence. */
+ DEP_TYPE (dep1) == REG_DEP_TRUE)
+ tmp_class = 1;
+ else
+ tmp_class = 2;
- /* Note if an edge has been passed. */
- sbitmap passed;
+ dep2 = sd_find_dep_between (last, tmp2, true);
- /* Note if a block is a natural loop header. */
- sbitmap header;
+ if (dep2 == NULL || dep_cost (dep2) == 1)
+ tmp2_class = 3;
+ else if (/* Data dependence. */
+ DEP_TYPE (dep2) == REG_DEP_TRUE)
+ tmp2_class = 1;
+ else
+ tmp2_class = 2;
- /* Note if a block is an natural inner loop header. */
- sbitmap inner;
+ if ((val = tmp2_class - tmp_class))
+ return val;
+ }
- /* Note if a block is in the block queue. */
- sbitmap in_queue;
+ /* Prefer the insn which has more later insns that depend on it.
+ This gives the scheduler more freedom when scheduling later
+ instructions at the expense of added register pressure. */
- /* Note if a block is in the block queue. */
- sbitmap in_stack;
+ val = (dep_list_size (tmp2) - dep_list_size (tmp));
- int num_edges = NUM_EDGES (edge_list);
+ if (flag_sched_dep_count_heuristic && val != 0)
+ return val;
- /* Perform a DFS traversal of the cfg. Identify loop headers, inner loops
- and a mapping from block to its loop header (if the block is contained
- in a loop, else -1).
+ /* If insns are equally good, sort by INSN_LUID (original insn order),
+ so that we make the sort stable. This minimizes instruction movement,
+ thus minimizing sched's effect on debugging and cross-jumping. */
+ return INSN_LUID (tmp) - INSN_LUID (tmp2);
+}
- Store results in HEADER, INNER, and MAX_HDR respectively, these will
- be used as inputs to the second traversal.
+/* Resort the array A in which only element at index N may be out of order. */
- STACK, SP and DFS_NR are only used during the first traversal. */
+HAIFA_INLINE static void
+swap_sort (rtx *a, int n)
+{
+ rtx insn = a[n - 1];
+ int i = n - 2;
- /* Allocate and initialize variables for the first traversal. */
- max_hdr = (int *) xmalloc (n_basic_blocks * sizeof (int));
- dfs_nr = (int *) xcalloc (n_basic_blocks, sizeof (int));
- stack = (int *) xmalloc (nr_edges * sizeof (int));
+ while (i >= 0 && rank_for_schedule (a + i, &insn) >= 0)
+ {
+ a[i + 1] = a[i];
+ i -= 1;
+ }
+ a[i + 1] = insn;
+}
- inner = sbitmap_alloc (n_basic_blocks);
- sbitmap_ones (inner);
+/* Add INSN to the insn queue so that it can be executed at least
+ N_CYCLES after the currently executing insn. Preserve insns
+ chain for debugging purposes. */
- header = sbitmap_alloc (n_basic_blocks);
- sbitmap_zero (header);
+HAIFA_INLINE static void
+queue_insn (rtx insn, int n_cycles)
+{
+ int next_q = NEXT_Q_AFTER (q_ptr, n_cycles);
+ rtx link = alloc_INSN_LIST (insn, insn_queue[next_q]);
- passed = sbitmap_alloc (nr_edges);
- sbitmap_zero (passed);
+ gcc_assert (n_cycles <= max_insn_queue_index);
+ gcc_assert (!DEBUG_INSN_P (insn));
- in_queue = sbitmap_alloc (n_basic_blocks);
- sbitmap_zero (in_queue);
+ insn_queue[next_q] = link;
+ q_size += 1;
- in_stack = sbitmap_alloc (n_basic_blocks);
- sbitmap_zero (in_stack);
+ if (sched_verbose >= 2)
+ {
+ fprintf (sched_dump, ";;\t\tReady-->Q: insn %s: ",
+ (*current_sched_info->print_insn) (insn, 0));
- for (i = 0; i < n_basic_blocks; i++)
- max_hdr[i] = -1;
+ fprintf (sched_dump, "queued for %d cycles.\n", n_cycles);
+ }
- /* DFS traversal to find inner loops in the cfg. */
+ QUEUE_INDEX (insn) = next_q;
+}
- sp = -1;
- while (1)
- {
- if (current_edge == 0 || TEST_BIT (passed, current_edge))
- {
- /* We have reached a leaf node or a node that was already
- processed. Pop edges off the stack until we find
- an edge that has not yet been processed. */
- while (sp >= 0
- && (current_edge == 0 || TEST_BIT (passed, current_edge)))
- {
- /* Pop entry off the stack. */
- current_edge = stack[sp--];
- node = FROM_BLOCK (current_edge);
- child = TO_BLOCK (current_edge);
- RESET_BIT (in_stack, child);
- if (max_hdr[child] >= 0 && TEST_BIT (in_stack, max_hdr[child]))
- UPDATE_LOOP_RELATIONS (node, max_hdr[child]);
- current_edge = NEXT_OUT (current_edge);
- }
+/* Remove INSN from queue. */
+static void
+queue_remove (rtx insn)
+{
+ gcc_assert (QUEUE_INDEX (insn) >= 0);
+ remove_free_INSN_LIST_elem (insn, &insn_queue[QUEUE_INDEX (insn)]);
+ q_size--;
+ QUEUE_INDEX (insn) = QUEUE_NOWHERE;
+}
- /* See if have finished the DFS tree traversal. */
- if (sp < 0 && TEST_BIT (passed, current_edge))
- break;
+/* Return a pointer to the bottom of the ready list, i.e. the insn
+ with the lowest priority. */
- /* Nope, continue the traversal with the popped node. */
- continue;
- }
+rtx *
+ready_lastpos (struct ready_list *ready)
+{
+ gcc_assert (ready->n_ready >= 1);
+ return ready->vec + ready->first - ready->n_ready + 1;
+}
- /* Process a node. */
- node = FROM_BLOCK (current_edge);
- child = TO_BLOCK (current_edge);
- SET_BIT (in_stack, node);
- dfs_nr[node] = ++count;
+/* Add an element INSN to the ready list so that it ends up with the
+ lowest/highest priority depending on FIRST_P. */
- /* If the successor is in the stack, then we've found a loop.
- Mark the loop, if it is not a natural loop, then it will
- be rejected during the second traversal. */
- if (TEST_BIT (in_stack, child))
+HAIFA_INLINE static void
+ready_add (struct ready_list *ready, rtx insn, bool first_p)
+{
+ if (!first_p)
+ {
+ if (ready->first == ready->n_ready)
{
- no_loops = 0;
- SET_BIT (header, child);
- UPDATE_LOOP_RELATIONS (node, child);
- SET_BIT (passed, current_edge);
- current_edge = NEXT_OUT (current_edge);
- continue;
+ memmove (ready->vec + ready->veclen - ready->n_ready,
+ ready_lastpos (ready),
+ ready->n_ready * sizeof (rtx));
+ ready->first = ready->veclen - 1;
}
-
- /* If the child was already visited, then there is no need to visit
- it again. Just update the loop relationships and restart
- with a new edge. */
- if (dfs_nr[child])
+ ready->vec[ready->first - ready->n_ready] = insn;
+ }
+ else
+ {
+ if (ready->first == ready->veclen - 1)
{
- if (max_hdr[child] >= 0 && TEST_BIT (in_stack, max_hdr[child]))
- UPDATE_LOOP_RELATIONS (node, max_hdr[child]);
- SET_BIT (passed, current_edge);
- current_edge = NEXT_OUT (current_edge);
- continue;
+ if (ready->n_ready)
+ /* ready_lastpos() fails when called with (ready->n_ready == 0). */
+ memmove (ready->vec + ready->veclen - ready->n_ready - 1,
+ ready_lastpos (ready),
+ ready->n_ready * sizeof (rtx));
+ ready->first = ready->veclen - 2;
}
-
- /* Push an entry on the stack and continue DFS traversal. */
- stack[++sp] = current_edge;
- SET_BIT (passed, current_edge);
- current_edge = OUT_EDGES (child);
-
- /* This is temporary until haifa is converted to use rth's new
- cfg routines which have true entry/exit blocks and the
- appropriate edges from/to those blocks.
-
- Generally we update dfs_nr for a node when we process its
- out edge. However, if the node has no out edge then we will
- not set dfs_nr for that node. This can confuse the scheduler
- into thinking that we have unreachable blocks, which in turn
- disables cross block scheduling.
-
- So, if we have a node with no out edges, go ahead and mark it
- as reachable now. */
- if (current_edge == 0)
- dfs_nr[child] = ++count;
+ ready->vec[++(ready->first)] = insn;
}
- /* Another check for unreachable blocks. The earlier test in
- is_cfg_nonregular only finds unreachable blocks that do not
- form a loop.
+ ready->n_ready++;
+ if (DEBUG_INSN_P (insn))
+ ready->n_debug++;
- The DFS traversal will mark every block that is reachable from
- the entry node by placing a nonzero value in dfs_nr. Thus if
- dfs_nr is zero for any block, then it must be unreachable. */
- unreachable = 0;
- for (i = 0; i < n_basic_blocks; i++)
- if (dfs_nr[i] == 0)
- {
- unreachable = 1;
- break;
- }
+ gcc_assert (QUEUE_INDEX (insn) != QUEUE_READY);
+ QUEUE_INDEX (insn) = QUEUE_READY;
+}
- /* Gross. To avoid wasting memory, the second pass uses the dfs_nr array
- to hold degree counts. */
- degree = dfs_nr;
+/* Remove the element with the highest priority from the ready list and
+ return it. */
- for (i = 0; i < n_basic_blocks; i++)
- degree[i] = 0;
- for (i = 0; i < num_edges; i++)
- {
- edge e = INDEX_EDGE (edge_list, i);
+HAIFA_INLINE static rtx
+ready_remove_first (struct ready_list *ready)
+{
+ rtx t;
- if (e->dest != EXIT_BLOCK_PTR)
- degree[e->dest->index]++;
- }
+ gcc_assert (ready->n_ready);
+ t = ready->vec[ready->first--];
+ ready->n_ready--;
+ if (DEBUG_INSN_P (t))
+ ready->n_debug--;
+ /* If the queue becomes empty, reset it. */
+ if (ready->n_ready == 0)
+ ready->first = ready->veclen - 1;
- /* Do not perform region scheduling if there are any unreachable
- blocks. */
- if (!unreachable)
- {
- int *queue;
-
- if (no_loops)
- SET_BIT (header, 0);
-
- /* Second travsersal:find reducible inner loops and topologically sort
- block of each region. */
-
- queue = (int *) xmalloc (n_basic_blocks * sizeof (int));
+ gcc_assert (QUEUE_INDEX (t) == QUEUE_READY);
+ QUEUE_INDEX (t) = QUEUE_NOWHERE;
- /* Find blocks which are inner loop headers. We still have non-reducible
- loops to consider at this point. */
- for (i = 0; i < n_basic_blocks; i++)
- {
- if (TEST_BIT (header, i) && TEST_BIT (inner, i))
- {
- edge e;
- int j;
+ return t;
+}
- /* Now check that the loop is reducible. We do this separate
- from finding inner loops so that we do not find a reducible
- loop which contains an inner non-reducible loop.
+/* The following code implements multi-pass scheduling for the first
+ cycle. In other words, we will try to choose ready insn which
+ permits to start maximum number of insns on the same cycle. */
- A simple way to find reducible/natural loops is to verify
- that each block in the loop is dominated by the loop
- header.
+/* Return a pointer to the element INDEX from the ready. INDEX for
+ insn with the highest priority is 0, and the lowest priority has
+ N_READY - 1. */
- If there exists a block that is not dominated by the loop
- header, then the block is reachable from outside the loop
- and thus the loop is not a natural loop. */
- for (j = 0; j < n_basic_blocks; j++)
- {
- /* First identify blocks in the loop, except for the loop
- entry block. */
- if (i == max_hdr[j] && i != j)
- {
- /* Now verify that the block is dominated by the loop
- header. */
- if (!TEST_BIT (dom[j], i))
- break;
- }
- }
+rtx
+ready_element (struct ready_list *ready, int index)
+{
+ gcc_assert (ready->n_ready && index < ready->n_ready);
- /* If we exited the loop early, then I is the header of
- a non-reducible loop and we should quit processing it
- now. */
- if (j != n_basic_blocks)
- continue;
+ return ready->vec[ready->first - index];
+}
- /* I is a header of an inner loop, or block 0 in a subroutine
- with no loops at all. */
- head = tail = -1;
- too_large_failure = 0;
- loop_head = max_hdr[i];
+/* Remove the element INDEX from the ready list and return it. INDEX
+ for insn with the highest priority is 0, and the lowest priority
+ has N_READY - 1. */
- /* Decrease degree of all I's successors for topological
- ordering. */
- for (e = BASIC_BLOCK (i)->succ; e; e = e->succ_next)
- if (e->dest != EXIT_BLOCK_PTR)
- --degree[e->dest->index];
+HAIFA_INLINE static rtx
+ready_remove (struct ready_list *ready, int index)
+{
+ rtx t;
+ int i;
- /* Estimate # insns, and count # blocks in the region. */
- num_bbs = 1;
- num_insns = (INSN_LUID (BLOCK_END (i))
- - INSN_LUID (BLOCK_HEAD (i)));
+ if (index == 0)
+ return ready_remove_first (ready);
+ gcc_assert (ready->n_ready && index < ready->n_ready);
+ t = ready->vec[ready->first - index];
+ ready->n_ready--;
+ if (DEBUG_INSN_P (t))
+ ready->n_debug--;
+ for (i = index; i < ready->n_ready; i++)
+ ready->vec[ready->first - i] = ready->vec[ready->first - i - 1];
+ QUEUE_INDEX (t) = QUEUE_NOWHERE;
+ return t;
+}
+/* Remove INSN from the ready list. */
+static void
+ready_remove_insn (rtx insn)
+{
+ int i;
- /* Find all loop latches (blocks with back edges to the loop
- header) or all the leaf blocks in the cfg has no loops.
+ for (i = 0; i < readyp->n_ready; i++)
+ if (ready_element (readyp, i) == insn)
+ {
+ ready_remove (readyp, i);
+ return;
+ }
+ gcc_unreachable ();
+}
- Place those blocks into the queue. */
- if (no_loops)
- {
- for (j = 0; j < n_basic_blocks; j++)
- /* Leaf nodes have only a single successor which must
- be EXIT_BLOCK. */
- if (BASIC_BLOCK (j)->succ
- && BASIC_BLOCK (j)->succ->dest == EXIT_BLOCK_PTR
- && BASIC_BLOCK (j)->succ->succ_next == NULL)
- {
- queue[++tail] = j;
- SET_BIT (in_queue, j);
-
- if (too_large (j, &num_bbs, &num_insns))
- {
- too_large_failure = 1;
- break;
- }
- }
- }
- else
- {
- edge e;
+/* Sort the ready list READY by ascending priority, using the SCHED_SORT
+ macro. */
- for (e = BASIC_BLOCK (i)->pred; e; e = e->pred_next)
- {
- if (e->src == ENTRY_BLOCK_PTR)
- continue;
+void
+ready_sort (struct ready_list *ready)
+{
+ int i;
+ rtx *first = ready_lastpos (ready);
- node = e->src->index;
+ if (sched_pressure_p)
+ {
+ for (i = 0; i < ready->n_ready; i++)
+ setup_insn_reg_pressure_info (first[i]);
+ }
+ SCHED_SORT (first, ready->n_ready);
+}
- if (max_hdr[node] == loop_head && node != i)
- {
- /* This is a loop latch. */
- queue[++tail] = node;
- SET_BIT (in_queue, node);
-
- if (too_large (node, &num_bbs, &num_insns))
- {
- too_large_failure = 1;
- break;
- }
- }
-
- }
- }
+/* PREV is an insn that is ready to execute. Adjust its priority if that
+ will help shorten or lengthen register lifetimes as appropriate. Also
+ provide a hook for the target to tweak itself. */
- /* Now add all the blocks in the loop to the queue.
+HAIFA_INLINE static void
+adjust_priority (rtx prev)
+{
+ /* ??? There used to be code here to try and estimate how an insn
+ affected register lifetimes, but it did it by looking at REG_DEAD
+ notes, which we removed in schedule_region. Nor did it try to
+ take into account register pressure or anything useful like that.
- We know the loop is a natural loop; however the algorithm
- above will not always mark certain blocks as being in the
- loop. Consider:
- node children
- a b,c
- b c
- c a,d
- d b
+ Revisit when we have a machine model to work with and not before. */
+ if (targetm.sched.adjust_priority)
+ INSN_PRIORITY (prev) =
+ targetm.sched.adjust_priority (prev, INSN_PRIORITY (prev));
+}
- The algorithm in the DFS traversal may not mark B & D as part
- of the loop (ie they will not have max_hdr set to A).
+/* Advance DFA state STATE on one cycle. */
+void
+advance_state (state_t state)
+{
+ if (targetm.sched.dfa_pre_advance_cycle)
+ targetm.sched.dfa_pre_advance_cycle ();
- We know they can not be loop latches (else they would have
- had max_hdr set since they'd have a backedge to a dominator
- block). So we don't need them on the initial queue.
+ if (targetm.sched.dfa_pre_cycle_insn)
+ state_transition (state,
+ targetm.sched.dfa_pre_cycle_insn ());
- We know they are part of the loop because they are dominated
- by the loop header and can be reached by a backwards walk of
- the edges starting with nodes on the initial queue.
+ state_transition (state, NULL);
- It is safe and desirable to include those nodes in the
- loop/scheduling region. To do so we would need to decrease
- the degree of a node if it is the target of a backedge
- within the loop itself as the node is placed in the queue.
+ if (targetm.sched.dfa_post_cycle_insn)
+ state_transition (state,
+ targetm.sched.dfa_post_cycle_insn ());
- We do not do this because I'm not sure that the actual
- scheduling code will properly handle this case. ?!? */
-
- while (head < tail && !too_large_failure)
- {
- edge e;
- child = queue[++head];
+ if (targetm.sched.dfa_post_advance_cycle)
+ targetm.sched.dfa_post_advance_cycle ();
+}
- for (e = BASIC_BLOCK (child)->pred; e; e = e->pred_next)
- {
- node = e->src->index;
+/* Advance time on one cycle. */
+HAIFA_INLINE static void
+advance_one_cycle (void)
+{
+ advance_state (curr_state);
+ if (sched_verbose >= 6)
+ fprintf (sched_dump, ";;\tAdvanced a state.\n");
+}
- /* See discussion above about nodes not marked as in
- this loop during the initial DFS traversal. */
- if (e->src == ENTRY_BLOCK_PTR
- || max_hdr[node] != loop_head)
- {
- tail = -1;
- break;
- }
- else if (!TEST_BIT (in_queue, node) && node != i)
- {
- queue[++tail] = node;
- SET_BIT (in_queue, node);
-
- if (too_large (node, &num_bbs, &num_insns))
- {
- too_large_failure = 1;
- break;
- }
- }
- }
- }
+/* Clock at which the previous instruction was issued. */
+static int last_clock_var;
- if (tail >= 0 && !too_large_failure)
- {
- /* Place the loop header into list of region blocks. */
- degree[i] = -1;
- rgn_bb_table[idx] = i;
- RGN_NR_BLOCKS (nr_regions) = num_bbs;
- RGN_BLOCKS (nr_regions) = idx++;
- CONTAINING_RGN (i) = nr_regions;
- BLOCK_TO_BB (i) = count = 0;
-
- /* Remove blocks from queue[] when their in degree
- becomes zero. Repeat until no blocks are left on the
- list. This produces a topological list of blocks in
- the region. */
- while (tail >= 0)
- {
- if (head < 0)
- head = tail;
- child = queue[head];
- if (degree[child] == 0)
- {
- edge e;
-
- degree[child] = -1;
- rgn_bb_table[idx++] = child;
- BLOCK_TO_BB (child) = ++count;
- CONTAINING_RGN (child) = nr_regions;
- queue[head] = queue[tail--];
-
- for (e = BASIC_BLOCK (child)->succ;
- e;
- e = e->succ_next)
- if (e->dest != EXIT_BLOCK_PTR)
- --degree[e->dest->index];
- }
- else
- --head;
- }
- ++nr_regions;
- }
- }
- }
- free (queue);
- }
+/* Update register pressure after scheduling INSN. */
+static void
+update_register_pressure (rtx insn)
+{
+ struct reg_use_data *use;
+ struct reg_set_data *set;
+
+ for (use = INSN_REG_USE_LIST (insn); use != NULL; use = use->next_insn_use)
+ if (dying_use_p (use) && bitmap_bit_p (curr_reg_live, use->regno))
+ mark_regno_birth_or_death (use->regno, false);
+ for (set = INSN_REG_SET_LIST (insn); set != NULL; set = set->next_insn_set)
+ mark_regno_birth_or_death (set->regno, true);
+}
- /* Any block that did not end up in a region is placed into a region
- by itself. */
- for (i = 0; i < n_basic_blocks; i++)
- if (degree[i] >= 0)
+/* Set up or update (if UPDATE_P) max register pressure (see its
+ meaning in sched-int.h::_haifa_insn_data) for all current BB insns
+ after insn AFTER. */
+static void
+setup_insn_max_reg_pressure (rtx after, bool update_p)
+{
+ int i, p;
+ bool eq_p;
+ rtx insn;
+ static int max_reg_pressure[N_REG_CLASSES];
+
+ save_reg_pressure ();
+ for (i = 0; i < ira_reg_class_cover_size; i++)
+ max_reg_pressure[ira_reg_class_cover[i]]
+ = curr_reg_pressure[ira_reg_class_cover[i]];
+ for (insn = NEXT_INSN (after);
+ insn != NULL_RTX && BLOCK_FOR_INSN (insn) == BLOCK_FOR_INSN (after);
+ insn = NEXT_INSN (insn))
+ if (NONDEBUG_INSN_P (insn))
{
- rgn_bb_table[idx] = i;
- RGN_NR_BLOCKS (nr_regions) = 1;
- RGN_BLOCKS (nr_regions) = idx++;
- CONTAINING_RGN (i) = nr_regions++;
- BLOCK_TO_BB (i) = 0;
+ eq_p = true;
+ for (i = 0; i < ira_reg_class_cover_size; i++)
+ {
+ p = max_reg_pressure[ira_reg_class_cover[i]];
+ if (INSN_MAX_REG_PRESSURE (insn)[i] != p)
+ {
+ eq_p = false;
+ INSN_MAX_REG_PRESSURE (insn)[i]
+ = max_reg_pressure[ira_reg_class_cover[i]];
+ }
+ }
+ if (update_p && eq_p)
+ break;
+ update_register_pressure (insn);
+ for (i = 0; i < ira_reg_class_cover_size; i++)
+ if (max_reg_pressure[ira_reg_class_cover[i]]
+ < curr_reg_pressure[ira_reg_class_cover[i]])
+ max_reg_pressure[ira_reg_class_cover[i]]
+ = curr_reg_pressure[ira_reg_class_cover[i]];
}
-
- free (max_hdr);
- free (dfs_nr);
- free (stack);
- free (passed);
- free (header);
- free (inner);
- free (in_queue);
- free (in_stack);
+ restore_reg_pressure ();
}
-
-/* Functions for regions scheduling information. */
-
-/* Compute dominators, probability, and potential-split-edges of bb.
- Assume that these values were already computed for bb's predecessors. */
-
+/* Update the current register pressure after scheduling INSN. Update
+ also max register pressure for unscheduled insns of the current
+ BB. */
static void
-compute_dom_prob_ps (bb)
- int bb;
+update_reg_and_insn_max_reg_pressure (rtx insn)
{
- int nxt_in_edge, fst_in_edge, pred;
- int fst_out_edge, nxt_out_edge, nr_out_edges, nr_rgn_out_edges;
-
- prob[bb] = 0.0;
- if (IS_RGN_ENTRY (bb))
- {
- BITSET_ADD (dom[bb], 0, bbset_size);
- prob[bb] = 1.0;
- return;
- }
-
- fst_in_edge = nxt_in_edge = IN_EDGES (BB_TO_BLOCK (bb));
-
- /* Intialize dom[bb] to '111..1'. */
- BITSET_INVERT (dom[bb], bbset_size);
+ int i;
+ int before[N_REG_CLASSES];
- do
- {
- pred = FROM_BLOCK (nxt_in_edge);
- BITSET_INTER (dom[bb], dom[BLOCK_TO_BB (pred)], bbset_size);
+ for (i = 0; i < ira_reg_class_cover_size; i++)
+ before[i] = curr_reg_pressure[ira_reg_class_cover[i]];
+ update_register_pressure (insn);
+ for (i = 0; i < ira_reg_class_cover_size; i++)
+ if (curr_reg_pressure[ira_reg_class_cover[i]] != before[i])
+ break;
+ if (i < ira_reg_class_cover_size)
+ setup_insn_max_reg_pressure (insn, true);
+}
- BITSET_UNION (ancestor_edges[bb], ancestor_edges[BLOCK_TO_BB (pred)],
- edgeset_size);
+/* Set up register pressure at the beginning of basic block BB whose
+ insns starting after insn AFTER. Set up also max register pressure
+ for all insns of the basic block. */
+void
+sched_setup_bb_reg_pressure_info (basic_block bb, rtx after)
+{
+ gcc_assert (sched_pressure_p);
+ initiate_bb_reg_pressure_info (bb);
+ setup_insn_max_reg_pressure (after, false);
+}
- BITSET_ADD (ancestor_edges[bb], EDGE_TO_BIT (nxt_in_edge), edgeset_size);
+/* INSN is the "currently executing insn". Launch each insn which was
+ waiting on INSN. READY is the ready list which contains the insns
+ that are ready to fire. CLOCK is the current cycle. The function
+ returns necessary cycle advance after issuing the insn (it is not
+ zero for insns in a schedule group). */
- nr_out_edges = 1;
- nr_rgn_out_edges = 0;
- fst_out_edge = OUT_EDGES (pred);
- nxt_out_edge = NEXT_OUT (fst_out_edge);
- BITSET_UNION (pot_split[bb], pot_split[BLOCK_TO_BB (pred)],
- edgeset_size);
+static int
+schedule_insn (rtx insn)
+{
+ sd_iterator_def sd_it;
+ dep_t dep;
+ int i;
+ int advance = 0;
- BITSET_ADD (pot_split[bb], EDGE_TO_BIT (fst_out_edge), edgeset_size);
+ if (sched_verbose >= 1)
+ {
+ struct reg_pressure_data *pressure_info;
+ char buf[2048];
- /* The successor doesn't belong in the region? */
- if (CONTAINING_RGN (TO_BLOCK (fst_out_edge)) !=
- CONTAINING_RGN (BB_TO_BLOCK (bb)))
- ++nr_rgn_out_edges;
+ print_insn (buf, insn, 0);
+ buf[40] = 0;
+ fprintf (sched_dump, ";;\t%3i--> %-40s:", clock_var, buf);
- while (fst_out_edge != nxt_out_edge)
+ if (recog_memoized (insn) < 0)
+ fprintf (sched_dump, "nothing");
+ else
+ print_reservation (sched_dump, insn);
+ pressure_info = INSN_REG_PRESSURE (insn);
+ if (pressure_info != NULL)
{
- ++nr_out_edges;
- /* The successor doesn't belong in the region? */
- if (CONTAINING_RGN (TO_BLOCK (nxt_out_edge)) !=
- CONTAINING_RGN (BB_TO_BLOCK (bb)))
- ++nr_rgn_out_edges;
- BITSET_ADD (pot_split[bb], EDGE_TO_BIT (nxt_out_edge), edgeset_size);
- nxt_out_edge = NEXT_OUT (nxt_out_edge);
-
+ fputc (':', sched_dump);
+ for (i = 0; i < ira_reg_class_cover_size; i++)
+ fprintf (sched_dump, "%s%+d(%d)",
+ reg_class_names[ira_reg_class_cover[i]],
+ pressure_info[i].set_increase, pressure_info[i].change);
}
-
- /* Now nr_rgn_out_edges is the number of region-exit edges from
- pred, and nr_out_edges will be the number of pred out edges
- not leaving the region. */
- nr_out_edges -= nr_rgn_out_edges;
- if (nr_rgn_out_edges > 0)
- prob[bb] += 0.9 * prob[BLOCK_TO_BB (pred)] / nr_out_edges;
- else
- prob[bb] += prob[BLOCK_TO_BB (pred)] / nr_out_edges;
- nxt_in_edge = NEXT_IN (nxt_in_edge);
+ fputc ('\n', sched_dump);
}
- while (fst_in_edge != nxt_in_edge);
-
- BITSET_ADD (dom[bb], bb, bbset_size);
- BITSET_DIFFER (pot_split[bb], ancestor_edges[bb], edgeset_size);
- if (sched_verbose >= 2)
- fprintf (dump, ";; bb_prob(%d, %d) = %3d\n", bb, BB_TO_BLOCK (bb), (int) (100.0 * prob[bb]));
-} /* compute_dom_prob_ps */
+ if (sched_pressure_p)
+ update_reg_and_insn_max_reg_pressure (insn);
-/* Functions for target info. */
+ /* Scheduling instruction should have all its dependencies resolved and
+ should have been removed from the ready list. */
+ gcc_assert (sd_lists_empty_p (insn, SD_LIST_BACK));
-/* Compute in BL the list of split-edges of bb_src relatively to bb_trg.
- Note that bb_trg dominates bb_src. */
+ /* Reset debug insns invalidated by moving this insn. */
+ if (MAY_HAVE_DEBUG_INSNS && !DEBUG_INSN_P (insn))
+ for (sd_it = sd_iterator_start (insn, SD_LIST_BACK);
+ sd_iterator_cond (&sd_it, &dep);)
+ {
+ rtx dbg = DEP_PRO (dep);
+
+ gcc_assert (DEBUG_INSN_P (dbg));
+
+ if (sched_verbose >= 6)
+ fprintf (sched_dump, ";;\t\tresetting: debug insn %d\n",
+ INSN_UID (dbg));
+
+ /* ??? Rather than resetting the debug insn, we might be able
+ to emit a debug temp before the just-scheduled insn, but
+ this would involve checking that the expression at the
+ point of the debug insn is equivalent to the expression
+ before the just-scheduled insn. They might not be: the
+ expression in the debug insn may depend on other insns not
+ yet scheduled that set MEMs, REGs or even other debug
+ insns. It's not clear that attempting to preserve debug
+ information in these cases is worth the effort, given how
+ uncommon these resets are and the likelihood that the debug
+ temps introduced won't survive the schedule change. */
+ INSN_VAR_LOCATION_LOC (dbg) = gen_rtx_UNKNOWN_VAR_LOC ();
+ df_insn_rescan (dbg);
+
+ /* We delete rather than resolve these deps, otherwise we
+ crash in sched_free_deps(), because forward deps are
+ expected to be released before backward deps. */
+ sd_delete_dep (sd_it);
+ }
-static void
-split_edges (bb_src, bb_trg, bl)
- int bb_src;
- int bb_trg;
- edgelst *bl;
-{
- int es = edgeset_size;
- edgeset src = (edgeset) xmalloc (es * sizeof (HOST_WIDE_INT));
-
- while (es--)
- src[es] = (pot_split[bb_src])[es];
- BITSET_DIFFER (src, pot_split[bb_trg], edgeset_size);
- extract_bitlst (src, edgeset_size, bl);
- free (src);
-}
+ gcc_assert (QUEUE_INDEX (insn) == QUEUE_NOWHERE);
+ QUEUE_INDEX (insn) = QUEUE_SCHEDULED;
+ gcc_assert (INSN_TICK (insn) >= MIN_TICK);
+ if (INSN_TICK (insn) > clock_var)
+ /* INSN has been prematurely moved from the queue to the ready list.
+ This is possible only if following flag is set. */
+ gcc_assert (flag_sched_stalled_insns);
-/* Find the valid candidate-source-blocks for the target block TRG, compute
- their probability, and check if they are speculative or not.
- For speculative sources, compute their update-blocks and split-blocks. */
+ /* ??? Probably, if INSN is scheduled prematurely, we should leave
+ INSN_TICK untouched. This is a machine-dependent issue, actually. */
+ INSN_TICK (insn) = clock_var;
-static void
-compute_trg_info (trg)
- int trg;
-{
- register candidate *sp;
- edgelst el;
- int check_block, update_idx;
- int i, j, k, fst_edge, nxt_edge;
-
- /* Define some of the fields for the target bb as well. */
- sp = candidate_table + trg;
- sp->is_valid = 1;
- sp->is_speculative = 0;
- sp->src_prob = 100;
-
- for (i = trg + 1; i < current_nr_blocks; i++)
+ /* Update dependent instructions. */
+ for (sd_it = sd_iterator_start (insn, SD_LIST_FORW);
+ sd_iterator_cond (&sd_it, &dep);)
{
- sp = candidate_table + i;
+ rtx next = DEP_CON (dep);
- sp->is_valid = IS_DOMINATED (i, trg);
- if (sp->is_valid)
- {
- sp->src_prob = GET_SRC_PROB (i, trg);
- sp->is_valid = (sp->src_prob >= MIN_PROBABILITY);
- }
+ /* Resolve the dependence between INSN and NEXT.
+ sd_resolve_dep () moves current dep to another list thus
+ advancing the iterator. */
+ sd_resolve_dep (sd_it);
- if (sp->is_valid)
- {
- split_edges (i, trg, &el);
- sp->is_speculative = (el.nr_members) ? 1 : 0;
- if (sp->is_speculative && !flag_schedule_speculative)
- sp->is_valid = 0;
- }
+ /* Don't bother trying to mark next as ready if insn is a debug
+ insn. If insn is the last hard dependency, it will have
+ already been discounted. */
+ if (DEBUG_INSN_P (insn) && !DEBUG_INSN_P (next))
+ continue;
- if (sp->is_valid)
+ if (!IS_SPECULATION_BRANCHY_CHECK_P (insn))
{
- sp->split_bbs.first_member = &bblst_table[bblst_last];
- sp->split_bbs.nr_members = el.nr_members;
- for (j = 0; j < el.nr_members; bblst_last++, j++)
- bblst_table[bblst_last] =
- TO_BLOCK (rgn_edges[el.first_member[j]]);
- sp->update_bbs.first_member = &bblst_table[bblst_last];
- update_idx = 0;
- for (j = 0; j < el.nr_members; j++)
- {
- check_block = FROM_BLOCK (rgn_edges[el.first_member[j]]);
- fst_edge = nxt_edge = OUT_EDGES (check_block);
- do
- {
- for (k = 0; k < el.nr_members; k++)
- if (EDGE_TO_BIT (nxt_edge) == el.first_member[k])
- break;
-
- if (k >= el.nr_members)
- {
- bblst_table[bblst_last++] = TO_BLOCK (nxt_edge);
- update_idx++;
- }
+ int effective_cost;
- nxt_edge = NEXT_OUT (nxt_edge);
- }
- while (fst_edge != nxt_edge);
- }
- sp->update_bbs.nr_members = update_idx;
+ effective_cost = try_ready (next);
+ if (effective_cost >= 0
+ && SCHED_GROUP_P (next)
+ && advance < effective_cost)
+ advance = effective_cost;
}
else
+ /* Check always has only one forward dependence (to the first insn in
+ the recovery block), therefore, this will be executed only once. */
{
- sp->split_bbs.nr_members = sp->update_bbs.nr_members = 0;
-
- sp->is_speculative = 0;
- sp->src_prob = 0;
+ gcc_assert (sd_lists_empty_p (insn, SD_LIST_FORW));
+ fix_recovery_deps (RECOVERY_BLOCK (insn));
}
}
-} /* compute_trg_info */
+ /* This is the place where scheduler doesn't *basically* need backward and
+ forward dependencies for INSN anymore. Nevertheless they are used in
+ heuristics in rank_for_schedule (), early_queue_to_ready () and in
+ some targets (e.g. rs6000). Thus the earliest place where we *can*
+ remove dependencies is after targetm.sched.md_finish () call in
+ schedule_block (). But, on the other side, the safest place to remove
+ dependencies is when we are finishing scheduling entire region. As we
+ don't generate [many] dependencies during scheduling itself, we won't
+ need memory until beginning of next region.
+ Bottom line: Dependencies are removed for all insns in the end of
+ scheduling the region. */
+
+ /* Annotate the instruction with issue information -- TImode
+ indicates that the instruction is expected not to be able
+ to issue on the same cycle as the previous insn. A machine
+ may use this information to decide how the instruction should
+ be aligned. */
+ if (issue_rate > 1
+ && GET_CODE (PATTERN (insn)) != USE
+ && GET_CODE (PATTERN (insn)) != CLOBBER
+ && !DEBUG_INSN_P (insn))
+ {
+ if (reload_completed)
+ PUT_MODE (insn, clock_var > last_clock_var ? TImode : VOIDmode);
+ last_clock_var = clock_var;
+ }
+
+ return advance;
+}
-/* Print candidates info, for debugging purposes. Callable from debugger. */
+/* Functions for handling of notes. */
+/* Add note list that ends on FROM_END to the end of TO_ENDP. */
void
-debug_candidate (i)
- int i;
+concat_note_lists (rtx from_end, rtx *to_endp)
{
- if (!candidate_table[i].is_valid)
+ rtx from_start;
+
+ /* It's easy when have nothing to concat. */
+ if (from_end == NULL)
return;
- if (candidate_table[i].is_speculative)
+ /* It's also easy when destination is empty. */
+ if (*to_endp == NULL)
{
- int j;
- fprintf (dump, "src b %d bb %d speculative \n", BB_TO_BLOCK (i), i);
+ *to_endp = from_end;
+ return;
+ }
- fprintf (dump, "split path: ");
- for (j = 0; j < candidate_table[i].split_bbs.nr_members; j++)
- {
- int b = candidate_table[i].split_bbs.first_member[j];
+ from_start = from_end;
+ while (PREV_INSN (from_start) != NULL)
+ from_start = PREV_INSN (from_start);
- fprintf (dump, " %d ", b);
- }
- fprintf (dump, "\n");
+ PREV_INSN (from_start) = *to_endp;
+ NEXT_INSN (*to_endp) = from_start;
+ *to_endp = from_end;
+}
+
+/* Delete notes between HEAD and TAIL and put them in the chain
+ of notes ended by NOTE_LIST. */
+void
+remove_notes (rtx head, rtx tail)
+{
+ rtx next_tail, insn, next;
+
+ note_list = 0;
+ if (head == tail && !INSN_P (head))
+ return;
+
+ next_tail = NEXT_INSN (tail);
+ for (insn = head; insn != next_tail; insn = next)
+ {
+ next = NEXT_INSN (insn);
+ if (!NOTE_P (insn))
+ continue;
- fprintf (dump, "update path: ");
- for (j = 0; j < candidate_table[i].update_bbs.nr_members; j++)
+ switch (NOTE_KIND (insn))
{
- int b = candidate_table[i].update_bbs.first_member[j];
+ case NOTE_INSN_BASIC_BLOCK:
+ continue;
+
+ case NOTE_INSN_EPILOGUE_BEG:
+ if (insn != tail)
+ {
+ remove_insn (insn);
+ add_reg_note (next, REG_SAVE_NOTE,
+ GEN_INT (NOTE_INSN_EPILOGUE_BEG));
+ break;
+ }
+ /* FALLTHRU */
+
+ default:
+ remove_insn (insn);
- fprintf (dump, " %d ", b);
+ /* Add the note to list that ends at NOTE_LIST. */
+ PREV_INSN (insn) = note_list;
+ NEXT_INSN (insn) = NULL_RTX;
+ if (note_list)
+ NEXT_INSN (note_list) = insn;
+ note_list = insn;
+ break;
}
- fprintf (dump, "\n");
- }
- else
- {
- fprintf (dump, " src %d equivalent\n", BB_TO_BLOCK (i));
+
+ gcc_assert ((sel_sched_p () || insn != tail) && insn != head);
}
}
-/* Print candidates info, for debugging purposes. Callable from debugger. */
-
+/* Return the head and tail pointers of ebb starting at BEG and ending
+ at END. */
void
-debug_candidates (trg)
- int trg;
+get_ebb_head_tail (basic_block beg, basic_block end, rtx *headp, rtx *tailp)
{
- int i;
-
- fprintf (dump, "----------- candidate table: target: b=%d bb=%d ---\n",
- BB_TO_BLOCK (trg), trg);
- for (i = trg + 1; i < current_nr_blocks; i++)
- debug_candidate (i);
-}
-
+ rtx beg_head = BB_HEAD (beg);
+ rtx beg_tail = BB_END (beg);
+ rtx end_head = BB_HEAD (end);
+ rtx end_tail = BB_END (end);
-/* Functions for speculative scheduing. */
+ /* Don't include any notes or labels at the beginning of the BEG
+ basic block, or notes at the end of the END basic blocks. */
-/* Return 0 if x is a set of a register alive in the beginning of one
- of the split-blocks of src, otherwise return 1. */
+ if (LABEL_P (beg_head))
+ beg_head = NEXT_INSN (beg_head);
-static int
-check_live_1 (src, x)
- int src;
- rtx x;
-{
- register int i;
- register int regno;
- register rtx reg = SET_DEST (x);
+ while (beg_head != beg_tail)
+ if (NOTE_P (beg_head) || BOUNDARY_DEBUG_INSN_P (beg_head))
+ beg_head = NEXT_INSN (beg_head);
+ else
+ break;
- if (reg == 0)
- return 1;
+ *headp = beg_head;
- while (GET_CODE (reg) == SUBREG || GET_CODE (reg) == ZERO_EXTRACT
- || GET_CODE (reg) == SIGN_EXTRACT
- || GET_CODE (reg) == STRICT_LOW_PART)
- reg = XEXP (reg, 0);
+ if (beg == end)
+ end_head = beg_head;
+ else if (LABEL_P (end_head))
+ end_head = NEXT_INSN (end_head);
- if (GET_CODE (reg) == PARALLEL
- && GET_MODE (reg) == BLKmode)
- {
- register int i;
- for (i = XVECLEN (reg, 0) - 1; i >= 0; i--)
- if (check_live_1 (src, XVECEXP (reg, 0, i)))
- return 1;
- return 0;
- }
+ while (end_head != end_tail)
+ if (NOTE_P (end_tail) || BOUNDARY_DEBUG_INSN_P (end_tail))
+ end_tail = PREV_INSN (end_tail);
+ else
+ break;
- if (GET_CODE (reg) != REG)
- return 1;
+ *tailp = end_tail;
+}
- regno = REGNO (reg);
+/* Return nonzero if there are no real insns in the range [ HEAD, TAIL ]. */
- if (regno < FIRST_PSEUDO_REGISTER && global_regs[regno])
+int
+no_real_insns_p (const_rtx head, const_rtx tail)
+{
+ while (head != NEXT_INSN (tail))
{
- /* Global registers are assumed live. */
- return 0;
+ if (!NOTE_P (head) && !LABEL_P (head)
+ && !BOUNDARY_DEBUG_INSN_P (head))
+ return 0;
+ head = NEXT_INSN (head);
}
- else
+ return 1;
+}
+
+/* Restore-other-notes: NOTE_LIST is the end of a chain of notes
+ previously found among the insns. Insert them just before HEAD. */
+rtx
+restore_other_notes (rtx head, basic_block head_bb)
+{
+ if (note_list != 0)
{
- if (regno < FIRST_PSEUDO_REGISTER)
- {
- /* Check for hard registers. */
- int j = HARD_REGNO_NREGS (regno, GET_MODE (reg));
- while (--j >= 0)
- {
- for (i = 0; i < candidate_table[src].split_bbs.nr_members; i++)
- {
- int b = candidate_table[src].split_bbs.first_member[i];
+ rtx note_head = note_list;
- if (REGNO_REG_SET_P (BASIC_BLOCK (b)->global_live_at_start,
- regno + j))
- {
- return 0;
- }
- }
- }
- }
+ if (head)
+ head_bb = BLOCK_FOR_INSN (head);
else
- {
- /* Check for psuedo registers. */
- for (i = 0; i < candidate_table[src].split_bbs.nr_members; i++)
- {
- int b = candidate_table[src].split_bbs.first_member[i];
+ head = NEXT_INSN (bb_note (head_bb));
- if (REGNO_REG_SET_P (BASIC_BLOCK (b)->global_live_at_start, regno))
- {
- return 0;
- }
- }
+ while (PREV_INSN (note_head))
+ {
+ set_block_for_insn (note_head, head_bb);
+ note_head = PREV_INSN (note_head);
}
+ /* In the above cycle we've missed this note. */
+ set_block_for_insn (note_head, head_bb);
+
+ PREV_INSN (note_head) = PREV_INSN (head);
+ NEXT_INSN (PREV_INSN (head)) = note_head;
+ PREV_INSN (head) = note_list;
+ NEXT_INSN (note_list) = head;
+
+ if (BLOCK_FOR_INSN (head) != head_bb)
+ BB_END (head_bb) = note_list;
+
+ head = note_head;
}
- return 1;
+ return head;
}
-
-/* If x is a set of a register R, mark that R is alive in the beginning
- of every update-block of src. */
+/* Move insns that became ready to fire from queue to ready list. */
static void
-update_live_1 (src, x)
- int src;
- rtx x;
+queue_to_ready (struct ready_list *ready)
{
- register int i;
- register int regno;
- register rtx reg = SET_DEST (x);
-
- if (reg == 0)
- return;
+ rtx insn;
+ rtx link;
+ rtx skip_insn;
- while (GET_CODE (reg) == SUBREG || GET_CODE (reg) == ZERO_EXTRACT
- || GET_CODE (reg) == SIGN_EXTRACT
- || GET_CODE (reg) == STRICT_LOW_PART)
- reg = XEXP (reg, 0);
+ q_ptr = NEXT_Q (q_ptr);
- if (GET_CODE (reg) == PARALLEL
- && GET_MODE (reg) == BLKmode)
+ if (dbg_cnt (sched_insn) == false)
{
- register int i;
- for (i = XVECLEN (reg, 0) - 1; i >= 0; i--)
- update_live_1 (src, XVECEXP (reg, 0, i));
- return;
+ /* If debug counter is activated do not requeue insn next after
+ last_scheduled_insn. */
+ skip_insn = next_nonnote_insn (last_scheduled_insn);
+ while (skip_insn && DEBUG_INSN_P (skip_insn))
+ skip_insn = next_nonnote_insn (skip_insn);
}
+ else
+ skip_insn = NULL_RTX;
- if (GET_CODE (reg) != REG)
- return;
-
- /* Global registers are always live, so the code below does not apply
- to them. */
-
- regno = REGNO (reg);
-
- if (regno >= FIRST_PSEUDO_REGISTER || !global_regs[regno])
+ /* Add all pending insns that can be scheduled without stalls to the
+ ready list. */
+ for (link = insn_queue[q_ptr]; link; link = XEXP (link, 1))
{
- if (regno < FIRST_PSEUDO_REGISTER)
- {
- int j = HARD_REGNO_NREGS (regno, GET_MODE (reg));
- while (--j >= 0)
- {
- for (i = 0; i < candidate_table[src].update_bbs.nr_members; i++)
- {
- int b = candidate_table[src].update_bbs.first_member[i];
+ insn = XEXP (link, 0);
+ q_size -= 1;
- SET_REGNO_REG_SET (BASIC_BLOCK (b)->global_live_at_start,
- regno + j);
- }
- }
+ if (sched_verbose >= 2)
+ fprintf (sched_dump, ";;\t\tQ-->Ready: insn %s: ",
+ (*current_sched_info->print_insn) (insn, 0));
+
+ /* If the ready list is full, delay the insn for 1 cycle.
+ See the comment in schedule_block for the rationale. */
+ if (!reload_completed
+ && ready->n_ready - ready->n_debug > MAX_SCHED_READY_INSNS
+ && !SCHED_GROUP_P (insn)
+ && insn != skip_insn)
+ {
+ if (sched_verbose >= 2)
+ fprintf (sched_dump, "requeued because ready full\n");
+ queue_insn (insn, 1);
}
else
{
- for (i = 0; i < candidate_table[src].update_bbs.nr_members; i++)
- {
- int b = candidate_table[src].update_bbs.first_member[i];
-
- SET_REGNO_REG_SET (BASIC_BLOCK (b)->global_live_at_start, regno);
- }
- }
- }
-}
-
-
-/* Return 1 if insn can be speculatively moved from block src to trg,
- otherwise return 0. Called before first insertion of insn to
- ready-list or before the scheduling. */
-
-static int
-check_live (insn, src)
- rtx insn;
- int src;
-{
- /* Find the registers set by instruction. */
- if (GET_CODE (PATTERN (insn)) == SET
- || GET_CODE (PATTERN (insn)) == CLOBBER)
- return check_live_1 (src, PATTERN (insn));
- else if (GET_CODE (PATTERN (insn)) == PARALLEL)
- {
- int j;
- for (j = XVECLEN (PATTERN (insn), 0) - 1; j >= 0; j--)
- if ((GET_CODE (XVECEXP (PATTERN (insn), 0, j)) == SET
- || GET_CODE (XVECEXP (PATTERN (insn), 0, j)) == CLOBBER)
- && !check_live_1 (src, XVECEXP (PATTERN (insn), 0, j)))
- return 0;
-
- return 1;
+ ready_add (ready, insn, false);
+ if (sched_verbose >= 2)
+ fprintf (sched_dump, "moving to ready without stalls\n");
+ }
}
+ free_INSN_LIST_list (&insn_queue[q_ptr]);
- return 1;
-}
-
-
-/* Update the live registers info after insn was moved speculatively from
- block src to trg. */
-
-static void
-update_live (insn, src)
- rtx insn;
- int src;
-{
- /* Find the registers set by instruction. */
- if (GET_CODE (PATTERN (insn)) == SET
- || GET_CODE (PATTERN (insn)) == CLOBBER)
- update_live_1 (src, PATTERN (insn));
- else if (GET_CODE (PATTERN (insn)) == PARALLEL)
+ /* If there are no ready insns, stall until one is ready and add all
+ of the pending insns at that point to the ready list. */
+ if (ready->n_ready == 0)
{
- int j;
- for (j = XVECLEN (PATTERN (insn), 0) - 1; j >= 0; j--)
- if (GET_CODE (XVECEXP (PATTERN (insn), 0, j)) == SET
- || GET_CODE (XVECEXP (PATTERN (insn), 0, j)) == CLOBBER)
- update_live_1 (src, XVECEXP (PATTERN (insn), 0, j));
- }
-}
-
-/* Exception Free Loads:
-
- We define five classes of speculative loads: IFREE, IRISKY,
- PFREE, PRISKY, and MFREE.
-
- IFREE loads are loads that are proved to be exception-free, just
- by examining the load insn. Examples for such loads are loads
- from TOC and loads of global data.
-
- IRISKY loads are loads that are proved to be exception-risky,
- just by examining the load insn. Examples for such loads are
- volatile loads and loads from shared memory.
-
- PFREE loads are loads for which we can prove, by examining other
- insns, that they are exception-free. Currently, this class consists
- of loads for which we are able to find a "similar load", either in
- the target block, or, if only one split-block exists, in that split
- block. Load2 is similar to load1 if both have same single base
- register. We identify only part of the similar loads, by finding
- an insn upon which both load1 and load2 have a DEF-USE dependence.
-
- PRISKY loads are loads for which we can prove, by examining other
- insns, that they are exception-risky. Currently we have two proofs for
- such loads. The first proof detects loads that are probably guarded by a
- test on the memory address. This proof is based on the
- backward and forward data dependence information for the region.
- Let load-insn be the examined load.
- Load-insn is PRISKY iff ALL the following hold:
-
- - insn1 is not in the same block as load-insn
- - there is a DEF-USE dependence chain (insn1, ..., load-insn)
- - test-insn is either a compare or a branch, not in the same block
- as load-insn
- - load-insn is reachable from test-insn
- - there is a DEF-USE dependence chain (insn1, ..., test-insn)
-
- This proof might fail when the compare and the load are fed
- by an insn not in the region. To solve this, we will add to this
- group all loads that have no input DEF-USE dependence.
-
- The second proof detects loads that are directly or indirectly
- fed by a speculative load. This proof is affected by the
- scheduling process. We will use the flag fed_by_spec_load.
- Initially, all insns have this flag reset. After a speculative
- motion of an insn, if insn is either a load, or marked as
- fed_by_spec_load, we will also mark as fed_by_spec_load every
- insn1 for which a DEF-USE dependence (insn, insn1) exists. A
- load which is fed_by_spec_load is also PRISKY.
-
- MFREE (maybe-free) loads are all the remaining loads. They may be
- exception-free, but we cannot prove it.
-
- Now, all loads in IFREE and PFREE classes are considered
- exception-free, while all loads in IRISKY and PRISKY classes are
- considered exception-risky. As for loads in the MFREE class,
- these are considered either exception-free or exception-risky,
- depending on whether we are pessimistic or optimistic. We have
- to take the pessimistic approach to assure the safety of
- speculative scheduling, but we can take the optimistic approach
- by invoking the -fsched_spec_load_dangerous option. */
-
-enum INSN_TRAP_CLASS
-{
- TRAP_FREE = 0, IFREE = 1, PFREE_CANDIDATE = 2,
- PRISKY_CANDIDATE = 3, IRISKY = 4, TRAP_RISKY = 5
-};
-
-#define WORST_CLASS(class1, class2) \
-((class1 > class2) ? class1 : class2)
-
-/* Non-zero if block bb_to is equal to, or reachable from block bb_from. */
-#define IS_REACHABLE(bb_from, bb_to) \
-(bb_from == bb_to \
- || IS_RGN_ENTRY (bb_from) \
- || (bitset_member (ancestor_edges[bb_to], \
- EDGE_TO_BIT (IN_EDGES (BB_TO_BLOCK (bb_from))), \
- edgeset_size)))
-
-/* Non-zero iff the address is comprised from at most 1 register. */
-#define CONST_BASED_ADDRESS_P(x) \
- (GET_CODE (x) == REG \
- || ((GET_CODE (x) == PLUS || GET_CODE (x) == MINUS \
- || (GET_CODE (x) == LO_SUM)) \
- && (GET_CODE (XEXP (x, 0)) == CONST_INT \
- || GET_CODE (XEXP (x, 1)) == CONST_INT)))
-
-/* Turns on the fed_by_spec_load flag for insns fed by load_insn. */
+ int stalls;
-static void
-set_spec_fed (load_insn)
- rtx load_insn;
-{
- rtx link;
-
- for (link = INSN_DEPEND (load_insn); link; link = XEXP (link, 1))
- if (GET_MODE (link) == VOIDmode)
- FED_BY_SPEC_LOAD (XEXP (link, 0)) = 1;
-} /* set_spec_fed */
-
-/* On the path from the insn to load_insn_bb, find a conditional
-branch depending on insn, that guards the speculative load. */
-
-static int
-find_conditional_protection (insn, load_insn_bb)
- rtx insn;
- int load_insn_bb;
-{
- rtx link;
-
- /* Iterate through DEF-USE forward dependences. */
- for (link = INSN_DEPEND (insn); link; link = XEXP (link, 1))
- {
- rtx next = XEXP (link, 0);
- if ((CONTAINING_RGN (BLOCK_NUM (next)) ==
- CONTAINING_RGN (BB_TO_BLOCK (load_insn_bb)))
- && IS_REACHABLE (INSN_BB (next), load_insn_bb)
- && load_insn_bb != INSN_BB (next)
- && GET_MODE (link) == VOIDmode
- && (GET_CODE (next) == JUMP_INSN
- || find_conditional_protection (next, load_insn_bb)))
- return 1;
- }
- return 0;
-} /* find_conditional_protection */
-
-/* Returns 1 if the same insn1 that participates in the computation
- of load_insn's address is feeding a conditional branch that is
- guarding on load_insn. This is true if we find a the two DEF-USE
- chains:
- insn1 -> ... -> conditional-branch
- insn1 -> ... -> load_insn,
- and if a flow path exist:
- insn1 -> ... -> conditional-branch -> ... -> load_insn,
- and if insn1 is on the path
- region-entry -> ... -> bb_trg -> ... load_insn.
-
- Locate insn1 by climbing on LOG_LINKS from load_insn.
- Locate the branch by following INSN_DEPEND from insn1. */
+ for (stalls = 1; stalls <= max_insn_queue_index; stalls++)
+ {
+ if ((link = insn_queue[NEXT_Q_AFTER (q_ptr, stalls)]))
+ {
+ for (; link; link = XEXP (link, 1))
+ {
+ insn = XEXP (link, 0);
+ q_size -= 1;
-static int
-is_conditionally_protected (load_insn, bb_src, bb_trg)
- rtx load_insn;
- int bb_src, bb_trg;
-{
- rtx link;
+ if (sched_verbose >= 2)
+ fprintf (sched_dump, ";;\t\tQ-->Ready: insn %s: ",
+ (*current_sched_info->print_insn) (insn, 0));
- for (link = LOG_LINKS (load_insn); link; link = XEXP (link, 1))
- {
- rtx insn1 = XEXP (link, 0);
+ ready_add (ready, insn, false);
+ if (sched_verbose >= 2)
+ fprintf (sched_dump, "moving to ready with %d stalls\n", stalls);
+ }
+ free_INSN_LIST_list (&insn_queue[NEXT_Q_AFTER (q_ptr, stalls)]);
- /* Must be a DEF-USE dependence upon non-branch. */
- if (GET_MODE (link) != VOIDmode
- || GET_CODE (insn1) == JUMP_INSN)
- continue;
+ advance_one_cycle ();
- /* Must exist a path: region-entry -> ... -> bb_trg -> ... load_insn. */
- if (INSN_BB (insn1) == bb_src
- || (CONTAINING_RGN (BLOCK_NUM (insn1))
- != CONTAINING_RGN (BB_TO_BLOCK (bb_src)))
- || (!IS_REACHABLE (bb_trg, INSN_BB (insn1))
- && !IS_REACHABLE (INSN_BB (insn1), bb_trg)))
- continue;
+ break;
+ }
- /* Now search for the conditional-branch. */
- if (find_conditional_protection (insn1, bb_src))
- return 1;
+ advance_one_cycle ();
+ }
- /* Recursive step: search another insn1, "above" current insn1. */
- return is_conditionally_protected (insn1, bb_src, bb_trg);
+ q_ptr = NEXT_Q_AFTER (q_ptr, stalls);
+ clock_var += stalls;
}
+}
- /* The chain does not exist. */
- return 0;
-} /* is_conditionally_protected */
-
-/* Returns 1 if a clue for "similar load" 'insn2' is found, and hence
- load_insn can move speculatively from bb_src to bb_trg. All the
- following must hold:
-
- (1) both loads have 1 base register (PFREE_CANDIDATEs).
- (2) load_insn and load1 have a def-use dependence upon
- the same insn 'insn1'.
- (3) either load2 is in bb_trg, or:
- - there's only one split-block, and
- - load1 is on the escape path, and
-
- From all these we can conclude that the two loads access memory
- addresses that differ at most by a constant, and hence if moving
- load_insn would cause an exception, it would have been caused by
- load2 anyhow. */
-
-static int
-is_pfree (load_insn, bb_src, bb_trg)
- rtx load_insn;
- int bb_src, bb_trg;
+/* Used by early_queue_to_ready. Determines whether it is "ok" to
+ prematurely move INSN from the queue to the ready list. Currently,
+ if a target defines the hook 'is_costly_dependence', this function
+ uses the hook to check whether there exist any dependences which are
+ considered costly by the target, between INSN and other insns that
+ have already been scheduled. Dependences are checked up to Y cycles
+ back, with default Y=1; The flag -fsched-stalled-insns-dep=Y allows
+ controlling this value.
+ (Other considerations could be taken into account instead (or in
+ addition) depending on user flags and target hooks. */
+
+static bool
+ok_for_early_queue_removal (rtx insn)
{
- rtx back_link;
- register candidate *candp = candidate_table + bb_src;
-
- if (candp->split_bbs.nr_members != 1)
- /* Must have exactly one escape block. */
- return 0;
+ int n_cycles;
+ rtx prev_insn = last_scheduled_insn;
- for (back_link = LOG_LINKS (load_insn);
- back_link; back_link = XEXP (back_link, 1))
+ if (targetm.sched.is_costly_dependence)
{
- rtx insn1 = XEXP (back_link, 0);
-
- if (GET_MODE (back_link) == VOIDmode)
+ for (n_cycles = flag_sched_stalled_insns_dep; n_cycles; n_cycles--)
{
- /* Found a DEF-USE dependence (insn1, load_insn). */
- rtx fore_link;
-
- for (fore_link = INSN_DEPEND (insn1);
- fore_link; fore_link = XEXP (fore_link, 1))
+ for ( ; prev_insn; prev_insn = PREV_INSN (prev_insn))
{
- rtx insn2 = XEXP (fore_link, 0);
- if (GET_MODE (fore_link) == VOIDmode)
- {
- /* Found a DEF-USE dependence (insn1, insn2). */
- if (haifa_classify_insn (insn2) != PFREE_CANDIDATE)
- /* insn2 not guaranteed to be a 1 base reg load. */
- continue;
-
- if (INSN_BB (insn2) == bb_trg)
- /* insn2 is the similar load, in the target block. */
- return 1;
-
- if (*(candp->split_bbs.first_member) == BLOCK_NUM (insn2))
- /* insn2 is a similar load, in a split-block. */
- return 1;
- }
- }
- }
- }
+ int cost;
- /* Couldn't find a similar load. */
- return 0;
-} /* is_pfree */
-
-/* Returns a class that insn with GET_DEST(insn)=x may belong to,
- as found by analyzing insn's expression. */
-
-static int
-may_trap_exp (x, is_store)
- rtx x;
- int is_store;
-{
- enum rtx_code code;
-
- if (x == 0)
- return TRAP_FREE;
- code = GET_CODE (x);
- if (is_store)
- {
- if (code == MEM)
- return TRAP_RISKY;
- else
- return TRAP_FREE;
- }
- if (code == MEM)
- {
- /* The insn uses memory: a volatile load. */
- if (MEM_VOLATILE_P (x))
- return IRISKY;
- /* An exception-free load. */
- if (!may_trap_p (x))
- return IFREE;
- /* A load with 1 base register, to be further checked. */
- if (CONST_BASED_ADDRESS_P (XEXP (x, 0)))
- return PFREE_CANDIDATE;
- /* No info on the load, to be further checked. */
- return PRISKY_CANDIDATE;
- }
- else
- {
- const char *fmt;
- int i, insn_class = TRAP_FREE;
-
- /* Neither store nor load, check if it may cause a trap. */
- if (may_trap_p (x))
- return TRAP_RISKY;
- /* Recursive step: walk the insn... */
- fmt = GET_RTX_FORMAT (code);
- for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
- {
- if (fmt[i] == 'e')
- {
- int tmp_class = may_trap_exp (XEXP (x, i), is_store);
- insn_class = WORST_CLASS (insn_class, tmp_class);
- }
- else if (fmt[i] == 'E')
- {
- int j;
- for (j = 0; j < XVECLEN (x, i); j++)
+ if (prev_insn == current_sched_info->prev_head)
{
- int tmp_class = may_trap_exp (XVECEXP (x, i, j), is_store);
- insn_class = WORST_CLASS (insn_class, tmp_class);
- if (insn_class == TRAP_RISKY || insn_class == IRISKY)
- break;
+ prev_insn = NULL;
+ break;
}
- }
- if (insn_class == TRAP_RISKY || insn_class == IRISKY)
- break;
- }
- return insn_class;
- }
-} /* may_trap_exp */
+ if (!NOTE_P (prev_insn))
+ {
+ dep_t dep;
-/* Classifies insn for the purpose of verifying that it can be
- moved speculatively, by examining it's patterns, returning:
- TRAP_RISKY: store, or risky non-load insn (e.g. division by variable).
- TRAP_FREE: non-load insn.
- IFREE: load from a globaly safe location.
- IRISKY: volatile load.
- PFREE_CANDIDATE, PRISKY_CANDIDATE: load that need to be checked for
- being either PFREE or PRISKY. */
+ dep = sd_find_dep_between (prev_insn, insn, true);
-static int
-haifa_classify_insn (insn)
- rtx insn;
-{
- rtx pat = PATTERN (insn);
- int tmp_class = TRAP_FREE;
- int insn_class = TRAP_FREE;
- enum rtx_code code;
+ if (dep != NULL)
+ {
+ cost = dep_cost (dep);
- if (GET_CODE (pat) == PARALLEL)
- {
- int i, len = XVECLEN (pat, 0);
+ if (targetm.sched.is_costly_dependence (dep, cost,
+ flag_sched_stalled_insns_dep - n_cycles))
+ return false;
+ }
+ }
- for (i = len - 1; i >= 0; i--)
- {
- code = GET_CODE (XVECEXP (pat, 0, i));
- switch (code)
- {
- case CLOBBER:
- /* Test if it is a 'store'. */
- tmp_class = may_trap_exp (XEXP (XVECEXP (pat, 0, i), 0), 1);
- break;
- case SET:
- /* Test if it is a store. */
- tmp_class = may_trap_exp (SET_DEST (XVECEXP (pat, 0, i)), 1);
- if (tmp_class == TRAP_RISKY)
+ if (GET_MODE (prev_insn) == TImode) /* end of dispatch group */
break;
- /* Test if it is a load. */
- tmp_class =
- WORST_CLASS (tmp_class,
- may_trap_exp (SET_SRC (XVECEXP (pat, 0, i)), 0));
- break;
- case TRAP_IF:
- tmp_class = TRAP_RISKY;
- break;
- default:;
}
- insn_class = WORST_CLASS (insn_class, tmp_class);
- if (insn_class == TRAP_RISKY || insn_class == IRISKY)
- break;
- }
- }
- else
- {
- code = GET_CODE (pat);
- switch (code)
- {
- case CLOBBER:
- /* Test if it is a 'store'. */
- tmp_class = may_trap_exp (XEXP (pat, 0), 1);
- break;
- case SET:
- /* Test if it is a store. */
- tmp_class = may_trap_exp (SET_DEST (pat), 1);
- if (tmp_class == TRAP_RISKY)
+
+ if (!prev_insn)
break;
- /* Test if it is a load. */
- tmp_class =
- WORST_CLASS (tmp_class,
- may_trap_exp (SET_SRC (pat), 0));
- break;
- case TRAP_IF:
- tmp_class = TRAP_RISKY;
- break;
- default:;
+ prev_insn = PREV_INSN (prev_insn);
}
- insn_class = tmp_class;
}
- return insn_class;
+ return true;
+}
-} /* haifa_classify_insn */
-/* Return 1 if load_insn is prisky (i.e. if load_insn is fed by
- a load moved speculatively, or if load_insn is protected by
- a compare on load_insn's address). */
+/* Remove insns from the queue, before they become "ready" with respect
+ to FU latency considerations. */
static int
-is_prisky (load_insn, bb_src, bb_trg)
- rtx load_insn;
- int bb_src, bb_trg;
+early_queue_to_ready (state_t state, struct ready_list *ready)
{
- if (FED_BY_SPEC_LOAD (load_insn))
- return 1;
+ rtx insn;
+ rtx link;
+ rtx next_link;
+ rtx prev_link;
+ bool move_to_ready;
+ int cost;
+ state_t temp_state = alloca (dfa_state_size);
+ int stalls;
+ int insns_removed = 0;
- if (LOG_LINKS (load_insn) == NULL)
- /* Dependence may 'hide' out of the region. */
- return 1;
+ /*
+ Flag '-fsched-stalled-insns=X' determines the aggressiveness of this
+ function:
- if (is_conditionally_protected (load_insn, bb_src, bb_trg))
- return 1;
+ X == 0: There is no limit on how many queued insns can be removed
+ prematurely. (flag_sched_stalled_insns = -1).
- return 0;
-} /* is_prisky */
+ X >= 1: Only X queued insns can be removed prematurely in each
+ invocation. (flag_sched_stalled_insns = X).
-/* Insn is a candidate to be moved speculatively from bb_src to bb_trg.
- Return 1 if insn is exception-free (and the motion is valid)
- and 0 otherwise. */
+ Otherwise: Early queue removal is disabled.
+ (flag_sched_stalled_insns = 0)
+ */
-static int
-is_exception_free (insn, bb_src, bb_trg)
- rtx insn;
- int bb_src, bb_trg;
-{
- int insn_class = haifa_classify_insn (insn);
-
- /* Handle non-load insns. */
- switch (insn_class)
- {
- case TRAP_FREE:
- return 1;
- case TRAP_RISKY:
- return 0;
- default:;
- }
-
- /* Handle loads. */
- if (!flag_schedule_speculative_load)
+ if (! flag_sched_stalled_insns)
return 0;
- IS_LOAD_INSN (insn) = 1;
- switch (insn_class)
- {
- case IFREE:
- return (1);
- case IRISKY:
- return 0;
- case PFREE_CANDIDATE:
- if (is_pfree (insn, bb_src, bb_trg))
- return 1;
- /* Don't 'break' here: PFREE-candidate is also PRISKY-candidate. */
- case PRISKY_CANDIDATE:
- if (!flag_schedule_speculative_load_dangerous
- || is_prisky (insn, bb_src, bb_trg))
- return 0;
- break;
- default:;
- }
-
- return flag_schedule_speculative_load_dangerous;
-} /* is_exception_free */
-
-/* Process an insn's memory dependencies. There are four kinds of
- dependencies:
-
- (0) read dependence: read follows read
- (1) true dependence: read follows write
- (2) anti dependence: write follows read
- (3) output dependence: write follows write
-
- We are careful to build only dependencies which actually exist, and
- use transitivity to avoid building too many links. */
-\f
-/* Return the INSN_LIST containing INSN in LIST, or NULL
- if LIST does not contain INSN. */
-
-HAIFA_INLINE static rtx
-find_insn_list (insn, list)
- rtx insn;
- rtx list;
-{
- while (list)
+ for (stalls = 0; stalls <= max_insn_queue_index; stalls++)
{
- if (XEXP (list, 0) == insn)
- return list;
- list = XEXP (list, 1);
- }
- return 0;
-}
-
+ if ((link = insn_queue[NEXT_Q_AFTER (q_ptr, stalls)]))
+ {
+ if (sched_verbose > 6)
+ fprintf (sched_dump, ";; look at index %d + %d\n", q_ptr, stalls);
-/* Return 1 if the pair (insn, x) is found in (LIST, LIST1), or 0
- otherwise. */
+ prev_link = 0;
+ while (link)
+ {
+ next_link = XEXP (link, 1);
+ insn = XEXP (link, 0);
+ if (insn && sched_verbose > 6)
+ print_rtl_single (sched_dump, insn);
+
+ memcpy (temp_state, state, dfa_state_size);
+ if (recog_memoized (insn) < 0)
+ /* non-negative to indicate that it's not ready
+ to avoid infinite Q->R->Q->R... */
+ cost = 0;
+ else
+ cost = state_transition (temp_state, insn);
-HAIFA_INLINE static char
-find_insn_mem_list (insn, x, list, list1)
- rtx insn, x;
- rtx list, list1;
-{
- while (list)
- {
- if (XEXP (list, 0) == insn
- && XEXP (list1, 0) == x)
- return 1;
- list = XEXP (list, 1);
- list1 = XEXP (list1, 1);
- }
- return 0;
-}
+ if (sched_verbose >= 6)
+ fprintf (sched_dump, "transition cost = %d\n", cost);
+ move_to_ready = false;
+ if (cost < 0)
+ {
+ move_to_ready = ok_for_early_queue_removal (insn);
+ if (move_to_ready == true)
+ {
+ /* move from Q to R */
+ q_size -= 1;
+ ready_add (ready, insn, false);
-/* Compute the function units used by INSN. This caches the value
- returned by function_units_used. A function unit is encoded as the
- unit number if the value is non-negative and the compliment of a
- mask if the value is negative. A function unit index is the
- non-negative encoding. */
+ if (prev_link)
+ XEXP (prev_link, 1) = next_link;
+ else
+ insn_queue[NEXT_Q_AFTER (q_ptr, stalls)] = next_link;
-HAIFA_INLINE static int
-insn_unit (insn)
- rtx insn;
-{
- register int unit = INSN_UNIT (insn);
+ free_INSN_LIST_node (link);
- if (unit == 0)
- {
- recog_memoized (insn);
+ if (sched_verbose >= 2)
+ fprintf (sched_dump, ";;\t\tEarly Q-->Ready: insn %s\n",
+ (*current_sched_info->print_insn) (insn, 0));
- /* A USE insn, or something else we don't need to understand.
- We can't pass these directly to function_units_used because it will
- trigger a fatal error for unrecognizable insns. */
- if (INSN_CODE (insn) < 0)
- unit = -1;
- else
- {
- unit = function_units_used (insn);
- /* Increment non-negative values so we can cache zero. */
- if (unit >= 0)
- unit++;
- }
- /* We only cache 16 bits of the result, so if the value is out of
- range, don't cache it. */
- if (FUNCTION_UNITS_SIZE < HOST_BITS_PER_SHORT
- || unit >= 0
- || (unit & ~((1 << (HOST_BITS_PER_SHORT - 1)) - 1)) == 0)
- INSN_UNIT (insn) = unit;
- }
- return (unit > 0 ? unit - 1 : unit);
-}
+ insns_removed++;
+ if (insns_removed == flag_sched_stalled_insns)
+ /* Remove no more than flag_sched_stalled_insns insns
+ from Q at a time. */
+ return insns_removed;
+ }
+ }
-/* Compute the blockage range for executing INSN on UNIT. This caches
- the value returned by the blockage_range_function for the unit.
- These values are encoded in an int where the upper half gives the
- minimum value and the lower half gives the maximum value. */
+ if (move_to_ready == false)
+ prev_link = link;
-HAIFA_INLINE static unsigned int
-blockage_range (unit, insn)
- int unit;
- rtx insn;
-{
- unsigned int blockage = INSN_BLOCKAGE (insn);
- unsigned int range;
+ link = next_link;
+ } /* while link */
+ } /* if link */
- if ((int) UNIT_BLOCKED (blockage) != unit + 1)
- {
- range = function_units[unit].blockage_range_function (insn);
- /* We only cache the blockage range for one unit and then only if
- the values fit. */
- if (HOST_BITS_PER_INT >= UNIT_BITS + 2 * BLOCKAGE_BITS)
- INSN_BLOCKAGE (insn) = ENCODE_BLOCKAGE (unit + 1, range);
- }
- else
- range = BLOCKAGE_RANGE (blockage);
+ } /* for stalls.. */
- return range;
+ return insns_removed;
}
-/* A vector indexed by function unit instance giving the last insn to use
- the unit. The value of the function unit instance index for unit U
- instance I is (U + I * FUNCTION_UNITS_SIZE). */
-static rtx unit_last_insn[FUNCTION_UNITS_SIZE * MAX_MULTIPLICITY];
-
-/* A vector indexed by function unit instance giving the minimum time when
- the unit will unblock based on the maximum blockage cost. */
-static int unit_tick[FUNCTION_UNITS_SIZE * MAX_MULTIPLICITY];
-/* A vector indexed by function unit number giving the number of insns
- that remain to use the unit. */
-static int unit_n_insns[FUNCTION_UNITS_SIZE];
-
-/* Reset the function unit state to the null state. */
+/* Print the ready list for debugging purposes. Callable from debugger. */
static void
-clear_units ()
+debug_ready_list (struct ready_list *ready)
{
- bzero ((char *) unit_last_insn, sizeof (unit_last_insn));
- bzero ((char *) unit_tick, sizeof (unit_tick));
- bzero ((char *) unit_n_insns, sizeof (unit_n_insns));
-}
-
-/* Return the issue-delay of an insn. */
+ rtx *p;
+ int i;
-HAIFA_INLINE static int
-insn_issue_delay (insn)
- rtx insn;
-{
- int i, delay = 0;
- int unit = insn_unit (insn);
-
- /* Efficiency note: in fact, we are working 'hard' to compute a
- value that was available in md file, and is not available in
- function_units[] structure. It would be nice to have this
- value there, too. */
- if (unit >= 0)
+ if (ready->n_ready == 0)
{
- if (function_units[unit].blockage_range_function &&
- function_units[unit].blockage_function)
- delay = function_units[unit].blockage_function (insn, insn);
+ fprintf (sched_dump, "\n");
+ return;
}
- else
- for (i = 0, unit = ~unit; unit; i++, unit >>= 1)
- if ((unit & 1) != 0 && function_units[i].blockage_range_function
- && function_units[i].blockage_function)
- delay = MAX (delay, function_units[i].blockage_function (insn, insn));
-
- return delay;
-}
-/* Return the actual hazard cost of executing INSN on the unit UNIT,
- instance INSTANCE at time CLOCK if the previous actual hazard cost
- was COST. */
-
-HAIFA_INLINE static int
-actual_hazard_this_instance (unit, instance, insn, clock, cost)
- int unit, instance, clock, cost;
- rtx insn;
-{
- int tick = unit_tick[instance]; /* Issue time of the last issued insn. */
-
- if (tick - clock > cost)
+ p = ready_lastpos (ready);
+ for (i = 0; i < ready->n_ready; i++)
{
- /* The scheduler is operating forward, so unit's last insn is the
- executing insn and INSN is the candidate insn. We want a
- more exact measure of the blockage if we execute INSN at CLOCK
- given when we committed the execution of the unit's last insn.
-
- The blockage value is given by either the unit's max blockage
- constant, blockage range function, or blockage function. Use
- the most exact form for the given unit. */
-
- if (function_units[unit].blockage_range_function)
- {
- if (function_units[unit].blockage_function)
- tick += (function_units[unit].blockage_function
- (unit_last_insn[instance], insn)
- - function_units[unit].max_blockage);
- else
- tick += ((int) MAX_BLOCKAGE_COST (blockage_range (unit, insn))
- - function_units[unit].max_blockage);
- }
- if (tick - clock > cost)
- cost = tick - clock;
+ fprintf (sched_dump, " %s:%d",
+ (*current_sched_info->print_insn) (p[i], 0),
+ INSN_LUID (p[i]));
+ if (sched_pressure_p)
+ fprintf (sched_dump, "(cost=%d",
+ INSN_REG_PRESSURE_EXCESS_COST_CHANGE (p[i]));
+ if (INSN_TICK (p[i]) > clock_var)
+ fprintf (sched_dump, ":delay=%d", INSN_TICK (p[i]) - clock_var);
+ if (sched_pressure_p)
+ fprintf (sched_dump, ")");
}
- return cost;
+ fprintf (sched_dump, "\n");
}
-/* Record INSN as having begun execution on the units encoded by UNIT at
- time CLOCK. */
-
-HAIFA_INLINE static void
-schedule_unit (unit, insn, clock)
- int unit, clock;
- rtx insn;
+/* Search INSN for REG_SAVE_NOTE notes and convert them back into insn
+ NOTEs. This is used for NOTE_INSN_EPILOGUE_BEG, so that sched-ebb
+ replaces the epilogue note in the correct basic block. */
+void
+reemit_notes (rtx insn)
{
- int i;
+ rtx note, last = insn;
- if (unit >= 0)
+ for (note = REG_NOTES (insn); note; note = XEXP (note, 1))
{
- int instance = unit;
-#if MAX_MULTIPLICITY > 1
- /* Find the first free instance of the function unit and use that
- one. We assume that one is free. */
- for (i = function_units[unit].multiplicity - 1; i > 0; i--)
+ if (REG_NOTE_KIND (note) == REG_SAVE_NOTE)
{
- if (!actual_hazard_this_instance (unit, instance, insn, clock, 0))
- break;
- instance += FUNCTION_UNITS_SIZE;
+ enum insn_note note_type = (enum insn_note) INTVAL (XEXP (note, 0));
+
+ last = emit_note_before (note_type, last);
+ remove_note (insn, note);
}
-#endif
- unit_last_insn[instance] = insn;
- unit_tick[instance] = (clock + function_units[unit].max_blockage);
}
- else
- for (i = 0, unit = ~unit; unit; i++, unit >>= 1)
- if ((unit & 1) != 0)
- schedule_unit (i, insn, clock);
}
-/* Return the actual hazard cost of executing INSN on the units encoded by
- UNIT at time CLOCK if the previous actual hazard cost was COST. */
-
-HAIFA_INLINE static int
-actual_hazard (unit, insn, clock, cost)
- int unit, clock, cost;
- rtx insn;
+/* Move INSN. Reemit notes if needed. Update CFG, if needed. */
+static void
+move_insn (rtx insn, rtx last, rtx nt)
{
- int i;
-
- if (unit >= 0)
+ if (PREV_INSN (insn) != last)
{
- /* Find the instance of the function unit with the minimum hazard. */
- int instance = unit;
- int best_cost = actual_hazard_this_instance (unit, instance, insn,
- clock, cost);
-#if MAX_MULTIPLICITY > 1
- int this_cost;
-
- if (best_cost > cost)
- {
- for (i = function_units[unit].multiplicity - 1; i > 0; i--)
- {
- instance += FUNCTION_UNITS_SIZE;
- this_cost = actual_hazard_this_instance (unit, instance, insn,
- clock, cost);
- if (this_cost < best_cost)
- {
- best_cost = this_cost;
- if (this_cost <= cost)
- break;
- }
- }
- }
-#endif
- cost = MAX (cost, best_cost);
- }
- else
- for (i = 0, unit = ~unit; unit; i++, unit >>= 1)
- if ((unit & 1) != 0)
- cost = actual_hazard (i, insn, clock, cost);
+ basic_block bb;
+ rtx note;
+ int jump_p = 0;
- return cost;
-}
+ bb = BLOCK_FOR_INSN (insn);
-/* Return the potential hazard cost of executing an instruction on the
- units encoded by UNIT if the previous potential hazard cost was COST.
- An insn with a large blockage time is chosen in preference to one
- with a smaller time; an insn that uses a unit that is more likely
- to be used is chosen in preference to one with a unit that is less
- used. We are trying to minimize a subsequent actual hazard. */
-
-HAIFA_INLINE static int
-potential_hazard (unit, insn, cost)
- int unit, cost;
- rtx insn;
-{
- int i, ncost;
- unsigned int minb, maxb;
+ /* BB_HEAD is either LABEL or NOTE. */
+ gcc_assert (BB_HEAD (bb) != insn);
- if (unit >= 0)
- {
- minb = maxb = function_units[unit].max_blockage;
- if (maxb > 1)
+ if (BB_END (bb) == insn)
+ /* If this is last instruction in BB, move end marker one
+ instruction up. */
{
- if (function_units[unit].blockage_range_function)
- {
- maxb = minb = blockage_range (unit, insn);
- maxb = MAX_BLOCKAGE_COST (maxb);
- minb = MIN_BLOCKAGE_COST (minb);
- }
+ /* Jumps are always placed at the end of basic block. */
+ jump_p = control_flow_insn_p (insn);
- if (maxb > 1)
- {
- /* Make the number of instructions left dominate. Make the
- minimum delay dominate the maximum delay. If all these
- are the same, use the unit number to add an arbitrary
- ordering. Other terms can be added. */
- ncost = minb * 0x40 + maxb;
- ncost *= (unit_n_insns[unit] - 1) * 0x1000 + unit;
- if (ncost > cost)
- cost = ncost;
- }
+ gcc_assert (!jump_p
+ || ((common_sched_info->sched_pass_id == SCHED_RGN_PASS)
+ && IS_SPECULATION_BRANCHY_CHECK_P (insn))
+ || (common_sched_info->sched_pass_id
+ == SCHED_EBB_PASS));
+
+ gcc_assert (BLOCK_FOR_INSN (PREV_INSN (insn)) == bb);
+
+ BB_END (bb) = PREV_INSN (insn);
}
- }
- else
- for (i = 0, unit = ~unit; unit; i++, unit >>= 1)
- if ((unit & 1) != 0)
- cost = potential_hazard (i, insn, cost);
- return cost;
-}
+ gcc_assert (BB_END (bb) != last);
-/* Compute cost of executing INSN given the dependence LINK on the insn USED.
- This is the number of cycles between instruction issue and
- instruction results. */
+ if (jump_p)
+ /* We move the block note along with jump. */
+ {
+ gcc_assert (nt);
-HAIFA_INLINE static int
-insn_cost (insn, link, used)
- rtx insn, link, used;
-{
- register int cost = INSN_COST (insn);
+ note = NEXT_INSN (insn);
+ while (NOTE_NOT_BB_P (note) && note != nt)
+ note = NEXT_INSN (note);
- if (cost == 0)
- {
- recog_memoized (insn);
+ if (note != nt
+ && (LABEL_P (note)
+ || BARRIER_P (note)))
+ note = NEXT_INSN (note);
- /* A USE insn, or something else we don't need to understand.
- We can't pass these directly to result_ready_cost because it will
- trigger a fatal error for unrecognizable insns. */
- if (INSN_CODE (insn) < 0)
- {
- INSN_COST (insn) = 1;
- return 1;
+ gcc_assert (NOTE_INSN_BASIC_BLOCK_P (note));
}
else
- {
- cost = result_ready_cost (insn);
+ note = insn;
- if (cost < 1)
- cost = 1;
+ NEXT_INSN (PREV_INSN (insn)) = NEXT_INSN (note);
+ PREV_INSN (NEXT_INSN (note)) = PREV_INSN (insn);
- INSN_COST (insn) = cost;
- }
- }
+ NEXT_INSN (note) = NEXT_INSN (last);
+ PREV_INSN (NEXT_INSN (last)) = note;
- /* In this case estimate cost without caring how insn is used. */
- if (link == 0 && used == 0)
- return cost;
-
- /* A USE insn should never require the value used to be computed. This
- allows the computation of a function's result and parameter values to
- overlap the return and call. */
- recog_memoized (used);
- if (INSN_CODE (used) < 0)
- LINK_COST_FREE (link) = 1;
-
- /* If some dependencies vary the cost, compute the adjustment. Most
- commonly, the adjustment is complete: either the cost is ignored
- (in the case of an output- or anti-dependence), or the cost is
- unchanged. These values are cached in the link as LINK_COST_FREE
- and LINK_COST_ZERO. */
-
- if (LINK_COST_FREE (link))
- cost = 0;
-#ifdef ADJUST_COST
- else if (!LINK_COST_ZERO (link))
- {
- int ncost = cost;
+ NEXT_INSN (last) = insn;
+ PREV_INSN (insn) = last;
+
+ bb = BLOCK_FOR_INSN (last);
- ADJUST_COST (used, link, insn, ncost);
- if (ncost < 1)
+ if (jump_p)
{
- LINK_COST_FREE (link) = 1;
- ncost = 0;
- }
- if (cost == ncost)
- LINK_COST_ZERO (link) = 1;
- cost = ncost;
- }
-#endif
- return cost;
-}
+ fix_jump_move (insn);
-/* Compute the priority number for INSN. */
+ if (BLOCK_FOR_INSN (insn) != bb)
+ move_block_after_check (insn);
-static int
-priority (insn)
- rtx insn;
-{
- int this_priority;
- rtx link;
+ gcc_assert (BB_END (bb) == last);
+ }
- if (GET_RTX_CLASS (GET_CODE (insn)) != 'i')
- return 0;
+ df_insn_change_bb (insn, bb);
- if ((this_priority = INSN_PRIORITY (insn)) == 0)
- {
- if (INSN_DEPEND (insn) == 0)
- this_priority = insn_cost (insn, 0, 0);
- else
- for (link = INSN_DEPEND (insn); link; link = XEXP (link, 1))
- {
- rtx next;
- int next_priority;
+ /* Update BB_END, if needed. */
+ if (BB_END (bb) == last)
+ BB_END (bb) = insn;
+ }
- if (RTX_INTEGRATED_P (link))
- continue;
+ SCHED_GROUP_P (insn) = 0;
+}
- next = XEXP (link, 0);
+/* Return true if scheduling INSN will finish current clock cycle. */
+static bool
+insn_finishes_cycle_p (rtx insn)
+{
+ if (SCHED_GROUP_P (insn))
+ /* After issuing INSN, rest of the sched_group will be forced to issue
+ in order. Don't make any plans for the rest of cycle. */
+ return true;
- /* Critical path is meaningful in block boundaries only. */
- if (BLOCK_NUM (next) != BLOCK_NUM (insn))
- continue;
+ /* Finishing the block will, apparently, finish the cycle. */
+ if (current_sched_info->insn_finishes_block_p
+ && current_sched_info->insn_finishes_block_p (insn))
+ return true;
- next_priority = insn_cost (insn, link, next) + priority (next);
- if (next_priority > this_priority)
- this_priority = next_priority;
- }
- INSN_PRIORITY (insn) = this_priority;
- }
- return this_priority;
+ return false;
}
-\f
-/* Remove all INSN_LISTs and EXPR_LISTs from the pending lists and add
- them to the unused_*_list variables, so that they can be reused. */
+/* The following structure describe an entry of the stack of choices. */
+struct choice_entry
+{
+ /* Ordinal number of the issued insn in the ready queue. */
+ int index;
+ /* The number of the rest insns whose issues we should try. */
+ int rest;
+ /* The number of issued essential insns. */
+ int n;
+ /* State after issuing the insn. */
+ state_t state;
+};
-static void
-free_pending_lists ()
+/* The following array is used to implement a stack of choices used in
+ function max_issue. */
+static struct choice_entry *choice_stack;
+
+/* The following variable value is number of essential insns issued on
+ the current cycle. An insn is essential one if it changes the
+ processors state. */
+int cycle_issued_insns;
+
+/* This holds the value of the target dfa_lookahead hook. */
+int dfa_lookahead;
+
+/* The following variable value is maximal number of tries of issuing
+ insns for the first cycle multipass insn scheduling. We define
+ this value as constant*(DFA_LOOKAHEAD**ISSUE_RATE). We would not
+ need this constraint if all real insns (with non-negative codes)
+ had reservations because in this case the algorithm complexity is
+ O(DFA_LOOKAHEAD**ISSUE_RATE). Unfortunately, the dfa descriptions
+ might be incomplete and such insn might occur. For such
+ descriptions, the complexity of algorithm (without the constraint)
+ could achieve DFA_LOOKAHEAD ** N , where N is the queue length. */
+static int max_lookahead_tries;
+
+/* The following value is value of hook
+ `first_cycle_multipass_dfa_lookahead' at the last call of
+ `max_issue'. */
+static int cached_first_cycle_multipass_dfa_lookahead = 0;
+
+/* The following value is value of `issue_rate' at the last call of
+ `sched_init'. */
+static int cached_issue_rate = 0;
+
+/* The following function returns maximal (or close to maximal) number
+ of insns which can be issued on the same cycle and one of which
+ insns is insns with the best rank (the first insn in READY). To
+ make this function tries different samples of ready insns. READY
+ is current queue `ready'. Global array READY_TRY reflects what
+ insns are already issued in this try. MAX_POINTS is the sum of points
+ of all instructions in READY. The function stops immediately,
+ if it reached the such a solution, that all instruction can be issued.
+ INDEX will contain index of the best insn in READY. The following
+ function is used only for first cycle multipass scheduling.
+
+ PRIVILEGED_N >= 0
+
+ This function expects recognized insns only. All USEs,
+ CLOBBERs, etc must be filtered elsewhere. */
+int
+max_issue (struct ready_list *ready, int privileged_n, state_t state,
+ int *index)
{
- int bb;
+ int n, i, all, n_ready, best, delay, tries_num, max_points;
+ int more_issue;
+ struct choice_entry *top;
+ rtx insn;
- for (bb = 0; bb < current_nr_blocks; bb++)
+ n_ready = ready->n_ready;
+ gcc_assert (dfa_lookahead >= 1 && privileged_n >= 0
+ && privileged_n <= n_ready);
+
+ /* Init MAX_LOOKAHEAD_TRIES. */
+ if (cached_first_cycle_multipass_dfa_lookahead != dfa_lookahead)
{
- free_INSN_LIST_list (&bb_deps[bb].pending_read_insns);
- free_INSN_LIST_list (&bb_deps[bb].pending_write_insns);
- free_EXPR_LIST_list (&bb_deps[bb].pending_read_mems);
- free_EXPR_LIST_list (&bb_deps[bb].pending_write_mems);
+ cached_first_cycle_multipass_dfa_lookahead = dfa_lookahead;
+ max_lookahead_tries = 100;
+ for (i = 0; i < issue_rate; i++)
+ max_lookahead_tries *= dfa_lookahead;
}
-}
-/* Add an INSN and MEM reference pair to a pending INSN_LIST and MEM_LIST.
- The MEM is a memory reference contained within INSN, which we are saving
- so that we can do memory aliasing on it. */
+ /* Init max_points. */
+ max_points = 0;
+ more_issue = issue_rate - cycle_issued_insns;
-static void
-add_insn_mem_dependence (deps, insn_list, mem_list, insn, mem)
- struct deps *deps;
- rtx *insn_list, *mem_list, insn, mem;
-{
- register rtx link;
+ /* ??? We used to assert here that we never issue more insns than issue_rate.
+ However, some targets (e.g. MIPS/SB1) claim lower issue rate than can be
+ achieved to get better performance. Until these targets are fixed to use
+ scheduler hooks to manipulate insns priority instead, the assert should
+ be disabled.
- link = alloc_INSN_LIST (insn, *insn_list);
- *insn_list = link;
+ gcc_assert (more_issue >= 0); */
- link = alloc_EXPR_LIST (VOIDmode, mem, *mem_list);
- *mem_list = link;
+ for (i = 0; i < n_ready; i++)
+ if (!ready_try [i])
+ {
+ if (more_issue-- > 0)
+ max_points += ISSUE_POINTS (ready_element (ready, i));
+ else
+ break;
+ }
- deps->pending_lists_length++;
-}
-\f
-/* Make a dependency between every memory reference on the pending lists
- and INSN, thus flushing the pending lists. If ONLY_WRITE, don't flush
- the read list. */
+ /* The number of the issued insns in the best solution. */
+ best = 0;
-static void
-flush_pending_lists (deps, insn, only_write)
- struct deps *deps;
- rtx insn;
- int only_write;
-{
- rtx u;
- rtx link;
+ top = choice_stack;
- while (deps->pending_read_insns && ! only_write)
- {
- add_dependence (insn, XEXP (deps->pending_read_insns, 0),
- REG_DEP_ANTI);
+ /* Set initial state of the search. */
+ memcpy (top->state, state, dfa_state_size);
+ top->rest = dfa_lookahead;
+ top->n = 0;
- link = deps->pending_read_insns;
- deps->pending_read_insns = XEXP (deps->pending_read_insns, 1);
- free_INSN_LIST_node (link);
+ /* Count the number of the insns to search among. */
+ for (all = i = 0; i < n_ready; i++)
+ if (!ready_try [i])
+ all++;
- link = deps->pending_read_mems;
- deps->pending_read_mems = XEXP (deps->pending_read_mems, 1);
- free_EXPR_LIST_node (link);
- }
- while (deps->pending_write_insns)
+ /* I is the index of the insn to try next. */
+ i = 0;
+ tries_num = 0;
+ for (;;)
{
- add_dependence (insn, XEXP (deps->pending_write_insns, 0),
- REG_DEP_ANTI);
+ if (/* If we've reached a dead end or searched enough of what we have
+ been asked... */
+ top->rest == 0
+ /* Or have nothing else to try. */
+ || i >= n_ready)
+ {
+ /* ??? (... || i == n_ready). */
+ gcc_assert (i <= n_ready);
+
+ if (top == choice_stack)
+ break;
- link = deps->pending_write_insns;
- deps->pending_write_insns = XEXP (deps->pending_write_insns, 1);
- free_INSN_LIST_node (link);
+ if (best < top - choice_stack)
+ {
+ if (privileged_n)
+ {
+ n = privileged_n;
+ /* Try to find issued privileged insn. */
+ while (n && !ready_try[--n]);
+ }
+
+ if (/* If all insns are equally good... */
+ privileged_n == 0
+ /* Or a privileged insn will be issued. */
+ || ready_try[n])
+ /* Then we have a solution. */
+ {
+ best = top - choice_stack;
+ /* This is the index of the insn issued first in this
+ solution. */
+ *index = choice_stack [1].index;
+ if (top->n == max_points || best == all)
+ break;
+ }
+ }
- link = deps->pending_write_mems;
- deps->pending_write_mems = XEXP (deps->pending_write_mems, 1);
- free_EXPR_LIST_node (link);
+ /* Set ready-list index to point to the last insn
+ ('i++' below will advance it to the next insn). */
+ i = top->index;
+
+ /* Backtrack. */
+ ready_try [i] = 0;
+ top--;
+ memcpy (state, top->state, dfa_state_size);
+ }
+ else if (!ready_try [i])
+ {
+ tries_num++;
+ if (tries_num > max_lookahead_tries)
+ break;
+ insn = ready_element (ready, i);
+ delay = state_transition (state, insn);
+ if (delay < 0)
+ {
+ if (state_dead_lock_p (state)
+ || insn_finishes_cycle_p (insn))
+ /* We won't issue any more instructions in the next
+ choice_state. */
+ top->rest = 0;
+ else
+ top->rest--;
+
+ n = top->n;
+ if (memcmp (top->state, state, dfa_state_size) != 0)
+ n += ISSUE_POINTS (insn);
+
+ /* Advance to the next choice_entry. */
+ top++;
+ /* Initialize it. */
+ top->rest = dfa_lookahead;
+ top->index = i;
+ top->n = n;
+ memcpy (top->state, state, dfa_state_size);
+
+ ready_try [i] = 1;
+ i = -1;
+ }
+ }
+
+ /* Increase ready-list index. */
+ i++;
}
- deps->pending_lists_length = 0;
- /* last_pending_memory_flush is now a list of insns. */
- for (u = deps->last_pending_memory_flush; u; u = XEXP (u, 1))
- add_dependence (insn, XEXP (u, 0), REG_DEP_ANTI);
+ /* Restore the original state of the DFA. */
+ memcpy (state, choice_stack->state, dfa_state_size);
- free_INSN_LIST_list (&deps->last_pending_memory_flush);
- deps->last_pending_memory_flush = alloc_INSN_LIST (insn, NULL_RTX);
+ return best;
}
-/* Analyze a single SET, CLOBBER, PRE_DEC, POST_DEC, PRE_INC or POST_INC
- rtx, X, creating all dependencies generated by the write to the
- destination of X, and reads of everything mentioned. */
-
-static void
-sched_analyze_1 (deps, x, insn)
- struct deps *deps;
- rtx x;
- rtx insn;
+/* The following function chooses insn from READY and modifies
+ READY. The following function is used only for first
+ cycle multipass scheduling.
+ Return:
+ -1 if cycle should be advanced,
+ 0 if INSN_PTR is set to point to the desirable insn,
+ 1 if choose_ready () should be restarted without advancing the cycle. */
+static int
+choose_ready (struct ready_list *ready, rtx *insn_ptr)
{
- register int regno;
- register rtx dest = XEXP (x, 0);
- enum rtx_code code = GET_CODE (x);
-
- if (dest == 0)
- return;
+ int lookahead;
- if (GET_CODE (dest) == PARALLEL
- && GET_MODE (dest) == BLKmode)
+ if (dbg_cnt (sched_insn) == false)
{
- register int i;
- for (i = XVECLEN (dest, 0) - 1; i >= 0; i--)
- sched_analyze_1 (deps, XVECEXP (dest, 0, i), insn);
- if (GET_CODE (x) == SET)
- sched_analyze_2 (deps, SET_SRC (x), insn);
- return;
- }
+ rtx insn;
- while (GET_CODE (dest) == STRICT_LOW_PART || GET_CODE (dest) == SUBREG
- || GET_CODE (dest) == ZERO_EXTRACT || GET_CODE (dest) == SIGN_EXTRACT)
- {
- if (GET_CODE (dest) == ZERO_EXTRACT || GET_CODE (dest) == SIGN_EXTRACT)
+ insn = next_nonnote_insn (last_scheduled_insn);
+
+ if (QUEUE_INDEX (insn) == QUEUE_READY)
+ /* INSN is in the ready_list. */
{
- /* The second and third arguments are values read by this insn. */
- sched_analyze_2 (deps, XEXP (dest, 1), insn);
- sched_analyze_2 (deps, XEXP (dest, 2), insn);
+ ready_remove_insn (insn);
+ *insn_ptr = insn;
+ return 0;
}
- dest = XEXP (dest, 0);
+
+ /* INSN is in the queue. Advance cycle to move it to the ready list. */
+ return -1;
}
- if (GET_CODE (dest) == REG)
+ lookahead = 0;
+
+ if (targetm.sched.first_cycle_multipass_dfa_lookahead)
+ lookahead = targetm.sched.first_cycle_multipass_dfa_lookahead ();
+ if (lookahead <= 0 || SCHED_GROUP_P (ready_element (ready, 0))
+ || DEBUG_INSN_P (ready_element (ready, 0)))
{
- register int i;
+ *insn_ptr = ready_remove_first (ready);
+ return 0;
+ }
+ else
+ {
+ /* Try to choose the better insn. */
+ int index = 0, i, n;
+ rtx insn;
+ int try_data = 1, try_control = 1;
+ ds_t ts;
- regno = REGNO (dest);
+ insn = ready_element (ready, 0);
+ if (INSN_CODE (insn) < 0)
+ {
+ *insn_ptr = ready_remove_first (ready);
+ return 0;
+ }
- /* A hard reg in a wide mode may really be multiple registers.
- If so, mark all of them just like the first. */
- if (regno < FIRST_PSEUDO_REGISTER)
+ if (spec_info
+ && spec_info->flags & (PREFER_NON_DATA_SPEC
+ | PREFER_NON_CONTROL_SPEC))
{
- i = HARD_REGNO_NREGS (regno, GET_MODE (dest));
- while (--i >= 0)
+ for (i = 0, n = ready->n_ready; i < n; i++)
{
- int r = regno + i;
- rtx u;
+ rtx x;
+ ds_t s;
- for (u = deps->reg_last_uses[r]; u; u = XEXP (u, 1))
- add_dependence (insn, XEXP (u, 0), REG_DEP_ANTI);
+ x = ready_element (ready, i);
+ s = TODO_SPEC (x);
- for (u = deps->reg_last_sets[r]; u; u = XEXP (u, 1))
- add_dependence (insn, XEXP (u, 0), REG_DEP_OUTPUT);
-
- /* Clobbers need not be ordered with respect to one
- another, but sets must be ordered with respect to a
- pending clobber. */
- if (code == SET)
+ if (spec_info->flags & PREFER_NON_DATA_SPEC
+ && !(s & DATA_SPEC))
{
- free_INSN_LIST_list (&deps->reg_last_uses[r]);
- for (u = deps->reg_last_clobbers[r]; u; u = XEXP (u, 1))
- add_dependence (insn, XEXP (u, 0), REG_DEP_OUTPUT);
- SET_REGNO_REG_SET (reg_pending_sets, r);
+ try_data = 0;
+ if (!(spec_info->flags & PREFER_NON_CONTROL_SPEC)
+ || !try_control)
+ break;
}
- else
- SET_REGNO_REG_SET (reg_pending_clobbers, r);
- /* Function calls clobber all call_used regs. */
- if (global_regs[r] || (code == SET && call_used_regs[r]))
- for (u = deps->last_function_call; u; u = XEXP (u, 1))
- add_dependence (insn, XEXP (u, 0), REG_DEP_ANTI);
+ if (spec_info->flags & PREFER_NON_CONTROL_SPEC
+ && !(s & CONTROL_SPEC))
+ {
+ try_control = 0;
+ if (!(spec_info->flags & PREFER_NON_DATA_SPEC) || !try_data)
+ break;
+ }
}
}
- else
+
+ ts = TODO_SPEC (insn);
+ if ((ts & SPECULATIVE)
+ && (((!try_data && (ts & DATA_SPEC))
+ || (!try_control && (ts & CONTROL_SPEC)))
+ || (targetm.sched.first_cycle_multipass_dfa_lookahead_guard_spec
+ && !targetm.sched
+ .first_cycle_multipass_dfa_lookahead_guard_spec (insn))))
+ /* Discard speculative instruction that stands first in the ready
+ list. */
{
- rtx u;
+ change_queue_index (insn, 1);
+ return 1;
+ }
- for (u = deps->reg_last_uses[regno]; u; u = XEXP (u, 1))
- add_dependence (insn, XEXP (u, 0), REG_DEP_ANTI);
+ ready_try[0] = 0;
- for (u = deps->reg_last_sets[regno]; u; u = XEXP (u, 1))
- add_dependence (insn, XEXP (u, 0), REG_DEP_OUTPUT);
+ for (i = 1; i < ready->n_ready; i++)
+ {
+ insn = ready_element (ready, i);
- if (code == SET)
- {
- free_INSN_LIST_list (&deps->reg_last_uses[regno]);
- for (u = deps->reg_last_clobbers[regno]; u; u = XEXP (u, 1))
- add_dependence (insn, XEXP (u, 0), REG_DEP_OUTPUT);
- SET_REGNO_REG_SET (reg_pending_sets, regno);
- }
- else
- SET_REGNO_REG_SET (reg_pending_clobbers, regno);
-
- /* Pseudos that are REG_EQUIV to something may be replaced
- by that during reloading. We need only add dependencies for
- the address in the REG_EQUIV note. */
- if (!reload_completed
- && reg_known_equiv_p[regno]
- && GET_CODE (reg_known_value[regno]) == MEM)
- sched_analyze_2 (deps, XEXP (reg_known_value[regno], 0), insn);
-
- /* Don't let it cross a call after scheduling if it doesn't
- already cross one. */
-
- if (REG_N_CALLS_CROSSED (regno) == 0)
- for (u = deps->last_function_call; u; u = XEXP (u, 1))
- add_dependence (insn, XEXP (u, 0), REG_DEP_ANTI);
+ ready_try [i]
+ = ((!try_data && (TODO_SPEC (insn) & DATA_SPEC))
+ || (!try_control && (TODO_SPEC (insn) & CONTROL_SPEC)));
}
- }
- else if (GET_CODE (dest) == MEM)
- {
- /* Writing memory. */
- if (deps->pending_lists_length > 32)
+ /* Let the target filter the search space. */
+ for (i = 1; i < ready->n_ready; i++)
+ if (!ready_try[i])
+ {
+ insn = ready_element (ready, i);
+
+#ifdef ENABLE_CHECKING
+ /* If this insn is recognizable we should have already
+ recognized it earlier.
+ ??? Not very clear where this is supposed to be done.
+ See dep_cost_1. */
+ gcc_assert (INSN_CODE (insn) >= 0
+ || recog_memoized (insn) < 0);
+#endif
+
+ ready_try [i]
+ = (/* INSN_CODE check can be omitted here as it is also done later
+ in max_issue (). */
+ INSN_CODE (insn) < 0
+ || (targetm.sched.first_cycle_multipass_dfa_lookahead_guard
+ && !targetm.sched.first_cycle_multipass_dfa_lookahead_guard
+ (insn)));
+ }
+
+ if (max_issue (ready, 1, curr_state, &index) == 0)
{
- /* Flush all pending reads and writes to prevent the pending lists
- from getting any larger. Insn scheduling runs too slowly when
- these lists get long. The number 32 was chosen because it
- seems like a reasonable number. When compiling GCC with itself,
- this flush occurs 8 times for sparc, and 10 times for m88k using
- the number 32. */
- flush_pending_lists (deps, insn, 0);
+ *insn_ptr = ready_remove_first (ready);
+ if (sched_verbose >= 4)
+ fprintf (sched_dump, ";;\t\tChosen insn (but can't issue) : %s \n",
+ (*current_sched_info->print_insn) (*insn_ptr, 0));
+ return 0;
}
else
{
- rtx u;
- rtx pending, pending_mem;
-
- pending = deps->pending_read_insns;
- pending_mem = deps->pending_read_mems;
- while (pending)
- {
- if (anti_dependence (XEXP (pending_mem, 0), dest))
- add_dependence (insn, XEXP (pending, 0), REG_DEP_ANTI);
-
- pending = XEXP (pending, 1);
- pending_mem = XEXP (pending_mem, 1);
- }
+ if (sched_verbose >= 4)
+ fprintf (sched_dump, ";;\t\tChosen insn : %s\n",
+ (*current_sched_info->print_insn)
+ (ready_element (ready, index), 0));
- pending = deps->pending_write_insns;
- pending_mem = deps->pending_write_mems;
- while (pending)
- {
- if (output_dependence (XEXP (pending_mem, 0), dest))
- add_dependence (insn, XEXP (pending, 0), REG_DEP_OUTPUT);
-
- pending = XEXP (pending, 1);
- pending_mem = XEXP (pending_mem, 1);
- }
-
- for (u = deps->last_pending_memory_flush; u; u = XEXP (u, 1))
- add_dependence (insn, XEXP (u, 0), REG_DEP_ANTI);
-
- add_insn_mem_dependence (deps, &deps->pending_write_insns,
- &deps->pending_write_mems, insn, dest);
+ *insn_ptr = ready_remove (ready, index);
+ return 0;
}
- sched_analyze_2 (deps, XEXP (dest, 0), insn);
}
-
- /* Analyze reads. */
- if (GET_CODE (x) == SET)
- sched_analyze_2 (deps, SET_SRC (x), insn);
}
-/* Analyze the uses of memory and registers in rtx X in INSN. */
+/* Use forward list scheduling to rearrange insns of block pointed to by
+ TARGET_BB, possibly bringing insns from subsequent blocks in the same
+ region. */
-static void
-sched_analyze_2 (deps, x, insn)
- struct deps *deps;
- rtx x;
- rtx insn;
+void
+schedule_block (basic_block *target_bb)
{
- register int i;
- register int j;
- register enum rtx_code code;
- register const char *fmt;
-
- if (x == 0)
- return;
-
- code = GET_CODE (x);
-
- switch (code)
- {
- case CONST_INT:
- case CONST_DOUBLE:
- case SYMBOL_REF:
- case CONST:
- case LABEL_REF:
- /* Ignore constants. Note that we must handle CONST_DOUBLE here
- because it may have a cc0_rtx in its CONST_DOUBLE_CHAIN field, but
- this does not mean that this insn is using cc0. */
- return;
-
-#ifdef HAVE_cc0
- case CC0:
- {
- rtx link, prev;
-
- /* User of CC0 depends on immediately preceding insn. */
- SCHED_GROUP_P (insn) = 1;
+ int i, first_cycle_insn_p;
+ int can_issue_more;
+ state_t temp_state = NULL; /* It is used for multipass scheduling. */
+ int sort_p, advance, start_clock_var;
- /* There may be a note before this insn now, but all notes will
- be removed before we actually try to schedule the insns, so
- it won't cause a problem later. We must avoid it here though. */
- prev = prev_nonnote_insn (insn);
+ /* Head/tail info for this block. */
+ rtx prev_head = current_sched_info->prev_head;
+ rtx next_tail = current_sched_info->next_tail;
+ rtx head = NEXT_INSN (prev_head);
+ rtx tail = PREV_INSN (next_tail);
- /* Make a copy of all dependencies on the immediately previous insn,
- and add to this insn. This is so that all the dependencies will
- apply to the group. Remove an explicit dependence on this insn
- as SCHED_GROUP_P now represents it. */
+ /* We used to have code to avoid getting parameters moved from hard
+ argument registers into pseudos.
- if (find_insn_list (prev, LOG_LINKS (insn)))
- remove_dependence (insn, prev);
+ However, it was removed when it proved to be of marginal benefit
+ and caused problems because schedule_block and compute_forward_dependences
+ had different notions of what the "head" insn was. */
- for (link = LOG_LINKS (prev); link; link = XEXP (link, 1))
- add_dependence (insn, XEXP (link, 0), REG_NOTE_KIND (link));
+ gcc_assert (head != tail || INSN_P (head));
- return;
- }
-#endif
+ haifa_recovery_bb_recently_added_p = false;
- case REG:
- {
- rtx u;
- int regno = REGNO (x);
- if (regno < FIRST_PSEUDO_REGISTER)
- {
- int i;
+ /* Debug info. */
+ if (sched_verbose)
+ dump_new_block_header (0, *target_bb, head, tail);
- i = HARD_REGNO_NREGS (regno, GET_MODE (x));
- while (--i >= 0)
- {
- int r = regno + i;
- deps->reg_last_uses[r]
- = alloc_INSN_LIST (insn, deps->reg_last_uses[r]);
+ state_reset (curr_state);
- for (u = deps->reg_last_sets[r]; u; u = XEXP (u, 1))
- add_dependence (insn, XEXP (u, 0), 0);
+ /* Clear the ready list. */
+ ready.first = ready.veclen - 1;
+ ready.n_ready = 0;
+ ready.n_debug = 0;
- /* ??? This should never happen. */
- for (u = deps->reg_last_clobbers[r]; u; u = XEXP (u, 1))
- add_dependence (insn, XEXP (u, 0), 0);
+ /* It is used for first cycle multipass scheduling. */
+ temp_state = alloca (dfa_state_size);
- if (call_used_regs[r] || global_regs[r])
- /* Function calls clobber all call_used regs. */
- for (u = deps->last_function_call; u; u = XEXP (u, 1))
- add_dependence (insn, XEXP (u, 0), REG_DEP_ANTI);
- }
- }
- else
- {
- deps->reg_last_uses[regno]
- = alloc_INSN_LIST (insn, deps->reg_last_uses[regno]);
-
- for (u = deps->reg_last_sets[regno]; u; u = XEXP (u, 1))
- add_dependence (insn, XEXP (u, 0), 0);
-
- /* ??? This should never happen. */
- for (u = deps->reg_last_clobbers[regno]; u; u = XEXP (u, 1))
- add_dependence (insn, XEXP (u, 0), 0);
-
- /* Pseudos that are REG_EQUIV to something may be replaced
- by that during reloading. We need only add dependencies for
- the address in the REG_EQUIV note. */
- if (!reload_completed
- && reg_known_equiv_p[regno]
- && GET_CODE (reg_known_value[regno]) == MEM)
- sched_analyze_2 (deps, XEXP (reg_known_value[regno], 0), insn);
-
- /* If the register does not already cross any calls, then add this
- insn to the sched_before_next_call list so that it will still
- not cross calls after scheduling. */
- if (REG_N_CALLS_CROSSED (regno) == 0)
- add_dependence (deps->sched_before_next_call, insn,
- REG_DEP_ANTI);
- }
- return;
- }
+ if (targetm.sched.md_init)
+ targetm.sched.md_init (sched_dump, sched_verbose, ready.veclen);
- case MEM:
- {
- /* Reading memory. */
- rtx u;
- rtx pending, pending_mem;
+ /* We start inserting insns after PREV_HEAD. */
+ last_scheduled_insn = prev_head;
- pending = deps->pending_read_insns;
- pending_mem = deps->pending_read_mems;
- while (pending)
- {
- if (read_dependence (XEXP (pending_mem, 0), x))
- add_dependence (insn, XEXP (pending, 0), REG_DEP_ANTI);
+ gcc_assert ((NOTE_P (last_scheduled_insn)
+ || BOUNDARY_DEBUG_INSN_P (last_scheduled_insn))
+ && BLOCK_FOR_INSN (last_scheduled_insn) == *target_bb);
- pending = XEXP (pending, 1);
- pending_mem = XEXP (pending_mem, 1);
- }
+ /* Initialize INSN_QUEUE. Q_SIZE is the total number of insns in the
+ queue. */
+ q_ptr = 0;
+ q_size = 0;
- pending = deps->pending_write_insns;
- pending_mem = deps->pending_write_mems;
- while (pending)
- {
- if (true_dependence (XEXP (pending_mem, 0), VOIDmode,
- x, rtx_varies_p))
- add_dependence (insn, XEXP (pending, 0), 0);
+ insn_queue = XALLOCAVEC (rtx, max_insn_queue_index + 1);
+ memset (insn_queue, 0, (max_insn_queue_index + 1) * sizeof (rtx));
- pending = XEXP (pending, 1);
- pending_mem = XEXP (pending_mem, 1);
- }
+ /* Start just before the beginning of time. */
+ clock_var = -1;
- for (u = deps->last_pending_memory_flush; u; u = XEXP (u, 1))
- add_dependence (insn, XEXP (u, 0), REG_DEP_ANTI);
+ /* We need queue and ready lists and clock_var be initialized
+ in try_ready () (which is called through init_ready_list ()). */
+ (*current_sched_info->init_ready_list) ();
- /* Always add these dependencies to pending_reads, since
- this insn may be followed by a write. */
- add_insn_mem_dependence (deps, &deps->pending_read_insns,
- &deps->pending_read_mems, insn, x);
+ /* The algorithm is O(n^2) in the number of ready insns at any given
+ time in the worst case. Before reload we are more likely to have
+ big lists so truncate them to a reasonable size. */
+ if (!reload_completed
+ && ready.n_ready - ready.n_debug > MAX_SCHED_READY_INSNS)
+ {
+ ready_sort (&ready);
- /* Take advantage of tail recursion here. */
- sched_analyze_2 (deps, XEXP (x, 0), insn);
- return;
- }
+ /* Find first free-standing insn past MAX_SCHED_READY_INSNS.
+ If there are debug insns, we know they're first. */
+ for (i = MAX_SCHED_READY_INSNS + ready.n_debug; i < ready.n_ready; i++)
+ if (!SCHED_GROUP_P (ready_element (&ready, i)))
+ break;
- /* Force pending stores to memory in case a trap handler needs them. */
- case TRAP_IF:
- flush_pending_lists (deps, insn, 1);
- break;
+ if (sched_verbose >= 2)
+ {
+ fprintf (sched_dump,
+ ";;\t\tReady list on entry: %d insns\n", ready.n_ready);
+ fprintf (sched_dump,
+ ";;\t\t before reload => truncated to %d insns\n", i);
+ }
- case ASM_OPERANDS:
- case ASM_INPUT:
- case UNSPEC_VOLATILE:
+ /* Delay all insns past it for 1 cycle. If debug counter is
+ activated make an exception for the insn right after
+ last_scheduled_insn. */
{
- rtx u;
+ rtx skip_insn;
- /* Traditional and volatile asm instructions must be considered to use
- and clobber all hard registers, all pseudo-registers and all of
- memory. So must TRAP_IF and UNSPEC_VOLATILE operations.
+ if (dbg_cnt (sched_insn) == false)
+ skip_insn = next_nonnote_insn (last_scheduled_insn);
+ else
+ skip_insn = NULL_RTX;
- Consider for instance a volatile asm that changes the fpu rounding
- mode. An insn should not be moved across this even if it only uses
- pseudo-regs because it might give an incorrectly rounded result. */
- if (code != ASM_OPERANDS || MEM_VOLATILE_P (x))
+ while (i < ready.n_ready)
{
- int max_reg = max_reg_num ();
- for (i = 0; i < max_reg; i++)
- {
- for (u = deps->reg_last_uses[i]; u; u = XEXP (u, 1))
- add_dependence (insn, XEXP (u, 0), REG_DEP_ANTI);
- free_INSN_LIST_list (&deps->reg_last_uses[i]);
-
- for (u = deps->reg_last_sets[i]; u; u = XEXP (u, 1))
- add_dependence (insn, XEXP (u, 0), 0);
-
- for (u = deps->reg_last_clobbers[i]; u; u = XEXP (u, 1))
- add_dependence (insn, XEXP (u, 0), 0);
- }
- reg_pending_sets_all = 1;
-
- flush_pending_lists (deps, insn, 0);
- }
+ rtx insn;
- /* For all ASM_OPERANDS, we must traverse the vector of input operands.
- We can not just fall through here since then we would be confused
- by the ASM_INPUT rtx inside ASM_OPERANDS, which do not indicate
- traditional asms unlike their normal usage. */
+ insn = ready_remove (&ready, i);
- if (code == ASM_OPERANDS)
- {
- for (j = 0; j < ASM_OPERANDS_INPUT_LENGTH (x); j++)
- sched_analyze_2 (deps, ASM_OPERANDS_INPUT (x, j), insn);
- return;
+ if (insn != skip_insn)
+ queue_insn (insn, 1);
}
- break;
}
-
- case PRE_DEC:
- case POST_DEC:
- case PRE_INC:
- case POST_INC:
- /* These both read and modify the result. We must handle them as writes
- to get proper dependencies for following instructions. We must handle
- them as reads to get proper dependencies from this to previous
- instructions. Thus we need to pass them to both sched_analyze_1
- and sched_analyze_2. We must call sched_analyze_2 first in order
- to get the proper antecedent for the read. */
- sched_analyze_2 (deps, XEXP (x, 0), insn);
- sched_analyze_1 (deps, x, insn);
- return;
-
- default:
- break;
}
- /* Other cases: walk the insn. */
- fmt = GET_RTX_FORMAT (code);
- for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
- {
- if (fmt[i] == 'e')
- sched_analyze_2 (deps, XEXP (x, i), insn);
- else if (fmt[i] == 'E')
- for (j = 0; j < XVECLEN (x, i); j++)
- sched_analyze_2 (deps, XVECEXP (x, i, j), insn);
- }
-}
+ /* Now we can restore basic block notes and maintain precise cfg. */
+ restore_bb_notes (*target_bb);
-/* Analyze an INSN with pattern X to find all dependencies. */
+ last_clock_var = -1;
-static void
-sched_analyze_insn (deps, x, insn, loop_notes)
- struct deps *deps;
- rtx x, insn;
- rtx loop_notes;
-{
- register RTX_CODE code = GET_CODE (x);
- rtx link;
- int maxreg = max_reg_num ();
- int i;
+ advance = 0;
- if (code == SET || code == CLOBBER)
- sched_analyze_1 (deps, x, insn);
- else if (code == PARALLEL)
+ sort_p = TRUE;
+ /* Loop until all the insns in BB are scheduled. */
+ while ((*current_sched_info->schedule_more_p) ())
{
- register int i;
- for (i = XVECLEN (x, 0) - 1; i >= 0; i--)
+ do
{
- code = GET_CODE (XVECEXP (x, 0, i));
- if (code == SET || code == CLOBBER)
- sched_analyze_1 (deps, XVECEXP (x, 0, i), insn);
- else
- sched_analyze_2 (deps, XVECEXP (x, 0, i), insn);
- }
- }
- else
- sched_analyze_2 (deps, x, insn);
+ start_clock_var = clock_var;
- /* Mark registers CLOBBERED or used by called function. */
- if (GET_CODE (insn) == CALL_INSN)
- for (link = CALL_INSN_FUNCTION_USAGE (insn); link; link = XEXP (link, 1))
- {
- if (GET_CODE (XEXP (link, 0)) == CLOBBER)
- sched_analyze_1 (deps, XEXP (link, 0), insn);
- else
- sched_analyze_2 (deps, XEXP (link, 0), insn);
- }
+ clock_var++;
- /* If there is a {LOOP,EHREGION}_{BEG,END} note in the middle of a basic
- block, then we must be sure that no instructions are scheduled across it.
- Otherwise, the reg_n_refs info (which depends on loop_depth) would
- become incorrect. */
+ advance_one_cycle ();
- if (loop_notes)
- {
- int max_reg = max_reg_num ();
- int schedule_barrier_found = 0;
- rtx link;
-
- /* Update loop_notes with any notes from this insn. Also determine
- if any of the notes on the list correspond to instruction scheduling
- barriers (loop, eh & setjmp notes, but not range notes. */
- link = loop_notes;
- while (XEXP (link, 1))
- {
- if (INTVAL (XEXP (link, 0)) == NOTE_INSN_LOOP_BEG
- || INTVAL (XEXP (link, 0)) == NOTE_INSN_LOOP_END
- || INTVAL (XEXP (link, 0)) == NOTE_INSN_EH_REGION_BEG
- || INTVAL (XEXP (link, 0)) == NOTE_INSN_EH_REGION_END
- || INTVAL (XEXP (link, 0)) == NOTE_INSN_SETJMP)
- schedule_barrier_found = 1;
-
- link = XEXP (link, 1);
- }
- XEXP (link, 1) = REG_NOTES (insn);
- REG_NOTES (insn) = loop_notes;
+ /* Add to the ready list all pending insns that can be issued now.
+ If there are no ready insns, increment clock until one
+ is ready and add all pending insns at that point to the ready
+ list. */
+ queue_to_ready (&ready);
- /* Add dependencies if a scheduling barrier was found. */
- if (schedule_barrier_found)
- {
- for (i = 0; i < max_reg; i++)
+ gcc_assert (ready.n_ready);
+
+ if (sched_verbose >= 2)
{
- rtx u;
- for (u = deps->reg_last_uses[i]; u; u = XEXP (u, 1))
- add_dependence (insn, XEXP (u, 0), REG_DEP_ANTI);
- free_INSN_LIST_list (&deps->reg_last_uses[i]);
+ fprintf (sched_dump, ";;\t\tReady list after queue_to_ready: ");
+ debug_ready_list (&ready);
+ }
+ advance -= clock_var - start_clock_var;
+ }
+ while (advance > 0);
- for (u = deps->reg_last_sets[i]; u; u = XEXP (u, 1))
- add_dependence (insn, XEXP (u, 0), 0);
+ if (sort_p)
+ {
+ /* Sort the ready list based on priority. */
+ ready_sort (&ready);
- for (u = deps->reg_last_clobbers[i]; u; u = XEXP (u, 1))
- add_dependence (insn, XEXP (u, 0), 0);
+ if (sched_verbose >= 2)
+ {
+ fprintf (sched_dump, ";;\t\tReady list after ready_sort: ");
+ debug_ready_list (&ready);
}
- reg_pending_sets_all = 1;
-
- flush_pending_lists (deps, insn, 0);
}
- }
-
- /* Accumulate clobbers until the next set so that it will be output dependent
- on all of them. At the next set we can clear the clobber list, since
- subsequent sets will be output dependent on it. */
- EXECUTE_IF_SET_IN_REG_SET
- (reg_pending_sets, 0, i,
- {
- free_INSN_LIST_list (&deps->reg_last_sets[i]);
- free_INSN_LIST_list (&deps->reg_last_clobbers[i]);
- deps->reg_last_sets[i] = alloc_INSN_LIST (insn, NULL_RTX);
- });
- EXECUTE_IF_SET_IN_REG_SET
- (reg_pending_clobbers, 0, i,
- {
- deps->reg_last_clobbers[i]
- = alloc_INSN_LIST (insn, deps->reg_last_clobbers[i]);
- });
- CLEAR_REG_SET (reg_pending_sets);
- CLEAR_REG_SET (reg_pending_clobbers);
-
- if (reg_pending_sets_all)
- {
- for (i = 0; i < maxreg; i++)
+ /* We don't want md sched reorder to even see debug isns, so put
+ them out right away. */
+ if (ready.n_ready && DEBUG_INSN_P (ready_element (&ready, 0)))
{
- free_INSN_LIST_list (&deps->reg_last_sets[i]);
- free_INSN_LIST_list (&deps->reg_last_clobbers[i]);
- deps->reg_last_sets[i] = alloc_INSN_LIST (insn, NULL_RTX);
- }
+ if (control_flow_insn_p (last_scheduled_insn))
+ {
+ *target_bb = current_sched_info->advance_target_bb
+ (*target_bb, 0);
- reg_pending_sets_all = 0;
- }
+ if (sched_verbose)
+ {
+ rtx x;
- /* Handle function calls and function returns created by the epilogue
- threading code. */
- if (GET_CODE (insn) == CALL_INSN || GET_CODE (insn) == JUMP_INSN)
- {
- rtx dep_insn;
- rtx prev_dep_insn;
-
- /* When scheduling instructions, we make sure calls don't lose their
- accompanying USE insns by depending them one on another in order.
-
- Also, we must do the same thing for returns created by the epilogue
- threading code. Note this code works only in this special case,
- because other passes make no guarantee that they will never emit
- an instruction between a USE and a RETURN. There is such a guarantee
- for USE instructions immediately before a call. */
-
- prev_dep_insn = insn;
- dep_insn = PREV_INSN (insn);
- while (GET_CODE (dep_insn) == INSN
- && GET_CODE (PATTERN (dep_insn)) == USE
- && GET_CODE (XEXP (PATTERN (dep_insn), 0)) == REG)
- {
- SCHED_GROUP_P (prev_dep_insn) = 1;
+ x = next_real_insn (last_scheduled_insn);
+ gcc_assert (x);
+ dump_new_block_header (1, *target_bb, x, tail);
+ }
- /* Make a copy of all dependencies on dep_insn, and add to insn.
- This is so that all of the dependencies will apply to the
- group. */
+ last_scheduled_insn = bb_note (*target_bb);
+ }
- for (link = LOG_LINKS (dep_insn); link; link = XEXP (link, 1))
- add_dependence (insn, XEXP (link, 0), REG_NOTE_KIND (link));
+ while (ready.n_ready && DEBUG_INSN_P (ready_element (&ready, 0)))
+ {
+ rtx insn = ready_remove_first (&ready);
+ gcc_assert (DEBUG_INSN_P (insn));
+ (*current_sched_info->begin_schedule_ready) (insn,
+ last_scheduled_insn);
+ move_insn (insn, last_scheduled_insn,
+ current_sched_info->next_tail);
+ last_scheduled_insn = insn;
+ advance = schedule_insn (insn);
+ gcc_assert (advance == 0);
+ if (ready.n_ready > 0)
+ ready_sort (&ready);
+ }
- prev_dep_insn = dep_insn;
- dep_insn = PREV_INSN (dep_insn);
+ if (!ready.n_ready)
+ continue;
}
- }
-}
-
-/* Analyze every insn between HEAD and TAIL inclusive, creating LOG_LINKS
- for every dependency. */
-static void
-sched_analyze (deps, head, tail)
- struct deps *deps;
- rtx head, tail;
-{
- register rtx insn;
- register rtx u;
- rtx loop_notes = 0;
+ /* Allow the target to reorder the list, typically for
+ better instruction bundling. */
+ if (sort_p && targetm.sched.reorder
+ && (ready.n_ready == 0
+ || !SCHED_GROUP_P (ready_element (&ready, 0))))
+ can_issue_more =
+ targetm.sched.reorder (sched_dump, sched_verbose,
+ ready_lastpos (&ready),
+ &ready.n_ready, clock_var);
+ else
+ can_issue_more = issue_rate;
- for (insn = head;; insn = NEXT_INSN (insn))
- {
- if (GET_CODE (insn) == INSN || GET_CODE (insn) == JUMP_INSN)
- {
- /* Clear out the stale LOG_LINKS from flow. */
- free_INSN_LIST_list (&LOG_LINKS (insn));
-
- /* Make each JUMP_INSN a scheduling barrier for memory
- references. */
- if (GET_CODE (insn) == JUMP_INSN)
- deps->last_pending_memory_flush
- = alloc_INSN_LIST (insn, deps->last_pending_memory_flush);
- sched_analyze_insn (deps, PATTERN (insn), insn, loop_notes);
- loop_notes = 0;
- }
- else if (GET_CODE (insn) == CALL_INSN)
+ first_cycle_insn_p = 1;
+ cycle_issued_insns = 0;
+ for (;;)
{
- rtx x;
- register int i;
+ rtx insn;
+ int cost;
+ bool asm_p = false;
+
+ if (sched_verbose >= 2)
+ {
+ fprintf (sched_dump, ";;\tReady list (t = %3d): ",
+ clock_var);
+ debug_ready_list (&ready);
+ if (sched_pressure_p)
+ print_curr_reg_pressure ();
+ }
+
+ if (ready.n_ready == 0
+ && can_issue_more
+ && reload_completed)
+ {
+ /* Allow scheduling insns directly from the queue in case
+ there's nothing better to do (ready list is empty) but
+ there are still vacant dispatch slots in the current cycle. */
+ if (sched_verbose >= 6)
+ fprintf (sched_dump,";;\t\tSecond chance\n");
+ memcpy (temp_state, curr_state, dfa_state_size);
+ if (early_queue_to_ready (temp_state, &ready))
+ ready_sort (&ready);
+ }
- CANT_MOVE (insn) = 1;
+ if (ready.n_ready == 0
+ || !can_issue_more
+ || state_dead_lock_p (curr_state)
+ || !(*current_sched_info->schedule_more_p) ())
+ break;
- /* Clear out the stale LOG_LINKS from flow. */
- free_INSN_LIST_list (&LOG_LINKS (insn));
+ /* Select and remove the insn from the ready list. */
+ if (sort_p)
+ {
+ int res;
- /* Any instruction using a hard register which may get clobbered
- by a call needs to be marked as dependent on this call.
- This prevents a use of a hard return reg from being moved
- past a void call (i.e. it does not explicitly set the hard
- return reg). */
+ insn = NULL_RTX;
+ res = choose_ready (&ready, &insn);
- /* If this call is followed by a NOTE_INSN_SETJMP, then assume that
- all registers, not just hard registers, may be clobbered by this
- call. */
+ if (res < 0)
+ /* Finish cycle. */
+ break;
+ if (res > 0)
+ /* Restart choose_ready (). */
+ continue;
- /* Insn, being a CALL_INSN, magically depends on
- `last_function_call' already. */
+ gcc_assert (insn != NULL_RTX);
+ }
+ else
+ insn = ready_remove_first (&ready);
- if (NEXT_INSN (insn) && GET_CODE (NEXT_INSN (insn)) == NOTE
- && NOTE_LINE_NUMBER (NEXT_INSN (insn)) == NOTE_INSN_SETJMP)
+ if (sched_pressure_p && INSN_TICK (insn) > clock_var)
{
- int max_reg = max_reg_num ();
- for (i = 0; i < max_reg; i++)
- {
- for (u = deps->reg_last_uses[i]; u; u = XEXP (u, 1))
- add_dependence (insn, XEXP (u, 0), REG_DEP_ANTI);
- free_INSN_LIST_list (&deps->reg_last_uses[i]);
+ ready_add (&ready, insn, true);
+ advance = 1;
+ break;
+ }
- for (u = deps->reg_last_sets[i]; u; u = XEXP (u, 1))
- add_dependence (insn, XEXP (u, 0), 0);
+ if (targetm.sched.dfa_new_cycle
+ && targetm.sched.dfa_new_cycle (sched_dump, sched_verbose,
+ insn, last_clock_var,
+ clock_var, &sort_p))
+ /* SORT_P is used by the target to override sorting
+ of the ready list. This is needed when the target
+ has modified its internal structures expecting that
+ the insn will be issued next. As we need the insn
+ to have the highest priority (so it will be returned by
+ the ready_remove_first call above), we invoke
+ ready_add (&ready, insn, true).
+ But, still, there is one issue: INSN can be later
+ discarded by scheduler's front end through
+ current_sched_info->can_schedule_ready_p, hence, won't
+ be issued next. */
+ {
+ ready_add (&ready, insn, true);
+ break;
+ }
- for (u = deps->reg_last_clobbers[i]; u; u = XEXP (u, 1))
- add_dependence (insn, XEXP (u, 0), 0);
- }
- reg_pending_sets_all = 1;
-
- /* Add a pair of REG_SAVE_NOTEs which we will later
- convert back into a NOTE_INSN_SETJMP note. See
- reemit_notes for why we use a pair of NOTEs. */
- REG_NOTES (insn) = alloc_EXPR_LIST (REG_SAVE_NOTE,
- GEN_INT (0),
- REG_NOTES (insn));
- REG_NOTES (insn) = alloc_EXPR_LIST (REG_SAVE_NOTE,
- GEN_INT (NOTE_INSN_SETJMP),
- REG_NOTES (insn));
+ sort_p = TRUE;
+ memcpy (temp_state, curr_state, dfa_state_size);
+ if (recog_memoized (insn) < 0)
+ {
+ asm_p = (GET_CODE (PATTERN (insn)) == ASM_INPUT
+ || asm_noperands (PATTERN (insn)) >= 0);
+ if (!first_cycle_insn_p && asm_p)
+ /* This is asm insn which is tried to be issued on the
+ cycle not first. Issue it on the next cycle. */
+ cost = 1;
+ else
+ /* A USE insn, or something else we don't need to
+ understand. We can't pass these directly to
+ state_transition because it will trigger a
+ fatal error for unrecognizable insns. */
+ cost = 0;
}
+ else if (sched_pressure_p)
+ cost = 0;
else
{
- for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
- if (call_used_regs[i] || global_regs[i])
- {
- for (u = deps->reg_last_uses[i]; u; u = XEXP (u, 1))
- add_dependence (insn, XEXP (u, 0), REG_DEP_ANTI);
+ cost = state_transition (temp_state, insn);
+ if (cost < 0)
+ cost = 0;
+ else if (cost == 0)
+ cost = 1;
+ }
- for (u = deps->reg_last_sets[i]; u; u = XEXP (u, 1))
- add_dependence (insn, XEXP (u, 0), REG_DEP_ANTI);
+ if (cost >= 1)
+ {
+ queue_insn (insn, cost);
+ if (SCHED_GROUP_P (insn))
+ {
+ advance = cost;
+ break;
+ }
- SET_REGNO_REG_SET (reg_pending_clobbers, i);
- }
+ continue;
}
- /* For each insn which shouldn't cross a call, add a dependence
- between that insn and this call insn. */
- x = LOG_LINKS (deps->sched_before_next_call);
- while (x)
+ if (current_sched_info->can_schedule_ready_p
+ && ! (*current_sched_info->can_schedule_ready_p) (insn))
+ /* We normally get here only if we don't want to move
+ insn from the split block. */
{
- add_dependence (insn, XEXP (x, 0), REG_DEP_ANTI);
- x = XEXP (x, 1);
+ TODO_SPEC (insn) = (TODO_SPEC (insn) & ~SPECULATIVE) | HARD_DEP;
+ continue;
}
- free_INSN_LIST_list (&LOG_LINKS (deps->sched_before_next_call));
- sched_analyze_insn (deps, PATTERN (insn), insn, loop_notes);
- loop_notes = 0;
+ /* DECISION is made. */
- /* In the absence of interprocedural alias analysis, we must flush
- all pending reads and writes, and start new dependencies starting
- from here. But only flush writes for constant calls (which may
- be passed a pointer to something we haven't written yet). */
- flush_pending_lists (deps, insn, CONST_CALL_P (insn));
+ if (TODO_SPEC (insn) & SPECULATIVE)
+ generate_recovery_code (insn);
- /* Depend this function call (actually, the user of this
- function call) on all hard register clobberage. */
+ if (control_flow_insn_p (last_scheduled_insn)
+ /* This is used to switch basic blocks by request
+ from scheduler front-end (actually, sched-ebb.c only).
+ This is used to process blocks with single fallthru
+ edge. If succeeding block has jump, it [jump] will try
+ move at the end of current bb, thus corrupting CFG. */
+ || current_sched_info->advance_target_bb (*target_bb, insn))
+ {
+ *target_bb = current_sched_info->advance_target_bb
+ (*target_bb, 0);
- /* last_function_call is now a list of insns. */
- free_INSN_LIST_list (&deps->last_function_call);
- deps->last_function_call = alloc_INSN_LIST (insn, NULL_RTX);
- }
+ if (sched_verbose)
+ {
+ rtx x;
- /* See comments on reemit_notes as to why we do this.
- ??? Actually, the reemit_notes just say what is done, not why. */
+ x = next_real_insn (last_scheduled_insn);
+ gcc_assert (x);
+ dump_new_block_header (1, *target_bb, x, tail);
+ }
- else if (GET_CODE (insn) == NOTE
- && (NOTE_LINE_NUMBER (insn) == NOTE_INSN_RANGE_START
- || NOTE_LINE_NUMBER (insn) == NOTE_INSN_RANGE_END))
- {
- loop_notes = alloc_EXPR_LIST (REG_SAVE_NOTE, NOTE_RANGE_INFO (insn),
- loop_notes);
- loop_notes = alloc_EXPR_LIST (REG_SAVE_NOTE,
- GEN_INT (NOTE_LINE_NUMBER (insn)),
- loop_notes);
- }
- else if (GET_CODE (insn) == NOTE
- && (NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_BEG
- || NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_END
- || NOTE_LINE_NUMBER (insn) == NOTE_INSN_EH_REGION_BEG
- || NOTE_LINE_NUMBER (insn) == NOTE_INSN_EH_REGION_END
- || (NOTE_LINE_NUMBER (insn) == NOTE_INSN_SETJMP
- && GET_CODE (PREV_INSN (insn)) != CALL_INSN)))
- {
- rtx rtx_region;
+ last_scheduled_insn = bb_note (*target_bb);
+ }
- if (NOTE_LINE_NUMBER (insn) == NOTE_INSN_EH_REGION_BEG
- || NOTE_LINE_NUMBER (insn) == NOTE_INSN_EH_REGION_END)
- rtx_region = GEN_INT (NOTE_EH_HANDLER (insn));
- else
- rtx_region = GEN_INT (0);
-
- loop_notes = alloc_EXPR_LIST (REG_SAVE_NOTE,
- rtx_region,
- loop_notes);
- loop_notes = alloc_EXPR_LIST (REG_SAVE_NOTE,
- GEN_INT (NOTE_LINE_NUMBER (insn)),
- loop_notes);
- CONST_CALL_P (loop_notes) = CONST_CALL_P (insn);
- }
+ /* Update counters, etc in the scheduler's front end. */
+ (*current_sched_info->begin_schedule_ready) (insn,
+ last_scheduled_insn);
- if (insn == tail)
- return;
- }
- abort ();
-}
-\f
-/* Macros and functions for keeping the priority queue sorted, and
- dealing with queueing and dequeueing of instructions. */
+ move_insn (insn, last_scheduled_insn, current_sched_info->next_tail);
+ reemit_notes (insn);
+ last_scheduled_insn = insn;
-#define SCHED_SORT(READY, N_READY) \
-do { if ((N_READY) == 2) \
- swap_sort (READY, N_READY); \
- else if ((N_READY) > 2) \
- qsort (READY, N_READY, sizeof (rtx), rank_for_schedule); } \
-while (0)
+ if (memcmp (curr_state, temp_state, dfa_state_size) != 0)
+ {
+ cycle_issued_insns++;
+ memcpy (curr_state, temp_state, dfa_state_size);
+ }
+
+ if (targetm.sched.variable_issue)
+ can_issue_more =
+ targetm.sched.variable_issue (sched_dump, sched_verbose,
+ insn, can_issue_more);
+ /* A naked CLOBBER or USE generates no instruction, so do
+ not count them against the issue rate. */
+ else if (GET_CODE (PATTERN (insn)) != USE
+ && GET_CODE (PATTERN (insn)) != CLOBBER)
+ can_issue_more--;
+ advance = schedule_insn (insn);
+
+ /* After issuing an asm insn we should start a new cycle. */
+ if (advance == 0 && asm_p)
+ advance = 1;
+ if (advance != 0)
+ break;
-/* Returns a positive value if x is preferred; returns a negative value if
- y is preferred. Should never return 0, since that will make the sort
- unstable. */
+ first_cycle_insn_p = 0;
-static int
-rank_for_schedule (x, y)
- const PTR x;
- const PTR y;
-{
- rtx tmp = *(rtx *)y;
- rtx tmp2 = *(rtx *)x;
- rtx link;
- int tmp_class, tmp2_class, depend_count1, depend_count2;
- int val, priority_val, spec_val, prob_val, weight_val;
+ /* Sort the ready list based on priority. This must be
+ redone here, as schedule_insn may have readied additional
+ insns that will not be sorted correctly. */
+ if (ready.n_ready > 0)
+ ready_sort (&ready);
+ /* Quickly go through debug insns such that md sched
+ reorder2 doesn't have to deal with debug insns. */
+ if (ready.n_ready && DEBUG_INSN_P (ready_element (&ready, 0))
+ && (*current_sched_info->schedule_more_p) ())
+ {
+ if (control_flow_insn_p (last_scheduled_insn))
+ {
+ *target_bb = current_sched_info->advance_target_bb
+ (*target_bb, 0);
- /* Prefer insn with higher priority. */
- priority_val = INSN_PRIORITY (tmp2) - INSN_PRIORITY (tmp);
- if (priority_val)
- return priority_val;
+ if (sched_verbose)
+ {
+ rtx x;
- /* Prefer an insn with smaller contribution to registers-pressure. */
- if (!reload_completed &&
- (weight_val = INSN_REG_WEIGHT (tmp) - INSN_REG_WEIGHT (tmp2)))
- return (weight_val);
+ x = next_real_insn (last_scheduled_insn);
+ gcc_assert (x);
+ dump_new_block_header (1, *target_bb, x, tail);
+ }
- /* Some comparison make sense in interblock scheduling only. */
- if (INSN_BB (tmp) != INSN_BB (tmp2))
- {
- /* Prefer an inblock motion on an interblock motion. */
- if ((INSN_BB (tmp2) == target_bb) && (INSN_BB (tmp) != target_bb))
- return 1;
- if ((INSN_BB (tmp) == target_bb) && (INSN_BB (tmp2) != target_bb))
- return -1;
+ last_scheduled_insn = bb_note (*target_bb);
+ }
- /* Prefer a useful motion on a speculative one. */
- if ((spec_val = IS_SPECULATIVE_INSN (tmp) - IS_SPECULATIVE_INSN (tmp2)))
- return (spec_val);
+ while (ready.n_ready && DEBUG_INSN_P (ready_element (&ready, 0)))
+ {
+ insn = ready_remove_first (&ready);
+ gcc_assert (DEBUG_INSN_P (insn));
+ (*current_sched_info->begin_schedule_ready)
+ (insn, last_scheduled_insn);
+ move_insn (insn, last_scheduled_insn,
+ current_sched_info->next_tail);
+ advance = schedule_insn (insn);
+ last_scheduled_insn = insn;
+ gcc_assert (advance == 0);
+ if (ready.n_ready > 0)
+ ready_sort (&ready);
+ }
+ }
- /* Prefer a more probable (speculative) insn. */
- prob_val = INSN_PROBABILITY (tmp2) - INSN_PROBABILITY (tmp);
- if (prob_val)
- return (prob_val);
+ if (targetm.sched.reorder2
+ && (ready.n_ready == 0
+ || !SCHED_GROUP_P (ready_element (&ready, 0))))
+ {
+ can_issue_more =
+ targetm.sched.reorder2 (sched_dump, sched_verbose,
+ ready.n_ready
+ ? ready_lastpos (&ready) : NULL,
+ &ready.n_ready, clock_var);
+ }
+ }
}
- /* Compare insns based on their relation to the last-scheduled-insn. */
- if (last_scheduled_insn)
+ /* Debug info. */
+ if (sched_verbose)
{
- /* Classify the instructions into three classes:
- 1) Data dependent on last schedule insn.
- 2) Anti/Output dependent on last scheduled insn.
- 3) Independent of last scheduled insn, or has latency of one.
- Choose the insn from the highest numbered class if different. */
- link = find_insn_list (tmp, INSN_DEPEND (last_scheduled_insn));
- if (link == 0 || insn_cost (last_scheduled_insn, link, tmp) == 1)
- tmp_class = 3;
- else if (REG_NOTE_KIND (link) == 0) /* Data dependence. */
- tmp_class = 1;
- else
- tmp_class = 2;
-
- link = find_insn_list (tmp2, INSN_DEPEND (last_scheduled_insn));
- if (link == 0 || insn_cost (last_scheduled_insn, link, tmp2) == 1)
- tmp2_class = 3;
- else if (REG_NOTE_KIND (link) == 0) /* Data dependence. */
- tmp2_class = 1;
- else
- tmp2_class = 2;
-
- if ((val = tmp2_class - tmp_class))
- return val;
+ fprintf (sched_dump, ";;\tReady list (final): ");
+ debug_ready_list (&ready);
}
- /* Prefer the insn which has more later insns that depend on it.
- This gives the scheduler more freedom when scheduling later
- instructions at the expense of added register pressure. */
- depend_count1 = 0;
- for (link = INSN_DEPEND (tmp); link; link = XEXP (link, 1))
- depend_count1++;
+ if (current_sched_info->queue_must_finish_empty)
+ /* Sanity check -- queue must be empty now. Meaningless if region has
+ multiple bbs. */
+ gcc_assert (!q_size && !ready.n_ready && !ready.n_debug);
+ else
+ {
+ /* We must maintain QUEUE_INDEX between blocks in region. */
+ for (i = ready.n_ready - 1; i >= 0; i--)
+ {
+ rtx x;
- depend_count2 = 0;
- for (link = INSN_DEPEND (tmp2); link; link = XEXP (link, 1))
- depend_count2++;
+ x = ready_element (&ready, i);
+ QUEUE_INDEX (x) = QUEUE_NOWHERE;
+ TODO_SPEC (x) = (TODO_SPEC (x) & ~SPECULATIVE) | HARD_DEP;
+ }
- val = depend_count2 - depend_count1;
- if (val)
- return val;
-
- /* If insns are equally good, sort by INSN_LUID (original insn order),
- so that we make the sort stable. This minimizes instruction movement,
- thus minimizing sched's effect on debugging and cross-jumping. */
- return INSN_LUID (tmp) - INSN_LUID (tmp2);
-}
+ if (q_size)
+ for (i = 0; i <= max_insn_queue_index; i++)
+ {
+ rtx link;
+ for (link = insn_queue[i]; link; link = XEXP (link, 1))
+ {
+ rtx x;
-/* Resort the array A in which only element at index N may be out of order. */
+ x = XEXP (link, 0);
+ QUEUE_INDEX (x) = QUEUE_NOWHERE;
+ TODO_SPEC (x) = (TODO_SPEC (x) & ~SPECULATIVE) | HARD_DEP;
+ }
+ free_INSN_LIST_list (&insn_queue[i]);
+ }
+ }
-HAIFA_INLINE static void
-swap_sort (a, n)
- rtx *a;
- int n;
-{
- rtx insn = a[n - 1];
- int i = n - 2;
+ if (sched_verbose)
+ fprintf (sched_dump, ";; total time = %d\n", clock_var);
- while (i >= 0 && rank_for_schedule (a + i, &insn) >= 0)
+ if (!current_sched_info->queue_must_finish_empty
+ || haifa_recovery_bb_recently_added_p)
{
- a[i + 1] = a[i];
- i -= 1;
+ /* INSN_TICK (minimum clock tick at which the insn becomes
+ ready) may be not correct for the insn in the subsequent
+ blocks of the region. We should use a correct value of
+ `clock_var' or modify INSN_TICK. It is better to keep
+ clock_var value equal to 0 at the start of a basic block.
+ Therefore we modify INSN_TICK here. */
+ fix_inter_tick (NEXT_INSN (prev_head), last_scheduled_insn);
}
- a[i + 1] = insn;
-}
-static int max_priority;
+ if (targetm.sched.md_finish)
+ {
+ targetm.sched.md_finish (sched_dump, sched_verbose);
+ /* Target might have added some instructions to the scheduled block
+ in its md_finish () hook. These new insns don't have any data
+ initialized and to identify them we extend h_i_d so that they'll
+ get zero luids. */
+ sched_init_luids (NULL, NULL, NULL, NULL);
+ }
-/* Add INSN to the insn queue so that it can be executed at least
- N_CYCLES after the currently executing insn. Preserve insns
- chain for debugging purposes. */
+ if (sched_verbose)
+ fprintf (sched_dump, ";; new head = %d\n;; new tail = %d\n\n",
+ INSN_UID (head), INSN_UID (tail));
-HAIFA_INLINE static void
-queue_insn (insn, n_cycles)
- rtx insn;
- int n_cycles;
+ /* Update head/tail boundaries. */
+ head = NEXT_INSN (prev_head);
+ tail = last_scheduled_insn;
+
+ head = restore_other_notes (head, NULL);
+
+ current_sched_info->head = head;
+ current_sched_info->tail = tail;
+}
+\f
+/* Set_priorities: compute priority of each insn in the block. */
+
+int
+set_priorities (rtx head, rtx tail)
{
- int next_q = NEXT_Q_AFTER (q_ptr, n_cycles);
- rtx link = alloc_INSN_LIST (insn, insn_queue[next_q]);
- insn_queue[next_q] = link;
- q_size += 1;
+ rtx insn;
+ int n_insn;
+ int sched_max_insns_priority =
+ current_sched_info->sched_max_insns_priority;
+ rtx prev_head;
+
+ if (head == tail && (! INSN_P (head) || BOUNDARY_DEBUG_INSN_P (head)))
+ gcc_unreachable ();
+
+ n_insn = 0;
- if (sched_verbose >= 2)
+ prev_head = PREV_INSN (head);
+ for (insn = tail; insn != prev_head; insn = PREV_INSN (insn))
{
- fprintf (dump, ";;\t\tReady-->Q: insn %d: ", INSN_UID (insn));
+ if (!INSN_P (insn))
+ continue;
- if (INSN_BB (insn) != target_bb)
- fprintf (dump, "(b%d) ", BLOCK_NUM (insn));
+ n_insn++;
+ (void) priority (insn);
+
+ gcc_assert (INSN_PRIORITY_KNOWN (insn));
- fprintf (dump, "queued for %d cycles.\n", n_cycles);
+ sched_max_insns_priority = MAX (sched_max_insns_priority,
+ INSN_PRIORITY (insn));
}
-}
+ current_sched_info->sched_max_insns_priority = sched_max_insns_priority;
-/* PREV is an insn that is ready to execute. Adjust its priority if that
- will help shorten or lengthen register lifetimes as appropriate. Also
- provide a hook for the target to tweek itself. */
+ return n_insn;
+}
-HAIFA_INLINE static void
-adjust_priority (prev)
- rtx prev ATTRIBUTE_UNUSED;
+/* Set dump and sched_verbose for the desired debugging output. If no
+ dump-file was specified, but -fsched-verbose=N (any N), print to stderr.
+ For -fsched-verbose=N, N>=10, print everything to stderr. */
+void
+setup_sched_dump (void)
{
- /* ??? There used to be code here to try and estimate how an insn
- affected register lifetimes, but it did it by looking at REG_DEAD
- notes, which we removed in schedule_region. Nor did it try to
- take into account register pressure or anything useful like that.
-
- Revisit when we have a machine model to work with and not before. */
-
-#ifdef ADJUST_PRIORITY
- ADJUST_PRIORITY (prev);
-#endif
+ sched_verbose = sched_verbose_param;
+ if (sched_verbose_param == 0 && dump_file)
+ sched_verbose = 1;
+ sched_dump = ((sched_verbose_param >= 10 || !dump_file)
+ ? stderr : dump_file);
}
-/* Clock at which the previous instruction was issued. */
-static int last_clock_var;
-
-/* INSN is the "currently executing insn". Launch each insn which was
- waiting on INSN. READY is a vector of insns which are ready to fire.
- N_READY is the number of elements in READY. CLOCK is the current
- cycle. */
+/* Initialize some global state for the scheduler. This function works
+ with the common data shared between all the schedulers. It is called
+ from the scheduler specific initialization routine. */
-static int
-schedule_insn (insn, ready, n_ready, clock)
- rtx insn;
- rtx *ready;
- int n_ready;
- int clock;
+void
+sched_init (void)
{
- rtx link;
- int unit;
+ /* Disable speculative loads in their presence if cc0 defined. */
+#ifdef HAVE_cc0
+ flag_schedule_speculative_load = 0;
+#endif
- unit = insn_unit (insn);
+ sched_pressure_p = (flag_sched_pressure && ! reload_completed
+ && common_sched_info->sched_pass_id == SCHED_RGN_PASS);
+ if (sched_pressure_p)
+ ira_setup_eliminable_regset ();
- if (sched_verbose >= 2)
+ /* Initialize SPEC_INFO. */
+ if (targetm.sched.set_sched_flags)
{
- fprintf (dump, ";;\t\t--> scheduling insn <<<%d>>> on unit ",
- INSN_UID (insn));
- insn_print_units (insn);
- fprintf (dump, "\n");
- }
-
- if (sched_verbose && unit == -1)
- visualize_no_unit (insn);
-
- if (MAX_BLOCKAGE > 1 || issue_rate > 1 || sched_verbose)
- schedule_unit (unit, insn, clock);
+ spec_info = &spec_info_var;
+ targetm.sched.set_sched_flags (spec_info);
+
+ if (spec_info->mask != 0)
+ {
+ spec_info->data_weakness_cutoff =
+ (PARAM_VALUE (PARAM_SCHED_SPEC_PROB_CUTOFF) * MAX_DEP_WEAK) / 100;
+ spec_info->control_weakness_cutoff =
+ (PARAM_VALUE (PARAM_SCHED_SPEC_PROB_CUTOFF)
+ * REG_BR_PROB_BASE) / 100;
+ }
+ else
+ /* So we won't read anything accidentally. */
+ spec_info = NULL;
- if (INSN_DEPEND (insn) == 0)
- return n_ready;
+ }
+ else
+ /* So we won't read anything accidentally. */
+ spec_info = 0;
- /* This is used by the function adjust_priority above. */
- if (n_ready > 0)
- max_priority = MAX (INSN_PRIORITY (ready[0]), INSN_PRIORITY (insn));
+ /* Initialize issue_rate. */
+ if (targetm.sched.issue_rate)
+ issue_rate = targetm.sched.issue_rate ();
else
- max_priority = INSN_PRIORITY (insn);
+ issue_rate = 1;
- for (link = INSN_DEPEND (insn); link != 0; link = XEXP (link, 1))
+ if (cached_issue_rate != issue_rate)
{
- rtx next = XEXP (link, 0);
- int cost = insn_cost (insn, link, next);
+ cached_issue_rate = issue_rate;
+ /* To invalidate max_lookahead_tries: */
+ cached_first_cycle_multipass_dfa_lookahead = 0;
+ }
- INSN_TICK (next) = MAX (INSN_TICK (next), clock + cost);
+ if (targetm.sched.first_cycle_multipass_dfa_lookahead)
+ dfa_lookahead = targetm.sched.first_cycle_multipass_dfa_lookahead ();
+ else
+ dfa_lookahead = 0;
- if ((INSN_DEP_COUNT (next) -= 1) == 0)
- {
- int effective_cost = INSN_TICK (next) - clock;
-
- /* For speculative insns, before inserting to ready/queue,
- check live, exception-free, and issue-delay. */
- if (INSN_BB (next) != target_bb
- && (!IS_VALID (INSN_BB (next))
- || CANT_MOVE (next)
- || (IS_SPECULATIVE_INSN (next)
- && (insn_issue_delay (next) > 3
- || !check_live (next, INSN_BB (next))
- || !is_exception_free (next, INSN_BB (next), target_bb)))))
- continue;
+ if (targetm.sched.init_dfa_pre_cycle_insn)
+ targetm.sched.init_dfa_pre_cycle_insn ();
- if (sched_verbose >= 2)
- {
- fprintf (dump, ";;\t\tdependences resolved: insn %d ",
- INSN_UID (next));
+ if (targetm.sched.init_dfa_post_cycle_insn)
+ targetm.sched.init_dfa_post_cycle_insn ();
- if (current_nr_blocks > 1 && INSN_BB (next) != target_bb)
- fprintf (dump, "/b%d ", BLOCK_NUM (next));
+ dfa_start ();
+ dfa_state_size = state_size ();
- if (effective_cost < 1)
- fprintf (dump, "into ready\n");
- else
- fprintf (dump, "into queue with cost=%d\n", effective_cost);
- }
+ init_alias_analysis ();
- /* Adjust the priority of NEXT and either put it on the ready
- list or queue it. */
- adjust_priority (next);
- if (effective_cost < 1)
- ready[n_ready++] = next;
- else
- queue_insn (next, effective_cost);
- }
- }
+ df_set_flags (DF_LR_RUN_DCE);
+ df_note_add_problem ();
- /* Annotate the instruction with issue information -- TImode
- indicates that the instruction is expected not to be able
- to issue on the same cycle as the previous insn. A machine
- may use this information to decide how the instruction should
- be aligned. */
- if (reload_completed && issue_rate > 1)
+ /* More problems needed for interloop dep calculation in SMS. */
+ if (common_sched_info->sched_pass_id == SCHED_SMS_PASS)
{
- PUT_MODE (insn, clock > last_clock_var ? TImode : VOIDmode);
- last_clock_var = clock;
+ df_rd_add_problem ();
+ df_chain_add_problem (DF_DU_CHAIN + DF_UD_CHAIN);
}
- return n_ready;
-}
+ df_analyze ();
-/* Functions for handling of notes. */
+ /* Do not run DCE after reload, as this can kill nops inserted
+ by bundling. */
+ if (reload_completed)
+ df_clear_flags (DF_LR_RUN_DCE);
-/* Delete notes beginning with INSN and put them in the chain
- of notes ended by NOTE_LIST.
- Returns the insn following the notes. */
+ regstat_compute_calls_crossed ();
-static rtx
-unlink_other_notes (insn, tail)
- rtx insn, tail;
-{
- rtx prev = PREV_INSN (insn);
+ if (targetm.sched.md_init_global)
+ targetm.sched.md_init_global (sched_dump, sched_verbose,
+ get_max_uid () + 1);
- while (insn != tail && GET_CODE (insn) == NOTE)
+ if (sched_pressure_p)
{
- rtx next = NEXT_INSN (insn);
- /* Delete the note from its current position. */
- if (prev)
- NEXT_INSN (prev) = next;
- if (next)
- PREV_INSN (next) = prev;
-
- /* See sched_analyze to see how these are handled. */
- if (NOTE_LINE_NUMBER (insn) != NOTE_INSN_SETJMP
- && NOTE_LINE_NUMBER (insn) != NOTE_INSN_LOOP_BEG
- && NOTE_LINE_NUMBER (insn) != NOTE_INSN_LOOP_END
- && NOTE_LINE_NUMBER (insn) != NOTE_INSN_RANGE_START
- && NOTE_LINE_NUMBER (insn) != NOTE_INSN_RANGE_END
- && NOTE_LINE_NUMBER (insn) != NOTE_INSN_EH_REGION_BEG
- && NOTE_LINE_NUMBER (insn) != NOTE_INSN_EH_REGION_END)
- {
- /* Insert the note at the end of the notes list. */
- PREV_INSN (insn) = note_list;
- if (note_list)
- NEXT_INSN (note_list) = insn;
- note_list = insn;
- }
-
- insn = next;
+ int i, max_regno = max_reg_num ();
+
+ ira_set_pseudo_classes (sched_verbose ? sched_dump : NULL);
+ sched_regno_cover_class
+ = (enum reg_class *) xmalloc (max_regno * sizeof (enum reg_class));
+ for (i = 0; i < max_regno; i++)
+ sched_regno_cover_class[i]
+ = (i < FIRST_PSEUDO_REGISTER
+ ? ira_class_translate[REGNO_REG_CLASS (i)]
+ : reg_cover_class (i));
+ curr_reg_live = BITMAP_ALLOC (NULL);
+ saved_reg_live = BITMAP_ALLOC (NULL);
+ region_ref_regs = BITMAP_ALLOC (NULL);
}
- return insn;
+
+ curr_state = xmalloc (dfa_state_size);
}
-/* Delete line notes beginning with INSN. Record line-number notes so
- they can be reused. Returns the insn following the notes. */
+static void haifa_init_only_bb (basic_block, basic_block);
-static rtx
-unlink_line_notes (insn, tail)
- rtx insn, tail;
+/* Initialize data structures specific to the Haifa scheduler. */
+void
+haifa_sched_init (void)
{
- rtx prev = PREV_INSN (insn);
+ setup_sched_dump ();
+ sched_init ();
- while (insn != tail && GET_CODE (insn) == NOTE)
+ if (spec_info != NULL)
{
- rtx next = NEXT_INSN (insn);
-
- if (write_symbols != NO_DEBUG && NOTE_LINE_NUMBER (insn) > 0)
- {
- /* Delete the note from its current position. */
- if (prev)
- NEXT_INSN (prev) = next;
- if (next)
- PREV_INSN (next) = prev;
-
- /* Record line-number notes so they can be reused. */
- LINE_NOTE (insn) = insn;
- }
- else
- prev = insn;
-
- insn = next;
+ sched_deps_info->use_deps_list = 1;
+ sched_deps_info->generate_spec_deps = 1;
}
- return insn;
-}
-/* Return the head and tail pointers of BB. */
+ /* Initialize luids, dependency caches, target and h_i_d for the
+ whole function. */
+ {
+ bb_vec_t bbs = VEC_alloc (basic_block, heap, n_basic_blocks);
+ basic_block bb;
-HAIFA_INLINE static void
-get_block_head_tail (b, headp, tailp)
- int b;
- rtx *headp;
- rtx *tailp;
-{
+ sched_init_bbs ();
- rtx head;
- rtx tail;
+ FOR_EACH_BB (bb)
+ VEC_quick_push (basic_block, bbs, bb);
+ sched_init_luids (bbs, NULL, NULL, NULL);
+ sched_deps_init (true);
+ sched_extend_target ();
+ haifa_init_h_i_d (bbs, NULL, NULL, NULL);
- /* HEAD and TAIL delimit the basic block being scheduled. */
- head = BLOCK_HEAD (b);
- tail = BLOCK_END (b);
+ VEC_free (basic_block, heap, bbs);
+ }
- /* Don't include any notes or labels at the beginning of the
- basic block, or notes at the ends of basic blocks. */
- while (head != tail)
- {
- if (GET_CODE (head) == NOTE)
- head = NEXT_INSN (head);
- else if (GET_CODE (tail) == NOTE)
- tail = PREV_INSN (tail);
- else if (GET_CODE (head) == CODE_LABEL)
- head = NEXT_INSN (head);
- else
- break;
- }
+ sched_init_only_bb = haifa_init_only_bb;
+ sched_split_block = sched_split_block_1;
+ sched_create_empty_bb = sched_create_empty_bb_1;
+ haifa_recovery_bb_ever_added_p = false;
- *headp = head;
- *tailp = tail;
-}
+#ifdef ENABLE_CHECKING
+ /* This is used preferably for finding bugs in check_cfg () itself.
+ We must call sched_bbs_init () before check_cfg () because check_cfg ()
+ assumes that the last insn in the last bb has a non-null successor. */
+ check_cfg (0, 0);
+#endif
-HAIFA_INLINE static void
-get_bb_head_tail (bb, headp, tailp)
- int bb;
- rtx *headp;
- rtx *tailp;
-{
- get_block_head_tail (BB_TO_BLOCK (bb), headp, tailp);
+ nr_begin_data = nr_begin_control = nr_be_in_data = nr_be_in_control = 0;
+ before_recovery = 0;
+ after_recovery = 0;
}
-/* Delete line notes from bb. Save them so they can be later restored
- (in restore_line_notes ()). */
-
-static void
-rm_line_notes (bb)
- int bb;
+/* Finish work with the data specific to the Haifa scheduler. */
+void
+haifa_sched_finish (void)
{
- rtx next_tail;
- rtx tail;
- rtx head;
- rtx insn;
-
- get_bb_head_tail (bb, &head, &tail);
-
- if (head == tail
- && (GET_RTX_CLASS (GET_CODE (head)) != 'i'))
- return;
+ sched_create_empty_bb = NULL;
+ sched_split_block = NULL;
+ sched_init_only_bb = NULL;
- next_tail = NEXT_INSN (tail);
- for (insn = head; insn != next_tail; insn = NEXT_INSN (insn))
+ if (spec_info && spec_info->dump)
{
- rtx prev;
-
- /* Farm out notes, and maybe save them in NOTE_LIST.
- This is needed to keep the debugger from
- getting completely deranged. */
- if (GET_CODE (insn) == NOTE)
- {
- prev = insn;
- insn = unlink_line_notes (insn, next_tail);
-
- if (prev == tail)
- abort ();
- if (prev == head)
- abort ();
- if (insn == next_tail)
- abort ();
- }
+ char c = reload_completed ? 'a' : 'b';
+
+ fprintf (spec_info->dump,
+ ";; %s:\n", current_function_name ());
+
+ fprintf (spec_info->dump,
+ ";; Procedure %cr-begin-data-spec motions == %d\n",
+ c, nr_begin_data);
+ fprintf (spec_info->dump,
+ ";; Procedure %cr-be-in-data-spec motions == %d\n",
+ c, nr_be_in_data);
+ fprintf (spec_info->dump,
+ ";; Procedure %cr-begin-control-spec motions == %d\n",
+ c, nr_begin_control);
+ fprintf (spec_info->dump,
+ ";; Procedure %cr-be-in-control-spec motions == %d\n",
+ c, nr_be_in_control);
}
+
+ /* Finalize h_i_d, dependency caches, and luids for the whole
+ function. Target will be finalized in md_global_finish (). */
+ sched_deps_finish ();
+ sched_finish_luids ();
+ current_sched_info = NULL;
+ sched_finish ();
}
-/* Save line number notes for each insn in bb. */
+/* Free global data used during insn scheduling. This function works with
+ the common data shared between the schedulers. */
-static void
-save_line_notes (bb)
- int bb;
+void
+sched_finish (void)
{
- rtx head, tail;
- rtx next_tail;
-
- /* We must use the true line number for the first insn in the block
- that was computed and saved at the start of this pass. We can't
- use the current line number, because scheduling of the previous
- block may have changed the current line number. */
-
- rtx line = line_note_head[BB_TO_BLOCK (bb)];
- rtx insn;
-
- get_bb_head_tail (bb, &head, &tail);
- next_tail = NEXT_INSN (tail);
-
- for (insn = BLOCK_HEAD (BB_TO_BLOCK (bb));
- insn != next_tail;
- insn = NEXT_INSN (insn))
- if (GET_CODE (insn) == NOTE && NOTE_LINE_NUMBER (insn) > 0)
- line = insn;
- else
- LINE_NOTE (insn) = line;
-}
-
+ haifa_finish_h_i_d ();
+ if (sched_pressure_p)
+ {
+ free (sched_regno_cover_class);
+ BITMAP_FREE (region_ref_regs);
+ BITMAP_FREE (saved_reg_live);
+ BITMAP_FREE (curr_reg_live);
+ }
+ free (curr_state);
-/* After bb was scheduled, insert line notes into the insns list. */
+ if (targetm.sched.md_finish_global)
+ targetm.sched.md_finish_global (sched_dump, sched_verbose);
-static void
-restore_line_notes (bb)
- int bb;
-{
- rtx line, note, prev, new;
- int added_notes = 0;
- int b;
- rtx head, next_tail, insn;
-
- b = BB_TO_BLOCK (bb);
-
- head = BLOCK_HEAD (b);
- next_tail = NEXT_INSN (BLOCK_END (b));
-
- /* Determine the current line-number. We want to know the current
- line number of the first insn of the block here, in case it is
- different from the true line number that was saved earlier. If
- different, then we need a line number note before the first insn
- of this block. If it happens to be the same, then we don't want to
- emit another line number note here. */
- for (line = head; line; line = PREV_INSN (line))
- if (GET_CODE (line) == NOTE && NOTE_LINE_NUMBER (line) > 0)
- break;
+ end_alias_analysis ();
- /* Walk the insns keeping track of the current line-number and inserting
- the line-number notes as needed. */
- for (insn = head; insn != next_tail; insn = NEXT_INSN (insn))
- if (GET_CODE (insn) == NOTE && NOTE_LINE_NUMBER (insn) > 0)
- line = insn;
- /* This used to emit line number notes before every non-deleted note.
- However, this confuses a debugger, because line notes not separated
- by real instructions all end up at the same address. I can find no
- use for line number notes before other notes, so none are emitted. */
- else if (GET_CODE (insn) != NOTE
- && (note = LINE_NOTE (insn)) != 0
- && note != line
- && (line == 0
- || NOTE_LINE_NUMBER (note) != NOTE_LINE_NUMBER (line)
- || NOTE_SOURCE_FILE (note) != NOTE_SOURCE_FILE (line)))
- {
- line = note;
- prev = PREV_INSN (insn);
- if (LINE_NOTE (note))
- {
- /* Re-use the original line-number note. */
- LINE_NOTE (note) = 0;
- PREV_INSN (note) = prev;
- NEXT_INSN (prev) = note;
- PREV_INSN (insn) = note;
- NEXT_INSN (note) = insn;
- }
- else
- {
- added_notes++;
- new = emit_note_after (NOTE_LINE_NUMBER (note), prev);
- NOTE_SOURCE_FILE (new) = NOTE_SOURCE_FILE (note);
- RTX_INTEGRATED_P (new) = RTX_INTEGRATED_P (note);
- }
- }
- if (sched_verbose && added_notes)
- fprintf (dump, ";; added %d line-number notes\n", added_notes);
-}
+ regstat_free_calls_crossed ();
-/* After scheduling the function, delete redundant line notes from the
- insns list. */
+ dfa_finish ();
-static void
-rm_redundant_line_notes ()
-{
- rtx line = 0;
- rtx insn = get_insns ();
- int active_insn = 0;
- int notes = 0;
-
- /* Walk the insns deleting redundant line-number notes. Many of these
- are already present. The remainder tend to occur at basic
- block boundaries. */
- for (insn = get_last_insn (); insn; insn = PREV_INSN (insn))
- if (GET_CODE (insn) == NOTE && NOTE_LINE_NUMBER (insn) > 0)
- {
- /* If there are no active insns following, INSN is redundant. */
- if (active_insn == 0)
- {
- notes++;
- NOTE_SOURCE_FILE (insn) = 0;
- NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
- }
- /* If the line number is unchanged, LINE is redundant. */
- else if (line
- && NOTE_LINE_NUMBER (line) == NOTE_LINE_NUMBER (insn)
- && NOTE_SOURCE_FILE (line) == NOTE_SOURCE_FILE (insn))
- {
- notes++;
- NOTE_SOURCE_FILE (line) = 0;
- NOTE_LINE_NUMBER (line) = NOTE_INSN_DELETED;
- line = insn;
- }
- else
- line = insn;
- active_insn = 0;
- }
- else if (!((GET_CODE (insn) == NOTE
- && NOTE_LINE_NUMBER (insn) == NOTE_INSN_DELETED)
- || (GET_CODE (insn) == INSN
- && (GET_CODE (PATTERN (insn)) == USE
- || GET_CODE (PATTERN (insn)) == CLOBBER))))
- active_insn++;
-
- if (sched_verbose && notes)
- fprintf (dump, ";; deleted %d line-number notes\n", notes);
+#ifdef ENABLE_CHECKING
+ /* After reload ia64 backend clobbers CFG, so can't check anything. */
+ if (!reload_completed)
+ check_cfg (0, 0);
+#endif
}
-/* Delete notes between head and tail and put them in the chain
- of notes ended by NOTE_LIST. */
-
+/* Fix INSN_TICKs of the instructions in the current block as well as
+ INSN_TICKs of their dependents.
+ HEAD and TAIL are the begin and the end of the current scheduled block. */
static void
-rm_other_notes (head, tail)
- rtx head;
- rtx tail;
+fix_inter_tick (rtx head, rtx tail)
{
- rtx next_tail;
- rtx insn;
-
- if (head == tail
- && (GET_RTX_CLASS (GET_CODE (head)) != 'i'))
- return;
-
- next_tail = NEXT_INSN (tail);
- for (insn = head; insn != next_tail; insn = NEXT_INSN (insn))
+ /* Set of instructions with corrected INSN_TICK. */
+ bitmap_head processed;
+ /* ??? It is doubtful if we should assume that cycle advance happens on
+ basic block boundaries. Basically insns that are unconditionally ready
+ on the start of the block are more preferable then those which have
+ a one cycle dependency over insn from the previous block. */
+ int next_clock = clock_var + 1;
+
+ bitmap_initialize (&processed, 0);
+
+ /* Iterates over scheduled instructions and fix their INSN_TICKs and
+ INSN_TICKs of dependent instructions, so that INSN_TICKs are consistent
+ across different blocks. */
+ for (tail = NEXT_INSN (tail); head != tail; head = NEXT_INSN (head))
{
- rtx prev;
-
- /* Farm out notes, and maybe save them in NOTE_LIST.
- This is needed to keep the debugger from
- getting completely deranged. */
- if (GET_CODE (insn) == NOTE)
+ if (INSN_P (head))
{
- prev = insn;
+ int tick;
+ sd_iterator_def sd_it;
+ dep_t dep;
- insn = unlink_other_notes (insn, next_tail);
+ tick = INSN_TICK (head);
+ gcc_assert (tick >= MIN_TICK);
- if (prev == tail)
- abort ();
- if (prev == head)
- abort ();
- if (insn == next_tail)
- abort ();
- }
- }
-}
+ /* Fix INSN_TICK of instruction from just scheduled block. */
+ if (!bitmap_bit_p (&processed, INSN_LUID (head)))
+ {
+ bitmap_set_bit (&processed, INSN_LUID (head));
+ tick -= next_clock;
-/* Functions for computation of registers live/usage info. */
+ if (tick < MIN_TICK)
+ tick = MIN_TICK;
-/* Calculate INSN_REG_WEIGHT for all insns of a block. */
+ INSN_TICK (head) = tick;
+ }
-static void
-find_insn_reg_weight (b)
- int b;
-{
- rtx insn, next_tail, head, tail;
+ FOR_EACH_DEP (head, SD_LIST_RES_FORW, sd_it, dep)
+ {
+ rtx next;
- get_block_head_tail (b, &head, &tail);
- next_tail = NEXT_INSN (tail);
+ next = DEP_CON (dep);
+ tick = INSN_TICK (next);
- for (insn = head; insn != next_tail; insn = NEXT_INSN (insn))
- {
- int reg_weight = 0;
- rtx x;
+ if (tick != INVALID_TICK
+ /* If NEXT has its INSN_TICK calculated, fix it.
+ If not - it will be properly calculated from
+ scratch later in fix_tick_ready. */
+ && !bitmap_bit_p (&processed, INSN_LUID (next)))
+ {
+ bitmap_set_bit (&processed, INSN_LUID (next));
+ tick -= next_clock;
- /* Handle register life information. */
- if (GET_RTX_CLASS (GET_CODE (insn)) != 'i')
- continue;
+ if (tick < MIN_TICK)
+ tick = MIN_TICK;
- /* Increment weight for each register born here. */
- x = PATTERN (insn);
- if ((GET_CODE (x) == SET || GET_CODE (x) == CLOBBER)
- && register_operand (SET_DEST (x), VOIDmode))
- reg_weight++;
- else if (GET_CODE (x) == PARALLEL)
- {
- int j;
- for (j = XVECLEN (x, 0) - 1; j >= 0; j--)
- {
- x = XVECEXP (PATTERN (insn), 0, j);
- if ((GET_CODE (x) == SET || GET_CODE (x) == CLOBBER)
- && register_operand (SET_DEST (x), VOIDmode))
- reg_weight++;
- }
- }
+ if (tick > INTER_TICK (next))
+ INTER_TICK (next) = tick;
+ else
+ tick = INTER_TICK (next);
- /* Decrement weight for each register that dies here. */
- for (x = REG_NOTES (insn); x; x = XEXP (x, 1))
- {
- if (REG_NOTE_KIND (x) == REG_DEAD
- || REG_NOTE_KIND (x) == REG_UNUSED)
- reg_weight--;
+ INSN_TICK (next) = tick;
+ }
+ }
}
-
- INSN_REG_WEIGHT (insn) = reg_weight;
}
+ bitmap_clear (&processed);
}
-/* Scheduling clock, modified in schedule_block() and queue_to_ready (). */
-static int clock_var;
-
-/* Move insns that became ready to fire from queue to ready list. */
+static int haifa_speculate_insn (rtx, ds_t, rtx *);
-static int
-queue_to_ready (ready, n_ready)
- rtx ready[];
- int n_ready;
+/* Check if NEXT is ready to be added to the ready or queue list.
+ If "yes", add it to the proper list.
+ Returns:
+ -1 - is not ready yet,
+ 0 - added to the ready list,
+ 0 < N - queued for N cycles. */
+int
+try_ready (rtx next)
{
- rtx insn;
- rtx link;
-
- q_ptr = NEXT_Q (q_ptr);
-
- /* Add all pending insns that can be scheduled without stalls to the
- ready list. */
- for (link = insn_queue[q_ptr]; link; link = XEXP (link, 1))
- {
+ ds_t old_ts, *ts;
- insn = XEXP (link, 0);
- q_size -= 1;
+ ts = &TODO_SPEC (next);
+ old_ts = *ts;
- if (sched_verbose >= 2)
- fprintf (dump, ";;\t\tQ-->Ready: insn %d: ", INSN_UID (insn));
+ gcc_assert (!(old_ts & ~(SPECULATIVE | HARD_DEP))
+ && ((old_ts & HARD_DEP)
+ || (old_ts & SPECULATIVE)));
- if (sched_verbose >= 2 && INSN_BB (insn) != target_bb)
- fprintf (dump, "(b%d) ", BLOCK_NUM (insn));
+ if (sd_lists_empty_p (next, SD_LIST_BACK))
+ /* NEXT has all its dependencies resolved. */
+ {
+ /* Remove HARD_DEP bit from NEXT's status. */
+ *ts &= ~HARD_DEP;
- ready[n_ready++] = insn;
- if (sched_verbose >= 2)
- fprintf (dump, "moving to ready without stalls\n");
+ if (current_sched_info->flags & DO_SPECULATION)
+ /* Remove all speculative bits from NEXT's status. */
+ *ts &= ~SPECULATIVE;
}
- insn_queue[q_ptr] = 0;
-
- /* If there are no ready insns, stall until one is ready and add all
- of the pending insns at that point to the ready list. */
- if (n_ready == 0)
+ else
{
- register int stalls;
+ /* One of the NEXT's dependencies has been resolved.
+ Recalculate NEXT's status. */
- for (stalls = 1; stalls < INSN_QUEUE_SIZE; stalls++)
+ *ts &= ~SPECULATIVE & ~HARD_DEP;
+
+ if (sd_lists_empty_p (next, SD_LIST_HARD_BACK))
+ /* Now we've got NEXT with speculative deps only.
+ 1. Look at the deps to see what we have to do.
+ 2. Check if we can do 'todo'. */
{
- if ((link = insn_queue[NEXT_Q_AFTER (q_ptr, stalls)]))
+ sd_iterator_def sd_it;
+ dep_t dep;
+ bool first_p = true;
+
+ FOR_EACH_DEP (next, SD_LIST_BACK, sd_it, dep)
{
- for (; link; link = XEXP (link, 1))
- {
- insn = XEXP (link, 0);
- q_size -= 1;
+ ds_t ds = DEP_STATUS (dep) & SPECULATIVE;
- if (sched_verbose >= 2)
- fprintf (dump, ";;\t\tQ-->Ready: insn %d: ", INSN_UID (insn));
+ if (DEBUG_INSN_P (DEP_PRO (dep))
+ && !DEBUG_INSN_P (next))
+ continue;
- if (sched_verbose >= 2 && INSN_BB (insn) != target_bb)
- fprintf (dump, "(b%d) ", BLOCK_NUM (insn));
+ if (first_p)
+ {
+ first_p = false;
- ready[n_ready++] = insn;
- if (sched_verbose >= 2)
- fprintf (dump, "moving to ready with %d stalls\n", stalls);
+ *ts = ds;
}
- insn_queue[NEXT_Q_AFTER (q_ptr, stalls)] = 0;
-
- if (n_ready)
- break;
+ else
+ *ts = ds_merge (*ts, ds);
}
- }
- if (sched_verbose && stalls)
- visualize_stall_cycles (BB_TO_BLOCK (target_bb), stalls);
- q_ptr = NEXT_Q_AFTER (q_ptr, stalls);
- clock_var += stalls;
+ if (ds_weak (*ts) < spec_info->data_weakness_cutoff)
+ /* Too few points. */
+ *ts = (*ts & ~SPECULATIVE) | HARD_DEP;
+ }
+ else
+ *ts |= HARD_DEP;
}
- return n_ready;
-}
-/* Print the ready list for debugging purposes. Callable from debugger. */
-
-static void
-debug_ready_list (ready, n_ready)
- rtx ready[];
- int n_ready;
-{
- int i;
-
- for (i = 0; i < n_ready; i++)
+ if (*ts & HARD_DEP)
+ gcc_assert (*ts == old_ts
+ && QUEUE_INDEX (next) == QUEUE_NOWHERE);
+ else if (current_sched_info->new_ready)
+ *ts = current_sched_info->new_ready (next, *ts);
+
+ /* * if !(old_ts & SPECULATIVE) (e.g. HARD_DEP or 0), then insn might
+ have its original pattern or changed (speculative) one. This is due
+ to changing ebb in region scheduling.
+ * But if (old_ts & SPECULATIVE), then we are pretty sure that insn
+ has speculative pattern.
+
+ We can't assert (!(*ts & HARD_DEP) || *ts == old_ts) here because
+ control-speculative NEXT could have been discarded by sched-rgn.c
+ (the same case as when discarded by can_schedule_ready_p ()). */
+
+ if ((*ts & SPECULATIVE)
+ /* If (old_ts == *ts), then (old_ts & SPECULATIVE) and we don't
+ need to change anything. */
+ && *ts != old_ts)
{
- fprintf (dump, " %d", INSN_UID (ready[i]));
- if (current_nr_blocks > 1 && INSN_BB (ready[i]) != target_bb)
- fprintf (dump, "/b%d", BLOCK_NUM (ready[i]));
- }
- fprintf (dump, "\n");
-}
-
-/* Print names of units on which insn can/should execute, for debugging. */
+ int res;
+ rtx new_pat;
-static void
-insn_print_units (insn)
- rtx insn;
-{
- int i;
- int unit = insn_unit (insn);
+ gcc_assert ((*ts & SPECULATIVE) && !(*ts & ~SPECULATIVE));
- if (unit == -1)
- fprintf (dump, "none");
- else if (unit >= 0)
- fprintf (dump, "%s", function_units[unit].name);
- else
- {
- fprintf (dump, "[");
- for (i = 0, unit = ~unit; unit; i++, unit >>= 1)
- if (unit & 1)
- {
- fprintf (dump, "%s", function_units[i].name);
- if (unit != 1)
- fprintf (dump, " ");
- }
- fprintf (dump, "]");
- }
-}
+ res = haifa_speculate_insn (next, *ts, &new_pat);
-/* MAX_VISUAL_LINES is the maximum number of lines in visualization table
- of a basic block. If more lines are needed, table is splitted to two.
- n_visual_lines is the number of lines printed so far for a block.
- visual_tbl contains the block visualization info.
- vis_no_unit holds insns in a cycle that are not mapped to any unit. */
-#define MAX_VISUAL_LINES 100
-#define INSN_LEN 30
-int n_visual_lines;
-char *visual_tbl;
-int n_vis_no_unit;
-rtx vis_no_unit[10];
-
-/* Finds units that are in use in this fuction. Required only
- for visualization. */
+ switch (res)
+ {
+ case -1:
+ /* It would be nice to change DEP_STATUS of all dependences,
+ which have ((DEP_STATUS & SPECULATIVE) == *ts) to HARD_DEP,
+ so we won't reanalyze anything. */
+ *ts = (*ts & ~SPECULATIVE) | HARD_DEP;
+ break;
-static void
-init_target_units ()
-{
- rtx insn;
- int unit;
+ case 0:
+ /* We follow the rule, that every speculative insn
+ has non-null ORIG_PAT. */
+ if (!ORIG_PAT (next))
+ ORIG_PAT (next) = PATTERN (next);
+ break;
- for (insn = get_last_insn (); insn; insn = PREV_INSN (insn))
- {
- if (GET_RTX_CLASS (GET_CODE (insn)) != 'i')
- continue;
+ case 1:
+ if (!ORIG_PAT (next))
+ /* If we gonna to overwrite the original pattern of insn,
+ save it. */
+ ORIG_PAT (next) = PATTERN (next);
- unit = insn_unit (insn);
+ haifa_change_pattern (next, new_pat);
+ break;
- if (unit < 0)
- target_units |= ~unit;
- else
- target_units |= (1 << unit);
+ default:
+ gcc_unreachable ();
+ }
}
-}
-
-/* Return the length of the visualization table. */
-static int
-get_visual_tbl_length ()
-{
- int unit, i;
- int n, n1;
- char *s;
-
- /* Compute length of one field in line. */
- s = (char *) alloca (INSN_LEN + 6);
- sprintf (s, " %33s", "uname");
- n1 = strlen (s);
-
- /* Compute length of one line. */
- n = strlen (";; ");
- n += n1;
- for (unit = 0; unit < FUNCTION_UNITS_SIZE; unit++)
- if (function_units[unit].bitmask & target_units)
- for (i = 0; i < function_units[unit].multiplicity; i++)
- n += n1;
- n += n1;
- n += strlen ("\n") + 2;
-
- /* Compute length of visualization string. */
- return (MAX_VISUAL_LINES * n);
-}
-
-/* Init block visualization debugging info. */
-
-static void
-init_block_visualization ()
-{
- strcpy (visual_tbl, "");
- n_visual_lines = 0;
- n_vis_no_unit = 0;
-}
+ /* We need to restore pattern only if (*ts == 0), because otherwise it is
+ either correct (*ts & SPECULATIVE),
+ or we simply don't care (*ts & HARD_DEP). */
-#define BUF_LEN 256
+ gcc_assert (!ORIG_PAT (next)
+ || !IS_SPECULATION_BRANCHY_CHECK_P (next));
-static char *
-safe_concat (buf, cur, str)
- char *buf;
- char *cur;
- const char *str;
-{
- char *end = buf + BUF_LEN - 2; /* Leave room for null. */
- int c;
+ if (*ts & HARD_DEP)
+ {
+ /* We can't assert (QUEUE_INDEX (next) == QUEUE_NOWHERE) here because
+ control-speculative NEXT could have been discarded by sched-rgn.c
+ (the same case as when discarded by can_schedule_ready_p ()). */
+ /*gcc_assert (QUEUE_INDEX (next) == QUEUE_NOWHERE);*/
+
+ change_queue_index (next, QUEUE_NOWHERE);
+ return -1;
+ }
+ else if (!(*ts & BEGIN_SPEC) && ORIG_PAT (next) && !IS_SPECULATION_CHECK_P (next))
+ /* We should change pattern of every previously speculative
+ instruction - and we determine if NEXT was speculative by using
+ ORIG_PAT field. Except one case - speculation checks have ORIG_PAT
+ pat too, so skip them. */
+ {
+ haifa_change_pattern (next, ORIG_PAT (next));
+ ORIG_PAT (next) = 0;
+ }
- if (cur > end)
+ if (sched_verbose >= 2)
{
- *end = '\0';
- return end;
+ int s = TODO_SPEC (next);
+
+ fprintf (sched_dump, ";;\t\tdependencies resolved: insn %s",
+ (*current_sched_info->print_insn) (next, 0));
+
+ if (spec_info && spec_info->dump)
+ {
+ if (s & BEGIN_DATA)
+ fprintf (spec_info->dump, "; data-spec;");
+ if (s & BEGIN_CONTROL)
+ fprintf (spec_info->dump, "; control-spec;");
+ if (s & BE_IN_CONTROL)
+ fprintf (spec_info->dump, "; in-control-spec;");
+ }
+
+ fprintf (sched_dump, "\n");
}
- while (cur < end && (c = *str++) != '\0')
- *cur++ = c;
+ adjust_priority (next);
- *cur = '\0';
- return cur;
+ return fix_tick_ready (next);
}
-/* This recognizes rtx, I classified as expressions. These are always
- represent some action on values or results of other expression, that
- may be stored in objects representing values. */
-
-static void
-print_exp (buf, x, verbose)
- char *buf;
- rtx x;
- int verbose;
+/* Calculate INSN_TICK of NEXT and add it to either ready or queue list. */
+static int
+fix_tick_ready (rtx next)
{
- char tmp[BUF_LEN];
- const char *st[4];
- char *cur = buf;
- const char *fun = (char *)0;
- const char *sep;
- rtx op[4];
- int i;
+ int tick, delay;
- for (i = 0; i < 4; i++)
+ if (!sd_lists_empty_p (next, SD_LIST_RES_BACK))
{
- st[i] = (char *)0;
- op[i] = NULL_RTX;
- }
+ int full_p;
+ sd_iterator_def sd_it;
+ dep_t dep;
- switch (GET_CODE (x))
- {
- case PLUS:
- op[0] = XEXP (x, 0);
- if (GET_CODE (XEXP (x, 1)) == CONST_INT
- && INTVAL (XEXP (x, 1)) < 0)
- {
- st[1] = "-";
- op[1] = GEN_INT (-INTVAL (XEXP (x, 1)));
- }
- else
- {
- st[1] = "+";
- op[1] = XEXP (x, 1);
- }
- break;
- case LO_SUM:
- op[0] = XEXP (x, 0);
- st[1] = "+low(";
- op[1] = XEXP (x, 1);
- st[2] = ")";
- break;
- case MINUS:
- op[0] = XEXP (x, 0);
- st[1] = "-";
- op[1] = XEXP (x, 1);
- break;
- case COMPARE:
- fun = "cmp";
- op[0] = XEXP (x, 0);
- op[1] = XEXP (x, 1);
- break;
- case NEG:
- st[0] = "-";
- op[0] = XEXP (x, 0);
- break;
- case MULT:
- op[0] = XEXP (x, 0);
- st[1] = "*";
- op[1] = XEXP (x, 1);
- break;
- case DIV:
- op[0] = XEXP (x, 0);
- st[1] = "/";
- op[1] = XEXP (x, 1);
- break;
- case UDIV:
- fun = "udiv";
- op[0] = XEXP (x, 0);
- op[1] = XEXP (x, 1);
- break;
- case MOD:
- op[0] = XEXP (x, 0);
- st[1] = "%";
- op[1] = XEXP (x, 1);
- break;
- case UMOD:
- fun = "umod";
- op[0] = XEXP (x, 0);
- op[1] = XEXP (x, 1);
- break;
- case SMIN:
- fun = "smin";
- op[0] = XEXP (x, 0);
- op[1] = XEXP (x, 1);
- break;
- case SMAX:
- fun = "smax";
- op[0] = XEXP (x, 0);
- op[1] = XEXP (x, 1);
- break;
- case UMIN:
- fun = "umin";
- op[0] = XEXP (x, 0);
- op[1] = XEXP (x, 1);
- break;
- case UMAX:
- fun = "umax";
- op[0] = XEXP (x, 0);
- op[1] = XEXP (x, 1);
- break;
- case NOT:
- st[0] = "!";
- op[0] = XEXP (x, 0);
- break;
- case AND:
- op[0] = XEXP (x, 0);
- st[1] = "&";
- op[1] = XEXP (x, 1);
- break;
- case IOR:
- op[0] = XEXP (x, 0);
- st[1] = "|";
- op[1] = XEXP (x, 1);
- break;
- case XOR:
- op[0] = XEXP (x, 0);
- st[1] = "^";
- op[1] = XEXP (x, 1);
- break;
- case ASHIFT:
- op[0] = XEXP (x, 0);
- st[1] = "<<";
- op[1] = XEXP (x, 1);
- break;
- case LSHIFTRT:
- op[0] = XEXP (x, 0);
- st[1] = " 0>>";
- op[1] = XEXP (x, 1);
- break;
- case ASHIFTRT:
- op[0] = XEXP (x, 0);
- st[1] = ">>";
- op[1] = XEXP (x, 1);
- break;
- case ROTATE:
- op[0] = XEXP (x, 0);
- st[1] = "<-<";
- op[1] = XEXP (x, 1);
- break;
- case ROTATERT:
- op[0] = XEXP (x, 0);
- st[1] = ">->";
- op[1] = XEXP (x, 1);
- break;
- case ABS:
- fun = "abs";
- op[0] = XEXP (x, 0);
- break;
- case SQRT:
- fun = "sqrt";
- op[0] = XEXP (x, 0);
- break;
- case FFS:
- fun = "ffs";
- op[0] = XEXP (x, 0);
- break;
- case EQ:
- op[0] = XEXP (x, 0);
- st[1] = "==";
- op[1] = XEXP (x, 1);
- break;
- case NE:
- op[0] = XEXP (x, 0);
- st[1] = "!=";
- op[1] = XEXP (x, 1);
- break;
- case GT:
- op[0] = XEXP (x, 0);
- st[1] = ">";
- op[1] = XEXP (x, 1);
- break;
- case GTU:
- fun = "gtu";
- op[0] = XEXP (x, 0);
- op[1] = XEXP (x, 1);
- break;
- case LT:
- op[0] = XEXP (x, 0);
- st[1] = "<";
- op[1] = XEXP (x, 1);
- break;
- case LTU:
- fun = "ltu";
- op[0] = XEXP (x, 0);
- op[1] = XEXP (x, 1);
- break;
- case GE:
- op[0] = XEXP (x, 0);
- st[1] = ">=";
- op[1] = XEXP (x, 1);
- break;
- case GEU:
- fun = "geu";
- op[0] = XEXP (x, 0);
- op[1] = XEXP (x, 1);
- break;
- case LE:
- op[0] = XEXP (x, 0);
- st[1] = "<=";
- op[1] = XEXP (x, 1);
- break;
- case LEU:
- fun = "leu";
- op[0] = XEXP (x, 0);
- op[1] = XEXP (x, 1);
- break;
- case SIGN_EXTRACT:
- fun = (verbose) ? "sign_extract" : "sxt";
- op[0] = XEXP (x, 0);
- op[1] = XEXP (x, 1);
- op[2] = XEXP (x, 2);
- break;
- case ZERO_EXTRACT:
- fun = (verbose) ? "zero_extract" : "zxt";
- op[0] = XEXP (x, 0);
- op[1] = XEXP (x, 1);
- op[2] = XEXP (x, 2);
- break;
- case SIGN_EXTEND:
- fun = (verbose) ? "sign_extend" : "sxn";
- op[0] = XEXP (x, 0);
- break;
- case ZERO_EXTEND:
- fun = (verbose) ? "zero_extend" : "zxn";
- op[0] = XEXP (x, 0);
- break;
- case FLOAT_EXTEND:
- fun = (verbose) ? "float_extend" : "fxn";
- op[0] = XEXP (x, 0);
- break;
- case TRUNCATE:
- fun = (verbose) ? "trunc" : "trn";
- op[0] = XEXP (x, 0);
- break;
- case FLOAT_TRUNCATE:
- fun = (verbose) ? "float_trunc" : "ftr";
- op[0] = XEXP (x, 0);
- break;
- case FLOAT:
- fun = (verbose) ? "float" : "flt";
- op[0] = XEXP (x, 0);
- break;
- case UNSIGNED_FLOAT:
- fun = (verbose) ? "uns_float" : "ufl";
- op[0] = XEXP (x, 0);
- break;
- case FIX:
- fun = "fix";
- op[0] = XEXP (x, 0);
- break;
- case UNSIGNED_FIX:
- fun = (verbose) ? "uns_fix" : "ufx";
- op[0] = XEXP (x, 0);
- break;
- case PRE_DEC:
- st[0] = "--";
- op[0] = XEXP (x, 0);
- break;
- case PRE_INC:
- st[0] = "++";
- op[0] = XEXP (x, 0);
- break;
- case POST_DEC:
- op[0] = XEXP (x, 0);
- st[1] = "--";
- break;
- case POST_INC:
- op[0] = XEXP (x, 0);
- st[1] = "++";
- break;
- case CALL:
- st[0] = "call ";
- op[0] = XEXP (x, 0);
- if (verbose)
- {
- st[1] = " argc:";
- op[1] = XEXP (x, 1);
- }
- break;
- case IF_THEN_ELSE:
- st[0] = "{(";
- op[0] = XEXP (x, 0);
- st[1] = ")?";
- op[1] = XEXP (x, 1);
- st[2] = ":";
- op[2] = XEXP (x, 2);
- st[3] = "}";
- break;
- case TRAP_IF:
- fun = "trap_if";
- op[0] = TRAP_CONDITION (x);
- break;
- case UNSPEC:
- case UNSPEC_VOLATILE:
- {
- cur = safe_concat (buf, cur, "unspec");
- if (GET_CODE (x) == UNSPEC_VOLATILE)
- cur = safe_concat (buf, cur, "/v");
- cur = safe_concat (buf, cur, "[");
- sep = "";
- for (i = 0; i < XVECLEN (x, 0); i++)
- {
- print_pattern (tmp, XVECEXP (x, 0, i), verbose);
- cur = safe_concat (buf, cur, sep);
- cur = safe_concat (buf, cur, tmp);
- sep = ",";
- }
- cur = safe_concat (buf, cur, "] ");
- sprintf (tmp, "%d", XINT (x, 1));
- cur = safe_concat (buf, cur, tmp);
- }
- break;
- default:
- /* If (verbose) debug_rtx (x); */
- st[0] = GET_RTX_NAME (GET_CODE (x));
- break;
- }
+ tick = INSN_TICK (next);
+ /* if tick is not equal to INVALID_TICK, then update
+ INSN_TICK of NEXT with the most recent resolved dependence
+ cost. Otherwise, recalculate from scratch. */
+ full_p = (tick == INVALID_TICK);
- /* Print this as a function? */
- if (fun)
- {
- cur = safe_concat (buf, cur, fun);
- cur = safe_concat (buf, cur, "(");
- }
+ FOR_EACH_DEP (next, SD_LIST_RES_BACK, sd_it, dep)
+ {
+ rtx pro = DEP_PRO (dep);
+ int tick1;
- for (i = 0; i < 4; i++)
- {
- if (st[i])
- cur = safe_concat (buf, cur, st[i]);
+ gcc_assert (INSN_TICK (pro) >= MIN_TICK);
- if (op[i])
- {
- if (fun && i != 0)
- cur = safe_concat (buf, cur, ",");
+ tick1 = INSN_TICK (pro) + dep_cost (dep);
+ if (tick1 > tick)
+ tick = tick1;
- print_value (tmp, op[i], verbose);
- cur = safe_concat (buf, cur, tmp);
- }
+ if (!full_p)
+ break;
+ }
}
+ else
+ tick = -1;
- if (fun)
- cur = safe_concat (buf, cur, ")");
-} /* print_exp */
+ INSN_TICK (next) = tick;
-/* Prints rtxes, I customly classified as values. They're constants,
- registers, labels, symbols and memory accesses. */
+ delay = tick - clock_var;
+ if (delay <= 0 || sched_pressure_p)
+ delay = QUEUE_READY;
+ change_queue_index (next, delay);
+
+ return delay;
+}
+
+/* Move NEXT to the proper queue list with (DELAY >= 1),
+ or add it to the ready list (DELAY == QUEUE_READY),
+ or remove it from ready and queue lists at all (DELAY == QUEUE_NOWHERE). */
static void
-print_value (buf, x, verbose)
- char *buf;
- rtx x;
- int verbose;
+change_queue_index (rtx next, int delay)
{
- char t[BUF_LEN];
- char *cur = buf;
+ int i = QUEUE_INDEX (next);
+
+ gcc_assert (QUEUE_NOWHERE <= delay && delay <= max_insn_queue_index
+ && delay != 0);
+ gcc_assert (i != QUEUE_SCHEDULED);
+
+ if ((delay > 0 && NEXT_Q_AFTER (q_ptr, delay) == i)
+ || (delay < 0 && delay == i))
+ /* We have nothing to do. */
+ return;
+
+ /* Remove NEXT from wherever it is now. */
+ if (i == QUEUE_READY)
+ ready_remove_insn (next);
+ else if (i >= 0)
+ queue_remove (next);
- switch (GET_CODE (x))
+ /* Add it to the proper place. */
+ if (delay == QUEUE_READY)
+ ready_add (readyp, next, false);
+ else if (delay >= 1)
+ queue_insn (next, delay);
+
+ if (sched_verbose >= 2)
{
- case CONST_INT:
- sprintf (t, HOST_WIDE_INT_PRINT_HEX, INTVAL (x));
- cur = safe_concat (buf, cur, t);
- break;
- case CONST_DOUBLE:
- sprintf (t, "<0x%lx,0x%lx>", (long)XWINT (x, 2), (long)XWINT (x, 3));
- cur = safe_concat (buf, cur, t);
- break;
- case CONST_STRING:
- cur = safe_concat (buf, cur, "\"");
- cur = safe_concat (buf, cur, XSTR (x, 0));
- cur = safe_concat (buf, cur, "\"");
- break;
- case SYMBOL_REF:
- cur = safe_concat (buf, cur, "`");
- cur = safe_concat (buf, cur, XSTR (x, 0));
- cur = safe_concat (buf, cur, "'");
- break;
- case LABEL_REF:
- sprintf (t, "L%d", INSN_UID (XEXP (x, 0)));
- cur = safe_concat (buf, cur, t);
- break;
- case CONST:
- print_value (t, XEXP (x, 0), verbose);
- cur = safe_concat (buf, cur, "const(");
- cur = safe_concat (buf, cur, t);
- cur = safe_concat (buf, cur, ")");
- break;
- case HIGH:
- print_value (t, XEXP (x, 0), verbose);
- cur = safe_concat (buf, cur, "high(");
- cur = safe_concat (buf, cur, t);
- cur = safe_concat (buf, cur, ")");
- break;
- case REG:
- if (REGNO (x) < FIRST_PSEUDO_REGISTER)
- {
- int c = reg_names[ REGNO (x) ][0];
- if (c >= '0' && c <= '9')
- cur = safe_concat (buf, cur, "%");
+ fprintf (sched_dump, ";;\t\ttick updated: insn %s",
+ (*current_sched_info->print_insn) (next, 0));
- cur = safe_concat (buf, cur, reg_names[ REGNO (x) ]);
- }
+ if (delay == QUEUE_READY)
+ fprintf (sched_dump, " into ready\n");
+ else if (delay >= 1)
+ fprintf (sched_dump, " into queue with cost=%d\n", delay);
else
- {
- sprintf (t, "r%d", REGNO (x));
- cur = safe_concat (buf, cur, t);
- }
- break;
- case SUBREG:
- print_value (t, SUBREG_REG (x), verbose);
- cur = safe_concat (buf, cur, t);
- sprintf (t, "#%d", SUBREG_WORD (x));
- cur = safe_concat (buf, cur, t);
- break;
- case SCRATCH:
- cur = safe_concat (buf, cur, "scratch");
- break;
- case CC0:
- cur = safe_concat (buf, cur, "cc0");
- break;
- case PC:
- cur = safe_concat (buf, cur, "pc");
- break;
- case MEM:
- print_value (t, XEXP (x, 0), verbose);
- cur = safe_concat (buf, cur, "[");
- cur = safe_concat (buf, cur, t);
- cur = safe_concat (buf, cur, "]");
- break;
- default:
- print_exp (t, x, verbose);
- cur = safe_concat (buf, cur, t);
- break;
+ fprintf (sched_dump, " removed from ready or queue lists\n");
}
-} /* print_value */
+}
-/* The next step in insn detalization, its pattern recognition. */
+static int sched_ready_n_insns = -1;
-static void
-print_pattern (buf, x, verbose)
- char *buf;
- rtx x;
- int verbose;
+/* Initialize per region data structures. */
+void
+sched_extend_ready_list (int new_sched_ready_n_insns)
{
- char t1[BUF_LEN], t2[BUF_LEN], t3[BUF_LEN];
+ int i;
- switch (GET_CODE (x))
+ if (sched_ready_n_insns == -1)
+ /* At the first call we need to initialize one more choice_stack
+ entry. */
{
- case SET:
- print_value (t1, SET_DEST (x), verbose);
- print_value (t2, SET_SRC (x), verbose);
- sprintf (buf, "%s=%s", t1, t2);
- break;
- case RETURN:
- sprintf (buf, "return");
- break;
- case CALL:
- print_exp (buf, x, verbose);
- break;
- case CLOBBER:
- print_value (t1, XEXP (x, 0), verbose);
- sprintf (buf, "clobber %s", t1);
- break;
- case USE:
- print_value (t1, XEXP (x, 0), verbose);
- sprintf (buf, "use %s", t1);
- break;
- case PARALLEL:
- {
- int i;
+ i = 0;
+ sched_ready_n_insns = 0;
+ }
+ else
+ i = sched_ready_n_insns + 1;
- sprintf (t1, "{");
- for (i = 0; i < XVECLEN (x, 0); i++)
- {
- print_pattern (t2, XVECEXP (x, 0, i), verbose);
- sprintf (t3, "%s%s;", t1, t2);
- strcpy (t1, t3);
- }
- sprintf (buf, "%s}", t1);
- }
- break;
- case SEQUENCE:
- {
- int i;
+ ready.veclen = new_sched_ready_n_insns + issue_rate;
+ ready.vec = XRESIZEVEC (rtx, ready.vec, ready.veclen);
- sprintf (t1, "%%{");
- for (i = 0; i < XVECLEN (x, 0); i++)
- {
- print_insn (t2, XVECEXP (x, 0, i), verbose);
- sprintf (t3, "%s%s;", t1, t2);
- strcpy (t1, t3);
- }
- sprintf (buf, "%s%%}", t1);
- }
- break;
- case ASM_INPUT:
- sprintf (buf, "asm {%s}", XSTR (x, 0));
- break;
- case ADDR_VEC:
- break;
- case ADDR_DIFF_VEC:
- print_value (buf, XEXP (x, 0), verbose);
- break;
- case TRAP_IF:
- print_value (t1, TRAP_CONDITION (x), verbose);
- sprintf (buf, "trap_if %s", t1);
- break;
- case UNSPEC:
- {
- int i;
+ gcc_assert (new_sched_ready_n_insns >= sched_ready_n_insns);
- sprintf (t1, "unspec{");
- for (i = 0; i < XVECLEN (x, 0); i++)
- {
- print_pattern (t2, XVECEXP (x, 0, i), verbose);
- sprintf (t3, "%s%s;", t1, t2);
- strcpy (t1, t3);
- }
- sprintf (buf, "%s}", t1);
- }
- break;
- case UNSPEC_VOLATILE:
- {
- int i;
+ ready_try = (char *) xrecalloc (ready_try, new_sched_ready_n_insns,
+ sched_ready_n_insns, sizeof (*ready_try));
- sprintf (t1, "unspec/v{");
- for (i = 0; i < XVECLEN (x, 0); i++)
- {
- print_pattern (t2, XVECEXP (x, 0, i), verbose);
- sprintf (t3, "%s%s;", t1, t2);
- strcpy (t1, t3);
- }
- sprintf (buf, "%s}", t1);
- }
- break;
- default:
- print_value (buf, x, verbose);
- }
-} /* print_pattern */
+ /* We allocate +1 element to save initial state in the choice_stack[0]
+ entry. */
+ choice_stack = XRESIZEVEC (struct choice_entry, choice_stack,
+ new_sched_ready_n_insns + 1);
-/* This is the main function in rtl visualization mechanism. It
- accepts an rtx and tries to recognize it as an insn, then prints it
- properly in human readable form, resembling assembler mnemonics.
- For every insn it prints its UID and BB the insn belongs too.
- (Probably the last "option" should be extended somehow, since it
- depends now on sched.c inner variables ...) */
+ for (; i <= new_sched_ready_n_insns; i++)
+ choice_stack[i].state = xmalloc (dfa_state_size);
-static void
-print_insn (buf, x, verbose)
- char *buf;
- rtx x;
- int verbose;
+ sched_ready_n_insns = new_sched_ready_n_insns;
+}
+
+/* Free per region data structures. */
+void
+sched_finish_ready_list (void)
{
- char t[BUF_LEN];
- rtx insn = x;
+ int i;
- switch (GET_CODE (x))
- {
- case INSN:
- print_pattern (t, PATTERN (x), verbose);
- if (verbose)
- sprintf (buf, "b%d: i% 4d: %s", INSN_BB (x),
- INSN_UID (x), t);
- else
- sprintf (buf, "%-4d %s", INSN_UID (x), t);
- break;
- case JUMP_INSN:
- print_pattern (t, PATTERN (x), verbose);
- if (verbose)
- sprintf (buf, "b%d: i% 4d: jump %s", INSN_BB (x),
- INSN_UID (x), t);
- else
- sprintf (buf, "%-4d %s", INSN_UID (x), t);
- break;
- case CALL_INSN:
- x = PATTERN (insn);
- if (GET_CODE (x) == PARALLEL)
- {
- x = XVECEXP (x, 0, 0);
- print_pattern (t, x, verbose);
- }
- else
- strcpy (t, "call <...>");
- if (verbose)
- sprintf (buf, "b%d: i% 4d: %s", INSN_BB (insn),
- INSN_UID (insn), t);
- else
- sprintf (buf, "%-4d %s", INSN_UID (insn), t);
- break;
- case CODE_LABEL:
- sprintf (buf, "L%d:", INSN_UID (x));
- break;
- case BARRIER:
- sprintf (buf, "i% 4d: barrier", INSN_UID (x));
- break;
- case NOTE:
- if (NOTE_LINE_NUMBER (x) > 0)
- sprintf (buf, "%4d note \"%s\" %d", INSN_UID (x),
- NOTE_SOURCE_FILE (x), NOTE_LINE_NUMBER (x));
- else
- sprintf (buf, "%4d %s", INSN_UID (x),
- GET_NOTE_INSN_NAME (NOTE_LINE_NUMBER (x)));
- break;
- default:
- if (verbose)
- {
- sprintf (buf, "Not an INSN at all\n");
- debug_rtx (x);
- }
- else
- sprintf (buf, "i%-4d <What?>", INSN_UID (x));
- }
-} /* print_insn */
+ free (ready.vec);
+ ready.vec = NULL;
+ ready.veclen = 0;
-/* Print visualization debugging info. */
+ free (ready_try);
+ ready_try = NULL;
-static void
-print_block_visualization (b, s)
- int b;
- const char *s;
-{
- int unit, i;
-
- /* Print header. */
- fprintf (dump, "\n;; ==================== scheduling visualization for block %d %s \n", b, s);
-
- /* Print names of units. */
- fprintf (dump, ";; %-8s", "clock");
- for (unit = 0; unit < FUNCTION_UNITS_SIZE; unit++)
- if (function_units[unit].bitmask & target_units)
- for (i = 0; i < function_units[unit].multiplicity; i++)
- fprintf (dump, " %-33s", function_units[unit].name);
- fprintf (dump, " %-8s\n", "no-unit");
-
- fprintf (dump, ";; %-8s", "=====");
- for (unit = 0; unit < FUNCTION_UNITS_SIZE; unit++)
- if (function_units[unit].bitmask & target_units)
- for (i = 0; i < function_units[unit].multiplicity; i++)
- fprintf (dump, " %-33s", "==============================");
- fprintf (dump, " %-8s\n", "=======");
-
- /* Print insns in each cycle. */
- fprintf (dump, "%s\n", visual_tbl);
+ for (i = 0; i <= sched_ready_n_insns; i++)
+ free (choice_stack [i].state);
+ free (choice_stack);
+ choice_stack = NULL;
+
+ sched_ready_n_insns = -1;
}
-/* Print insns in the 'no_unit' column of visualization. */
+static int
+haifa_luid_for_non_insn (rtx x)
+{
+ gcc_assert (NOTE_P (x) || LABEL_P (x));
+
+ return 0;
+}
+/* Generates recovery code for INSN. */
static void
-visualize_no_unit (insn)
- rtx insn;
+generate_recovery_code (rtx insn)
{
- vis_no_unit[n_vis_no_unit] = insn;
- n_vis_no_unit++;
-}
+ if (TODO_SPEC (insn) & BEGIN_SPEC)
+ begin_speculative_block (insn);
-/* Print insns scheduled in clock, for visualization. */
+ /* Here we have insn with no dependencies to
+ instructions other then CHECK_SPEC ones. */
+ if (TODO_SPEC (insn) & BE_IN_SPEC)
+ add_to_speculative_block (insn);
+}
+
+/* Helper function.
+ Tries to add speculative dependencies of type FS between instructions
+ in deps_list L and TWIN. */
static void
-visualize_scheduled_insns (b, clock)
- int b, clock;
+process_insn_forw_deps_be_in_spec (rtx insn, rtx twin, ds_t fs)
{
- int i, unit;
+ sd_iterator_def sd_it;
+ dep_t dep;
- /* If no more room, split table into two. */
- if (n_visual_lines >= MAX_VISUAL_LINES)
+ FOR_EACH_DEP (insn, SD_LIST_FORW, sd_it, dep)
{
- print_block_visualization (b, "(incomplete)");
- init_block_visualization ();
- }
+ ds_t ds;
+ rtx consumer;
+
+ consumer = DEP_CON (dep);
- n_visual_lines++;
+ ds = DEP_STATUS (dep);
- sprintf (visual_tbl + strlen (visual_tbl), ";; %-8d", clock);
- for (unit = 0; unit < FUNCTION_UNITS_SIZE; unit++)
- if (function_units[unit].bitmask & target_units)
- for (i = 0; i < function_units[unit].multiplicity; i++)
+ if (/* If we want to create speculative dep. */
+ fs
+ /* And we can do that because this is a true dep. */
+ && (ds & DEP_TYPES) == DEP_TRUE)
{
- int instance = unit + i * FUNCTION_UNITS_SIZE;
- rtx insn = unit_last_insn[instance];
+ gcc_assert (!(ds & BE_IN_SPEC));
- /* Print insns that still keep the unit busy. */
- if (insn &&
- actual_hazard_this_instance (unit, instance, insn, clock, 0))
+ if (/* If this dep can be overcome with 'begin speculation'. */
+ ds & BEGIN_SPEC)
+ /* Then we have a choice: keep the dep 'begin speculative'
+ or transform it into 'be in speculative'. */
{
- char str[BUF_LEN];
- print_insn (str, insn, 0);
- str[INSN_LEN] = '\0';
- sprintf (visual_tbl + strlen (visual_tbl), " %-33s", str);
+ if (/* In try_ready we assert that if insn once became ready
+ it can be removed from the ready (or queue) list only
+ due to backend decision. Hence we can't let the
+ probability of the speculative dep to decrease. */
+ ds_weak (ds) <= ds_weak (fs))
+ {
+ ds_t new_ds;
+
+ new_ds = (ds & ~BEGIN_SPEC) | fs;
+
+ if (/* consumer can 'be in speculative'. */
+ sched_insn_is_legitimate_for_speculation_p (consumer,
+ new_ds))
+ /* Transform it to be in speculative. */
+ ds = new_ds;
+ }
}
else
- sprintf (visual_tbl + strlen (visual_tbl), " %-33s", "------------------------------");
+ /* Mark the dep as 'be in speculative'. */
+ ds |= fs;
}
- /* Print insns that are not assigned to any unit. */
- for (i = 0; i < n_vis_no_unit; i++)
- sprintf (visual_tbl + strlen (visual_tbl), " %-8d",
- INSN_UID (vis_no_unit[i]));
- n_vis_no_unit = 0;
+ {
+ dep_def _new_dep, *new_dep = &_new_dep;
+
+ init_dep_1 (new_dep, twin, consumer, DEP_TYPE (dep), ds);
+ sd_add_dep (new_dep, false);
+ }
+ }
+}
+
+/* Generates recovery code for BEGIN speculative INSN. */
+static void
+begin_speculative_block (rtx insn)
+{
+ if (TODO_SPEC (insn) & BEGIN_DATA)
+ nr_begin_data++;
+ if (TODO_SPEC (insn) & BEGIN_CONTROL)
+ nr_begin_control++;
- sprintf (visual_tbl + strlen (visual_tbl), "\n");
+ create_check_block_twin (insn, false);
+
+ TODO_SPEC (insn) &= ~BEGIN_SPEC;
}
-/* Print stalled cycles. */
+static void haifa_init_insn (rtx);
+/* Generates recovery code for BE_IN speculative INSN. */
static void
-visualize_stall_cycles (b, stalls)
- int b, stalls;
+add_to_speculative_block (rtx insn)
{
- int i;
+ ds_t ts;
+ sd_iterator_def sd_it;
+ dep_t dep;
+ rtx twins = NULL;
+ rtx_vec_t priorities_roots;
+
+ ts = TODO_SPEC (insn);
+ gcc_assert (!(ts & ~BE_IN_SPEC));
+
+ if (ts & BE_IN_DATA)
+ nr_be_in_data++;
+ if (ts & BE_IN_CONTROL)
+ nr_be_in_control++;
- /* If no more room, split table into two. */
- if (n_visual_lines >= MAX_VISUAL_LINES)
+ TODO_SPEC (insn) &= ~BE_IN_SPEC;
+ gcc_assert (!TODO_SPEC (insn));
+
+ DONE_SPEC (insn) |= ts;
+
+ /* First we convert all simple checks to branchy. */
+ for (sd_it = sd_iterator_start (insn, SD_LIST_SPEC_BACK);
+ sd_iterator_cond (&sd_it, &dep);)
{
- print_block_visualization (b, "(incomplete)");
- init_block_visualization ();
+ rtx check = DEP_PRO (dep);
+
+ if (IS_SPECULATION_SIMPLE_CHECK_P (check))
+ {
+ create_check_block_twin (check, true);
+
+ /* Restart search. */
+ sd_it = sd_iterator_start (insn, SD_LIST_SPEC_BACK);
+ }
+ else
+ /* Continue search. */
+ sd_iterator_next (&sd_it);
}
- n_visual_lines++;
+ priorities_roots = NULL;
+ clear_priorities (insn, &priorities_roots);
- sprintf (visual_tbl + strlen (visual_tbl), ";; ");
- for (i = 0; i < stalls; i++)
- sprintf (visual_tbl + strlen (visual_tbl), ".");
- sprintf (visual_tbl + strlen (visual_tbl), "\n");
-}
+ while (1)
+ {
+ rtx check, twin;
+ basic_block rec;
-/* move_insn1: Remove INSN from insn chain, and link it after LAST insn. */
+ /* Get the first backward dependency of INSN. */
+ sd_it = sd_iterator_start (insn, SD_LIST_SPEC_BACK);
+ if (!sd_iterator_cond (&sd_it, &dep))
+ /* INSN has no backward dependencies left. */
+ break;
-static rtx
-move_insn1 (insn, last)
- rtx insn, last;
-{
- NEXT_INSN (PREV_INSN (insn)) = NEXT_INSN (insn);
- PREV_INSN (NEXT_INSN (insn)) = PREV_INSN (insn);
+ gcc_assert ((DEP_STATUS (dep) & BEGIN_SPEC) == 0
+ && (DEP_STATUS (dep) & BE_IN_SPEC) != 0
+ && (DEP_STATUS (dep) & DEP_TYPES) == DEP_TRUE);
- NEXT_INSN (insn) = NEXT_INSN (last);
- PREV_INSN (NEXT_INSN (last)) = insn;
+ check = DEP_PRO (dep);
- NEXT_INSN (last) = insn;
- PREV_INSN (insn) = last;
+ gcc_assert (!IS_SPECULATION_CHECK_P (check) && !ORIG_PAT (check)
+ && QUEUE_INDEX (check) == QUEUE_NOWHERE);
- return insn;
-}
+ rec = BLOCK_FOR_INSN (check);
-/* Search INSN for REG_SAVE_NOTE note pairs for NOTE_INSN_SETJMP,
- NOTE_INSN_{LOOP,EHREGION}_{BEG,END}; and convert them back into
- NOTEs. The REG_SAVE_NOTE note following first one is contains the
- saved value for NOTE_BLOCK_NUMBER which is useful for
- NOTE_INSN_EH_REGION_{BEG,END} NOTEs. LAST is the last instruction
- output by the instruction scheduler. Return the new value of LAST. */
-
-static rtx
-reemit_notes (insn, last)
- rtx insn;
- rtx last;
-{
- rtx note, retval;
+ twin = emit_insn_before (copy_insn (PATTERN (insn)), BB_END (rec));
+ haifa_init_insn (twin);
- retval = last;
- for (note = REG_NOTES (insn); note; note = XEXP (note, 1))
- {
- if (REG_NOTE_KIND (note) == REG_SAVE_NOTE)
+ sd_copy_back_deps (twin, insn, true);
+
+ if (sched_verbose && spec_info->dump)
+ /* INSN_BB (insn) isn't determined for twin insns yet.
+ So we can't use current_sched_info->print_insn. */
+ fprintf (spec_info->dump, ";;\t\tGenerated twin insn : %d/rec%d\n",
+ INSN_UID (twin), rec->index);
+
+ twins = alloc_INSN_LIST (twin, twins);
+
+ /* Add dependences between TWIN and all appropriate
+ instructions from REC. */
+ FOR_EACH_DEP (insn, SD_LIST_SPEC_BACK, sd_it, dep)
{
- int note_type = INTVAL (XEXP (note, 0));
- if (note_type == NOTE_INSN_SETJMP)
- {
- retval = emit_note_after (NOTE_INSN_SETJMP, insn);
- CONST_CALL_P (retval) = CONST_CALL_P (note);
- remove_note (insn, note);
- note = XEXP (note, 1);
- }
- else if (note_type == NOTE_INSN_RANGE_START
- || note_type == NOTE_INSN_RANGE_END)
+ rtx pro = DEP_PRO (dep);
+
+ gcc_assert (DEP_TYPE (dep) == REG_DEP_TRUE);
+
+ /* INSN might have dependencies from the instructions from
+ several recovery blocks. At this iteration we process those
+ producers that reside in REC. */
+ if (BLOCK_FOR_INSN (pro) == rec)
{
- last = emit_note_before (note_type, last);
- remove_note (insn, note);
- note = XEXP (note, 1);
- NOTE_RANGE_INFO (last) = XEXP (note, 0);
+ dep_def _new_dep, *new_dep = &_new_dep;
+
+ init_dep (new_dep, pro, twin, REG_DEP_TRUE);
+ sd_add_dep (new_dep, false);
}
+ }
+
+ process_insn_forw_deps_be_in_spec (insn, twin, ts);
+
+ /* Remove all dependencies between INSN and insns in REC. */
+ for (sd_it = sd_iterator_start (insn, SD_LIST_SPEC_BACK);
+ sd_iterator_cond (&sd_it, &dep);)
+ {
+ rtx pro = DEP_PRO (dep);
+
+ if (BLOCK_FOR_INSN (pro) == rec)
+ sd_delete_dep (sd_it);
else
- {
- last = emit_note_before (note_type, last);
- remove_note (insn, note);
- note = XEXP (note, 1);
- if (note_type == NOTE_INSN_EH_REGION_BEG
- || note_type == NOTE_INSN_EH_REGION_END)
- NOTE_EH_HANDLER (last) = INTVAL (XEXP (note, 0));
- }
- remove_note (insn, note);
+ sd_iterator_next (&sd_it);
}
}
- return retval;
-}
-/* Move INSN, and all insns which should be issued before it,
- due to SCHED_GROUP_P flag. Reemit notes if needed.
+ /* We couldn't have added the dependencies between INSN and TWINS earlier
+ because that would make TWINS appear in the INSN_BACK_DEPS (INSN). */
+ while (twins)
+ {
+ rtx twin;
+
+ twin = XEXP (twins, 0);
- Return the last insn emitted by the scheduler, which is the
- return value from the first call to reemit_notes. */
+ {
+ dep_def _new_dep, *new_dep = &_new_dep;
-static rtx
-move_insn (insn, last)
- rtx insn, last;
-{
- rtx retval = NULL;
+ init_dep (new_dep, insn, twin, REG_DEP_OUTPUT);
+ sd_add_dep (new_dep, false);
+ }
- /* If INSN has SCHED_GROUP_P set, then issue it and any other
- insns with SCHED_GROUP_P set first. */
- while (SCHED_GROUP_P (insn))
- {
- rtx prev = PREV_INSN (insn);
-
- /* Move a SCHED_GROUP_P insn. */
- move_insn1 (insn, last);
- /* If this is the first call to reemit_notes, then record
- its return value. */
- if (retval == NULL_RTX)
- retval = reemit_notes (insn, insn);
- else
- reemit_notes (insn, insn);
- insn = prev;
+ twin = XEXP (twins, 1);
+ free_INSN_LIST_node (twins);
+ twins = twin;
}
- /* Now move the first non SCHED_GROUP_P insn. */
- move_insn1 (insn, last);
+ calc_priorities (priorities_roots);
+ VEC_free (rtx, heap, priorities_roots);
+}
+
+/* Extends and fills with zeros (only the new part) array pointed to by P. */
+void *
+xrecalloc (void *p, size_t new_nmemb, size_t old_nmemb, size_t size)
+{
+ gcc_assert (new_nmemb >= old_nmemb);
+ p = XRESIZEVAR (void, p, new_nmemb * size);
+ memset (((char *) p) + old_nmemb * size, 0, (new_nmemb - old_nmemb) * size);
+ return p;
+}
+
+/* Helper function.
+ Find fallthru edge from PRED. */
+edge
+find_fallthru_edge (basic_block pred)
+{
+ edge e;
+ edge_iterator ei;
+ basic_block succ;
- /* If this is the first call to reemit_notes, then record
- its return value. */
- if (retval == NULL_RTX)
- retval = reemit_notes (insn, insn);
+ succ = pred->next_bb;
+ gcc_assert (succ->prev_bb == pred);
+
+ if (EDGE_COUNT (pred->succs) <= EDGE_COUNT (succ->preds))
+ {
+ FOR_EACH_EDGE (e, ei, pred->succs)
+ if (e->flags & EDGE_FALLTHRU)
+ {
+ gcc_assert (e->dest == succ);
+ return e;
+ }
+ }
else
- reemit_notes (insn, insn);
+ {
+ FOR_EACH_EDGE (e, ei, succ->preds)
+ if (e->flags & EDGE_FALLTHRU)
+ {
+ gcc_assert (e->src == pred);
+ return e;
+ }
+ }
- return retval;
+ return NULL;
}
-/* Return an insn which represents a SCHED_GROUP, which is
- the last insn in the group. */
-
-static rtx
-group_leader (insn)
- rtx insn;
+/* Extend per basic block data structures. */
+static void
+sched_extend_bb (void)
{
- rtx prev;
+ rtx insn;
- do
+ /* The following is done to keep current_sched_info->next_tail non null. */
+ insn = BB_END (EXIT_BLOCK_PTR->prev_bb);
+ if (NEXT_INSN (insn) == 0
+ || (!NOTE_P (insn)
+ && !LABEL_P (insn)
+ /* Don't emit a NOTE if it would end up before a BARRIER. */
+ && !BARRIER_P (NEXT_INSN (insn))))
{
- prev = insn;
- insn = next_nonnote_insn (insn);
+ rtx note = emit_note_after (NOTE_INSN_DELETED, insn);
+ /* Make insn appear outside BB. */
+ set_block_for_insn (note, NULL);
+ BB_END (EXIT_BLOCK_PTR->prev_bb) = insn;
}
- while (insn && SCHED_GROUP_P (insn) && (GET_CODE (insn) != CODE_LABEL));
-
- return prev;
}
-/* Use forward list scheduling to rearrange insns of block BB in region RGN,
- possibly bringing insns from subsequent blocks in the same region.
- Return number of insns scheduled. */
-
-static int
-schedule_block (bb, rgn_n_insns)
- int bb;
- int rgn_n_insns;
+/* Init per basic block data structures. */
+void
+sched_init_bbs (void)
{
- /* Local variables. */
- rtx insn, last;
- rtx *ready;
- int n_ready = 0;
- int can_issue_more;
-
- /* Flow block of this bb. */
- int b = BB_TO_BLOCK (bb);
-
- /* target_n_insns == number of insns in b before scheduling starts.
- sched_target_n_insns == how many of b's insns were scheduled.
- sched_n_insns == how many insns were scheduled in b. */
- int target_n_insns = 0;
- int sched_target_n_insns = 0;
- int sched_n_insns = 0;
-
-#define NEED_NOTHING 0
-#define NEED_HEAD 1
-#define NEED_TAIL 2
- int new_needs;
+ sched_extend_bb ();
+}
- /* Head/tail info for this block. */
- rtx prev_head;
- rtx next_tail;
- rtx head;
- rtx tail;
- int bb_src;
+/* Initialize BEFORE_RECOVERY variable. */
+static void
+init_before_recovery (basic_block *before_recovery_ptr)
+{
+ basic_block last;
+ edge e;
- /* We used to have code to avoid getting parameters moved from hard
- argument registers into pseudos.
+ last = EXIT_BLOCK_PTR->prev_bb;
+ e = find_fallthru_edge (last);
- However, it was removed when it proved to be of marginal benefit
- and caused problems because schedule_block and compute_forward_dependences
- had different notions of what the "head" insn was. */
- get_bb_head_tail (bb, &head, &tail);
-
- /* Interblock scheduling could have moved the original head insn from this
- block into a proceeding block. This may also cause schedule_block and
- compute_forward_dependences to have different notions of what the
- "head" insn was.
-
- If the interblock movement happened to make this block start with
- some notes (LOOP, EH or SETJMP) before the first real insn, then
- HEAD will have various special notes attached to it which must be
- removed so that we don't end up with extra copies of the notes. */
- if (GET_RTX_CLASS (GET_CODE (head)) == 'i')
+ if (e)
{
- rtx note;
-
- for (note = REG_NOTES (head); note; note = XEXP (note, 1))
- if (REG_NOTE_KIND (note) == REG_SAVE_NOTE)
- remove_note (head, note);
- }
-
- next_tail = NEXT_INSN (tail);
- prev_head = PREV_INSN (head);
-
- /* If the only insn left is a NOTE or a CODE_LABEL, then there is no need
- to schedule this block. */
- if (head == tail
- && (GET_RTX_CLASS (GET_CODE (head)) != 'i'))
- return (sched_n_insns);
+ /* We create two basic blocks:
+ 1. Single instruction block is inserted right after E->SRC
+ and has jump to
+ 2. Empty block right before EXIT_BLOCK.
+ Between these two blocks recovery blocks will be emitted. */
+
+ basic_block single, empty;
+ rtx x, label;
+
+ /* If the fallthrough edge to exit we've found is from the block we've
+ created before, don't do anything more. */
+ if (last == after_recovery)
+ return;
- /* Debug info. */
- if (sched_verbose)
- {
- fprintf (dump, ";; ======================================================\n");
- fprintf (dump,
- ";; -- basic block %d from %d to %d -- %s reload\n",
- b, INSN_UID (BLOCK_HEAD (b)), INSN_UID (BLOCK_END (b)),
- (reload_completed ? "after" : "before"));
- fprintf (dump, ";; ======================================================\n");
- fprintf (dump, "\n");
-
- visual_tbl = (char *) alloca (get_visual_tbl_length ());
- init_block_visualization ();
- }
+ adding_bb_to_current_region_p = false;
- /* Remove remaining note insns from the block, save them in
- note_list. These notes are restored at the end of
- schedule_block (). */
- note_list = 0;
- rm_other_notes (head, tail);
+ single = sched_create_empty_bb (last);
+ empty = sched_create_empty_bb (single);
- target_bb = bb;
+ /* Add new blocks to the root loop. */
+ if (current_loops != NULL)
+ {
+ add_bb_to_loop (single, VEC_index (loop_p, current_loops->larray, 0));
+ add_bb_to_loop (empty, VEC_index (loop_p, current_loops->larray, 0));
+ }
- /* Prepare current target block info. */
- if (current_nr_blocks > 1)
- {
- candidate_table = (candidate *) xmalloc (current_nr_blocks
- * sizeof (candidate));
-
- bblst_last = 0;
- /* ??? It is not clear why bblst_size is computed this way. The original
- number was clearly too small as it resulted in compiler failures.
- Multiplying by the original number by 2 (to account for update_bbs
- members) seems to be a reasonable solution. */
- /* ??? Or perhaps there is a bug somewhere else in this file? */
- bblst_size = (current_nr_blocks - bb) * rgn_nr_edges * 2;
- bblst_table = (int *) xmalloc (bblst_size * sizeof (int));
-
- bitlst_table_last = 0;
- bitlst_table_size = rgn_nr_edges;
- bitlst_table = (int *) xmalloc (rgn_nr_edges * sizeof (int));
-
- compute_trg_info (bb);
+ single->count = last->count;
+ empty->count = last->count;
+ single->frequency = last->frequency;
+ empty->frequency = last->frequency;
+ BB_COPY_PARTITION (single, last);
+ BB_COPY_PARTITION (empty, last);
+
+ redirect_edge_succ (e, single);
+ make_single_succ_edge (single, empty, 0);
+ make_single_succ_edge (empty, EXIT_BLOCK_PTR,
+ EDGE_FALLTHRU | EDGE_CAN_FALLTHRU);
+
+ label = block_label (empty);
+ x = emit_jump_insn_after (gen_jump (label), BB_END (single));
+ JUMP_LABEL (x) = label;
+ LABEL_NUSES (label)++;
+ haifa_init_insn (x);
+
+ emit_barrier_after (x);
+
+ sched_init_only_bb (empty, NULL);
+ sched_init_only_bb (single, NULL);
+ sched_extend_bb ();
+
+ adding_bb_to_current_region_p = true;
+ before_recovery = single;
+ after_recovery = empty;
+
+ if (before_recovery_ptr)
+ *before_recovery_ptr = before_recovery;
+
+ if (sched_verbose >= 2 && spec_info->dump)
+ fprintf (spec_info->dump,
+ ";;\t\tFixed fallthru to EXIT : %d->>%d->%d->>EXIT\n",
+ last->index, single->index, empty->index);
}
+ else
+ before_recovery = last;
+}
- clear_units ();
-
- /* Allocate the ready list. */
- ready = (rtx *) xmalloc ((rgn_n_insns + 1) * sizeof (rtx));
+/* Returns new recovery block. */
+basic_block
+sched_create_recovery_block (basic_block *before_recovery_ptr)
+{
+ rtx label;
+ rtx barrier;
+ basic_block rec;
- /* Print debugging information. */
- if (sched_verbose >= 5)
- debug_dependencies ();
+ haifa_recovery_bb_recently_added_p = true;
+ haifa_recovery_bb_ever_added_p = true;
+ init_before_recovery (before_recovery_ptr);
- /* Initialize ready list with all 'ready' insns in target block.
- Count number of insns in the target block being scheduled. */
- n_ready = 0;
- for (insn = head; insn != next_tail; insn = NEXT_INSN (insn))
- {
- rtx next;
+ barrier = get_last_bb_insn (before_recovery);
+ gcc_assert (BARRIER_P (barrier));
- if (GET_RTX_CLASS (GET_CODE (insn)) != 'i')
- continue;
- next = NEXT_INSN (insn);
+ label = emit_label_after (gen_label_rtx (), barrier);
- if (INSN_DEP_COUNT (insn) == 0
- && (SCHED_GROUP_P (next) == 0 || GET_RTX_CLASS (GET_CODE (next)) != 'i'))
- ready[n_ready++] = insn;
- if (!(SCHED_GROUP_P (insn)))
- target_n_insns++;
- }
+ rec = create_basic_block (label, label, before_recovery);
- /* Add to ready list all 'ready' insns in valid source blocks.
- For speculative insns, check-live, exception-free, and
- issue-delay. */
- for (bb_src = bb + 1; bb_src < current_nr_blocks; bb_src++)
- if (IS_VALID (bb_src))
- {
- rtx src_head;
- rtx src_next_tail;
- rtx tail, head;
+ /* A recovery block always ends with an unconditional jump. */
+ emit_barrier_after (BB_END (rec));
- get_bb_head_tail (bb_src, &head, &tail);
- src_next_tail = NEXT_INSN (tail);
- src_head = head;
+ if (BB_PARTITION (before_recovery) != BB_UNPARTITIONED)
+ BB_SET_PARTITION (rec, BB_COLD_PARTITION);
- if (head == tail
- && (GET_RTX_CLASS (GET_CODE (head)) != 'i'))
- continue;
+ if (sched_verbose && spec_info->dump)
+ fprintf (spec_info->dump, ";;\t\tGenerated recovery block rec%d\n",
+ rec->index);
- for (insn = src_head; insn != src_next_tail; insn = NEXT_INSN (insn))
- {
- if (GET_RTX_CLASS (GET_CODE (insn)) != 'i')
- continue;
+ return rec;
+}
- if (!CANT_MOVE (insn)
- && (!IS_SPECULATIVE_INSN (insn)
- || (insn_issue_delay (insn) <= 3
- && check_live (insn, bb_src)
- && is_exception_free (insn, bb_src, target_bb))))
- {
- rtx next;
-
- /* Note that we havn't squirrled away the notes for
- blocks other than the current. So if this is a
- speculative insn, NEXT might otherwise be a note. */
- next = next_nonnote_insn (insn);
- if (INSN_DEP_COUNT (insn) == 0
- && (! next
- || SCHED_GROUP_P (next) == 0
- || GET_RTX_CLASS (GET_CODE (next)) != 'i'))
- ready[n_ready++] = insn;
- }
- }
- }
+/* Create edges: FIRST_BB -> REC; FIRST_BB -> SECOND_BB; REC -> SECOND_BB
+ and emit necessary jumps. */
+void
+sched_create_recovery_edges (basic_block first_bb, basic_block rec,
+ basic_block second_bb)
+{
+ rtx label;
+ rtx jump;
+ int edge_flags;
+
+ /* This is fixing of incoming edge. */
+ /* ??? Which other flags should be specified? */
+ if (BB_PARTITION (first_bb) != BB_PARTITION (rec))
+ /* Partition type is the same, if it is "unpartitioned". */
+ edge_flags = EDGE_CROSSING;
+ else
+ edge_flags = 0;
-#ifdef MD_SCHED_INIT
- MD_SCHED_INIT (dump, sched_verbose);
-#endif
+ make_edge (first_bb, rec, edge_flags);
+ label = block_label (second_bb);
+ jump = emit_jump_insn_after (gen_jump (label), BB_END (rec));
+ JUMP_LABEL (jump) = label;
+ LABEL_NUSES (label)++;
- /* No insns scheduled in this block yet. */
- last_scheduled_insn = 0;
+ if (BB_PARTITION (second_bb) != BB_PARTITION (rec))
+ /* Partition type is the same, if it is "unpartitioned". */
+ {
+ /* Rewritten from cfgrtl.c. */
+ if (flag_reorder_blocks_and_partition
+ && targetm.have_named_sections)
+ {
+ /* We don't need the same note for the check because
+ any_condjump_p (check) == true. */
+ add_reg_note (jump, REG_CROSSING_JUMP, NULL_RTX);
+ }
+ edge_flags = EDGE_CROSSING;
+ }
+ else
+ edge_flags = 0;
- /* Q_SIZE is the total number of insns in the queue. */
- q_ptr = 0;
- q_size = 0;
- last_clock_var = 0;
- bzero ((char *) insn_queue, sizeof (insn_queue));
+ make_single_succ_edge (rec, second_bb, edge_flags);
+}
- /* Start just before the beginning of time. */
- clock_var = -1;
+/* This function creates recovery code for INSN. If MUTATE_P is nonzero,
+ INSN is a simple check, that should be converted to branchy one. */
+static void
+create_check_block_twin (rtx insn, bool mutate_p)
+{
+ basic_block rec;
+ rtx label, check, twin;
+ ds_t fs;
+ sd_iterator_def sd_it;
+ dep_t dep;
+ dep_def _new_dep, *new_dep = &_new_dep;
+ ds_t todo_spec;
+
+ gcc_assert (ORIG_PAT (insn) != NULL_RTX);
+
+ if (!mutate_p)
+ todo_spec = TODO_SPEC (insn);
+ else
+ {
+ gcc_assert (IS_SPECULATION_SIMPLE_CHECK_P (insn)
+ && (TODO_SPEC (insn) & SPECULATIVE) == 0);
- /* We start inserting insns after PREV_HEAD. */
- last = prev_head;
+ todo_spec = CHECK_SPEC (insn);
+ }
- /* Initialize INSN_QUEUE, LIST and NEW_NEEDS. */
- new_needs = (NEXT_INSN (prev_head) == BLOCK_HEAD (b)
- ? NEED_HEAD : NEED_NOTHING);
- if (PREV_INSN (next_tail) == BLOCK_END (b))
- new_needs |= NEED_TAIL;
+ todo_spec &= SPECULATIVE;
- /* Loop until all the insns in BB are scheduled. */
- while (sched_target_n_insns < target_n_insns)
+ /* Create recovery block. */
+ if (mutate_p || targetm.sched.needs_block_p (todo_spec))
{
- clock_var++;
+ rec = sched_create_recovery_block (NULL);
+ label = BB_HEAD (rec);
+ }
+ else
+ {
+ rec = EXIT_BLOCK_PTR;
+ label = NULL_RTX;
+ }
- /* Add to the ready list all pending insns that can be issued now.
- If there are no ready insns, increment clock until one
- is ready and add all pending insns at that point to the ready
- list. */
- n_ready = queue_to_ready (ready, n_ready);
+ /* Emit CHECK. */
+ check = targetm.sched.gen_spec_check (insn, label, todo_spec);
- if (n_ready == 0)
- abort ();
+ if (rec != EXIT_BLOCK_PTR)
+ {
+ /* To have mem_reg alive at the beginning of second_bb,
+ we emit check BEFORE insn, so insn after splitting
+ insn will be at the beginning of second_bb, which will
+ provide us with the correct life information. */
+ check = emit_jump_insn_before (check, insn);
+ JUMP_LABEL (check) = label;
+ LABEL_NUSES (label)++;
+ }
+ else
+ check = emit_insn_before (check, insn);
- if (sched_verbose >= 2)
- {
- fprintf (dump, ";;\t\tReady list after queue_to_ready: ");
- debug_ready_list (ready, n_ready);
- }
+ /* Extend data structures. */
+ haifa_init_insn (check);
- /* Sort the ready list based on priority. */
- SCHED_SORT (ready, n_ready);
+ /* CHECK is being added to current region. Extend ready list. */
+ gcc_assert (sched_ready_n_insns != -1);
+ sched_extend_ready_list (sched_ready_n_insns + 1);
- /* Allow the target to reorder the list, typically for
- better instruction bundling. */
-#ifdef MD_SCHED_REORDER
- MD_SCHED_REORDER (dump, sched_verbose, ready, n_ready, clock_var,
- can_issue_more);
-#else
- can_issue_more = issue_rate;
-#endif
+ if (current_sched_info->add_remove_insn)
+ current_sched_info->add_remove_insn (insn, 0);
- if (sched_verbose)
- {
- fprintf (dump, "\n;;\tReady list (t =%3d): ", clock_var);
- debug_ready_list (ready, n_ready);
- }
+ RECOVERY_BLOCK (check) = rec;
- /* Issue insns from ready list. */
- while (n_ready != 0 && can_issue_more)
- {
- /* Select and remove the insn from the ready list. */
- rtx insn = ready[--n_ready];
- int cost = actual_hazard (insn_unit (insn), insn, clock_var, 0);
+ if (sched_verbose && spec_info->dump)
+ fprintf (spec_info->dump, ";;\t\tGenerated check insn : %s\n",
+ (*current_sched_info->print_insn) (check, 0));
- if (cost >= 1)
- {
- queue_insn (insn, cost);
- continue;
- }
+ gcc_assert (ORIG_PAT (insn));
- /* An interblock motion? */
- if (INSN_BB (insn) != target_bb)
- {
- rtx temp;
- basic_block b1;
+ /* Initialize TWIN (twin is a duplicate of original instruction
+ in the recovery block). */
+ if (rec != EXIT_BLOCK_PTR)
+ {
+ sd_iterator_def sd_it;
+ dep_t dep;
- if (IS_SPECULATIVE_INSN (insn))
- {
- if (!check_live (insn, INSN_BB (insn)))
- continue;
- update_live (insn, INSN_BB (insn));
+ FOR_EACH_DEP (insn, SD_LIST_RES_BACK, sd_it, dep)
+ if ((DEP_STATUS (dep) & DEP_OUTPUT) != 0)
+ {
+ struct _dep _dep2, *dep2 = &_dep2;
- /* For speculative load, mark insns fed by it. */
- if (IS_LOAD_INSN (insn) || FED_BY_SPEC_LOAD (insn))
- set_spec_fed (insn);
+ init_dep (dep2, DEP_PRO (dep), check, REG_DEP_TRUE);
- nr_spec++;
- }
- nr_inter++;
+ sd_add_dep (dep2, true);
+ }
- /* Find the beginning of the scheduling group. */
- /* ??? Ought to update basic block here, but later bits of
- schedule_block assumes the original insn block is
- still intact. */
+ twin = emit_insn_after (ORIG_PAT (insn), BB_END (rec));
+ haifa_init_insn (twin);
- temp = insn;
- while (SCHED_GROUP_P (temp))
- temp = PREV_INSN (temp);
+ if (sched_verbose && spec_info->dump)
+ /* INSN_BB (insn) isn't determined for twin insns yet.
+ So we can't use current_sched_info->print_insn. */
+ fprintf (spec_info->dump, ";;\t\tGenerated twin insn : %d/rec%d\n",
+ INSN_UID (twin), rec->index);
+ }
+ else
+ {
+ ORIG_PAT (check) = ORIG_PAT (insn);
+ HAS_INTERNAL_DEP (check) = 1;
+ twin = check;
+ /* ??? We probably should change all OUTPUT dependencies to
+ (TRUE | OUTPUT). */
+ }
- /* Update source block boundaries. */
- b1 = BLOCK_FOR_INSN (temp);
- if (temp == b1->head && insn == b1->end)
- {
- /* We moved all the insns in the basic block.
- Emit a note after the last insn and update the
- begin/end boundaries to point to the note. */
- rtx note = emit_note_after (NOTE_INSN_DELETED, insn);
- b1->head = note;
- b1->end = note;
- }
- else if (insn == b1->end)
- {
- /* We took insns from the end of the basic block,
- so update the end of block boundary so that it
- points to the first insn we did not move. */
- b1->end = PREV_INSN (temp);
- }
- else if (temp == b1->head)
- {
- /* We took insns from the start of the basic block,
- so update the start of block boundary so that
- it points to the first insn we did not move. */
- b1->head = NEXT_INSN (insn);
- }
- }
- else
- {
- /* In block motion. */
- sched_target_n_insns++;
- }
+ /* Copy all resolved back dependencies of INSN to TWIN. This will
+ provide correct value for INSN_TICK (TWIN). */
+ sd_copy_back_deps (twin, insn, true);
- last_scheduled_insn = insn;
- last = move_insn (insn, last);
- sched_n_insns++;
+ if (rec != EXIT_BLOCK_PTR)
+ /* In case of branchy check, fix CFG. */
+ {
+ basic_block first_bb, second_bb;
+ rtx jump;
-#ifdef MD_SCHED_VARIABLE_ISSUE
- MD_SCHED_VARIABLE_ISSUE (dump, sched_verbose, insn,
- can_issue_more);
-#else
- can_issue_more--;
-#endif
+ first_bb = BLOCK_FOR_INSN (check);
+ second_bb = sched_split_block (first_bb, check);
- n_ready = schedule_insn (insn, ready, n_ready, clock_var);
+ sched_create_recovery_edges (first_bb, rec, second_bb);
- /* Close this block after scheduling its jump. */
- if (GET_CODE (last_scheduled_insn) == JUMP_INSN)
- break;
- }
+ sched_init_only_bb (second_bb, first_bb);
+ sched_init_only_bb (rec, EXIT_BLOCK_PTR);
- /* Debug info. */
- if (sched_verbose)
- visualize_scheduled_insns (b, clock_var);
+ jump = BB_END (rec);
+ haifa_init_insn (jump);
}
- /* Debug info. */
- if (sched_verbose)
+ /* Move backward dependences from INSN to CHECK and
+ move forward dependences from INSN to TWIN. */
+
+ /* First, create dependencies between INSN's producers and CHECK & TWIN. */
+ FOR_EACH_DEP (insn, SD_LIST_BACK, sd_it, dep)
{
- fprintf (dump, ";;\tReady list (final): ");
- debug_ready_list (ready, n_ready);
- print_block_visualization (b, "");
- }
+ rtx pro = DEP_PRO (dep);
+ ds_t ds;
- /* Sanity check -- queue must be empty now. Meaningless if region has
- multiple bbs. */
- if (current_nr_blocks > 1)
- if (!flag_schedule_interblock && q_size != 0)
- abort ();
+ /* If BEGIN_DATA: [insn ~~TRUE~~> producer]:
+ check --TRUE--> producer ??? or ANTI ???
+ twin --TRUE--> producer
+ twin --ANTI--> check
- /* Update head/tail boundaries. */
- head = NEXT_INSN (prev_head);
- tail = last;
+ If BEGIN_CONTROL: [insn ~~ANTI~~> producer]:
+ check --ANTI--> producer
+ twin --ANTI--> producer
+ twin --ANTI--> check
- /* Restore-other-notes: NOTE_LIST is the end of a chain of notes
- previously found among the insns. Insert them at the beginning
- of the insns. */
- if (note_list != 0)
- {
- rtx note_head = note_list;
+ If BE_IN_SPEC: [insn ~~TRUE~~> producer]:
+ check ~~TRUE~~> producer
+ twin ~~TRUE~~> producer
+ twin --ANTI--> check */
- while (PREV_INSN (note_head))
+ ds = DEP_STATUS (dep);
+
+ if (ds & BEGIN_SPEC)
{
- note_head = PREV_INSN (note_head);
+ gcc_assert (!mutate_p);
+ ds &= ~BEGIN_SPEC;
}
- PREV_INSN (note_head) = PREV_INSN (head);
- NEXT_INSN (PREV_INSN (head)) = note_head;
- PREV_INSN (head) = note_list;
- NEXT_INSN (note_list) = head;
- head = note_head;
- }
-
- /* Update target block boundaries. */
- if (new_needs & NEED_HEAD)
- BLOCK_HEAD (b) = head;
+ init_dep_1 (new_dep, pro, check, DEP_TYPE (dep), ds);
+ sd_add_dep (new_dep, false);
- if (new_needs & NEED_TAIL)
- BLOCK_END (b) = tail;
-
- /* Debugging. */
- if (sched_verbose)
- {
- fprintf (dump, ";; total time = %d\n;; new basic block head = %d\n",
- clock_var, INSN_UID (BLOCK_HEAD (b)));
- fprintf (dump, ";; new basic block end = %d\n\n",
- INSN_UID (BLOCK_END (b)));
+ if (rec != EXIT_BLOCK_PTR)
+ {
+ DEP_CON (new_dep) = twin;
+ sd_add_dep (new_dep, false);
+ }
}
- /* Clean up. */
- if (current_nr_blocks > 1)
+ /* Second, remove backward dependencies of INSN. */
+ for (sd_it = sd_iterator_start (insn, SD_LIST_SPEC_BACK);
+ sd_iterator_cond (&sd_it, &dep);)
{
- free (candidate_table);
- free (bblst_table);
- free (bitlst_table);
+ if ((DEP_STATUS (dep) & BEGIN_SPEC)
+ || mutate_p)
+ /* We can delete this dep because we overcome it with
+ BEGIN_SPECULATION. */
+ sd_delete_dep (sd_it);
+ else
+ sd_iterator_next (&sd_it);
}
- free (ready);
-
- return (sched_n_insns);
-} /* schedule_block () */
-\f
-
-/* Print the bit-set of registers, S, callable from debugger. */
-extern void
-debug_reg_vector (s)
- regset s;
-{
- int regno;
+ /* Future Speculations. Determine what BE_IN speculations will be like. */
+ fs = 0;
- EXECUTE_IF_SET_IN_REG_SET (s, 0, regno,
- {
- fprintf (dump, " %d", regno);
- });
+ /* Fields (DONE_SPEC (x) & BEGIN_SPEC) and CHECK_SPEC (x) are set only
+ here. */
- fprintf (dump, "\n");
-}
+ gcc_assert (!DONE_SPEC (insn));
-/* Use the backward dependences from LOG_LINKS to build
- forward dependences in INSN_DEPEND. */
+ if (!mutate_p)
+ {
+ ds_t ts = TODO_SPEC (insn);
+
+ DONE_SPEC (insn) = ts & BEGIN_SPEC;
+ CHECK_SPEC (check) = ts & BEGIN_SPEC;
+
+ /* Luckiness of future speculations solely depends upon initial
+ BEGIN speculation. */
+ if (ts & BEGIN_DATA)
+ fs = set_dep_weak (fs, BE_IN_DATA, get_dep_weak (ts, BEGIN_DATA));
+ if (ts & BEGIN_CONTROL)
+ fs = set_dep_weak (fs, BE_IN_CONTROL,
+ get_dep_weak (ts, BEGIN_CONTROL));
+ }
+ else
+ CHECK_SPEC (check) = CHECK_SPEC (insn);
-static void
-compute_block_forward_dependences (bb)
- int bb;
-{
- rtx insn, link;
- rtx tail, head;
- rtx next_tail;
- enum reg_note dep_type;
+ /* Future speculations: call the helper. */
+ process_insn_forw_deps_be_in_spec (insn, twin, fs);
- get_bb_head_tail (bb, &head, &tail);
- next_tail = NEXT_INSN (tail);
- for (insn = head; insn != next_tail; insn = NEXT_INSN (insn))
+ if (rec != EXIT_BLOCK_PTR)
{
- if (GET_RTX_CLASS (GET_CODE (insn)) != 'i')
- continue;
+ /* Which types of dependencies should we use here is,
+ generally, machine-dependent question... But, for now,
+ it is not. */
- insn = group_leader (insn);
+ if (!mutate_p)
+ {
+ init_dep (new_dep, insn, check, REG_DEP_TRUE);
+ sd_add_dep (new_dep, false);
- for (link = LOG_LINKS (insn); link; link = XEXP (link, 1))
+ init_dep (new_dep, insn, twin, REG_DEP_OUTPUT);
+ sd_add_dep (new_dep, false);
+ }
+ else
{
- rtx x = group_leader (XEXP (link, 0));
- rtx new_link;
+ if (spec_info->dump)
+ fprintf (spec_info->dump, ";;\t\tRemoved simple check : %s\n",
+ (*current_sched_info->print_insn) (insn, 0));
- if (x != XEXP (link, 0))
- continue;
+ /* Remove all dependencies of the INSN. */
+ {
+ sd_it = sd_iterator_start (insn, (SD_LIST_FORW
+ | SD_LIST_BACK
+ | SD_LIST_RES_BACK));
+ while (sd_iterator_cond (&sd_it, &dep))
+ sd_delete_dep (sd_it);
+ }
-#ifdef ENABLE_CHECKING
- /* If add_dependence is working properly there should never
- be notes, deleted insns or duplicates in the backward
- links. Thus we need not check for them here.
-
- However, if we have enabled checking we might as well go
- ahead and verify that add_dependence worked properly. */
- if (GET_CODE (x) == NOTE
- || INSN_DELETED_P (x)
- || find_insn_list (insn, INSN_DEPEND (x)))
- abort ();
-#endif
+ /* If former check (INSN) already was moved to the ready (or queue)
+ list, add new check (CHECK) there too. */
+ if (QUEUE_INDEX (insn) != QUEUE_NOWHERE)
+ try_ready (check);
- new_link = alloc_INSN_LIST (insn, INSN_DEPEND (x));
+ /* Remove old check from instruction stream and free its
+ data. */
+ sched_remove_insn (insn);
+ }
+
+ init_dep (new_dep, check, twin, REG_DEP_ANTI);
+ sd_add_dep (new_dep, false);
+ }
+ else
+ {
+ init_dep_1 (new_dep, insn, check, REG_DEP_TRUE, DEP_TRUE | DEP_OUTPUT);
+ sd_add_dep (new_dep, false);
+ }
- dep_type = REG_NOTE_KIND (link);
- PUT_REG_NOTE_KIND (new_link, dep_type);
+ if (!mutate_p)
+ /* Fix priorities. If MUTATE_P is nonzero, this is not necessary,
+ because it'll be done later in add_to_speculative_block. */
+ {
+ rtx_vec_t priorities_roots = NULL;
- INSN_DEPEND (x) = new_link;
- INSN_DEP_COUNT (insn) += 1;
- }
+ clear_priorities (twin, &priorities_roots);
+ calc_priorities (priorities_roots);
+ VEC_free (rtx, heap, priorities_roots);
}
}
-/* Initialize variables for region data dependence analysis.
- n_bbs is the number of region blocks. */
-
+/* Removes dependency between instructions in the recovery block REC
+ and usual region instructions. It keeps inner dependences so it
+ won't be necessary to recompute them. */
static void
-init_deps (deps)
- struct deps *deps;
+fix_recovery_deps (basic_block rec)
{
- int maxreg = max_reg_num ();
- deps->reg_last_uses = (rtx *) xcalloc (maxreg, sizeof (rtx));
- deps->reg_last_sets = (rtx *) xcalloc (maxreg, sizeof (rtx));
- deps->reg_last_clobbers = (rtx *) xcalloc (maxreg, sizeof (rtx));
-
- deps->pending_read_insns = 0;
- deps->pending_read_mems = 0;
- deps->pending_write_insns = 0;
- deps->pending_write_mems = 0;
- deps->pending_lists_length = 0;
- deps->last_pending_memory_flush = 0;
- deps->last_function_call = 0;
-
- deps->sched_before_next_call
- = gen_rtx_INSN (VOIDmode, 0, NULL_RTX, NULL_RTX,
- NULL_RTX, 0, NULL_RTX, NULL_RTX);
- LOG_LINKS (deps->sched_before_next_call) = 0;
-}
+ rtx note, insn, jump, ready_list = 0;
+ bitmap_head in_ready;
+ rtx link;
-/* Add dependences so that branches are scheduled to run last in their
- block. */
+ bitmap_initialize (&in_ready, 0);
-static void
-add_branch_dependences (head, tail)
- rtx head, tail;
-{
- rtx insn, last;
-
- /* For all branches, calls, uses, clobbers, and cc0 setters, force them
- to remain in order at the end of the block by adding dependencies and
- giving the last a high priority. There may be notes present, and
- prev_head may also be a note.
-
- Branches must obviously remain at the end. Calls should remain at the
- end since moving them results in worse register allocation. Uses remain
- at the end to ensure proper register allocation. cc0 setters remaim
- at the end because they can't be moved away from their cc0 user. */
- insn = tail;
- last = 0;
- while (GET_CODE (insn) == CALL_INSN
- || GET_CODE (insn) == JUMP_INSN
- || (GET_CODE (insn) == INSN
- && (GET_CODE (PATTERN (insn)) == USE
- || GET_CODE (PATTERN (insn)) == CLOBBER
-#ifdef HAVE_cc0
- || sets_cc0_p (PATTERN (insn))
-#endif
- ))
- || GET_CODE (insn) == NOTE)
+ /* NOTE - a basic block note. */
+ note = NEXT_INSN (BB_HEAD (rec));
+ gcc_assert (NOTE_INSN_BASIC_BLOCK_P (note));
+ insn = BB_END (rec);
+ gcc_assert (JUMP_P (insn));
+ insn = PREV_INSN (insn);
+
+ do
{
- if (GET_CODE (insn) != NOTE)
+ sd_iterator_def sd_it;
+ dep_t dep;
+
+ for (sd_it = sd_iterator_start (insn, SD_LIST_FORW);
+ sd_iterator_cond (&sd_it, &dep);)
{
- if (last != 0
- && !find_insn_list (insn, LOG_LINKS (last)))
- {
- add_dependence (last, insn, REG_DEP_ANTI);
- INSN_REF_COUNT (insn)++;
- }
+ rtx consumer = DEP_CON (dep);
- CANT_MOVE (insn) = 1;
+ if (BLOCK_FOR_INSN (consumer) != rec)
+ {
+ sd_delete_dep (sd_it);
- last = insn;
- /* Skip over insns that are part of a group.
- Make each insn explicitly depend on the previous insn.
- This ensures that only the group header will ever enter
- the ready queue (and, when scheduled, will automatically
- schedule the SCHED_GROUP_P block). */
- while (SCHED_GROUP_P (insn))
+ if (!bitmap_bit_p (&in_ready, INSN_LUID (consumer)))
+ {
+ ready_list = alloc_INSN_LIST (consumer, ready_list);
+ bitmap_set_bit (&in_ready, INSN_LUID (consumer));
+ }
+ }
+ else
{
- rtx temp = prev_nonnote_insn (insn);
- add_dependence (insn, temp, REG_DEP_ANTI);
- insn = temp;
+ gcc_assert ((DEP_STATUS (dep) & DEP_TYPES) == DEP_TRUE);
+
+ sd_iterator_next (&sd_it);
}
}
- /* Don't overrun the bounds of the basic block. */
- if (insn == head)
- break;
-
insn = PREV_INSN (insn);
}
+ while (insn != note);
- /* Make sure these insns are scheduled last in their block. */
- insn = last;
- if (insn != 0)
- while (insn != head)
- {
- insn = prev_nonnote_insn (insn);
+ bitmap_clear (&in_ready);
- if (INSN_REF_COUNT (insn) != 0)
- continue;
+ /* Try to add instructions to the ready or queue list. */
+ for (link = ready_list; link; link = XEXP (link, 1))
+ try_ready (XEXP (link, 0));
+ free_INSN_LIST_list (&ready_list);
- add_dependence (last, insn, REG_DEP_ANTI);
- INSN_REF_COUNT (insn) = 1;
+ /* Fixing jump's dependences. */
+ insn = BB_HEAD (rec);
+ jump = BB_END (rec);
- /* Skip over insns that are part of a group. */
- while (SCHED_GROUP_P (insn))
- insn = prev_nonnote_insn (insn);
- }
+ gcc_assert (LABEL_P (insn));
+ insn = NEXT_INSN (insn);
+
+ gcc_assert (NOTE_INSN_BASIC_BLOCK_P (insn));
+ add_jump_dependencies (insn, jump);
}
-/* After computing the dependencies for block BB, propagate the dependencies
- found in TMP_DEPS to the successors of the block. MAX_REG is the number
- of registers. */
-static void
-propagate_deps (bb, tmp_deps, max_reg)
- int bb;
- struct deps *tmp_deps;
- int max_reg;
+/* Change pattern of INSN to NEW_PAT. */
+void
+sched_change_pattern (rtx insn, rtx new_pat)
{
- int b = BB_TO_BLOCK (bb);
- int e, first_edge;
- int reg;
- rtx link_insn, link_mem;
- rtx u;
-
- /* These lists should point to the right place, for correct
- freeing later. */
- bb_deps[bb].pending_read_insns = tmp_deps->pending_read_insns;
- bb_deps[bb].pending_read_mems = tmp_deps->pending_read_mems;
- bb_deps[bb].pending_write_insns = tmp_deps->pending_write_insns;
- bb_deps[bb].pending_write_mems = tmp_deps->pending_write_mems;
-
- /* bb's structures are inherited by its successors. */
- first_edge = e = OUT_EDGES (b);
- if (e <= 0)
- return;
+ int t;
- do
- {
- rtx x;
- int b_succ = TO_BLOCK (e);
- int bb_succ = BLOCK_TO_BB (b_succ);
- struct deps *succ_deps = bb_deps + bb_succ;
+ t = validate_change (insn, &PATTERN (insn), new_pat, 0);
+ gcc_assert (t);
+ dfa_clear_single_insn_cache (insn);
+}
- /* Only bbs "below" bb, in the same region, are interesting. */
- if (CONTAINING_RGN (b) != CONTAINING_RGN (b_succ)
- || bb_succ <= bb)
- {
- e = NEXT_OUT (e);
- continue;
- }
+/* Change pattern of INSN to NEW_PAT. Invalidate cached haifa
+ instruction data. */
+static void
+haifa_change_pattern (rtx insn, rtx new_pat)
+{
+ sched_change_pattern (insn, new_pat);
- for (reg = 0; reg < max_reg; reg++)
- {
- /* reg-last-uses lists are inherited by bb_succ. */
- for (u = tmp_deps->reg_last_uses[reg]; u; u = XEXP (u, 1))
- {
- if (find_insn_list (XEXP (u, 0),
- succ_deps->reg_last_uses[reg]))
- continue;
+ /* Invalidate INSN_COST, so it'll be recalculated. */
+ INSN_COST (insn) = -1;
+ /* Invalidate INSN_TICK, so it'll be recalculated. */
+ INSN_TICK (insn) = INVALID_TICK;
+}
- succ_deps->reg_last_uses[reg]
- = alloc_INSN_LIST (XEXP (u, 0),
- succ_deps->reg_last_uses[reg]);
- }
+/* -1 - can't speculate,
+ 0 - for speculation with REQUEST mode it is OK to use
+ current instruction pattern,
+ 1 - need to change pattern for *NEW_PAT to be speculative. */
+int
+sched_speculate_insn (rtx insn, ds_t request, rtx *new_pat)
+{
+ gcc_assert (current_sched_info->flags & DO_SPECULATION
+ && (request & SPECULATIVE)
+ && sched_insn_is_legitimate_for_speculation_p (insn, request));
- /* reg-last-defs lists are inherited by bb_succ. */
- for (u = tmp_deps->reg_last_sets[reg]; u; u = XEXP (u, 1))
- {
- if (find_insn_list (XEXP (u, 0),
- succ_deps->reg_last_sets[reg]))
- continue;
+ if ((request & spec_info->mask) != request)
+ return -1;
- succ_deps->reg_last_sets[reg]
- = alloc_INSN_LIST (XEXP (u, 0),
- succ_deps->reg_last_sets[reg]);
- }
+ if (request & BE_IN_SPEC
+ && !(request & BEGIN_SPEC))
+ return 0;
- for (u = tmp_deps->reg_last_clobbers[reg]; u; u = XEXP (u, 1))
- {
- if (find_insn_list (XEXP (u, 0),
- succ_deps->reg_last_clobbers[reg]))
- continue;
+ return targetm.sched.speculate_insn (insn, request, new_pat);
+}
- succ_deps->reg_last_clobbers[reg]
- = alloc_INSN_LIST (XEXP (u, 0),
- succ_deps->reg_last_clobbers[reg]);
- }
- }
+static int
+haifa_speculate_insn (rtx insn, ds_t request, rtx *new_pat)
+{
+ gcc_assert (sched_deps_info->generate_spec_deps
+ && !IS_SPECULATION_CHECK_P (insn));
- /* Mem read/write lists are inherited by bb_succ. */
- link_insn = tmp_deps->pending_read_insns;
- link_mem = tmp_deps->pending_read_mems;
- while (link_insn)
- {
- if (!(find_insn_mem_list (XEXP (link_insn, 0),
- XEXP (link_mem, 0),
- succ_deps->pending_read_insns,
- succ_deps->pending_read_mems)))
- add_insn_mem_dependence (succ_deps, &succ_deps->pending_read_insns,
- &succ_deps->pending_read_mems,
- XEXP (link_insn, 0), XEXP (link_mem, 0));
- link_insn = XEXP (link_insn, 1);
- link_mem = XEXP (link_mem, 1);
- }
+ if (HAS_INTERNAL_DEP (insn)
+ || SCHED_GROUP_P (insn))
+ return -1;
- link_insn = tmp_deps->pending_write_insns;
- link_mem = tmp_deps->pending_write_mems;
- while (link_insn)
- {
- if (!(find_insn_mem_list (XEXP (link_insn, 0),
- XEXP (link_mem, 0),
- succ_deps->pending_write_insns,
- succ_deps->pending_write_mems)))
- add_insn_mem_dependence (succ_deps,
- &succ_deps->pending_write_insns,
- &succ_deps->pending_write_mems,
- XEXP (link_insn, 0), XEXP (link_mem, 0));
-
- link_insn = XEXP (link_insn, 1);
- link_mem = XEXP (link_mem, 1);
- }
+ return sched_speculate_insn (insn, request, new_pat);
+}
- /* last_function_call is inherited by bb_succ. */
- for (u = tmp_deps->last_function_call; u; u = XEXP (u, 1))
- {
- if (find_insn_list (XEXP (u, 0),
- succ_deps->last_function_call))
- continue;
+/* Print some information about block BB, which starts with HEAD and
+ ends with TAIL, before scheduling it.
+ I is zero, if scheduler is about to start with the fresh ebb. */
+static void
+dump_new_block_header (int i, basic_block bb, rtx head, rtx tail)
+{
+ if (!i)
+ fprintf (sched_dump,
+ ";; ======================================================\n");
+ else
+ fprintf (sched_dump,
+ ";; =====================ADVANCING TO=====================\n");
+ fprintf (sched_dump,
+ ";; -- basic block %d from %d to %d -- %s reload\n",
+ bb->index, INSN_UID (head), INSN_UID (tail),
+ (reload_completed ? "after" : "before"));
+ fprintf (sched_dump,
+ ";; ======================================================\n");
+ fprintf (sched_dump, "\n");
+}
+
+/* Unlink basic block notes and labels and saves them, so they
+ can be easily restored. We unlink basic block notes in EBB to
+ provide back-compatibility with the previous code, as target backends
+ assume, that there'll be only instructions between
+ current_sched_info->{head and tail}. We restore these notes as soon
+ as we can.
+ FIRST (LAST) is the first (last) basic block in the ebb.
+ NB: In usual case (FIRST == LAST) nothing is really done. */
+void
+unlink_bb_notes (basic_block first, basic_block last)
+{
+ /* We DON'T unlink basic block notes of the first block in the ebb. */
+ if (first == last)
+ return;
- succ_deps->last_function_call
- = alloc_INSN_LIST (XEXP (u, 0),
- succ_deps->last_function_call);
- }
+ bb_header = XNEWVEC (rtx, last_basic_block);
- /* last_pending_memory_flush is inherited by bb_succ. */
- for (u = tmp_deps->last_pending_memory_flush; u; u = XEXP (u, 1))
- {
- if (find_insn_list (XEXP (u, 0),
- succ_deps->last_pending_memory_flush))
- continue;
+ /* Make a sentinel. */
+ if (last->next_bb != EXIT_BLOCK_PTR)
+ bb_header[last->next_bb->index] = 0;
- succ_deps->last_pending_memory_flush
- = alloc_INSN_LIST (XEXP (u, 0),
- succ_deps->last_pending_memory_flush);
- }
+ first = first->next_bb;
+ do
+ {
+ rtx prev, label, note, next;
- /* sched_before_next_call is inherited by bb_succ. */
- x = LOG_LINKS (tmp_deps->sched_before_next_call);
- for (; x; x = XEXP (x, 1))
- add_dependence (succ_deps->sched_before_next_call,
- XEXP (x, 0), REG_DEP_ANTI);
+ label = BB_HEAD (last);
+ if (LABEL_P (label))
+ note = NEXT_INSN (label);
+ else
+ note = label;
+ gcc_assert (NOTE_INSN_BASIC_BLOCK_P (note));
- e = NEXT_OUT (e);
- }
- while (e != first_edge);
-}
+ prev = PREV_INSN (label);
+ next = NEXT_INSN (note);
+ gcc_assert (prev && next);
-/* Compute backward dependences inside bb. In a multiple blocks region:
- (1) a bb is analyzed after its predecessors, and (2) the lists in
- effect at the end of bb (after analyzing for bb) are inherited by
- bb's successrs.
+ NEXT_INSN (prev) = next;
+ PREV_INSN (next) = prev;
- Specifically for reg-reg data dependences, the block insns are
- scanned by sched_analyze () top-to-bottom. Two lists are
- maintained by sched_analyze (): reg_last_sets[] for register DEFs,
- and reg_last_uses[] for register USEs.
+ bb_header[last->index] = label;
- When analysis is completed for bb, we update for its successors:
- ; - DEFS[succ] = Union (DEFS [succ], DEFS [bb])
- ; - USES[succ] = Union (USES [succ], DEFS [bb])
+ if (last == first)
+ break;
- The mechanism for computing mem-mem data dependence is very
- similar, and the result is interblock dependences in the region. */
+ last = last->prev_bb;
+ }
+ while (1);
+}
+/* Restore basic block notes.
+ FIRST is the first basic block in the ebb. */
static void
-compute_block_backward_dependences (bb)
- int bb;
+restore_bb_notes (basic_block first)
{
- int i;
- rtx head, tail;
- int max_reg = max_reg_num ();
- struct deps tmp_deps;
+ if (!bb_header)
+ return;
- tmp_deps = bb_deps[bb];
+ /* We DON'T unlink basic block notes of the first block in the ebb. */
+ first = first->next_bb;
+ /* Remember: FIRST is actually a second basic block in the ebb. */
- /* Do the analysis for this block. */
- get_bb_head_tail (bb, &head, &tail);
- sched_analyze (&tmp_deps, head, tail);
- add_branch_dependences (head, tail);
+ while (first != EXIT_BLOCK_PTR
+ && bb_header[first->index])
+ {
+ rtx prev, label, note, next;
- if (current_nr_blocks > 1)
- propagate_deps (bb, &tmp_deps, max_reg);
+ label = bb_header[first->index];
+ prev = PREV_INSN (label);
+ next = NEXT_INSN (prev);
- /* Free up the INSN_LISTs.
+ if (LABEL_P (label))
+ note = NEXT_INSN (label);
+ else
+ note = label;
+ gcc_assert (NOTE_INSN_BASIC_BLOCK_P (note));
- Note this loop is executed max_reg * nr_regions times. It's first
- implementation accounted for over 90% of the calls to free_INSN_LIST_list.
- The list was empty for the vast majority of those calls. On the PA, not
- calling free_INSN_LIST_list in those cases improves -O2 compile times by
- 3-5% on average. */
- for (i = 0; i < max_reg; ++i)
- {
- if (tmp_deps.reg_last_clobbers[i])
- free_INSN_LIST_list (&tmp_deps.reg_last_clobbers[i]);
- if (tmp_deps.reg_last_sets[i])
- free_INSN_LIST_list (&tmp_deps.reg_last_sets[i]);
- if (tmp_deps.reg_last_uses[i])
- free_INSN_LIST_list (&tmp_deps.reg_last_uses[i]);
+ bb_header[first->index] = 0;
+
+ NEXT_INSN (prev) = label;
+ NEXT_INSN (note) = next;
+ PREV_INSN (next) = note;
+
+ first = first->next_bb;
}
- /* Assert that we won't need bb_reg_last_* for this block anymore. */
- free (bb_deps[bb].reg_last_uses);
- free (bb_deps[bb].reg_last_sets);
- free (bb_deps[bb].reg_last_clobbers);
- bb_deps[bb].reg_last_uses = 0;
- bb_deps[bb].reg_last_sets = 0;
- bb_deps[bb].reg_last_clobbers = 0;
+ free (bb_header);
+ bb_header = 0;
}
-/* Print dependences for debugging, callable from debugger. */
-
-void
-debug_dependencies ()
+/* Helper function.
+ Fix CFG after both in- and inter-block movement of
+ control_flow_insn_p JUMP. */
+static void
+fix_jump_move (rtx jump)
{
- int bb;
+ basic_block bb, jump_bb, jump_bb_next;
- fprintf (dump, ";; --------------- forward dependences: ------------ \n");
- for (bb = 0; bb < current_nr_blocks; bb++)
- {
- if (1)
- {
- rtx head, tail;
- rtx next_tail;
- rtx insn;
+ bb = BLOCK_FOR_INSN (PREV_INSN (jump));
+ jump_bb = BLOCK_FOR_INSN (jump);
+ jump_bb_next = jump_bb->next_bb;
- get_bb_head_tail (bb, &head, &tail);
- next_tail = NEXT_INSN (tail);
- fprintf (dump, "\n;; --- Region Dependences --- b %d bb %d \n",
- BB_TO_BLOCK (bb), bb);
+ gcc_assert (common_sched_info->sched_pass_id == SCHED_EBB_PASS
+ || IS_SPECULATION_BRANCHY_CHECK_P (jump));
- fprintf (dump, ";; %7s%6s%6s%6s%6s%6s%11s%6s\n",
- "insn", "code", "bb", "dep", "prio", "cost", "blockage", "units");
- fprintf (dump, ";; %7s%6s%6s%6s%6s%6s%11s%6s\n",
- "----", "----", "--", "---", "----", "----", "--------", "-----");
- for (insn = head; insn != next_tail; insn = NEXT_INSN (insn))
- {
- rtx link;
- int unit, range;
+ if (!NOTE_INSN_BASIC_BLOCK_P (BB_END (jump_bb_next)))
+ /* if jump_bb_next is not empty. */
+ BB_END (jump_bb) = BB_END (jump_bb_next);
- if (GET_RTX_CLASS (GET_CODE (insn)) != 'i')
- {
- int n;
- fprintf (dump, ";; %6d ", INSN_UID (insn));
- if (GET_CODE (insn) == NOTE)
- {
- n = NOTE_LINE_NUMBER (insn);
- if (n < 0)
- fprintf (dump, "%s\n", GET_NOTE_INSN_NAME (n));
- else
- fprintf (dump, "line %d, file %s\n", n,
- NOTE_SOURCE_FILE (insn));
- }
- else
- fprintf (dump, " {%s}\n", GET_RTX_NAME (GET_CODE (insn)));
- continue;
- }
+ if (BB_END (bb) != PREV_INSN (jump))
+ /* Then there are instruction after jump that should be placed
+ to jump_bb_next. */
+ BB_END (jump_bb_next) = BB_END (bb);
+ else
+ /* Otherwise jump_bb_next is empty. */
+ BB_END (jump_bb_next) = NEXT_INSN (BB_HEAD (jump_bb_next));
- unit = insn_unit (insn);
- range = (unit < 0
- || function_units[unit].blockage_range_function == 0) ? 0 :
- function_units[unit].blockage_range_function (insn);
- fprintf (dump,
- ";; %s%5d%6d%6d%6d%6d%6d %3d -%3d ",
- (SCHED_GROUP_P (insn) ? "+" : " "),
- INSN_UID (insn),
- INSN_CODE (insn),
- INSN_BB (insn),
- INSN_DEP_COUNT (insn),
- INSN_PRIORITY (insn),
- insn_cost (insn, 0, 0),
- (int) MIN_BLOCKAGE_COST (range),
- (int) MAX_BLOCKAGE_COST (range));
- insn_print_units (insn);
- fprintf (dump, "\t: ");
- for (link = INSN_DEPEND (insn); link; link = XEXP (link, 1))
- fprintf (dump, "%d ", INSN_UID (XEXP (link, 0)));
- fprintf (dump, "\n");
- }
- }
- }
- fprintf (dump, "\n");
-}
+ /* To make assertion in move_insn happy. */
+ BB_END (bb) = PREV_INSN (jump);
-/* Set_priorities: compute priority of each insn in the block. */
+ update_bb_for_insn (jump_bb_next);
+}
-static int
-set_priorities (bb)
- int bb;
+/* Fix CFG after interblock movement of control_flow_insn_p JUMP. */
+static void
+move_block_after_check (rtx jump)
{
- rtx insn;
- int n_insn;
+ basic_block bb, jump_bb, jump_bb_next;
+ VEC(edge,gc) *t;
- rtx tail;
- rtx prev_head;
- rtx head;
+ bb = BLOCK_FOR_INSN (PREV_INSN (jump));
+ jump_bb = BLOCK_FOR_INSN (jump);
+ jump_bb_next = jump_bb->next_bb;
- get_bb_head_tail (bb, &head, &tail);
- prev_head = PREV_INSN (head);
+ update_bb_for_insn (jump_bb);
- if (head == tail
- && (GET_RTX_CLASS (GET_CODE (head)) != 'i'))
- return 0;
+ gcc_assert (IS_SPECULATION_CHECK_P (jump)
+ || IS_SPECULATION_CHECK_P (BB_END (jump_bb_next)));
- n_insn = 0;
- for (insn = tail; insn != prev_head; insn = PREV_INSN (insn))
- {
+ unlink_block (jump_bb_next);
+ link_block (jump_bb_next, bb);
- if (GET_CODE (insn) == NOTE)
- continue;
+ t = bb->succs;
+ bb->succs = 0;
+ move_succs (&(jump_bb->succs), bb);
+ move_succs (&(jump_bb_next->succs), jump_bb);
+ move_succs (&t, jump_bb_next);
- if (!(SCHED_GROUP_P (insn)))
- n_insn++;
- (void) priority (insn);
- }
+ df_mark_solutions_dirty ();
- return n_insn;
+ common_sched_info->fix_recovery_cfg
+ (bb->index, jump_bb->index, jump_bb_next->index);
}
-/* Schedule a region. A region is either an inner loop, a loop-free
- subroutine, or a single basic block. Each bb in the region is
- scheduled after its flow predecessors. */
-
+/* Helper function for move_block_after_check.
+ This functions attaches edge vector pointed to by SUCCSP to
+ block TO. */
static void
-schedule_region (rgn)
- int rgn;
+move_succs (VEC(edge,gc) **succsp, basic_block to)
{
- int bb;
- int rgn_n_insns = 0;
- int sched_rgn_n_insns = 0;
+ edge e;
+ edge_iterator ei;
- /* Set variables for the current region. */
- current_nr_blocks = RGN_NR_BLOCKS (rgn);
- current_blocks = RGN_BLOCKS (rgn);
+ gcc_assert (to->succs == 0);
- reg_pending_sets = ALLOCA_REG_SET ();
- reg_pending_clobbers = ALLOCA_REG_SET ();
- reg_pending_sets_all = 0;
+ to->succs = *succsp;
- /* Initializations for region data dependence analyisis. */
- bb_deps = (struct deps *) xmalloc (sizeof (struct deps) * current_nr_blocks);
- for (bb = 0; bb < current_nr_blocks; bb++)
- init_deps (bb_deps + bb);
+ FOR_EACH_EDGE (e, ei, to->succs)
+ e->src = to;
- /* Compute LOG_LINKS. */
- for (bb = 0; bb < current_nr_blocks; bb++)
- compute_block_backward_dependences (bb);
+ *succsp = 0;
+}
- /* Compute INSN_DEPEND. */
- for (bb = current_nr_blocks - 1; bb >= 0; bb--)
- compute_block_forward_dependences (bb);
+/* Remove INSN from the instruction stream.
+ INSN should have any dependencies. */
+static void
+sched_remove_insn (rtx insn)
+{
+ sd_finish_insn (insn);
- /* Delete line notes and set priorities. */
- for (bb = 0; bb < current_nr_blocks; bb++)
- {
- if (write_symbols != NO_DEBUG)
- {
- save_line_notes (bb);
- rm_line_notes (bb);
- }
+ change_queue_index (insn, QUEUE_NOWHERE);
+ current_sched_info->add_remove_insn (insn, 1);
+ remove_insn (insn);
+}
- rgn_n_insns += set_priorities (bb);
- }
+/* Clear priorities of all instructions, that are forward dependent on INSN.
+ Store in vector pointed to by ROOTS_PTR insns on which priority () should
+ be invoked to initialize all cleared priorities. */
+static void
+clear_priorities (rtx insn, rtx_vec_t *roots_ptr)
+{
+ sd_iterator_def sd_it;
+ dep_t dep;
+ bool insn_is_root_p = true;
- /* Compute interblock info: probabilities, split-edges, dominators, etc. */
- if (current_nr_blocks > 1)
+ gcc_assert (QUEUE_INDEX (insn) != QUEUE_SCHEDULED);
+
+ FOR_EACH_DEP (insn, SD_LIST_BACK, sd_it, dep)
{
- int i;
-
- prob = (float *) xmalloc ((current_nr_blocks) * sizeof (float));
-
- bbset_size = current_nr_blocks / HOST_BITS_PER_WIDE_INT + 1;
- dom = (bbset *) xmalloc (current_nr_blocks * sizeof (bbset));
- for (i = 0; i < current_nr_blocks; i++)
- dom[i] = (bbset) xcalloc (bbset_size, sizeof (HOST_WIDE_INT));
-
- /* Edge to bit. */
- rgn_nr_edges = 0;
- edge_to_bit = (int *) xmalloc (nr_edges * sizeof (int));
- for (i = 1; i < nr_edges; i++)
- if (CONTAINING_RGN (FROM_BLOCK (i)) == rgn)
- EDGE_TO_BIT (i) = rgn_nr_edges++;
- rgn_edges = (int *) xmalloc (rgn_nr_edges * sizeof (int));
-
- rgn_nr_edges = 0;
- for (i = 1; i < nr_edges; i++)
- if (CONTAINING_RGN (FROM_BLOCK (i)) == (rgn))
- rgn_edges[rgn_nr_edges++] = i;
-
- /* Split edges. */
- edgeset_size = rgn_nr_edges / HOST_BITS_PER_WIDE_INT + 1;
- pot_split = (edgeset *) xmalloc (current_nr_blocks * sizeof (edgeset));
- ancestor_edges
- = (edgeset *) xmalloc (current_nr_blocks * sizeof (edgeset));
- for (i = 0; i < current_nr_blocks; i++)
+ rtx pro = DEP_PRO (dep);
+
+ if (INSN_PRIORITY_STATUS (pro) >= 0
+ && QUEUE_INDEX (insn) != QUEUE_SCHEDULED)
{
- pot_split[i] =
- (edgeset) xcalloc (edgeset_size, sizeof (HOST_WIDE_INT));
- ancestor_edges[i] =
- (edgeset) xcalloc (edgeset_size, sizeof (HOST_WIDE_INT));
- }
+ /* If DEP doesn't contribute to priority then INSN itself should
+ be added to priority roots. */
+ if (contributes_to_priority_p (dep))
+ insn_is_root_p = false;
- /* Compute probabilities, dominators, split_edges. */
- for (bb = 0; bb < current_nr_blocks; bb++)
- compute_dom_prob_ps (bb);
+ INSN_PRIORITY_STATUS (pro) = -1;
+ clear_priorities (pro, roots_ptr);
+ }
}
- /* Now we can schedule all blocks. */
- for (bb = 0; bb < current_nr_blocks; bb++)
- sched_rgn_n_insns += schedule_block (bb, rgn_n_insns);
-
- /* Sanity check: verify that all region insns were scheduled. */
- if (sched_rgn_n_insns != rgn_n_insns)
- abort ();
-
- /* Restore line notes. */
- if (write_symbols != NO_DEBUG)
- {
- for (bb = 0; bb < current_nr_blocks; bb++)
- restore_line_notes (bb);
- }
+ if (insn_is_root_p)
+ VEC_safe_push (rtx, heap, *roots_ptr, insn);
+}
- /* Done with this region. */
- free_pending_lists ();
+/* Recompute priorities of instructions, whose priorities might have been
+ changed. ROOTS is a vector of instructions whose priority computation will
+ trigger initialization of all cleared priorities. */
+static void
+calc_priorities (rtx_vec_t roots)
+{
+ int i;
+ rtx insn;
- FREE_REG_SET (reg_pending_sets);
- FREE_REG_SET (reg_pending_clobbers);
+ for (i = 0; VEC_iterate (rtx, roots, i, insn); i++)
+ priority (insn);
+}
- free (bb_deps);
- if (current_nr_blocks > 1)
+/* Add dependences between JUMP and other instructions in the recovery
+ block. INSN is the first insn the recovery block. */
+static void
+add_jump_dependencies (rtx insn, rtx jump)
+{
+ do
{
- int i;
+ insn = NEXT_INSN (insn);
+ if (insn == jump)
+ break;
- free (prob);
- for (i = 0; i < current_nr_blocks; ++i)
+ if (dep_list_size (insn) == 0)
{
- free (dom[i]);
- free (pot_split[i]);
- free (ancestor_edges[i]);
+ dep_def _new_dep, *new_dep = &_new_dep;
+
+ init_dep (new_dep, insn, jump, REG_DEP_ANTI);
+ sd_add_dep (new_dep, false);
}
- free (dom);
- free (edge_to_bit);
- free (rgn_edges);
- free (pot_split);
- free (ancestor_edges);
}
-}
+ while (1);
-/* The one entry point in this file. DUMP_FILE is the dump file for
- this pass. */
+ gcc_assert (!sd_lists_empty_p (jump, SD_LIST_BACK));
+}
-void
-schedule_insns (dump_file)
- FILE *dump_file;
+/* Return the NOTE_INSN_BASIC_BLOCK of BB. */
+rtx
+bb_note (basic_block bb)
{
- int *deaths_in_region;
- sbitmap blocks, large_region_blocks;
- int max_uid;
- int b;
- rtx insn;
- int rgn;
- int luid;
- int any_large_regions;
-
- /* Disable speculative loads in their presence if cc0 defined. */
-#ifdef HAVE_cc0
- flag_schedule_speculative_load = 0;
-#endif
+ rtx note;
- /* Taking care of this degenerate case makes the rest of
- this code simpler. */
- if (n_basic_blocks == 0)
- return;
-
- /* Set dump and sched_verbose for the desired debugging output. If no
- dump-file was specified, but -fsched-verbose-N (any N), print to stderr.
- For -fsched-verbose-N, N>=10, print everything to stderr. */
- sched_verbose = sched_verbose_param;
- if (sched_verbose_param == 0 && dump_file)
- sched_verbose = 1;
- dump = ((sched_verbose_param >= 10 || !dump_file) ? stderr : dump_file);
+ note = BB_HEAD (bb);
+ if (LABEL_P (note))
+ note = NEXT_INSN (note);
- nr_inter = 0;
- nr_spec = 0;
+ gcc_assert (NOTE_INSN_BASIC_BLOCK_P (note));
+ return note;
+}
- /* Initialize issue_rate. */
- issue_rate = ISSUE_RATE;
+#ifdef ENABLE_CHECKING
+/* Helper function for check_cfg.
+ Return nonzero, if edge vector pointed to by EL has edge with TYPE in
+ its flags. */
+static int
+has_edge_p (VEC(edge,gc) *el, int type)
+{
+ edge e;
+ edge_iterator ei;
- split_all_insns (1);
+ FOR_EACH_EDGE (e, ei, el)
+ if (e->flags & type)
+ return 1;
+ return 0;
+}
- /* We use LUID 0 for the fake insn (UID 0) which holds dependencies for
- pseudos which do not cross calls. */
- max_uid = get_max_uid () + 1;
+/* Search back, starting at INSN, for an insn that is not a
+ NOTE_INSN_VAR_LOCATION. Don't search beyond HEAD, and return it if
+ no such insn can be found. */
+static inline rtx
+prev_non_location_insn (rtx insn, rtx head)
+{
+ while (insn != head && NOTE_P (insn)
+ && NOTE_KIND (insn) == NOTE_INSN_VAR_LOCATION)
+ insn = PREV_INSN (insn);
- h_i_d = (struct haifa_insn_data *) xcalloc (max_uid, sizeof (*h_i_d));
+ return insn;
+}
- h_i_d[0].luid = 0;
- luid = 1;
- for (b = 0; b < n_basic_blocks; b++)
- for (insn = BLOCK_HEAD (b);; insn = NEXT_INSN (insn))
- {
- INSN_LUID (insn) = luid;
+/* Check few properties of CFG between HEAD and TAIL.
+ If HEAD (TAIL) is NULL check from the beginning (till the end) of the
+ instruction stream. */
+static void
+check_cfg (rtx head, rtx tail)
+{
+ rtx next_tail;
+ basic_block bb = 0;
+ int not_first = 0, not_last;
- /* Increment the next luid, unless this is a note. We don't
- really need separate IDs for notes and we don't want to
- schedule differently depending on whether or not there are
- line-number notes, i.e., depending on whether or not we're
- generating debugging information. */
- if (GET_CODE (insn) != NOTE)
- ++luid;
+ if (head == NULL)
+ head = get_insns ();
+ if (tail == NULL)
+ tail = get_last_insn ();
+ next_tail = NEXT_INSN (tail);
- if (insn == BLOCK_END (b))
- break;
- }
-
- /* ?!? We could save some memory by computing a per-region luid mapping
- which could reduce both the number of vectors in the cache and the size
- of each vector. Instead we just avoid the cache entirely unless the
- average number of instructions in a basic block is very high. See
- the comment before the declaration of true_dependency_cache for
- what we consider "very high". */
- if (luid / n_basic_blocks > 100 * 5)
+ do
{
- true_dependency_cache = sbitmap_vector_alloc (luid, luid);
- sbitmap_vector_zero (true_dependency_cache, luid);
- }
-
- nr_regions = 0;
- rgn_table = (region *) xmalloc ((n_basic_blocks) * sizeof (region));
- rgn_bb_table = (int *) xmalloc ((n_basic_blocks) * sizeof (int));
- block_to_bb = (int *) xmalloc ((n_basic_blocks) * sizeof (int));
- containing_rgn = (int *) xmalloc ((n_basic_blocks) * sizeof (int));
+ not_last = head != tail;
- blocks = sbitmap_alloc (n_basic_blocks);
- large_region_blocks = sbitmap_alloc (n_basic_blocks);
+ if (not_first)
+ gcc_assert (NEXT_INSN (PREV_INSN (head)) == head);
+ if (not_last)
+ gcc_assert (PREV_INSN (NEXT_INSN (head)) == head);
- compute_bb_for_insn (max_uid);
+ if (LABEL_P (head)
+ || (NOTE_INSN_BASIC_BLOCK_P (head)
+ && (!not_first
+ || (not_first && !LABEL_P (PREV_INSN (head))))))
+ {
+ gcc_assert (bb == 0);
+ bb = BLOCK_FOR_INSN (head);
+ if (bb != 0)
+ gcc_assert (BB_HEAD (bb) == head);
+ else
+ /* This is the case of jump table. See inside_basic_block_p (). */
+ gcc_assert (LABEL_P (head) && !inside_basic_block_p (head));
+ }
- /* Compute regions for scheduling. */
- if (reload_completed
- || n_basic_blocks == 1
- || !flag_schedule_interblock)
- {
- find_single_block_region ();
- }
- else
- {
- /* Verify that a 'good' control flow graph can be built. */
- if (is_cfg_nonregular ())
+ if (bb == 0)
{
- find_single_block_region ();
+ gcc_assert (!inside_basic_block_p (head));
+ head = NEXT_INSN (head);
}
else
{
- sbitmap *dom;
- struct edge_list *edge_list;
-
- dom = sbitmap_vector_alloc (n_basic_blocks, n_basic_blocks);
-
- /* The scheduler runs after flow; therefore, we can't blindly call
- back into find_basic_blocks since doing so could invalidate the
- info in global_live_at_start.
-
- Consider a block consisting entirely of dead stores; after life
- analysis it would be a block of NOTE_INSN_DELETED notes. If
- we call find_basic_blocks again, then the block would be removed
- entirely and invalidate our the register live information.
-
- We could (should?) recompute register live information. Doing
- so may even be beneficial. */
- edge_list = create_edge_list ();
-
- /* Compute the dominators and post dominators. We don't
- currently use post dominators, but we should for
- speculative motion analysis. */
- compute_flow_dominators (dom, NULL);
-
- /* build_control_flow will return nonzero if it detects unreachable
- blocks or any other irregularity with the cfg which prevents
- cross block scheduling. */
- if (build_control_flow (edge_list) != 0)
- find_single_block_region ();
- else
- find_rgns (edge_list, dom);
+ gcc_assert (inside_basic_block_p (head)
+ || NOTE_P (head));
+ gcc_assert (BLOCK_FOR_INSN (head) == bb);
- if (sched_verbose >= 3)
- debug_regions ();
+ if (LABEL_P (head))
+ {
+ head = NEXT_INSN (head);
+ gcc_assert (NOTE_INSN_BASIC_BLOCK_P (head));
+ }
+ else
+ {
+ if (control_flow_insn_p (head))
+ {
+ gcc_assert (prev_non_location_insn (BB_END (bb), head)
+ == head);
+
+ if (any_uncondjump_p (head))
+ gcc_assert (EDGE_COUNT (bb->succs) == 1
+ && BARRIER_P (NEXT_INSN (head)));
+ else if (any_condjump_p (head))
+ gcc_assert (/* Usual case. */
+ (EDGE_COUNT (bb->succs) > 1
+ && !BARRIER_P (NEXT_INSN (head)))
+ /* Or jump to the next instruction. */
+ || (EDGE_COUNT (bb->succs) == 1
+ && (BB_HEAD (EDGE_I (bb->succs, 0)->dest)
+ == JUMP_LABEL (head))));
+ }
+ if (BB_END (bb) == head)
+ {
+ if (EDGE_COUNT (bb->succs) > 1)
+ gcc_assert (control_flow_insn_p (prev_non_location_insn
+ (head, BB_HEAD (bb)))
+ || has_edge_p (bb->succs, EDGE_COMPLEX));
+ bb = 0;
+ }
- /* For now. This will move as more and more of haifa is converted
- to using the cfg code in flow.c. */
- free (dom);
+ head = NEXT_INSN (head);
+ }
}
+
+ not_first = 1;
}
+ while (head != next_tail);
- deaths_in_region = (int *) xmalloc (sizeof(int) * nr_regions);
+ gcc_assert (bb == 0);
+}
- init_alias_analysis ();
+#endif /* ENABLE_CHECKING */
+
+/* Extend per basic block data structures. */
+static void
+extend_bb (void)
+{
+ if (sched_scan_info->extend_bb)
+ sched_scan_info->extend_bb ();
+}
+
+/* Init data for BB. */
+static void
+init_bb (basic_block bb)
+{
+ if (sched_scan_info->init_bb)
+ sched_scan_info->init_bb (bb);
+}
+
+/* Extend per insn data structures. */
+static void
+extend_insn (void)
+{
+ if (sched_scan_info->extend_insn)
+ sched_scan_info->extend_insn ();
+}
+
+/* Init data structures for INSN. */
+static void
+init_insn (rtx insn)
+{
+ if (sched_scan_info->init_insn)
+ sched_scan_info->init_insn (insn);
+}
+
+/* Init all insns in BB. */
+static void
+init_insns_in_bb (basic_block bb)
+{
+ rtx insn;
+
+ FOR_BB_INSNS (bb, insn)
+ init_insn (insn);
+}
- if (write_symbols != NO_DEBUG)
+/* A driver function to add a set of basic blocks (BBS),
+ a single basic block (BB), a set of insns (INSNS) or a single insn (INSN)
+ to the scheduling region. */
+void
+sched_scan (const struct sched_scan_info_def *ssi,
+ bb_vec_t bbs, basic_block bb, insn_vec_t insns, rtx insn)
+{
+ sched_scan_info = ssi;
+
+ if (bbs != NULL || bb != NULL)
{
- rtx line;
+ extend_bb ();
- line_note_head = (rtx *) xcalloc (n_basic_blocks, sizeof (rtx));
+ if (bbs != NULL)
+ {
+ unsigned i;
+ basic_block x;
- /* Save-line-note-head:
- Determine the line-number at the start of each basic block.
- This must be computed and saved now, because after a basic block's
- predecessor has been scheduled, it is impossible to accurately
- determine the correct line number for the first insn of the block. */
+ for (i = 0; VEC_iterate (basic_block, bbs, i, x); i++)
+ init_bb (x);
+ }
- for (b = 0; b < n_basic_blocks; b++)
- for (line = BLOCK_HEAD (b); line; line = PREV_INSN (line))
- if (GET_CODE (line) == NOTE && NOTE_LINE_NUMBER (line) > 0)
- {
- line_note_head[b] = line;
- break;
- }
+ if (bb != NULL)
+ init_bb (bb);
}
- /* Find units used in this fuction, for visualization. */
- if (sched_verbose)
- init_target_units ();
-
- /* ??? Add a NOTE after the last insn of the last basic block. It is not
- known why this is done. */
+ extend_insn ();
- insn = BLOCK_END (n_basic_blocks - 1);
- if (NEXT_INSN (insn) == 0
- || (GET_CODE (insn) != NOTE
- && GET_CODE (insn) != CODE_LABEL
- /* Don't emit a NOTE if it would end up between an unconditional
- jump and a BARRIER. */
- && !(GET_CODE (insn) == JUMP_INSN
- && GET_CODE (NEXT_INSN (insn)) == BARRIER)))
- emit_note_after (NOTE_INSN_DELETED, BLOCK_END (n_basic_blocks - 1));
-
- /* Compute INSN_REG_WEIGHT for all blocks. We must do this before
- removing death notes. */
- for (b = n_basic_blocks - 1; b >= 0; b--)
- find_insn_reg_weight (b);
-
- /* Remove all death notes from the subroutine. */
- for (rgn = 0; rgn < nr_regions; rgn++)
+ if (bbs != NULL)
{
- sbitmap_zero (blocks);
- for (b = RGN_NR_BLOCKS (rgn) - 1; b >= 0; --b)
- SET_BIT (blocks, rgn_bb_table [RGN_BLOCKS (rgn) + b]);
+ unsigned i;
+ basic_block x;
- deaths_in_region[rgn] = count_or_remove_death_notes (blocks, 1);
+ for (i = 0; VEC_iterate (basic_block, bbs, i, x); i++)
+ init_insns_in_bb (x);
}
- /* Schedule every region in the subroutine. */
- for (rgn = 0; rgn < nr_regions; rgn++)
- schedule_region (rgn);
+ if (bb != NULL)
+ init_insns_in_bb (bb);
- /* Update life analysis for the subroutine. Do single block regions
- first so that we can verify that live_at_start didn't change. Then
- do all other blocks. */
- /* ??? There is an outside possibility that update_life_info, or more
- to the point propagate_block, could get called with non-zero flags
- more than once for one basic block. This would be kinda bad if it
- were to happen, since REG_INFO would be accumulated twice for the
- block, and we'd have twice the REG_DEAD notes.
+ if (insns != NULL)
+ {
+ unsigned i;
+ rtx x;
- I'm fairly certain that this _shouldn't_ happen, since I don't think
- that live_at_start should change at region heads. Not sure what the
- best way to test for this kind of thing... */
+ for (i = 0; VEC_iterate (rtx, insns, i, x); i++)
+ init_insn (x);
+ }
- allocate_reg_life_data ();
- compute_bb_for_insn (max_uid);
+ if (insn != NULL)
+ init_insn (insn);
+}
- any_large_regions = 0;
- sbitmap_ones (large_region_blocks);
- for (rgn = 0; rgn < nr_regions; rgn++)
- if (RGN_NR_BLOCKS (rgn) > 1)
- any_large_regions = 1;
- else
- {
- sbitmap_zero (blocks);
- SET_BIT (blocks, rgn_bb_table[RGN_BLOCKS (rgn)]);
- RESET_BIT (large_region_blocks, rgn_bb_table[RGN_BLOCKS (rgn)]);
+/* Extend data structures for logical insn UID. */
+static void
+luids_extend_insn (void)
+{
+ int new_luids_max_uid = get_max_uid () + 1;
- update_life_info (blocks, UPDATE_LIFE_LOCAL,
- PROP_DEATH_NOTES | PROP_REG_INFO);
+ VEC_safe_grow_cleared (int, heap, sched_luids, new_luids_max_uid);
+}
- /* In the single block case, the count of registers that died should
- not have changed during the schedule. */
- if (count_or_remove_death_notes (blocks, 0) != deaths_in_region[rgn])
- abort ();
- }
+/* Initialize LUID for INSN. */
+static void
+luids_init_insn (rtx insn)
+{
+ int i = INSN_P (insn) ? 1 : common_sched_info->luid_for_non_insn (insn);
+ int luid;
- if (any_large_regions)
+ if (i >= 0)
{
- update_life_info (large_region_blocks, UPDATE_LIFE_GLOBAL,
- PROP_DEATH_NOTES | PROP_REG_INFO);
+ luid = sched_max_luid;
+ sched_max_luid += i;
}
+ else
+ luid = -1;
- /* Reposition the prologue and epilogue notes in case we moved the
- prologue/epilogue insns. */
- if (reload_completed)
- reposition_prologue_and_epilogue_notes (get_insns ());
+ SET_INSN_LUID (insn, luid);
+}
+
+/* Initialize luids for BBS, BB, INSNS and INSN.
+ The hook common_sched_info->luid_for_non_insn () is used to determine
+ if notes, labels, etc. need luids. */
+void
+sched_init_luids (bb_vec_t bbs, basic_block bb, insn_vec_t insns, rtx insn)
+{
+ const struct sched_scan_info_def ssi =
+ {
+ NULL, /* extend_bb */
+ NULL, /* init_bb */
+ luids_extend_insn, /* extend_insn */
+ luids_init_insn /* init_insn */
+ };
- /* Delete redundant line notes. */
- if (write_symbols != NO_DEBUG)
- rm_redundant_line_notes ();
+ sched_scan (&ssi, bbs, bb, insns, insn);
+}
- if (sched_verbose)
+/* Free LUIDs. */
+void
+sched_finish_luids (void)
+{
+ VEC_free (int, heap, sched_luids);
+ sched_max_luid = 1;
+}
+
+/* Return logical uid of INSN. Helpful while debugging. */
+int
+insn_luid (rtx insn)
+{
+ return INSN_LUID (insn);
+}
+
+/* Extend per insn data in the target. */
+void
+sched_extend_target (void)
+{
+ if (targetm.sched.h_i_d_extended)
+ targetm.sched.h_i_d_extended ();
+}
+
+/* Extend global scheduler structures (those, that live across calls to
+ schedule_block) to include information about just emitted INSN. */
+static void
+extend_h_i_d (void)
+{
+ int reserve = (get_max_uid () + 1
+ - VEC_length (haifa_insn_data_def, h_i_d));
+ if (reserve > 0
+ && ! VEC_space (haifa_insn_data_def, h_i_d, reserve))
{
- if (reload_completed == 0 && flag_schedule_interblock)
- {
- fprintf (dump, "\n;; Procedure interblock/speculative motions == %d/%d \n",
- nr_inter, nr_spec);
- }
- else
- {
- if (nr_inter > 0)
- abort ();
- }
- fprintf (dump, "\n\n");
+ VEC_safe_grow_cleared (haifa_insn_data_def, heap, h_i_d,
+ 3 * get_max_uid () / 2);
+ sched_extend_target ();
}
+}
- /* Clean up. */
- end_alias_analysis ();
-
- if (true_dependency_cache)
+/* Initialize h_i_d entry of the INSN with default values.
+ Values, that are not explicitly initialized here, hold zero. */
+static void
+init_h_i_d (rtx insn)
+{
+ if (INSN_LUID (insn) > 0)
{
- free (true_dependency_cache);
- true_dependency_cache = NULL;
+ INSN_COST (insn) = -1;
+ QUEUE_INDEX (insn) = QUEUE_NOWHERE;
+ INSN_TICK (insn) = INVALID_TICK;
+ INTER_TICK (insn) = INVALID_TICK;
+ TODO_SPEC (insn) = HARD_DEP;
}
- free (rgn_table);
- free (rgn_bb_table);
- free (block_to_bb);
- free (containing_rgn);
+}
+
+/* Initialize haifa_insn_data for BBS, BB, INSNS and INSN. */
+void
+haifa_init_h_i_d (bb_vec_t bbs, basic_block bb, insn_vec_t insns, rtx insn)
+{
+ const struct sched_scan_info_def ssi =
+ {
+ NULL, /* extend_bb */
+ NULL, /* init_bb */
+ extend_h_i_d, /* extend_insn */
+ init_h_i_d /* init_insn */
+ };
- free (h_i_d);
+ sched_scan (&ssi, bbs, bb, insns, insn);
+}
- if (write_symbols != NO_DEBUG)
- free (line_note_head);
+/* Finalize haifa_insn_data. */
+void
+haifa_finish_h_i_d (void)
+{
+ int i;
+ haifa_insn_data_t data;
+ struct reg_use_data *use, *next;
- if (edge_table)
+ for (i = 0; VEC_iterate (haifa_insn_data_def, h_i_d, i, data); i++)
{
- free (edge_table);
- edge_table = NULL;
+ if (data->reg_pressure != NULL)
+ free (data->reg_pressure);
+ for (use = data->reg_use_list; use != NULL; use = next)
+ {
+ next = use->next_insn_use;
+ free (use);
+ }
}
+ VEC_free (haifa_insn_data_def, heap, h_i_d);
+}
- if (in_edges)
- {
- free (in_edges);
- in_edges = NULL;
- }
- if (out_edges)
+/* Init data for the new insn INSN. */
+static void
+haifa_init_insn (rtx insn)
+{
+ gcc_assert (insn != NULL);
+
+ sched_init_luids (NULL, NULL, NULL, insn);
+ sched_extend_target ();
+ sched_deps_init (false);
+ haifa_init_h_i_d (NULL, NULL, NULL, insn);
+
+ if (adding_bb_to_current_region_p)
{
- free (out_edges);
- out_edges = NULL;
+ sd_init_insn (insn);
+
+ /* Extend dependency caches by one element. */
+ extend_dependency_caches (1, false);
}
+}
- sbitmap_free (blocks);
- sbitmap_free (large_region_blocks);
+/* Init data for the new basic block BB which comes after AFTER. */
+static void
+haifa_init_only_bb (basic_block bb, basic_block after)
+{
+ gcc_assert (bb != NULL);
+
+ sched_init_bbs ();
+
+ if (common_sched_info->add_block)
+ /* This changes only data structures of the front-end. */
+ common_sched_info->add_block (bb, after);
+}
+
+/* A generic version of sched_split_block (). */
+basic_block
+sched_split_block_1 (basic_block first_bb, rtx after)
+{
+ edge e;
+
+ e = split_block (first_bb, after);
+ gcc_assert (e->src == first_bb);
- free (deaths_in_region);
+ /* sched_split_block emits note if *check == BB_END. Probably it
+ is better to rip that note off. */
+
+ return e->dest;
+}
+
+/* A generic version of sched_create_empty_bb (). */
+basic_block
+sched_create_empty_bb_1 (basic_block after)
+{
+ return create_empty_bb (after);
+}
+
+/* Insert PAT as an INSN into the schedule and update the necessary data
+ structures to account for it. */
+rtx
+sched_emit_insn (rtx pat)
+{
+ rtx insn = emit_insn_after (pat, last_scheduled_insn);
+ last_scheduled_insn = insn;
+ haifa_init_insn (insn);
+ return insn;
}
#endif /* INSN_SCHEDULING */
OSDN Git Service
