* Type Layout:: Defining sizes and properties of basic user data types.
* Registers:: Naming and describing the hardware registers.
* Register Classes:: Defining the classes of hardware registers.
+* Old Constraints:: The old way to define machine-specific constraints.
* Stack and Calling:: Defining which way the stack grows and by how much.
* Varargs:: Defining the varargs macros.
* Trampolines:: Code set up at run time to enter a nested function.
@option{-O}. That is what @code{OPTIMIZATION_OPTIONS} is for.
@end defmac
+@defmac C_COMMON_OVERRIDE_OPTIONS
+This is similar to @code{OVERRIDE_OPTIONS} but is only used in the C
+language frontends (C, Objective-C, C++, Objective-C++) and so can be
+used to alter option flag variables which only exist in those
+frontends.
+@end defmac
+
@defmac OPTIMIZATION_OPTIONS (@var{level}, @var{size})
Some machines may desire to change what optimizations are performed for
various optimization levels. This macro, if defined, is executed once
the alignment requirements of an unnamed bitfield's type.
@end deftypefn
+@deftypefn {Target Hook} bool TARGET_NARROW_VOLATILE_BITFIELDS (void)
+This target hook should return @code{true} if accesses to volatile bitfields
+should use the narrowest mode possible. It should return @code{false} if
+these accesses should use the bitfield container type.
+
+The default is @code{!TARGET_STRICT_ALIGN}.
+@end deftypefn
+
@defmac MEMBER_TYPE_FORCES_BLK (@var{field}, @var{mode})
Return 1 if a structure or array containing @var{field} should be accessed using
@code{BLKMODE}.
addresses have different requirements than other base register uses.
@end defmac
+@defmac MODE_CODE_BASE_REG_CLASS (@var{mode}, @var{outer_code}, @var{index_code})
+A C expression whose value is the register class to which a valid
+base register must belong. @var{outer_code} and @var{index_code} define the
+context in which the base register occurs. @var{outer_code} is the code of
+the immediately enclosing expression (@code{MEM} for the top level of an
+address, @code{ADDRESS} for something that occurs in an
+@code{address_operand}). @var{index_code} is the code of the corresponding
+index expression if @var{outer_code} is @code{PLUS}; @code{SCRATCH} otherwise.
+@end defmac
+
@defmac INDEX_REG_CLASS
A macro whose definition is the name of the class to which a valid
index register must belong. An index register is one used in an
added to another register (as well as added to a displacement).
@end defmac
-@defmac CONSTRAINT_LEN (@var{char}, @var{str})
-For the constraint at the start of @var{str}, which starts with the letter
-@var{c}, return the length. This allows you to have register class /
-constant / extra constraints that are longer than a single letter;
-you don't need to define this macro if you can do with single-letter
-constraints only. The definition of this macro should use
-DEFAULT_CONSTRAINT_LEN for all the characters that you don't want
-to handle specially.
-There are some sanity checks in genoutput.c that check the constraint lengths
-for the md file, so you can also use this macro to help you while you are
-transitioning from a byzantine single-letter-constraint scheme: when you
-return a negative length for a constraint you want to re-use, genoutput
-will complain about every instance where it is used in the md file.
-@end defmac
-
-@defmac REG_CLASS_FROM_LETTER (@var{char})
-A C expression which defines the machine-dependent operand constraint
-letters for register classes. If @var{char} is such a letter, the
-value should be the register class corresponding to it. Otherwise,
-the value should be @code{NO_REGS}. The register letter @samp{r},
-corresponding to class @code{GENERAL_REGS}, will not be passed
-to this macro; you do not need to handle it.
-@end defmac
-
-@defmac REG_CLASS_FROM_CONSTRAINT (@var{char}, @var{str})
-Like @code{REG_CLASS_FROM_LETTER}, but you also get the constraint string
-passed in @var{str}, so that you can use suffixes to distinguish between
-different variants.
-@end defmac
-
@defmac REGNO_OK_FOR_BASE_P (@var{num})
A C expression which is nonzero if register number @var{num} is
suitable for use as a base register in operand addresses. It may be
@var{mode}. You should define this macro if the mode of the memory
reference affects whether a register may be used as a base register. If
you define this macro, the compiler will use it instead of
-@code{REGNO_OK_FOR_BASE_P}.
+@code{REGNO_OK_FOR_BASE_P}. The mode may be @code{VOIDmode} for addresses
+that appear outside a @code{MEM}, i.e. as an @code{address_operand}.
+
@end defmac
@defmac REGNO_MODE_OK_FOR_REG_BASE_P (@var{num}, @var{mode})
pseudo register that has been allocated such a hard register. You should
define this macro if base plus index addresses have different requirements
than other base register uses.
+
+Use of this macro is deprecated; please use the more general
+@code{REGNO_MODE_CODE_OK_FOR_BASE_P}.
+@end defmac
+
+@defmac REGNO_MODE_CODE_OK_FOR_BASE_P (@var{num}, @var{mode}, @var{outer_code}, @var{index_code})
+A C expression that is just like @code{REGNO_MODE_OK_FOR_BASE_P}, except that
+that expression may examine the context in which the register appears in the
+memory reference. @var{outer_code} is the code of the immediately enclosing
+expression (@code{MEM} if at the top level of the address, @code{ADDRESS} for
+something that occurs in an @code{address_operand}). @var{index_code} is the
+code of the corresponding index expression if @var{outer_code} is @code{PLUS};
+@code{SCRATCH} otherwise. The mode may be @code{VOIDmode} for addresses
+that appear outside a @code{MEM}, i.e. as an @code{address_operand}.
@end defmac
@defmac REGNO_OK_FOR_INDEX_P (@var{num})
into any kind of register, code generation will be better if
@code{LEGITIMATE_CONSTANT_P} makes the constant illegitimate instead
of using @code{PREFERRED_RELOAD_CLASS}.
+
+If an insn has pseudos in it after register allocation, reload will go
+through the alternatives and call repeatedly @code{PREFERRED_RELOAD_CLASS}
+to find the best one. Returning @code{NO_REGS}, in this case, makes
+reload add a @code{!} in front of the constraint: the x86 back-end uses
+this feature to discourage usage of 387 registers when math is done in
+the SSE registers (and vice versa).
@end defmac
@defmac PREFERRED_OUTPUT_RELOAD_CLASS (@var{x}, @var{class})
Like @code{PREFERRED_RELOAD_CLASS}, but for output reloads instead of
input reloads. If you don't define this macro, the default is to use
@var{class}, unchanged.
+
+You can also use @code{PREFERRED_OUTPUT_RELOAD_CLASS} to discourage
+reload from using some alternatives, like @code{PREFERRED_RELOAD_CLASS}.
@end defmac
@defmac LIMIT_RELOAD_CLASS (@var{mode}, @var{class})
@end smallexample
@end defmac
-Three other special macros describe which operands fit which constraint
-letters.
+@node Old Constraints
+@section Obsolete Macros for Defining Constraints
+@cindex defining constraints, obsolete method
+@cindex constraints, defining, obsolete method
+
+Machine-specific constraints can be defined with these macros instead
+of the machine description constructs described in @ref{Define
+Constraints}. This mechanism is obsolete. New ports should not use
+it; old ports should convert to the new mechanism.
+
+@defmac CONSTRAINT_LEN (@var{char}, @var{str})
+For the constraint at the start of @var{str}, which starts with the letter
+@var{c}, return the length. This allows you to have register class /
+constant / extra constraints that are longer than a single letter;
+you don't need to define this macro if you can do with single-letter
+constraints only. The definition of this macro should use
+DEFAULT_CONSTRAINT_LEN for all the characters that you don't want
+to handle specially.
+There are some sanity checks in genoutput.c that check the constraint lengths
+for the md file, so you can also use this macro to help you while you are
+transitioning from a byzantine single-letter-constraint scheme: when you
+return a negative length for a constraint you want to re-use, genoutput
+will complain about every instance where it is used in the md file.
+@end defmac
+
+@defmac REG_CLASS_FROM_LETTER (@var{char})
+A C expression which defines the machine-dependent operand constraint
+letters for register classes. If @var{char} is such a letter, the
+value should be the register class corresponding to it. Otherwise,
+the value should be @code{NO_REGS}. The register letter @samp{r},
+corresponding to class @code{GENERAL_REGS}, will not be passed
+to this macro; you do not need to handle it.
+@end defmac
+
+@defmac REG_CLASS_FROM_CONSTRAINT (@var{char}, @var{str})
+Like @code{REG_CLASS_FROM_LETTER}, but you also get the constraint string
+passed in @var{str}, so that you can use suffixes to distinguish between
+different variants.
+@end defmac
@defmac CONST_OK_FOR_LETTER_P (@var{value}, @var{c})
A C expression that defines the machine-dependent operand constraint
should be defined.
@end defmac
+@defmac CFA_FRAME_BASE_OFFSET (@var{fundecl})
+If defined, a C expression whose value is an integer giving the offset
+in bytes from the canonical frame address (cfa) to the frame base used
+in DWARF 2 debug information. The default is zero. A different value
+may reduce the size of debug information on some ports.
+@end defmac
+
@node Exception Handling
@subsection Exception Handling Support
@cindex exception handling
is found by the called function is not the same place that the
caller put it. This can be due to register windows, or it could
be because the function prologue moves it to a different place.
-@var{incoming} is @code{true} when the location is needed in
-the context of the called function, and @code{false} in the context of
+@var{incoming} is @code{1} or @code{2} when the location is needed in
+the context of the called function, and @code{0} in the context of
the caller.
-If @var{incoming} is @code{true} and the address is to be found on the
-stack, return a @code{mem} which refers to the frame pointer.
+If @var{incoming} is nonzero and the address is to be found on the
+stack, return a @code{mem} which refers to the frame pointer. If
+@var{incoming} is @code{2}, the result is being used to fetch the
+structure value address at the beginning of a function. If you need
+to emit adjusting code, you should do it at this point.
@end deftypefn
@defmac PCC_STATIC_STRUCT_RETURN
Format}.
@end defmac
-@defmac REG_OK_FOR_BASE_P (@var{x})
-A C expression that is nonzero if @var{x} (assumed to be a @code{reg}
-RTX) is valid for use as a base register. For hard registers, it
-should always accept those which the hardware permits and reject the
-others. Whether the macro accepts or rejects pseudo registers must be
-controlled by @code{REG_OK_STRICT} as described above. This usually
-requires two variant definitions, of which @code{REG_OK_STRICT}
-controls the one actually used.
-@end defmac
-
-@defmac REG_MODE_OK_FOR_BASE_P (@var{x}, @var{mode})
-A C expression that is just like @code{REG_OK_FOR_BASE_P}, except that
-that expression may examine the mode of the memory reference in
-@var{mode}. You should define this macro if the mode of the memory
-reference affects whether a register may be used as a base register. If
-you define this macro, the compiler will use it instead of
-@code{REG_OK_FOR_BASE_P}.
-@end defmac
-
-@defmac REG_MODE_OK_FOR_REG_BASE_P (@var{x}, @var{mode})
-A C expression which is nonzero if @var{x} (assumed to be a @code{reg} RTX)
-is suitable for use as a base register in base plus index operand addresses,
-accessing memory in mode @var{mode}. It may be either a suitable hard
-register or a pseudo register that has been allocated such a hard register.
-You should define this macro if base plus index addresses have different
-requirements than other base register uses.
-@end defmac
-
-@defmac REG_OK_FOR_INDEX_P (@var{x})
-A C expression that is nonzero if @var{x} (assumed to be a @code{reg}
-RTX) is valid for use as an index register.
-
-The difference between an index register and a base register is that
-the index register may be scaled. If an address involves the sum of
-two registers, neither one of them scaled, then either one may be
-labeled the ``base'' and the other the ``index''; but whichever
-labeling is used must fit the machine's constraints of which registers
-may serve in each capacity. The compiler will try both labelings,
-looking for one that is valid, and will reload one or both registers
-only if neither labeling works.
-@end defmac
-
@defmac FIND_BASE_TERM (@var{x})
A C expression to determine the base term of address @var{x}.
This macro is used in only one place: `find_base_term' in alias.c.
@deftypefn {Target Hook} bool TARGET_USE_ANCHORS_FOR_SYMBOL_P (rtx @var{x})
Return true if GCC should attempt to use anchors to access @code{SYMBOL_REF}
-@var{x}. You can assume @samp{SYMBOL_REF_IN_BLOCK_P (@var{x})} and
+@var{x}. You can assume @samp{SYMBOL_REF_HAS_BLOCK_INFO_P (@var{x})} and
@samp{!SYMBOL_REF_ANCHOR_P (@var{x})}.
The default version is correct for most targets, but you might need to
@deftypefn {Target Hook} int TARGET_SCHED_ADJUST_PRIORITY (rtx @var{insn}, int @var{priority})
This hook adjusts the integer scheduling priority @var{priority} of
-@var{insn}. It should return the new priority. Reduce the priority to
-execute @var{insn} earlier, increase the priority to execute @var{insn}
+@var{insn}. It should return the new priority. Increase the priority to
+execute @var{insn} earlier, reduce the priority to execute @var{insn}
later. Do not define this hook if you do not need to adjust the
scheduling priorities of insns.
@end deftypefn
not in cases of "costly dependences", which this hooks allows to define.
@end deftypefn
+@deftypefn {Target Hook} int TARGET_SCHED_ADJUST_COST_2 (rtx @var{insn}, int @var{dep_type}, rtx @var{dep_insn}, int @var{cost})
+This hook is a modified version of @samp{TARGET_SCHED_ADJUST_COST}. Instead
+of passing dependence as a second parameter, it passes a type of that
+dependence. This is useful to calculate cost of dependence between insns
+not having the corresponding link. If @samp{TARGET_SCHED_ADJUST_COST_2} is
+defined it is used instead of @samp{TARGET_SCHED_ADJUST_COST}.
+@end deftypefn
+
+@deftypefn {Target Hook} void TARGET_SCHED_H_I_D_EXTENDED (void)
+This hook is called by the insn scheduler after emitting a new instruction to
+the instruction stream. The hook notifies a target backend to extend its
+per instruction data structures.
+@end deftypefn
+
+@deftypefn {Target Hook} int TARGET_SCHED_SPECULATE_INSN (rtx @var{insn}, int @var{request}, rtx *@var{new_pat})
+This hook is called by the insn scheduler when @var{insn} has only
+speculative dependencies and therefore can be scheduled speculatively.
+The hook is used to check if the pattern of @var{insn} has a speculative
+version and, in case of successful check, to generate that speculative
+pattern. The hook should return 1, if the instruction has a speculative form,
+or -1, if it doesn't. @var{request} describes the type of requested
+speculation. If the return value equals 1 then @var{new_pat} is assigned
+the generated speculative pattern.
+@end deftypefn
+
+@deftypefn {Target Hook} int TARGET_SCHED_NEEDS_BLOCK_P (rtx @var{insn})
+This hook is called by the insn scheduler during generation of recovery code
+for @var{insn}. It should return nonzero, if the corresponding check
+instruction should branch to recovery code, or zero otherwise.
+@end deftypefn
+
+@deftypefn {Target Hook} rtx TARGET_SCHED_GEN_CHECK (rtx @var{insn}, rtx @var{label}, int @var{mutate_p})
+This hook is called by the insn scheduler to generate a pattern for recovery
+check instruction. If @var{mutate_p} is zero, then @var{insn} is a
+speculative instruction for which the check should be generated.
+@var{label} is either a label of a basic block, where recovery code should
+be emitted, or a null pointer, when requested check doesn't branch to
+recovery code (a simple check). If @var{mutate_p} is nonzero, then
+a pattern for a branchy check corresponding to a simple check denoted by
+@var{insn} should be generated. In this case @var{label} can't be null.
+@end deftypefn
+
+@deftypefn {Target Hook} int TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD_SPEC (rtx @var{insn})
+This hook is used as a workaround for
+@samp{TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD} not being
+called on the first instruction of the ready list. The hook is used to
+discard speculative instruction that stand first in the ready list from
+being scheduled on the current cycle. For non-speculative instructions,
+the hook should always return nonzero. For example, in the ia64 backend
+the hook is used to cancel data speculative insns when the ALAT table
+is nearly full.
+@end deftypefn
+
+@deftypefn {Target Hook} void TARGET_SCHED_SET_SCHED_FLAGS (unsigned int *@var{flags}, spec_info_t @var{spec_info})
+This hook is used by the insn scheduler to find out what features should be
+enabled/used. @var{flags} initially may have either the SCHED_RGN or SCHED_EBB
+bit set. This denotes the scheduler pass for which the data should be
+provided. The target backend should modify @var{flags} by modifying
+the bits corresponding to the following features: USE_DEPS_LIST, USE_GLAT,
+DETACH_LIFE_INFO, and DO_SPECULATION. For the DO_SPECULATION feature
+an additional structure @var{spec_info} should be filled by the target.
+The structure describes speculation types that can be used in the scheduler.
+@end deftypefn
+
@node Sections
@section Dividing the Output into Sections (Texts, Data, @dots{})
@c the above section title is WAY too long. maybe cut the part between
This flag is true if the target supports @code{TARGET_ASM_NAMED_SECTION}.
@end deftypefn
+@anchor{TARGET_HAVE_SWITCHABLE_BSS_SECTIONS}
+@deftypefn {Target Hook} bool TARGET_HAVE_SWITCHABLE_BSS_SECTIONS
+This flag is true if we can create zeroed data by switching to a BSS
+section and then using @code{ASM_OUTPUT_SKIP} to allocate the space.
+This is true on most ELF targets.
+@end deftypefn
+
@deftypefn {Target Hook} {unsigned int} TARGET_SECTION_TYPE_FLAGS (tree @var{decl}, const char *@var{name}, int @var{reloc})
Choose a set of section attributes for use by @code{TARGET_ASM_NAMED_SECTION}
based on a variable or function decl, a section name, and whether or not the
before and after that, output the additional assembler syntax for defining
the name, and a newline.
-This macro controls how the assembler definitions of uninitialized global
-variables are output. This macro exists to properly support languages like
-C++ which do not have @code{common} data. However, this macro currently
-is not defined for all targets. If this macro and
-@code{ASM_OUTPUT_ALIGNED_BSS} are not defined then @code{ASM_OUTPUT_COMMON}
-or @code{ASM_OUTPUT_ALIGNED_COMMON} or
-@code{ASM_OUTPUT_ALIGNED_DECL_COMMON} is used.
+There are two ways of handling global BSS. One is to define either
+this macro or its aligned counterpart, @code{ASM_OUTPUT_ALIGNED_BSS}.
+The other is to have @code{TARGET_ASM_SELECT_SECTION} return a
+switchable BSS section (@pxref{TARGET_HAVE_SWITCHABLE_BSS_SECTIONS}).
+You do not need to do both.
+
+Some languages do not have @code{common} data, and require a
+non-common form of global BSS in order to handle uninitialized globals
+efficiently. C++ is one example of this. However, if the target does
+not support global BSS, the front end may choose to make globals
+common in order to save space in the object file.
@end defmac
@defmac ASM_OUTPUT_ALIGNED_BSS (@var{stream}, @var{decl}, @var{name}, @var{size}, @var{alignment})
@defmac ASM_OUTPUT_DWARF_DELTA (@var{stream}, @var{size}, @var{label1}, @var{label2})
A C statement to issue assembly directives that create a difference
-between the two given labels, using an integer of the given size.
+@var{lab1} minus @var{lab2}, using an integer of the given @var{size}.
@end defmac
-@defmac ASM_OUTPUT_DWARF_OFFSET (@var{stream}, @var{size}, @var{label})
+@defmac ASM_OUTPUT_DWARF_OFFSET (@var{stream}, @var{size}, @var{label}, @var{section})
A C statement to issue assembly directives that create a
-section-relative reference to the given label, using an integer of the
-given size.
+section-relative reference to the given @var{label}, using an integer of the
+given @var{size}. The label is known to be defined in the given @var{section}.
@end defmac
@defmac ASM_OUTPUT_DWARF_PCREL (@var{stream}, @var{size}, @var{label})
A C statement to issue assembly directives that create a self-relative
-reference to the given label, using an integer of the given size.
+reference to the given @var{label}, using an integer of the given @var{size}.
@end defmac
@deftypefn {Target Hook} void TARGET_ASM_OUTPUT_DWARF_DTPREL (FILE *@var{FILE}, int @var{size}, rtx @var{x})
such cases may improve things.
@end defmac
+@deftypefn {Target Hook} int TARGET_MODE_REP_EXTENDED (enum machine_mode @var{mode}, enum machine_mode @var{rep_mode})
+The representation of an intergral mode can be such that the values
+are always extended to a wider integral mode. Return
+@code{SIGN_EXTEND} if values of @var{mode} are represented in
+sign-extended form to @var{rep_mode}. Return @code{UNKNOWN}
+otherwise. (Currently, none of the targets use zero-extended
+representation this way so unlike @code{LOAD_EXTEND_OP},
+@code{TARGET_MODE_REP_EXTENDED} is expected to return either
+@code{SIGN_EXTEND} or @code{UNKNOWN}. Also no target extends
+@var{mode} to @var{mode_rep} so that @var{mode_rep} is not the next
+widest integral mode and currently we take advantage of this fact.)
+
+Similarly to @code{LOAD_EXTEND_OP} you may return a non-@code{UNKNOWN}
+value even if the extension is not performed on certain hard registers
+as long as for the @code{REGNO_REG_CLASS} of these hard registers
+@code{CANNOT_CHANGE_MODE_CLASS} returns nonzero.
+
+Note that @code{TARGET_MODE_REP_EXTENDED} and @code{LOAD_EXTEND_OP}
+describe two related properties. If you define
+@code{TARGET_MODE_REP_EXTENDED (mode, word_mode)} you probably also want
+to define @code{LOAD_EXTEND_OP (mode)} to return the same type of
+extension.
+
+In order to enforce the representation of @code{mode},
+@code{TRULY_NOOP_TRUNCATION} should return false when truncating to
+@code{mode}.
+@end deftypefn
+
@defmac STORE_FLAG_VALUE
A C expression describing the value returned by a comparison operator
with an integral mode and stored by a store-flag instruction
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