-@c Copyright (C) 1988, 1989, 1992, 1993, 1994, 1996, 1998, 2000, 2001
+@c Copyright (C) 1988, 1989, 1992, 1993, 1994, 1996, 1998, 1999, 2000, 2001, 2002
@c Free Software Foundation, Inc.
@c This is part of the GCC manual.
@c For copying conditions, see the file gcc.texi.
* Expander Definitions::Generating a sequence of several RTL insns
for a standard operation.
* Insn Splitting:: Splitting Instructions into Multiple Instructions.
+* Including Patterns:: Including Patterns in Machine Descriptions.
* Peephole Definitions::Defining machine-specific peephole optimizations.
* Insn Attributes:: Specifying the value of attributes for generated insns.
* Conditional Execution::Generating @code{define_insn} patterns for
insn list. If a @code{define_expand} is used, one of three things
happens, based on the condition logic. The condition logic may manually
create new insns for the insn list, say via @code{emit_insn()}, and
-invoke DONE. For certain named patterns, it may invoke FAIL to tell the
+invoke @code{DONE}. For certain named patterns, it may invoke @code{FAIL} to tell the
compiler to use an alternate way of performing that task. If it invokes
neither @code{DONE} nor @code{FAIL}, the template given in the pattern
is inserted, as if the @code{define_expand} were a @code{define_insn}.
(match_operand:SI 0 "general_operand" "rm"))]
""
"*
-@{ if (TARGET_68020 || ! ADDRESS_REG_P (operands[0]))
+@{
+ if (TARGET_68020 || ! ADDRESS_REG_P (operands[0]))
return \"tstl %0\";
- return \"cmpl #0,%0\"; @}")
+ return \"cmpl #0,%0\";
+@}")
+@end example
+
+@noindent
+This can also be written using braced strings:
+
+@example
+(define_insn "tstsi"
+ [(set (cc0)
+ (match_operand:SI 0 "general_operand" "rm"))]
+ ""
+@{
+ if (TARGET_68020 || ! ADDRESS_REG_P (operands[0]))
+ return "tstl %0";
+ return "cmpl #0,%0";
+@})
@end example
This is an instruction that sets the condition codes based on the value of
For an operand that must be a register, @var{predicate} should be
@code{"register_operand"}. Using @code{"general_operand"} would be
valid, since the reload pass would copy any non-register operands
-through registers, but this would make GNU CC do extra work, it would
+through registers, but this would make GCC do extra work, it would
prevent invariant operands (such as constant) from being removed from
loops, and it would prevent the register allocator from doing the best
possible job. On RISC machines, it is usually most efficient to allow
deciding whether the expression to be matched ``has'' that mode.
When constructing an insn, argument 3 of the gen-function will specify
-the operation (i.e. the expression code) for the expression to be
+the operation (i.e.@: the expression code) for the expression to be
made. It should be an RTL expression, whose expression code is copied
into a new expression whose operands are arguments 1 and 2 of the
gen-function. The subexpressions of argument 3 are not used;
@emph{and} the function @var{predicate} returns nonzero on the
@code{parallel} that is the body of the insn. It is the responsibility
of the predicate to validate elements of the @code{parallel} beyond
-those listed in the @code{match_parallel}.@refill
+those listed in the @code{match_parallel}.
A typical use of @code{match_parallel} is to match load and store
multiple expressions, which can contain a variable number of elements
in a @code{parallel}. For example,
-@c the following is *still* going over. need to change the code.
-@c also need to work on grouping of this example. --mew 1feb93
@smallexample
(define_insn ""
@end smallexample
This example comes from @file{a29k.md}. The function
-@code{load_multiple_operations} is defined in @file{a29k.c} and checks
+@code{load_multiple_operation} is defined in @file{a29k.c} and checks
that subsequent elements in the @code{parallel} are the same as the
@code{set} in the pattern, except that they are referencing subsequent
registers and memory locations.
require doublequote characters to delimit them. To include these
doublequote characters in the string, prefix each one with @samp{\}.
+If the output control string is written as a brace block instead of a
+double-quoted string, it is automatically assumed to be C code. In that
+case, it is not necessary to put in a leading asterisk, or to escape the
+doublequotes surrounding C string literals.
+
The operands may be found in the array @code{operands}, whose C data type
is @code{rtx []}.
[(set (match_operand:SI 0 "general_operand" "=r,m")
(const_int 0))]
""
- "*
+ @{
return (which_alternative == 0
- ? \"clrreg %0\" : \"clrmem %0\");
- ")
+ ? "clrreg %0" : "clrmem %0");
+ @})
@end smallexample
The example above, where the assembler code to generate was
@end ifset
@c Most of this node appears by itself (in a different place) even
-@c when the INTERNALS flag is clear. Passages that require the full
-@c manual's context are conditionalized to appear only in the full manual.
+@c when the INTERNALS flag is clear. Passages that require the internals
+@c manual's context are conditionalized to appear only in the internals manual.
@ifset INTERNALS
@node Constraints
@section Operand Constraints
digit is used together with letters within the same alternative, the
digit should come last.
+This number is allowed to be more than a single digit. If multiple
+digits are encountered consecutavely, they are interpreted as a single
+decimal integer. There is scant chance for ambiguity, since to-date
+it has never been desirable that @samp{10} be interpreted as matching
+either operand 1 @emph{or} operand 0. Should this be desired, one
+can use multiple alternatives instead.
+
@cindex matching constraint
@cindex constraint, matching
This is called a @dfn{matching constraint} and what it really means is
use as an input occurs before the early result is written. Adding
alternatives of this form often allows GCC to produce better code
when only some of the inputs can be affected by the earlyclobber.
-See, for example, the @samp{mulsi3} insn of the ARM.
+See, for example, the @samp{mulsi3} insn of the ARM@.
@samp{&} does not obviate the need to write @samp{=}.
ignored as a constraint. They are significant only for choosing
register preferences.
-@ifset INTERNALS
@cindex @samp{*} in constraint
@item *
Says that the following character should be ignored when choosing
register preferences. @samp{*} has no effect on the meaning of the
constraint as a constraint, and no effect on reloading.
+@ifset INTERNALS
Here is an example: the 68000 has an instruction to sign-extend a
halfword in a data register, and can also sign-extend a value by
copying it into an address register. While either kind of register is
@samp{I}, usually the letter indicating the most common
immediate-constant format.
-For each machine architecture, the @file{config/@var{machine}.h} file
-defines additional constraints. These constraints are used by the
-compiler itself for instruction generation, as well as for @code{asm}
-statements; therefore, some of the constraints are not particularly
-interesting for @code{asm}. The constraints are defined through these
-macros:
+For each machine architecture, the
+@file{config/@var{machine}/@var{machine}.h} file defines additional
+constraints. These constraints are used by the compiler itself for
+instruction generation, as well as for @code{asm} statements; therefore,
+some of the constraints are not particularly interesting for @code{asm}.
+The constraints are defined through these macros:
@table @code
@item REG_CLASS_FROM_LETTER
Constant in range 0 to 255 (for @code{out} instruction)
@item Z
-Constant in range 0 to 0xffffffff or symbolic reference known to fit specified range.
+Constant in range 0 to @code{0xffffffff} or symbolic reference known to fit specified range.
(for using immediates in zero extending 32-bit to 64-bit x86-64 instructions)
@item e
Symbolic address
@end table
+
+@item S/390 and zSeries---@file{s390.h}
+@table @code
+@item a
+Address register (general purpose register except r0)
+
+@item d
+Data register (arbitrary general purpose register)
+
+@item f
+Floating-point register
+
+@item I
+Unsigned 8-bit constant (0--255)
+
+@item J
+Unsigned 12-bit constant (0--4095)
+
+@item K
+Signed 16-bit constant (@minus{}32768--32767)
+
+@item L
+Unsigned 16-bit constant (0--65535)
+
+@item Q
+Memory reference without index register
+
+@item S
+Symbolic constant suitable for use with the @code{larl} instruction
+
+@end table
+
+@item Xstormy16---@file{stormy16.h}
+@table @code
+@item a
+Register r0.
+
+@item b
+Register r1.
+
+@item c
+Register r2.
+
+@item d
+Register r8.
+
+@item e
+Registers r0 through r7.
+
+@item t
+Registers r0 and r1.
+
+@item y
+The carry register.
+
+@item z
+Registers r8 and r9.
+
+@item I
+A constant between 0 and 3 inclusive.
+
+@item J
+A constant that has exactly one bit set.
+
+@item K
+A constant that has exactly one bit clear.
+
+@item L
+A constant between 0 and 255 inclusive.
+
+@item M
+A constant between @minus{}255 and 0 inclusive.
+
+@item N
+A constant between @minus{}3 and 0 inclusive.
+
+@item O
+A constant between 1 and 4 inclusive.
+
+@item P
+A constant between @minus{}4 and @minus{}1 inclusive.
+
+@item Q
+A memory reference that is a stack push.
+
+@item R
+A memory reference that is a stack pop.
+
+@item S
+A memory reference that refers to an constant address of known value.
+
+@item T
+The register indicated by Rx (not implemented yet).
+
+@item U
+A constant that is not between 2 and 15 inclusive.
+
+@end table
+
+@item Xtensa---@file{xtensa.h}
+@table @code
+@item a
+General-purpose 32-bit register
+
+@item b
+One-bit boolean register
+
+@item A
+MAC16 40-bit accumulator register
+
+@item I
+Signed 12-bit integer constant, for use in MOVI instructions
+
+@item J
+Signed 8-bit integer constant, for use in ADDI instructions
+
+@item K
+Integer constant valid for BccI instructions
+
+@item L
+Unsigned constant valid for BccUI instructions
+
+@end table
+
@end table
@ifset INTERNALS
If operand 0 is a @code{subreg} with mode @var{m} of a register whose
own mode is wider than @var{m}, the effect of this instruction is
to store the specified value in the part of the register that corresponds
-to mode @var{m}. The effect on the rest of the register is undefined.
+to mode @var{m}. Bits outside of @var{m}, but which are within the
+same target word as the @code{subreg} are undefined. Bits which are
+outside the target word are left unchanged.
This class of patterns is special in several ways. First of all, each
of these names up to and including full word size @emph{must} be defined,
If a scratch register is required to move an object to or from memory,
it can be allocated using @code{gen_reg_rtx} prior to life analysis.
-If there are cases needing
-scratch registers after reload, you must define
-@code{SECONDARY_INPUT_RELOAD_CLASS} and perhaps also
+If there are cases which need scratch registers during or after reload,
+you must define @code{SECONDARY_INPUT_RELOAD_CLASS} and/or
@code{SECONDARY_OUTPUT_RELOAD_CLASS} to detect them, and provide
patterns @samp{reload_in@var{m}} or @samp{reload_out@var{m}} to handle
them. @xref{Register Classes}.
register. See the discussion of the @code{SECONDARY_RELOAD_CLASS}
macro in @pxref{Register Classes}.
+There are special restrictions on the form of the @code{match_operand}s
+used in these patterns. First, only the predicate for the reload
+operand is examined, i.e., @code{reload_in} examines operand 1, but not
+the predicates for operand 0 or 2. Second, there may be only one
+alternative in the constraints. Third, only a single register class
+letter may be used for the constraint; subsequent constraint letters
+are ignored. As a special exception, an empty constraint string
+matches the @code{ALL_REGS} register class. This may relieve ports
+of the burden of defining an @code{ALL_REGS} constraint letter just
+for these patterns.
+
@cindex @code{movstrict@var{m}} instruction pattern
@item @samp{movstrict@var{m}}
Like @samp{mov@var{m}} except that if operand 0 is a @code{subreg}
consecutive memory locations, operand 1 is the first register, and
operand 2 is a constant: the number of consecutive registers.
+@cindex @code{push@var{m}} instruction pattern
+@item @samp{push@var{m}}
+Output an push instruction. Operand 0 is value to push. Used only when
+@code{PUSH_ROUNDING} is defined. For historical reason, this pattern may be
+missing and in such case an @code{mov} expander is used instead, with a
+@code{MEM} expression forming the push operation. The @code{mov} expander
+method is deprecated.
+
@cindex @code{add@var{m}3} instruction pattern
@item @samp{add@var{m}3}
Add operand 2 and operand 1, storing the result in operand 0. All operands
@cindex @code{call_value_pop} instruction pattern
@item @samp{call_pop}, @samp{call_value_pop}
Similar to @samp{call} and @samp{call_value}, except used if defined and
-if @code{RETURN_POPS_ARGS} is non-zero. They should emit a @code{parallel}
+if @code{RETURN_POPS_ARGS} is nonzero. They should emit a @code{parallel}
that contains both the function call and a @code{set} to indicate the
adjustment made to the frame pointer.
-For machines where @code{RETURN_POPS_ARGS} can be non-zero, the use of these
+For machines where @code{RETURN_POPS_ARGS} can be nonzero, the use of these
patterns increases the number of functions for which the frame pointer
can be eliminated, if desired.
@code{__builtin_apply} on machines where special instructions are needed
to call a subroutine with arbitrary arguments or to save the value
returned. This instruction pattern is required on machines that have
-multiple registers that can hold a return value (i.e.
-@code{FUNCTION_VALUE_REGNO_P} is true for more than one register).
+multiple registers that can hold a return value
+(i.e.@: @code{FUNCTION_VALUE_REGNO_P} is true for more than one register).
@cindex @code{return} instruction pattern
@item @samp{return}
@findex reload_completed
@findex leaf_function_p
For such machines, the condition specified in this pattern should only
-be true when @code{reload_completed} is non-zero and the function's
+be true when @code{reload_completed} is nonzero and the function's
epilogue would only be a single instruction. For machines with register
windows, the routine @code{leaf_function_p} may be used to determine if
a register window push is required.
@cindex @code{decrement_and_branch_until_zero} instruction pattern
@item @samp{decrement_and_branch_until_zero}
Conditional branch instruction that decrements a register and
-jumps if the register is non-zero. Operand 0 is the register to
+jumps if the register is nonzero. Operand 0 is the register to
decrement and test; operand 1 is the label to jump to if the
-register is non-zero. @xref{Looping Patterns}.
+register is nonzero. @xref{Looping Patterns}.
This optional instruction pattern is only used by the combiner,
typically for loops reversed by the loop optimizer when strength
@cindex @code{doloop_end} instruction pattern
@item @samp{doloop_end}
Conditional branch instruction that decrements a register and jumps if
-the register is non-zero. This instruction takes five operands: Operand
+the register is nonzero. This instruction takes five operands: Operand
0 is the register to decrement and test; operand 1 is the number of loop
iterations as a @code{const_int} or @code{const0_rtx} if this cannot be
determined until run-time; operand 2 is the actual or estimated maximum
number of iterations as a @code{const_int}; operand 3 is the number of
enclosed loops as a @code{const_int} (an innermost loop has a value of
-1); operand 4 is the label to jump to if the register is non-zero.
+1); operand 4 is the label to jump to if the register is nonzero.
@xref{Looping Patterns}.
This optional instruction pattern should be defined for machines with
@cindex @code{doloop_begin} instruction pattern
@item @samp{doloop_begin}
Companion instruction to @code{doloop_end} required for machines that
-need to perform some initialisation, such as loading special registers
-used by a low-overhead looping instruction. If initialisation insns do
+need to perform some initialization, such as loading special registers
+used by a low-overhead looping instruction. If initialization insns do
not always need to be emitted, use a @code{define_expand}
(@pxref{Expander Definitions}) and make it fail.
and the last is the address of the label, to be placed in the
location for the incoming static chain.
-On most machines you need not define this pattern, since GNU CC will
+On most machines you need not define this pattern, since GCC will
already generate the correct code, which is to load the frame pointer
and static chain, restore the stack (using the
@samp{restore_stack_nonlocal} pattern, if defined), and jump indirectly
@cindex @code{nonlocal_goto_receiver} instruction pattern
@item @samp{nonlocal_goto_receiver}
This pattern, if defined, contains code needed at the target of a
-nonlocal goto after the code already generated by GNU CC. You will not
+nonlocal goto after the code already generated by GCC@. You will not
normally need to define this pattern. A typical reason why you might
need this pattern is if some value, such as a pointer to a global table,
must be restored when the frame pointer is restored. Note that a nonlocal
pattern to some special register or memory location.
This pattern only needs to be defined if call frame exception handling
-is to be used, and simple moves to @code{EH_RETURN_STACKADJ_RTX} and
-@code{EH_RETURN_HANDLER_RTX} are not sufficient.
+is to be used, and simple moves involving @code{EH_RETURN_STACKADJ_RTX}
+and @code{EH_RETURN_HANDLER_RTX} are not sufficient.
@cindex @code{prologue} instruction pattern
+@anchor{prologue instruction pattern}
@item @samp{prologue}
This pattern, if defined, emits RTL for entry to a function. The function
entry is responsible for setting up the stack frame, initializing the frame
pointer register, saving callee saved registers, etc.
Using a prologue pattern is generally preferred over defining
-@code{FUNCTION_PROLOGUE} to emit assembly code for the prologue.
+@code{TARGET_ASM_FUNCTION_PROLOGUE} to emit assembly code for the prologue.
The @code{prologue} pattern is particularly useful for targets which perform
instruction scheduling.
@cindex @code{epilogue} instruction pattern
+@anchor{epilogue instruction pattern}
@item @samp{epilogue}
-This pattern, if defined, emits RTL for exit from a function. The function
+This pattern emits RTL for exit from a function. The function
exit is responsible for deallocating the stack frame, restoring callee saved
registers and emitting the return instruction.
Using an epilogue pattern is generally preferred over defining
-@code{FUNCTION_EPILOGUE} to emit assembly code for the prologue.
+@code{TARGET_ASM_FUNCTION_EPILOGUE} to emit assembly code for the epilogue.
The @code{epilogue} pattern is particularly useful for targets which perform
instruction scheduling or which have delay slots for their return instruction.
"@dots{}")
@end smallexample
+@cindex @code{prefetch} instruction pattern
+@item @samp{prefetch}
+
+This pattern, if defined, emits code for a non-faulting data prefetch
+instruction. Operand 0 is the address of the memory to prefetch. Operand 1
+is a constant 1 if the prefetch is preparing for a write to the memory
+address, or a constant 0 otherwise. Operand 2 is the expected degree of
+temporal locality of the data and is a value between 0 and 3, inclusive; 0
+means that the data has no temporal locality, so it need not be left in the
+cache after the access; 3 means that the data has a high degree of temporal
+locality and should be left in all levels of cache possible; 1 and 2 mean,
+respectively, a low or moderate degree of temporal locality.
+
+Targets that do not support write prefetches or locality hints can ignore
+the values of operands 1 and 2.
+
@cindex @code{cycle_display} instruction pattern
@item @samp{cycle_display}
@cindex jump instruction patterns
@cindex defining jump instruction patterns
-For most machines, GNU CC assumes that the machine has a condition code.
+For most machines, GCC assumes that the machine has a condition code.
A comparison insn sets the condition code, recording the results of both
signed and unsigned comparison of the given operands. A separate branch
insn tests the condition code and branches or not according its value.
The branch insns come in distinct signed and unsigned flavors. Many
-common machines, such as the Vax, the 68000 and the 32000, work this
+common machines, such as the VAX, the 68000 and the 32000, work this
way.
Some machines have distinct signed and unsigned compare instructions, and
otherwise output a signed compare. When the branch itself is output, you
can treat signed and unsigned branches identically.
-The reason you can do this is that GNU CC always generates a pair of
+The reason you can do this is that GCC always generates a pair of
consecutive RTL insns, possibly separated by @code{note} insns, one to
set the condition code and one to test it, and keeps the pair inviolate
until the end.
@samp{dbra}-like instruction and avoids pipeline stalls associated with
the jump.
-GNU CC has three special named patterns to support low overhead looping,
-@samp{decrement_and_branch_until_zero}, @samp{doloop_begin}, and
-@samp{doloop_end}. The first pattern,
+GCC has three special named patterns to support low overhead looping.
+They are @samp{decrement_and_branch_until_zero}, @samp{doloop_begin},
+and @samp{doloop_end}. The first pattern,
@samp{decrement_and_branch_until_zero}, is not emitted during RTL
generation but may be emitted during the instruction combination phase.
This requires the assistance of the loop optimizer, using information
@end smallexample
The other two special looping patterns, @samp{doloop_begin} and
-@samp{doloop_end}, are emitted by the loop optimiser for certain
+@samp{doloop_end}, are emitted by the loop optimizer for certain
well-behaved loops with a finite number of loop iterations using
information collected during strength reduction.
The @samp{doloop_end} pattern describes the actual looping instruction
(or the implicit looping operation) and the @samp{doloop_begin} pattern
-is an optional companion pattern that can be used for initialisation
+is an optional companion pattern that can be used for initialization
needed for some low-overhead looping instructions.
Note that some machines require the actual looping instruction to be
@item
The only possible RTL expressions involving both bitwise exclusive-or
and bitwise negation are @code{(xor:@var{m} @var{x} @var{y})}
-and @code{(not:@var{m} (xor:@var{m} @var{x} @var{y}))}.@refill
+and @code{(not:@var{m} (xor:@var{m} @var{x} @var{y}))}.
@item
The sum of three items, one of which is a constant, will only appear in
@item
On machines that do not use @code{cc0},
@code{(compare @var{x} (const_int 0))} will be converted to
-@var{x}.@refill
+@var{x}.
@cindex @code{zero_extract}, canonicalization of
@cindex @code{sign_extract}, canonicalization of
On some target machines, some standard pattern names for RTL generation
cannot be handled with single insn, but a sequence of RTL insns can
represent them. For these target machines, you can write a
-@code{define_expand} to specify how to generate the sequence of RTL.
+@code{define_expand} to specify how to generate the sequence of RTL@.
@findex define_expand
A @code{define_expand} is an RTL expression that looks almost like a
@item
The condition, a string containing a C expression. This expression is
used to express how the availability of this pattern depends on
-subclasses of target machine, selected by command-line options when GNU
-CC is run. This is just like the condition of a @code{define_insn} that
+subclasses of target machine, selected by command-line options when GCC
+is run. This is just like the condition of a @code{define_insn} that
has a standard name. Therefore, the condition (if present) may not
depend on the data in the insn being matched, but only the
target-machine-type flags. The compiler needs to test these conditions
A true operand, which needs to be specified in order to generate RTL from
the pattern, should be described with a @code{match_operand} in its first
occurrence in the RTL template. This enters information on the operand's
-predicate into the tables that record such things. GNU CC uses the
+predicate into the tables that record such things. GCC uses the
information to preload the operand into a register if that is required for
valid RTL code. If the operand is referred to more than once, subsequent
references should use @code{match_dup}.
@code{jump_insn} or @code{call_insn}. If you don't need a real insn
at the end, emit an insn to copy the result of the operation into
itself. Such an insn will generate no code, but it can avoid problems
-in the compiler.@refill
+in the compiler.
@node Insn Splitting
@section Defining How to Split Instructions
circumstances. If an insn needs to be split for delay slot scheduling
or insn scheduling, the insn is already known to be valid, which means
that it must have been matched by some @code{define_insn} and, if
-@code{reload_completed} is non-zero, is known to satisfy the constraints
+@code{reload_completed} is nonzero, is known to satisfy the constraints
of that @code{define_insn}. In that case, the new insn patterns must
also be insns that are matched by some @code{define_insn} and, if
-@code{reload_completed} is non-zero, must also satisfy the constraints
+@code{reload_completed} is nonzero, must also satisfy the constraints
of those definitions.
As an example of this usage of @code{define_split}, consider the following
definitions, one for the insns that are valid and one for the insns that
are not valid.
+The splitter is allowed to split jump instructions into sequence of
+jumps or create new jumps in while splitting non-jump instructions. As
+the central flowgraph and branch prediction information needs to be updated,
+several restriction apply.
+
+Splitting of jump instruction into sequence that over by another jump
+instruction is always valid, as compiler expect identical behavior of new
+jump. When new sequence contains multiple jump instructions or new labels,
+more assistance is needed. Splitter is required to create only unconditional
+jumps, or simple conditional jump instructions. Additionally it must attach a
+@code{REG_BR_PROB} note to each conditional jump. An global variable
+@code{split_branch_probability} hold the probability of original branch in case
+it was an simple conditional jump, @minus{}1 otherwise. To simplify
+recomputing of edge frequencies, new sequence is required to have only
+forward jumps to the newly created labels.
+
+@findex define_insn_and_split
For the common case where the pattern of a define_split exactly matches the
pattern of a define_insn, use @code{define_insn_and_split}. It looks like
this:
"TARGET_ZERO_EXTEND_WITH_AND && !optimize_size"
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0) (and:SI (match_dup 0) (const_int 65535)))
+ [(parallel [(set (match_dup 0)
+ (and:SI (match_dup 0) (const_int 65535)))
(clobber (reg:CC 17))])]
""
[(set_attr "type" "alu1")])
@end smallexample
In this case, the actual split condition will be
-"TARGET_ZERO_EXTEND_WITH_AND && !optimize_size && reload_completed."
+@samp{TARGET_ZERO_EXTEND_WITH_AND && !optimize_size && reload_completed}.
The @code{define_insn_and_split} construction provides exactly the same
functionality as two separate @code{define_insn} and @code{define_split}
patterns. It exists for compactness, and as a maintenance tool to prevent
having to ensure the two patterns' templates match.
+@node Including Patterns
+@section Including Patterns in Machine Descriptions.
+@cindex insn includes
+
+@findex include
+The @code{include} pattern tells the compiler tools where to
+look for patterns that are in files other than in the file
+@file{.md}. This is used only at build time and there is no preprocessing allowed.
+
+It looks like:
+
+@smallexample
+
+(include
+ @var{pathname})
+@end smallexample
+
+For example:
+
+@smallexample
+
+(include "filestuff")
+
+@end smallexample
+
+Where @var{pathname} is a string that specifies the the location of the file,
+specifies the include file to be in @file{gcc/config/target/filestuff}. The
+directory @file{gcc/config/target} is regarded as the default directory.
+
+
+Machine descriptions may be split up into smaller more manageable subsections
+and placed into subdirectories.
+
+By specifying:
+
+@smallexample
+
+(include "BOGUS/filestuff")
+
+@end smallexample
+
+the include file is specified to be in @file{gcc/config/@var{target}/BOGUS/filestuff}.
+
+Specifying an absolute path for the include file such as;
+@smallexample
+
+(include "/u2/BOGUS/filestuff")
+
+@end smallexample
+is permitted but is not encouraged.
+
+@subsection RTL Generation Tool Options for Directory Search
+@cindex directory options .md
+@cindex options, directory search
+@cindex search options
+
+The @option{-I@var{dir}} option specifies directories to search for machine descriptions.
+For example:
+
+@smallexample
+
+genrecog -I/p1/abc/proc1 -I/p2/abcd/pro2 target.md
+
+@end smallexample
+
+
+Add the directory @var{dir} to the head of the list of directories to be
+searched for header files. This can be used to override a system machine definition
+file, substituting your own version, since these directories are
+searched before the default machine description file directories. If you use more than
+one @option{-I} option, the directories are scanned in left-to-right
+order; the standard default directory come after.
+
+
@node Peephole Definitions
@section Machine-Specific Peephole Optimizers
@cindex peephole optimizer definitions
In this skeleton, @var{insn-pattern-1} and so on are patterns to match
consecutive insns. The optimization applies to a sequence of insns when
@var{insn-pattern-1} matches the first one, @var{insn-pattern-2} matches
-the next, and so on.@refill
+the next, and so on.
Each of the insns matched by a peephole must also match a
@code{define_insn}. Peepholes are checked only at the last stage just
@var{op})}, where @var{insn} is the insn in which you expect the value
to be used for the last time (from the value of @code{insn}, together
with use of @code{prev_nonnote_insn}), and @var{op} is the intermediate
-value (from @code{operands[@var{i}]}).@refill
+value (from @code{operands[@var{i}]}).
Applying the optimization means replacing the sequence of insns with one
new insn. The @var{template} controls ultimate output of assembler code
(set (match_operand:DF 0 "register_operand" "=f")
(match_operand:DF 1 "register_operand" "ad"))]
"FP_REG_P (operands[0]) && ! FP_REG_P (operands[1])"
- "*
@{
rtx xoperands[2];
xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
#ifdef MOTOROLA
- output_asm_insn (\"move.l %1,(sp)\", xoperands);
- output_asm_insn (\"move.l %1,-(sp)\", operands);
- return \"fmove.d (sp)+,%0\";
+ output_asm_insn ("move.l %1,(sp)", xoperands);
+ output_asm_insn ("move.l %1,-(sp)", operands);
+ return "fmove.d (sp)+,%0";
#else
- output_asm_insn (\"movel %1,sp@@\", xoperands);
- output_asm_insn (\"movel %1,sp@@-\", operands);
- return \"fmoved sp@@+,%0\";
+ output_asm_insn ("movel %1,sp@@", xoperands);
+ output_asm_insn ("movel %1,sp@@-", operands);
+ return "fmoved sp@@+,%0";
#endif
-@}
-")
+@})
@end smallexample
@need 1000
If @var{value} is specified as @samp{"*"}, it means that the default value of
the attribute is to be used for the insn containing this expression.
@samp{"*"} obviously cannot be used in the @var{default} expression
-of a @code{define_attr}.@refill
+of a @code{define_attr}.
If the attribute whose value is being specified is numeric, @var{value}
must be a string containing a non-negative integer (normally
@table @code
@cindex @code{const_int} and attribute tests
@item (const_int @var{i})
-This test is true if @var{i} is non-zero and false otherwise.
+This test is true if @var{i} is nonzero and false otherwise.
@cindex @code{not} and attributes
@cindex @code{ior} and attributes
This test is true if operand @var{n} of the insn whose attribute value
is being determined has mode @var{m} (this part of the test is ignored
if @var{m} is @code{VOIDmode}) and the function specified by the string
-@var{pred} returns a non-zero value when passed operand @var{n} and mode
+@var{pred} returns a nonzero value when passed operand @var{n} and mode
@var{m} (this part of the test is ignored if @var{pred} is the null
string).
expressions is true. Arithmetic expressions are formed with
@code{plus}, @code{minus}, @code{mult}, @code{div}, @code{mod},
@code{abs}, @code{neg}, @code{and}, @code{ior}, @code{xor}, @code{not},
-@code{ashift}, @code{lshiftrt}, and @code{ashiftrt} expressions.@refill
+@code{ashift}, @code{lshiftrt}, and @code{ashiftrt} expressions.
@findex get_attr
@code{const_int} and @code{symbol_ref} are always valid terms (@pxref{Insn
Lengths},for additional forms). @code{symbol_ref} is a string
denoting a C expression that yields an @code{int} when evaluated by the
@samp{get_attr_@dots{}} routine. It should normally be a global
-variable.@refill
+variable.
@findex eq_attr
@item (eq_attr @var{name} @var{value})
If @var{name} specifies an attribute of @samp{alternative}, it refers to the
value of the compiler variable @code{which_alternative}
(@pxref{Output Statement}) and the values must be small integers. For
-example,@refill
+example,
@smallexample
(eq_attr "alternative" "2,3")
Note that, for most attributes, an @code{eq_attr} test is simplified in cases
where the value of the attribute being tested is known for all insns matching
-a particular pattern. This is by far the most common case.@refill
+a particular pattern. This is by far the most common case.
@findex attr_flag
@item (attr_flag @var{name})
@code{define_attr}. Extensive use of default values for attributes
permits the specification of the values for only one or two attributes
in the definition of most insn patterns, as seen in the example in the
-next section.@refill
+next section.
The optional last argument of @code{define_insn} and
@code{define_peephole} is a vector of expressions, each of which defines
attribute's value is to use a @code{set} expression whose first operand is an
@code{attr} expression giving the name of the attribute being set. The
second operand of the @code{set} is an attribute expression
-(@pxref{Expressions}) giving the value of the attribute.@refill
+(@pxref{Expressions}) giving the value of the attribute.
When the attribute value depends on the @samp{alternative} attribute
(i.e., which is the applicable alternative in the constraint of the
updated with the correct length of the insn.
This macro will normally not be required. A case in which it is
-required is the ROMP. On this machine, the size of an @code{addr_vec}
+required is the ROMP@. On this machine, the size of an @code{addr_vec}
insn must be increased by two to compensate for the fact that alignment
may be required.
@end table
[(set (pc)
(label_ref (match_operand 0 "" "")))]
""
- "*
@{
return (get_attr_length (insn) == 4
- ? \"b %l0\" : \"l r15,=a(%l0); br r15\");
-@}"
- [(set (attr "length") (if_then_else (lt (match_dup 0) (const_int 4096))
- (const_int 4)
- (const_int 6)))])
+ ? "b %l0" : "l r15,=a(%l0); br r15");
+@}
+ [(set (attr "length")
+ (if_then_else (lt (match_dup 0) (const_int 4096))
+ (const_int 4)
+ (const_int 6)))])
@end smallexample
@node Constant Attributes
attribute test that specifies which insns may be annulled if the branch
is true. Similarly, @var{annul-false-n} specifies which insns in the
delay slot may be annulled if the branch is false. If annulling is not
-supported for that delay slot, @code{(nil)} should be coded.@refill
+supported for that delay slot, @code{(nil)} should be coded.
For example, in the common case where branch and call insns require
a single delay slot, which may contain any insn other than a branch or
used during their execution and there is no way of representing that
conflict. We welcome any examples of how function unit conflicts work
in such processors and suggestions for their representation.
-@end ifset
@node Conditional Execution
@section Conditional Execution
When @code{define_cond_exec} is used, an implicit reference to
the @code{predicable} instruction attribute is made.
-@xref{Insn Attributes}. This attribute must be boolean (i.e. have
+@xref{Insn Attributes}. This attribute must be boolean (i.e.@: have
exactly two elements in its @var{list-of-values}). Further, it must
not be used with complex expressions. That is, the default and all
uses in the insns must be a simple constant, not dependent on the
The constants that are defined with a define_constant are also output
in the insn-codes.h header file as #defines.
+@end ifset
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