Floating point constant that can be loaded into a register with one
instruction per word
+@item H
+Integer/Floating point constant that can be loaded into a register using
+three instructions
+
@item Q
Memory operand that is an offset from a register (@samp{m} is preferable
for @code{asm} statements)
+@item Z
+Memory operand that is an indexed or indirect from a register (@samp{m} is
+preferable for @code{asm} statements)
+
@item R
AIX TOC entry
+@item a
+Address operand that is an indexed or indirect from a register (@samp{p} is
+preferable for @code{asm} statements)
+
@item S
Constant suitable as a 64-bit mask operand
@item U
System V Release 4 small data area reference
+
+@item t
+AND masks that can be performed by two rldic@{l, r@} instructions
+
+@item W
+Vector constant that does not require memory
+
@end table
@item MorphoTech family---@file{config/mt/mt.h}
@item b
I register
-@item B
+@item v
B register
@item f
@item C
The CC register.
+@item t
+LT0 or LT1.
+
+@item k
+LC0 or LC1.
+
+@item u
+LB0 or LB1.
+
@item x
Any D, P, B, M, I or L register.
@end table
+@item SPU---@file{config/spu/spu.h}
+@table @code
+@item a
+An immediate which can be loaded with the il/ila/ilh/ilhu instructions. const_int is treated as a 64 bit value.
+
+@item c
+An immediate for and/xor/or instructions. const_int is treated as a 64 bit value.
+
+@item d
+An immediate for the @code{iohl} instruction. const_int is treated as a 64 bit value.
+
+@item f
+An immediate which can be loaded with @code{fsmbi}.
+
+@item A
+An immediate which can be loaded with the il/ila/ilh/ilhu instructions. const_int is treated as a 32 bit value.
+
+@item B
+An immediate for most arithmetic instructions. const_int is treated as a 32 bit value.
+
+@item C
+An immediate for and/xor/or instructions. const_int is treated as a 32 bit value.
+
+@item D
+An immediate for the @code{iohl} instruction. const_int is treated as a 32 bit value.
+
+@item I
+A constant in the range [-64, 63] for shift/rotate instructions.
+
+@item J
+An unsigned 7-bit constant for conversion/nop/channel instructions.
+
+@item K
+A signed 10-bit constant for most arithmetic instructions.
+
+@item M
+A signed 16 bit immediate for @code{stop}.
+
+@item N
+An unsigned 16-bit constant for @code{iohl} and @code{fsmbi}.
+
+@item O
+An unsigned 7-bit constant whose 3 least significant bits are 0.
+
+@item P
+An unsigned 3-bit constant for 16-byte rotates and shifts
+
+@item R
+Call operand, reg, for indirect calls
+
+@item S
+Call operand, symbol, for relative calls.
+
+@item T
+Call operand, const_int, for absolute calls.
+
+@item U
+An immediate which can be loaded with the il/ila/ilh/ilhu instructions. const_int is sign extended to 128 bit.
+
+@item W
+An immediate for shift and rotate instructions. const_int is treated as a 32 bit value.
+
+@item Y
+An immediate for and/xor/or instructions. const_int is sign extended as a 128 bit.
+
+@item Z
+An immediate for the @code{iohl} instruction. const_int is sign extended to 128 bit.
+
+@end table
+
@item TMS320C3x/C4x---@file{config/c4x/c4x.h}
@table @code
@item a
@end table
+@item Score family---@file{config/score/score.h}
+@table @code
+@item d
+Registers from r0 to r32.
+
+@item e
+Registers from r0 to r16.
+
+@item t
+r8---r11 or r22---r27 registers.
+
+@item h
+hi register.
+
+@item l
+lo register.
+
+@item x
+hi + lo register.
+
+@item q
+cnt register.
+
+@item y
+lcb register.
+
+@item z
+scb register.
+
+@item a
+cnt + lcb + scb register.
+
+@item c
+cr0---cr15 register.
+
+@item b
+cp1 registers.
+
+@item f
+cp2 registers.
+
+@item i
+cp3 registers.
+
+@item j
+cp1 + cp2 + cp3 registers.
+
+@item I
+Unsigned 15 bit integer (in the range 0 to 32767).
+
+@item J
+Unsigned 5 bit integer (in the range 0 to 31).
+
+@item K
+Unsigned 16 bit integer (in the range 0 to 65535).
+
+@item L
+Signed 16 bit integer (in the range @minus{}32768 to 32767).
+
+@item M
+Unsigned 14 bit integer (in the range 0 to 16383).
+
+@item N
+Signed 14 bit integer (in the range @minus{}8192 to 8191).
+
+@item O
+Signed 15 bit integer (in the range @minus{}16384 to 16383).
+
+@item P
+Signed 12 bit integer (in the range @minus{}2048 to 2047).
+
+@item J
+An integer constant with exactly a single bit set.
+
+@item Q
+An integer constant.
+
+@item Z
+Any SYMBOL_REF.
+@end table
+
@item Xstormy16---@file{config/stormy16/stormy16.h}
@table @code
@item a
@end table
-@item Xtensa---@file{config/xtensa/xtensa.h}
+@item Xtensa---@file{config/xtensa/constraints.md}
@table @code
@item a
General-purpose 32-bit register
Extract given field from the vector value. Operand 1 is the vector, operand 2
specify field index and operand 0 place to store value into.
+@cindex @code{vec_extract_even@var{m}} instruction pattern
+@item @samp{vec_extract_even@var{m}}
+Extract even elements from the input vectors (operand 1 and operand 2).
+The even elements of operand 2 are concatenated to the even elements of operand
+1 in their original order. The result is stored in operand 0.
+The output and input vectors should have the same modes.
+
+@cindex @code{vec_extract_odd@var{m}} instruction pattern
+@item @samp{vec_extract_odd@var{m}}
+Extract odd elements from the input vectors (operand 1 and operand 2).
+The odd elements of operand 2 are concatenated to the odd elements of operand
+1 in their original order. The result is stored in operand 0.
+The output and input vectors should have the same modes.
+
+@cindex @code{vec_interleave_high@var{m}} instruction pattern
+@item @samp{vec_interleave_high@var{m}}
+Merge high elements of the two input vectors into the output vector. The output
+and input vectors should have the same modes (@code{N} elements). The high
+@code{N/2} elements of the first input vector are interleaved with the high
+@code{N/2} elements of the second input vector.
+
+@cindex @code{vec_interleave_low@var{m}} instruction pattern
+@item @samp{vec_interleave_low@var{m}}
+Merge low elements of the two input vectors into the output vector. The output
+and input vectors should have the same modes (@code{N} elements). The low
+@code{N/2} elements of the first input vector are interleaved with the low
+@code{N/2} elements of the second input vector.
+
@cindex @code{vec_init@var{m}} instruction pattern
@item @samp{vec_init@var{m}}
Initialize the vector to given values. Operand 0 is the vector to initialize
Operand 0 is where the resulting shifted vector is stored.
The output and input vectors should have the same modes.
+@cindex @code{vec_pack_mod_@var{m}} instruction pattern
+@cindex @code{vec_pack_ssat_@var{m}} instruction pattern
+@cindex @code{vec_pack_usat_@var{m}} instruction pattern
+@item @samp{vec_pack_mod_@var{m}}, @samp{vec_pack_ssat_@var{m}}, @samp{vec_pack_usat_@var{m}}
+Narrow (demote) and merge the elements of two vectors.
+Operands 1 and 2 are vectors of the same mode.
+Operand 0 is the resulting vector in which the elements of the two input
+vectors are concatenated after narrowing them down using modulo arithmetic or
+signed/unsigned saturating arithmetic.
+
+@cindex @code{vec_unpacks_hi_@var{m}} instruction pattern
+@cindex @code{vec_unpacks_lo_@var{m}} instruction pattern
+@cindex @code{vec_unpacku_hi_@var{m}} instruction pattern
+@cindex @code{vec_unpacku_lo_@var{m}} instruction pattern
+@item @samp{vec_unpacks_hi_@var{m}}, @samp{vec_unpacks_lo_@var{m}}, @samp{vec_unpacku_hi_@var{m}}, @samp{vec_unpacku_lo_@var{m}}
+Extract and widen (promote) the high/low part of a vector of signed/unsigned
+elements. The input vector (operand 1) has N signed/unsigned elements of size S.
+Using sign/zero extension widen (promote) the high/low elements of the vector,
+and place the resulting N/2 values of size 2*S in the output vector (operand 0).
+
+@cindex @code{vec_widen_umult_hi_@var{m}} instruction pattern
+@cindex @code{vec_widen_umult_lo__@var{m}} instruction pattern
+@cindex @code{vec_widen_smult_hi_@var{m}} instruction pattern
+@cindex @code{vec_widen_smult_lo_@var{m}} instruction pattern
+@item @samp{vec_widen_umult_hi_@var{m}}, @samp{vec_widen_umult_lo_@var{m}}, @samp{vec_widen_smult_hi_@var{m}}, @samp{vec_widen_smult_lo_@var{m}}
+Signed/Unsigned widening multiplication.
+The two inputs (operands 1 and 2) are vectors with N
+signed/unsigned elements of size S. Multiply the high/low elements of the two
+vectors, and put the N/2 products of size 2*S in the output vector (operand 0).
+
@cindex @code{mulhisi3} instruction pattern
@item @samp{mulhisi3}
Multiply operands 1 and 2, which have mode @code{HImode}, and store
built-in function uses the mode which corresponds to the C data
type @code{float}.
+@cindex @code{fmod@var{m}3} instruction pattern
+@item @samp{fmod@var{m}3}
+Store the remainder of dividing operand 1 by operand 2 into
+operand 0, rounded towards zero to an integer.
+
+The @code{fmod} built-in function of C always uses the mode which
+corresponds to the C data type @code{double} and the @code{fmodf}
+built-in function uses the mode which corresponds to the C data
+type @code{float}.
+
+@cindex @code{remainder@var{m}3} instruction pattern
+@item @samp{remainder@var{m}3}
+Store the remainder of dividing operand 1 by operand 2 into
+operand 0, rounded to the nearest integer.
+
+The @code{remainder} built-in function of C always uses the mode
+which corresponds to the C data type @code{double} and the
+@code{remainderf} built-in function uses the mode which corresponds
+to the C data type @code{float}.
+
@cindex @code{cos@var{m}2} instruction pattern
@item @samp{cos@var{m}2}
Store the cosine of operand 1 into operand 0.
built-in function uses the mode which corresponds to the C data
type @code{float}.
+@cindex @code{lrint@var{m}@var{n}2}
+@item @samp{lrint@var{m}@var{n}2}
+Convert operand 1 (valid for floating point mode @var{m}) to fixed
+point mode @var{n} as a signed number according to the current
+rounding mode and store in operand 0 (which has mode @var{n}).
+
+@cindex @code{lround@var{m}@var{n}2}
+@item @samp{lround@var{m}2}
+Convert operand 1 (valid for floating point mode @var{m}) to fixed
+point mode @var{n} as a signed number rounding to nearest and away
+from zero and store in operand 0 (which has mode @var{n}).
+
+@cindex @code{lfloor@var{m}@var{n}2}
+@item @samp{lfloor@var{m}2}
+Convert operand 1 (valid for floating point mode @var{m}) to fixed
+point mode @var{n} as a signed number rounding down and store in
+operand 0 (which has mode @var{n}).
+
+@cindex @code{lceil@var{m}@var{n}2}
+@item @samp{lceil@var{m}2}
+Convert operand 1 (valid for floating point mode @var{m}) to fixed
+point mode @var{n} as a signed number rounding up and store in
+operand 0 (which has mode @var{n}).
+
@cindex @code{copysign@var{m}3} instruction pattern
@item @samp{copysign@var{m}3}
Store a value with the magnitude of operand 1 and the sign of operand
Targets that do not support write prefetches or locality hints can ignore
the values of operands 1 and 2.
+@cindex @code{blockage} instruction pattern
+@item @samp{blockage}
+
+This pattern defines a pseudo insn that prevents the instruction
+scheduler from moving instructions across the boundary defined by the
+blockage insn. Normally an UNSPEC_VOLATILE pattern.
+
@cindex @code{memory_barrier} instruction pattern
@item @samp{memory_barrier}
unit in the first string can be reserved only if each pattern of units
whose names are in the second string is not reserved. This is an
asymmetric relation (actually @samp{exclusion_set} is analogous to
-this one but it is symmetric). For example, it is useful for
-description that @acronym{VLIW} @samp{slot0} can not be reserved after
-@samp{slot1} or @samp{slot2} reservation. We could describe it by the
-following construction
+this one but it is symmetric). For example it might be useful in a
+@acronym{VLIW} description to say that @samp{slot0} cannot be reserved
+after either @samp{slot1} or @samp{slot2} have been reserved. This
+can be described as:
@smallexample
-(absence_set "slot2" "slot0, slot1")
+(absence_set "slot0" "slot1, slot2")
@end smallexample
Or @samp{slot2} can not be reserved if @samp{slot0} and unit @samp{b0}
look more accurately at reservations of states.
@item
-@dfn{time} means printing additional time statistics about
-generation of automata.
+@dfn{time} means printing time statistics about the generation of
+automata.
+
+@item
+@dfn{stats} means printing statistics about the generated automata
+such as the number of DFA states, NDFA states and arcs.
@item
@dfn{v} means a generation of the file describing the result automata.
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