Many options have long names starting with @samp{-f} or with
@samp{-W}---for example,
-@option{-fstrength-reduce}, @option{-Wformat} and so on. Most of
+@option{-fmove-loop-invariants}, @option{-Wformat} and so on. Most of
these have both positive and negative forms; the negative form of
@option{-ffoo} would be @option{-fno-foo}. This manual documents
only one of these two forms, whichever one is not the default.
-Wmain -Wmissing-braces -Wmissing-field-initializers @gol
-Wmissing-format-attribute -Wmissing-include-dirs @gol
-Wmissing-noreturn @gol
--Wno-multichar -Wnonnull -Woverlength-strings -Wpacked -Wpadded @gol
+-Wno-multichar -Wnonnull -Wno-overflow @gol
+-Woverlength-strings -Wpacked -Wpadded @gol
-Wparentheses -Wpointer-arith -Wno-pointer-to-int-cast @gol
-Wredundant-decls @gol
-Wreturn-type -Wsequence-point -Wshadow @gol
-ftree-vectorizer-verbose=@var{n} @gol
-fdump-tree-storeccp@r{[}-@var{n}@r{]} @gol
-feliminate-dwarf2-dups -feliminate-unused-debug-types @gol
--feliminate-unused-debug-symbols -fmem-report -fprofile-arcs @gol
+-feliminate-unused-debug-symbols -femit-class-debug-always @gol
+-fmem-report -fprofile-arcs @gol
-frandom-seed=@var{string} -fsched-verbose=@var{n} @gol
-ftest-coverage -ftime-report -fvar-tracking @gol
-g -g@var{level} -gcoff -gdwarf-2 @gol
-fexpensive-optimizations -ffast-math -ffloat-store @gol
-fforce-addr -ffunction-sections @gol
-fgcse -fgcse-lm -fgcse-sm -fgcse-las -fgcse-after-reload @gol
--floop-optimize -fcrossjumping -fif-conversion -fif-conversion2 @gol
+-fcrossjumping -fif-conversion -fif-conversion2 @gol
-finline-functions -finline-functions-called-once @gol
-finline-limit=@var{n} -fkeep-inline-functions @gol
-fkeep-static-consts -fmerge-constants -fmerge-all-constants @gol
-funsafe-math-optimizations -funsafe-loop-optimizations -ffinite-math-only @gol
-fno-toplevel-reorder -fno-trapping-math -fno-zero-initialized-in-bss @gol
-fomit-frame-pointer -foptimize-register-move @gol
--foptimize-sibling-calls -fprefetch-loop-arrays -fprefetch-loop-arrays-rtl @gol
+-foptimize-sibling-calls -fprefetch-loop-arrays @gol
-fprofile-generate -fprofile-use @gol
-fregmove -frename-registers @gol
-freorder-blocks -freorder-blocks-and-partition -freorder-functions @gol
--frerun-cse-after-loop -frerun-loop-opt @gol
+-frerun-cse-after-loop @gol
-frounding-math -frtl-abstract-sequences @gol
-fschedule-insns -fschedule-insns2 @gol
-fno-sched-interblock -fno-sched-spec -fsched-spec-load @gol
-fsched-spec-load-dangerous @gol
-fsched-stalled-insns=@var{n} -fsched-stalled-insns-dep=@var{n} @gol
-fsched2-use-superblocks @gol
--fsched2-use-traces -freschedule-modulo-scheduled-loops @gol
+-fsched2-use-traces -fsee -freschedule-modulo-scheduled-loops @gol
-fsection-anchors -fsignaling-nans -fsingle-precision-constant @gol
-fstack-protector -fstack-protector-all @gol
--fstrength-reduce -fstrict-aliasing -ftracer -fthread-jumps @gol
+-fstrict-aliasing -ftracer -fthread-jumps @gol
-funroll-all-loops -funroll-loops -fpeel-loops @gol
-fsplit-ivs-in-unroller -funswitch-loops @gol
-fvariable-expansion-in-unroller @gol
-mno-fp-ret-in-387 -msoft-float -msvr3-shlib @gol
-mno-wide-multiply -mrtd -malign-double @gol
-mpreferred-stack-boundary=@var{num} @gol
--mmmx -msse -msse2 -msse3 -m3dnow -msselibm @gol
+-mmmx -msse -msse2 -msse3 -m3dnow @gol
-mthreads -mno-align-stringops -minline-all-stringops @gol
-mpush-args -maccumulate-outgoing-args -m128bit-long-double @gol
-m96bit-long-double -mregparm=@var{num} -msseregparm @gol
+-mstackrealign @gol
-momit-leaf-frame-pointer -mno-red-zone -mno-tls-direct-seg-refs @gol
-mcmodel=@var{code-model} @gol
-m32 -m64 -mlarge-data-threshold=@var{num}}
-minline-sqrt-min-latency -minline-sqrt-max-throughput @gol
-mno-dwarf2-asm -mearly-stop-bits @gol
-mfixed-range=@var{register-range} -mtls-size=@var{tls-size} @gol
--mtune=@var{cpu-type} -mt -pthread -milp32 -mlp64}
+-mtune=@var{cpu-type} -mt -pthread -milp32 -mlp64 @gol
+-mno-sched-br-data-spec -msched-ar-data-spec -mno-sched-control-spec @gol
+-msched-br-in-data-spec -msched-ar-in-data-spec -msched-in-control-spec @gol
+-msched-ldc -mno-sched-control-ldc -mno-sched-spec-verbose @gol
+-mno-sched-prefer-non-data-spec-insns @gol
+-mno-sched-prefer-non-control-spec-insns @gol
+-mno-sched-count-spec-in-critical-path}
@emph{M32R/D Options}
@gccoptlist{-m32r2 -m32rx -m32r @gol
@gccoptlist{-EL -EB -march=@var{arch} -mtune=@var{arch} @gol
-mips1 -mips2 -mips3 -mips4 -mips32 -mips32r2 -mips64 @gol
-mips16 -mno-mips16 -mabi=@var{abi} -mabicalls -mno-abicalls @gol
--mxgot -mno-xgot -mgp32 -mgp64 -mfp32 -mfp64 @gol
--mhard-float -msoft-float -msingle-float -mdouble-float @gol
--mdsp -mpaired-single -mips3d @gol
+-mshared -mno-shared -mxgot -mno-xgot -mgp32 -mgp64 @gol
+-mfp32 -mfp64 -mhard-float -msoft-float @gol
+-msingle-float -mdouble-float -mdsp -mpaired-single -mips3d @gol
-mlong64 -mlong32 -msym32 -mno-sym32 @gol
-G@var{num} -membedded-data -mno-embedded-data @gol
-muninit-const-in-rodata -mno-uninit-const-in-rodata @gol
-mspe=yes -mspe=no @gol
-mvrsave -mno-vrsave @gol
-mmulhw -mno-mulhw @gol
+-mdlmzb -mno-dlmzb @gol
-mfloat-gprs=yes -mfloat-gprs=no -mfloat-gprs=single -mfloat-gprs=double @gol
-mprototype -mno-prototype @gol
-msim -mmvme -mads -myellowknife -memb -msdata @gol
-fverbose-asm -fpack-struct[=@var{n}] -fstack-check @gol
-fstack-limit-register=@var{reg} -fstack-limit-symbol=@var{sym} @gol
-fargument-alias -fargument-noalias @gol
--fargument-noalias-global -fleading-underscore @gol
--ftls-model=@var{model} @gol
+-fargument-noalias-global -fargument-noalias-anything
+-fleading-underscore -ftls-model=@var{model} @gol
-ftrapv -fwrapv -fbounds-check @gol
-fvisibility -fopenmp}
@end table
phase of the compiler returns a non-success return code. If you specify
@option{-pass-exit-codes}, the @command{gcc} program will instead return with
numerically highest error produced by any phase that returned an error
-indication.
+indication. The C, C++, and Fortran frontends return 4, if an internal
+compiler error is encountered.
@end table
If you only want some of the stages of compilation, you can use
@item -fvisibility-inlines-hidden
@opindex fvisibility-inlines-hidden
-Causes all inlined methods to be marked with
+This switch declares that the user does not attempt to compare
+pointers to inline methods where the addresses of the two functions
+were taken in different shared objects.
+
+The effect of this is that GCC may, effectively, mark inline methods with
@code{__attribute__ ((visibility ("hidden")))} so that they do not
appear in the export table of a DSO and do not require a PLT indirection
when used within the DSO@. Enabling this option can have a dramatic effect
on load and link times of a DSO as it massively reduces the size of the
-dynamic export table when the library makes heavy use of templates. While
-it can cause bloating through duplication of code within each DSO where
-it is used, often the wastage is less than the considerable space occupied
-by a long symbol name in the export table which is typical when using
-templates and namespaces. For even more savings, combine with the
-@option{-fvisibility=hidden} switch.
+dynamic export table when the library makes heavy use of templates.
+
+The behavior of this switch is not quite the same as marking the
+methods as hidden directly. Normally if there is a class with default
+visibility which has a hidden method, the effect of this is that the
+method must be defined in only one shared object. This switch does
+not have this restriction.
+
+You may mark a method as having a visibility explicitly to negate the
+effect of the switch for that method. For example, if you do want to
+compare pointers to a particular inline method, you might mark it as
+having default visibility.
@item -fno-weak
@opindex fno-weak
These warnings are possible only in optimizing compilation,
because they require data flow information that is computed only
-when optimizing. If you don't specify @option{-O}, you simply won't
-get these warnings.
+when optimizing. If you do not specify @option{-O}, you will not get
+these warnings. Instead, GCC will issue a warning about @option{-Wuninitialized}
+requiring @option{-O}.
If you want to warn about code which uses the uninitialized value of the
variable in its own initializer, use the @option{-Winit-self} option.
been applied. For instance @code{\u207F}, ``SUPERSCRIPT LATIN SMALL
LETTER N'', will display just like a regular @code{n} which has been
placed in a superscript. ISO 10646 defines the @dfn{NFKC}
-normalisation scheme to convert all these into a standard form as
+normalization scheme to convert all these into a standard form as
well, and GCC will warn if your code is not in NFKC if you use
@option{-Wnormalized=nfkc}. This warning is comparable to warning
about every identifier that contains the letter O because it might be
(@pxref{Function Attributes}, @pxref{Variable Attributes},
@pxref{Type Attributes}.)
+@item -Wno-overflow
+@opindex Wno-overflow
+Do not warn about compile-time overflow in constant expressions.
+
@item -Wpacked
@opindex Wpacked
Warn if a structure is given the packed attribute, but the packed
Produce debugging information in stabs format (if that is supported),
for only symbols that are actually used.
+@item -femit-class-debug-always
+Instead of emitting debugging information for a C++ class in only one
+object file, emit it in all object files using the class. This option
+should be used only with debuggers that are unable to handle the way GCC
+normally emits debugging information for classes because using this
+option will increase the size of debugging information by as much as a
+factor of two.
+
@item -gstabs+
@opindex gstabs+
Produce debugging information in stabs format (if that is supported),
@opindex dA
Annotate the assembler output with miscellaneous debugging information.
-@item -db
-@itemx -fdump-rtl-bp
-@opindex db
-@opindex fdump-rtl-bp
-Dump after computing branch probabilities, to @file{@var{file}.09.bp}.
-
@item -dB
@itemx -fdump-rtl-bbro
@opindex dB
@opindex fdump-rtl-bbro
-Dump after block reordering, to @file{@var{file}.30.bbro}.
+Dump after block reordering, to @file{@var{file}.148r.bbro}.
@item -dc
@itemx -fdump-rtl-combine
@opindex dc
@opindex fdump-rtl-combine
-Dump after instruction combination, to the file @file{@var{file}.17.combine}.
+Dump after instruction combination, to the file @file{@var{file}.129r.combine}.
@item -dC
@itemx -fdump-rtl-ce1
@opindex fdump-rtl-ce1
@opindex fdump-rtl-ce2
@option{-dC} and @option{-fdump-rtl-ce1} enable dumping after the
-first if conversion, to the file @file{@var{file}.11.ce1}. @option{-dC}
+first if conversion, to the file @file{@var{file}.117r.ce1}. @option{-dC}
and @option{-fdump-rtl-ce2} enable dumping after the second if
-conversion, to the file @file{@var{file}.18.ce2}.
+conversion, to the file @file{@var{file}.130r.ce2}.
@item -dd
@itemx -fdump-rtl-btl
@itemx -fdump-rtl-ce3
@opindex dE
@opindex fdump-rtl-ce3
-Dump after the third if conversion, to @file{@var{file}.28.ce3}.
+Dump after the third if conversion, to @file{@var{file}.146r.ce3}.
@item -df
@itemx -fdump-rtl-cfg
@opindex fdump-rtl-cfg
@opindex fdump-rtl-life
@option{-df} and @option{-fdump-rtl-cfg} enable dumping after control
-and data flow analysis, to @file{@var{file}.08.cfg}. @option{-df}
+and data flow analysis, to @file{@var{file}.116r.cfg}. @option{-df}
and @option{-fdump-rtl-cfg} enable dumping dump after life analysis,
-to @file{@var{file}.16.life}.
+to @file{@var{file}.128r.life1} and @file{@var{file}.135r.life2}.
@item -dg
@itemx -fdump-rtl-greg
@opindex dg
@opindex fdump-rtl-greg
-Dump after global register allocation, to @file{@var{file}.23.greg}.
+Dump after global register allocation, to @file{@var{file}.139r.greg}.
@item -dG
@itemx -fdump-rtl-gcse
@opindex fdump-rtl-gcse
@opindex fdump-rtl-bypass
@option{-dG} and @option{-fdump-rtl-gcse} enable dumping after GCSE, to
-@file{@var{file}.05.gcse}. @option{-dG} and @option{-fdump-rtl-bypass}
+@file{@var{file}.114r.gcse}. @option{-dG} and @option{-fdump-rtl-bypass}
enable dumping after jump bypassing and control flow optimizations, to
-@file{@var{file}.07.bypass}.
+@file{@var{file}.115r.bypass}.
@item -dh
@itemx -fdump-rtl-eh
@itemx -fdump-rtl-sibling
@opindex di
@opindex fdump-rtl-sibling
-Dump after sibling call optimizations, to @file{@var{file}.01.sibling}.
+Dump after sibling call optimizations, to @file{@var{file}.106r.sibling}.
@item -dj
@itemx -fdump-rtl-jump
@opindex dj
@opindex fdump-rtl-jump
-Dump after the first jump optimization, to @file{@var{file}.03.jump}.
+Dump after the first jump optimization, to @file{@var{file}.112r.jump}.
@item -dk
@itemx -fdump-rtl-stack
@opindex dk
@opindex fdump-rtl-stack
-Dump after conversion from registers to stack, to @file{@var{file}.33.stack}.
+Dump after conversion from registers to stack, to @file{@var{file}.152r.stack}.
@item -dl
@itemx -fdump-rtl-lreg
@opindex dl
@opindex fdump-rtl-lreg
-Dump after local register allocation, to @file{@var{file}.22.lreg}.
+Dump after local register allocation, to @file{@var{file}.138r.lreg}.
@item -dL
-@itemx -fdump-rtl-loop
@itemx -fdump-rtl-loop2
@opindex dL
-@opindex fdump-rtl-loop
@opindex fdump-rtl-loop2
-@option{-dL} and @option{-fdump-rtl-loop} enable dumping after the first
-loop optimization pass, to @file{@var{file}.06.loop}. @option{-dL} and
-@option{-fdump-rtl-loop2} enable dumping after the second pass, to
-@file{@var{file}.13.loop2}.
+@option{-dL} and @option{-fdump-rtl-loop2} enable dumping after the
+loop optimization pass, to @file{@var{file}.119r.loop2},
+@file{@var{file}.120r.loop2_init},
+@file{@var{file}.121r.loop2_invariant}, and
+@file{@var{file}.125r.loop2_done}.
@item -dm
@itemx -fdump-rtl-sms
@opindex dm
@opindex fdump-rtl-sms
-Dump after modulo scheduling, to @file{@var{file}.20.sms}.
+Dump after modulo scheduling, to @file{@var{file}.136r.sms}.
@item -dM
@itemx -fdump-rtl-mach
@opindex dM
@opindex fdump-rtl-mach
Dump after performing the machine dependent reorganization pass, to
-@file{@var{file}.35.mach}.
+@file{@var{file}.155r.mach}.
@item -dn
@itemx -fdump-rtl-rnreg
@opindex dn
@opindex fdump-rtl-rnreg
-Dump after register renumbering, to @file{@var{file}.29.rnreg}.
+Dump after register renumbering, to @file{@var{file}.147r.rnreg}.
@item -dN
@itemx -fdump-rtl-regmove
@opindex dN
@opindex fdump-rtl-regmove
-Dump after the register move pass, to @file{@var{file}.19.regmove}.
+Dump after the register move pass, to @file{@var{file}.132r.regmove}.
@item -do
@itemx -fdump-rtl-postreload
@itemx -fdump-rtl-expand
@opindex dr
@opindex fdump-rtl-expand
-Dump after RTL generation, to @file{@var{file}.00.expand}.
+Dump after RTL generation, to @file{@var{file}.104r.expand}.
@item -dR
@itemx -fdump-rtl-sched2
@opindex dR
@opindex fdump-rtl-sched2
-Dump after the second scheduling pass, to @file{@var{file}.32.sched2}.
+Dump after the second scheduling pass, to @file{@var{file}.150r.sched2}.
@item -ds
@itemx -fdump-rtl-cse
@opindex ds
@opindex fdump-rtl-cse
Dump after CSE (including the jump optimization that sometimes follows
-CSE), to @file{@var{file}.04.cse}.
+CSE), to @file{@var{file}.113r.cse}.
@item -dS
@itemx -fdump-rtl-sched
@opindex dt
@opindex fdump-rtl-cse2
Dump after the second CSE pass (including the jump optimization that
-sometimes follows CSE), to @file{@var{file}.15.cse2}.
+sometimes follows CSE), to @file{@var{file}.127r.cse2}.
@item -dT
@itemx -fdump-rtl-tracer
@opindex dT
@opindex fdump-rtl-tracer
-Dump after running tracer, to @file{@var{file}.12.tracer}.
+Dump after running tracer, to @file{@var{file}.118r.tracer}.
@item -dV
@itemx -fdump-rtl-vpt
@option{-dV} and @option{-fdump-rtl-vpt} enable dumping after the value
profile transformations, to @file{@var{file}.10.vpt}. @option{-dV}
and @option{-fdump-rtl-vartrack} enable dumping after variable tracking,
-to @file{@var{file}.34.vartrack}.
+to @file{@var{file}.154r.vartrack}.
@item -dw
@itemx -fdump-rtl-flow2
@opindex dw
@opindex fdump-rtl-flow2
-Dump after the second flow pass, to @file{@var{file}.26.flow2}.
+Dump after the second flow pass, to @file{@var{file}.142r.flow2}.
@item -dz
@itemx -fdump-rtl-peephole2
@opindex dz
@opindex fdump-rtl-peephole2
-Dump after the peephole pass, to @file{@var{file}.27.peephole2}.
+Dump after the peephole pass, to @file{@var{file}.145r.peephole2}.
@item -dZ
@itemx -fdump-rtl-web
@opindex dZ
@opindex fdump-rtl-web
-Dump after live range splitting, to @file{@var{file}.14.web}.
+Dump after live range splitting, to @file{@var{file}.126r.web}.
@item -da
@itemx -fdump-rtl-all
@item -ftree-vectorizer-verbose=@var{n}
@opindex ftree-vectorizer-verbose
This option controls the amount of debugging output the vectorizer prints.
-This information is written to standard error, unless @option{-fdump-tree-all}
-or @option{-fdump-tree-vect} is specified, in which case it is output to the
-usual dump listing file, @file{.vect}.
+This information is written to standard error, unless
+@option{-fdump-tree-all} or @option{-fdump-tree-vect} is specified,
+in which case it is output to the usual dump listing file, @file{.vect}.
+For @var{n}=0 no diagnostic information is reported.
+If @var{n}=1 the vectorizer reports each loop that got vectorized,
+and the total number of loops that got vectorized.
+If @var{n}=2 the vectorizer also reports non-vectorized loops that passed
+the first analysis phase (vect_analyze_loop_form) - i.e. countable,
+inner-most, single-bb, single-entry/exit loops. This is the same verbosity
+level that @option{-fdump-tree-vect-stats} uses.
+Higher verbosity levels mean either more information dumped for each
+reported loop, or same amount of information reported for more loops:
+If @var{n}=3, alignment related information is added to the reports.
+If @var{n}=4, data-references related information (e.g. memory dependences,
+memory access-patterns) is added to the reports.
+If @var{n}=5, the vectorizer reports also non-vectorized inner-most loops
+that did not pass the first analysis phase (i.e. may not be countable, or
+may have complicated control-flow).
+If @var{n}=6, the vectorizer reports also non-vectorized nested loops.
+For @var{n}=7, all the information the vectorizer generates during its
+analysis and transformation is reported. This is the same verbosity level
+that @option{-fdump-tree-vect-details} uses.
@item -frandom-seed=@var{string}
@opindex frandom-string
and possibly the ability to debug the program.
The compiler performs optimization based on the knowledge it has of
-the program. Optimization levels @option{-O2} and above, in
+the program. Optimization levels @option{-O} and above, in
particular, enable @emph{unit-at-a-time} mode, which allows the
compiler to consider information gained from later functions in
the file when compiling a function. Compiling multiple files at
-fdelayed-branch @gol
-fguess-branch-probability @gol
-fcprop-registers @gol
--floop-optimize @gol
-fif-conversion @gol
-fif-conversion2 @gol
-ftree-ccp @gol
-ftree-copyrename @gol
-ftree-fre @gol
-ftree-ch @gol
+-funit-at-a-time @gol
-fmerge-constants}
@option{-O} also turns on @option{-fomit-frame-pointer} on machines
-fcse-follow-jumps -fcse-skip-blocks @gol
-fgcse -fgcse-lm @gol
-fexpensive-optimizations @gol
--fstrength-reduce @gol
--frerun-cse-after-loop -frerun-loop-opt @gol
+-frerun-cse-after-loop @gol
-fcaller-saves @gol
-fpeephole2 @gol
-fschedule-insns -fschedule-insns2 @gol
-fstrict-aliasing @gol
-fdelete-null-pointer-checks @gol
-freorder-blocks -freorder-functions @gol
--funit-at-a-time @gol
-falign-functions -falign-jumps @gol
-falign-loops -falign-labels @gol
-ftree-vrp @gol
This option is only meaningful on architectures that support such
instructions, which include x86, PowerPC, IA-64 and S/390.
-The default is @option{-fbranch-count-reg}, enabled when
-@option{-fstrength-reduce} is enabled.
+The default is @option{-fbranch-count-reg}.
@item -fno-function-cse
@opindex fno-function-cse
some protection against outright memory corrupting writes, but allows
erroneously read data to propagate within a program.
-@item -fstrength-reduce
-@opindex fstrength-reduce
-Perform the optimizations of loop strength reduction and
-elimination of iteration variables.
-
-Enabled at levels @option{-O2}, @option{-O3}, @option{-Os}.
-
@item -fthread-jumps
@opindex fthread-jumps
Perform optimizations where we check to see if a jump branches to a
Enabled at levels @option{-O2}, @option{-O3}, @option{-Os}.
-@item -frerun-loop-opt
-@opindex frerun-loop-opt
-Run the loop optimizer twice.
-
-Enabled at levels @option{-O2}, @option{-O3}, @option{-Os}.
-
@item -fgcse
@opindex fgcse
Perform a global common subexpression elimination pass.
pass is performed after reload. The purpose of this pass is to cleanup
redundant spilling.
-@item -floop-optimize
-@opindex floop-optimize
-Perform loop optimizations: move constant expressions out of loops, simplify
-exit test conditions and optionally do strength-reduction as well.
-
-Enabled at levels @option{-O}, @option{-O2}, @option{-O3}, @option{-Os}.
-
@item -funsafe-loop-optimizations
@opindex funsafe-loop-optimizations
If given, the loop optimizer will assume that loop indices do not
sense when scheduling after register allocation, i.e.@: with
@option{-fschedule-insns2} or at @option{-O2} or higher.
+@item -fsee
+@opindex fsee
+Eliminates redundant extension instructions and move the non redundant
+ones to optimal placement using LCM.
+
@item -freschedule-modulo-scheduled-loops
@opindex fscheduling-in-modulo-scheduled-loops
The modulo scheduling comes before the traditional scheduling, if a loop was modulo scheduled
@item -funroll-loops
@opindex funroll-loops
Unroll loops whose number of iterations can be determined at compile
-time or upon entry to the loop. @option{-funroll-loops} implies both
-@option{-fstrength-reduce} and @option{-frerun-cse-after-loop}. This
-option makes code larger, and may or may not make it run faster.
+time or upon entry to the loop. @option{-funroll-loops} implies
+@option{-frerun-cse-after-loop}. This option makes code larger,
+and may or may not make it run faster.
@item -funroll-all-loops
@opindex funroll-all-loops
local variables when unrolling a loop which can result in superior code.
@item -fprefetch-loop-arrays
-@itemx -fprefetch-loop-arrays-rtl
@opindex fprefetch-loop-arrays
-@opindex fprefetch-loop-arrays-rtl
If supported by the target machine, generate instructions to prefetch
memory to improve the performance of loops that access large arrays.
-These options may generate better or worse code; results are highly
+This option may generate better or worse code; results are highly
dependent on the structure of loops within the source code.
+Disabled at level @option{-Os}.
+
@item -fno-peephole
@itemx -fno-peephole2
@opindex fno-peephole
As a temporary workaround, @option{-fno-unit-at-a-time} can be used,
but this scheme may not be supported by future releases of GCC@.
-Enabled at levels @option{-O2}, @option{-O3}.
+Enabled at levels @option{-O}, @option{-O2}, @option{-O3}, @option{-Os}.
@item -fno-toplevel-reorder
Do not reorder top-level functions, variables, and @code{asm}
generally profitable only with profile feedback available.
The following options are enabled: @code{-fbranch-probabilities}, @code{-fvpt},
-@code{-funroll-loops}, @code{-fpeel-loops}, @code{-ftracer},
-@code{-fno-loop-optimize}.
+@code{-funroll-loops}, @code{-fpeel-loops}, @code{-ftracer}
@end table
@item -fmove-loop-invariants
@opindex fmove-loop-invariants
-Enables the loop invariant motion pass in the new loop optimizer. Enabled
+Enables the loop invariant motion pass in the RTL loop optimizer. Enabled
at level @option{-O1}
@item -funswitch-loops
Move branches with loop invariant conditions out of the loop, with duplicates
of the loop on both branches (modified according to result of the condition).
-@item -fprefetch-loop-arrays
-@itemx -fprefetch-loop-arrays-rtl
-@opindex fprefetch-loop-arrays
-@opindex fprefetch-loop-arrays-rtl
-If supported by the target machine, generate instructions to prefetch
-memory to improve the performance of loops that access large arrays.
-
-Disabled at level @option{-Os}.
-
@item -ffunction-sections
@itemx -fdata-sections
@opindex ffunction-sections
@option{reorder-block-duplicate} since information about the hot spots is more
accurate.
+@item max-sched-ready-insns
+The maximum number of instructions ready to be issued the scheduler should
+consider at any given time during the first scheduling pass. Increasing
+values mean more thorough searches, making the compilation time increase
+with probably little benefit. The default value is 100.
+
@item max-sched-region-blocks
The maximum number of blocks in a region to be considered for
interblock scheduling. The default value is 10.
The minimum probability (in percents) of reaching a source block
for interblock speculative scheduling. The default value is 40.
+@item max-sched-extend-regions-iters
+The maximum number of iterations through CFG to extend regions.
+0 - disable region extension,
+N - do at most N iterations.
+The default value is 2.
+
+@item max-sched-insn-conflict-delay
+The maximum conflict delay for an insn to be considered for speculative motion.
+The default value is 3.
+
+@item sched-spec-prob-cutoff
+The minimal probability of speculation success (in percents), so that
+speculative insn will be scheduled.
+The default value is 40.
+
@item max-last-value-rtl
The maximum size measured as number of RTLs that can be recorded in an expression
generic instruction set applicable to all processors. In contrast,
@option{-mtune} indicates the processor (or, in this case, collection of
processors) for which the code is optimized.
+@item native
+This selects the CPU to tune for at compilation time by determining
+the processor type of the compiling machine. Using @option{-mtune=native}
+will produce code optimized for the local machine under the constraints
+of the selected instruction set. Using @option{-march=native} will
+enable all instruction subsets supported by the local machine (hence
+the result might not run on different machines).
@item i386
Original Intel's i386 CPU@.
@item i486
Intel PentiumPro CPU@.
@item i686
Same as @code{generic}, but when used as @code{march} option, PentiumPro
-instruction set will be used, so the code will run on all i686 familly chips.
+instruction set will be used, so the code will run on all i686 family chips.
@item pentium2
Intel Pentium2 CPU based on PentiumPro core with MMX instruction set support.
@item pentium3, pentium3m
modules with the same value, including any libraries. This includes
the system libraries and startup modules.
+@item -mstackrealign
+@opindex mstackrealign
+Realign the stack at entry. On the Intel x86, the
+@option{-mstackrealign} option will generate an alternate prologue and
+epilogue that realigns the runtime stack. This supports mixing legacy
+codes that keep a 4-byte aligned stack with modern codes that keep a
+16-byte stack for SSE compatibility. The alternate prologue and
+epilogue are slower and bigger than the regular ones, and the
+alternate prologue requires an extra scratch register; this lowers the
+number of registers available if used in conjunction with the
+@code{regparm} attribute. The @option{-mstackrealign} option is
+incompatible with the nested function prologue; this is considered a
+hard error. See also the attribute @code{force_align_arg_pointer},
+applicable to individual functions.
+
@item -mpreferred-stack-boundary=@var{num}
@opindex mpreferred-stack-boundary
Attempt to keep the stack boundary aligned to a 2 raised to @var{num}
the file containing the CPU detection code should be compiled without
these options.
-@item -msselibm
-@opindex msselibm
-Use special versions of certain libm routines that come with an SSE
-ABI and an SSE implementation. Useful together with @option{-mfpmath=sse}
-to avoid moving values between SSE registers and the x87 FP stack.
-
@item -mpush-args
@itemx -mno-push-args
@opindex mpush-args
The 64-bit environment sets int to 32 bits and long and pointer
to 64 bits. These are HP-UX specific flags.
+@item -mno-sched-br-data-spec
+@itemx -msched-br-data-spec
+@opindex -mno-sched-br-data-spec
+@opindex -msched-br-data-spec
+(Dis/En)able data speculative scheduling before reload.
+This will result in generation of the ld.a instructions and
+the corresponding check instructions (ld.c / chk.a).
+The default is 'disable'.
+
+@item -msched-ar-data-spec
+@itemx -mno-sched-ar-data-spec
+@opindex -msched-ar-data-spec
+@opindex -mno-sched-ar-data-spec
+(En/Dis)able data speculative scheduling after reload.
+This will result in generation of the ld.a instructions and
+the corresponding check instructions (ld.c / chk.a).
+The default is 'enable'.
+
+@item -mno-sched-control-spec
+@itemx -msched-control-spec
+@opindex -mno-sched-control-spec
+@opindex -msched-control-spec
+(Dis/En)able control speculative scheduling. This feature is
+available only during region scheduling (i.e. before reload).
+This will result in generation of the ld.s instructions and
+the corresponding check instructions chk.s .
+The default is 'disable'.
+
+@item -msched-br-in-data-spec
+@itemx -mno-sched-br-in-data-spec
+@opindex -msched-br-in-data-spec
+@opindex -mno-sched-br-in-data-spec
+(En/Dis)able speculative scheduling of the instructions that
+are dependent on the data speculative loads before reload.
+This is effective only with @option{-msched-br-data-spec} enabled.
+The default is 'enable'.
+
+@item -msched-ar-in-data-spec
+@itemx -mno-sched-ar-in-data-spec
+@opindex -msched-ar-in-data-spec
+@opindex -mno-sched-ar-in-data-spec
+(En/Dis)able speculative scheduling of the instructions that
+are dependent on the data speculative loads after reload.
+This is effective only with @option{-msched-ar-data-spec} enabled.
+The default is 'enable'.
+
+@item -msched-in-control-spec
+@itemx -mno-sched-in-control-spec
+@opindex -msched-in-control-spec
+@opindex -mno-sched-in-control-spec
+(En/Dis)able speculative scheduling of the instructions that
+are dependent on the control speculative loads.
+This is effective only with @option{-msched-control-spec} enabled.
+The default is 'enable'.
+
+@item -msched-ldc
+@itemx -mno-sched-ldc
+@opindex -msched-ldc
+@opindex -mno-sched-ldc
+(En/Dis)able use of simple data speculation checks ld.c .
+If disabled, only chk.a instructions will be emitted to check
+data speculative loads.
+The default is 'enable'.
+
+@item -mno-sched-control-ldc
+@itemx -msched-control-ldc
+@opindex -mno-sched-control-ldc
+@opindex -msched-control-ldc
+(Dis/En)able use of ld.c instructions to check control speculative loads.
+If enabled, in case of control speculative load with no speculatively
+scheduled dependent instructions this load will be emitted as ld.sa and
+ld.c will be used to check it.
+The default is 'disable'.
+
+@item -mno-sched-spec-verbose
+@itemx -msched-spec-verbose
+@opindex -mno-sched-spec-verbose
+@opindex -msched-spec-verbose
+(Dis/En)able printing of the information about speculative motions.
+
+@item -mno-sched-prefer-non-data-spec-insns
+@itemx -msched-prefer-non-data-spec-insns
+@opindex -mno-sched-prefer-non-data-spec-insns
+@opindex -msched-prefer-non-data-spec-insns
+If enabled, data speculative instructions will be chosen for schedule
+only if there are no other choices at the moment. This will make
+the use of the data speculation much more conservative.
+The default is 'disable'.
+
+@item -mno-sched-prefer-non-control-spec-insns
+@itemx -msched-prefer-non-control-spec-insns
+@opindex -mno-sched-prefer-non-control-spec-insns
+@opindex -msched-prefer-non-control-spec-insns
+If enabled, control speculative instructions will be chosen for schedule
+only if there are no other choices at the moment. This will make
+the use of the control speculation much more conservative.
+The default is 'disable'.
+
+@item -mno-sched-count-spec-in-critical-path
+@itemx -msched-count-spec-in-critical-path
+@opindex -mno-sched-count-spec-in-critical-path
+@opindex -msched-count-spec-in-critical-path
+If enabled, speculative dependencies will be considered during
+computation of the instructions priorities. This will make the use of the
+speculation a bit more conservative.
+The default is 'disable'.
+
@end table
@node M32C Options
@itemx -mno-abicalls
@opindex mabicalls
@opindex mno-abicalls
-Generate (do not generate) SVR4-style position-independent code.
-@option{-mabicalls} is the default for SVR4-based systems.
+Generate (do not generate) code that is suitable for SVR4-style
+dynamic objects. @option{-mabicalls} is the default for SVR4-based
+systems.
+
+@item -mshared
+@itemx -mno-shared
+Generate (do not generate) code that is fully position-independent,
+and that can therefore be linked into shared libraries. This option
+only affects @option{-mabicalls}.
+
+All @option{-mabicalls} code has traditionally been position-independent,
+regardless of options like @option{-fPIC} and @option{-fpic}. However,
+as an extension, the GNU toolchain allows executables to use absolute
+accesses for locally-binding symbols. It can also use shorter GP
+initialization sequences and generate direct calls to locally-defined
+functions. This mode is selected by @option{-mno-shared}.
+
+@option{-mno-shared} depends on binutils 2.16 or higher and generates
+objects that can only be linked by the GNU linker. However, the option
+does not affect the ABI of the final executable; it only affects the ABI
+of relocatable objects. Using @option{-mno-shared} will generally make
+executables both smaller and quicker.
+
+@option{-mshared} is the default.
@item -mxgot
@itemx -mno-xgot
@samp{7450}, @samp{750}, @samp{801}, @samp{821}, @samp{823},
@samp{860}, @samp{970}, @samp{8540}, @samp{ec603e}, @samp{G3},
@samp{G4}, @samp{G5}, @samp{power}, @samp{power2}, @samp{power3},
-@samp{power4}, @samp{power5}, @samp{power5+},
+@samp{power4}, @samp{power5}, @samp{power5+}, @samp{power6},
@samp{common}, @samp{powerpc}, @samp{powerpc64},
@samp{rios}, @samp{rios1}, @samp{rios2}, @samp{rsc}, and @samp{rs64}.
@option{-mhard-float}, @option{-mmfcrf}, @option{-mmultiple},
@option{-mnew-mnemonics}, @option{-mpopcntb}, @option{-mpower},
@option{-mpower2}, @option{-mpowerpc64}, @option{-mpowerpc-gpopt},
-@option{-mpowerpc-gfxopt}, @option{-mstring}, @option{-mmulhw}.
+@option{-mpowerpc-gfxopt}, @option{-mstring}, @option{-mmulhw}, @option{dlmzb}.
The particular options
set for any particular CPU will vary between compiler versions,
depending on what setting seems to produce optimal code for that CPU;
These instructions are generated by default when targetting those
processors.
+@item -mdlmzb
+@itemx -mno-dlmzb
+@opindex mdlmzb
+@opindex mno-dlmzb
+Generate code that uses (does not use) the string-search @samp{dlmzb}
+instruction on the IBM 405 and 440 processors. This instruction is
+generated by default when targetting those processors.
+
@item -mno-bit-align
@itemx -mbit-align
@opindex mno-bit-align
for machine type @var{cpu_type}. Supported values for @var{cpu_type} are
@samp{v7}, @samp{cypress}, @samp{v8}, @samp{supersparc}, @samp{sparclite},
@samp{f930}, @samp{f934}, @samp{hypersparc}, @samp{sparclite86x},
-@samp{sparclet}, @samp{tsc701}, @samp{v9}, @samp{ultrasparc}, and
-@samp{ultrasparc3}.
+@samp{sparclet}, @samp{tsc701}, @samp{v9}, @samp{ultrasparc},
+@samp{ultrasparc3}, and @samp{niagara}.
Default instruction scheduling parameters are used for values that select
an architecture and not an implementation. These are @samp{v7}, @samp{v8},
v8: supersparc, hypersparc
sparclite: f930, f934, sparclite86x
sparclet: tsc701
- v9: ultrasparc, ultrasparc3
+ v9: ultrasparc, ultrasparc3, niagara
@end smallexample
By default (unless configured otherwise), GCC generates code for the V7
architecture. This adds 64-bit integer and floating-point move instructions,
3 additional floating-point condition code registers and conditional move
instructions. With @option{-mcpu=ultrasparc}, the compiler additionally
-optimizes it for the Sun UltraSPARC I/II chips. With
+optimizes it for the Sun UltraSPARC I/II/IIi chips. With
@option{-mcpu=ultrasparc3}, the compiler additionally optimizes it for the
-Sun UltraSPARC III chip.
+Sun UltraSPARC III/III+/IIIi/IIIi+/IV/IV+ chips. With
+@option{-mcpu=niagara}, the compiler additionally optimizes it for
+Sun UltraSPARC T1 chips.
@item -mtune=@var{cpu_type}
@opindex mtune
@option{-mtune=@var{cpu_type}}, but the only useful values are those
that select a particular cpu implementation. Those are @samp{cypress},
@samp{supersparc}, @samp{hypersparc}, @samp{f930}, @samp{f934},
-@samp{sparclite86x}, @samp{tsc701}, @samp{ultrasparc}, and
-@samp{ultrasparc3}.
+@samp{sparclite86x}, @samp{tsc701}, @samp{ultrasparc},
+@samp{ultrasparc3}, and @samp{niagara}.
@item -mv8plus
@itemx -mno-v8plus
@item -fargument-alias
@itemx -fargument-noalias
@itemx -fargument-noalias-global
+@itemx -fargument-noalias-anything
@opindex fargument-alias
@opindex fargument-noalias
@opindex fargument-noalias-global
+@opindex fargument-noalias-anything
Specify the possible relationships among parameters and between
parameters and global data.
each other, but may alias global storage.@*
@option{-fargument-noalias-global} specifies that arguments do not
alias each other and do not alias global storage.
+@option{-fargument-noalias-anything} specifies that arguments do not
+alias any other storage.
Each language will automatically use whatever option is required by
the language standard. You should not need to use these options yourself.
Note that due to ISO C++ specification requirements, operator new and
operator delete must always be of default visibility.
+Be aware that headers from outside your project, in particular system
+headers and headers from any other library you use, may not be
+expecting to be compiled with visibility other than the default. You
+may need to explicitly say @samp{#pragma GCC visibility push(default)}
+before including any such headers.
+
An overview of these techniques, their benefits and how to use them
is at @w{@uref{http://gcc.gnu.org/wiki/Visibility}}.
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