-Werror -Werror-implicit-function-declaration @gol
-Wfloat-equal -Wformat -Wformat=2 @gol
-Wno-format-extra-args -Wformat-nonliteral @gol
--Wformat-security -Wno-format-y2k @gol
+-Wformat-security -Wformat-y2k @gol
-Wimplicit -Wimplicit-function-declaration -Wimplicit-int @gol
-Wimport -Wno-import -Winit-self -Winline @gol
-Wno-invalid-offsetof -Winvalid-pch @gol
-fsched-stalled-insns=@var{n} -sched-stalled-insns-dep=@var{n} @gol
-fsched2-use-superblocks @gol
-fsched2-use-traces -fsignaling-nans @gol
--fsingle-precision-constant -fssa -fssa-ccp -fssa-dce @gol
+-fsingle-precision-constant @gol
-fstrength-reduce -fstrict-aliasing -ftracer -fthread-jumps @gol
-funroll-all-loops -funroll-loops -fpeel-loops @gol
-funswitch-loops -fold-unroll-loops -fold-unroll-all-loops @gol
@gccoptlist{-m68000 -m68020 -m68020-40 -m68020-60 -m68030 -m68040 @gol
-m68060 -mcpu32 -m5200 -m68881 -mbitfield -mc68000 -mc68020 @gol
-mnobitfield -mrtd -mshort -msoft-float -mpcrel @gol
--malign-int -mstrict-align}
+-malign-int -mstrict-align -msep-data -mno-sep-data @gol
+-mshared-library-id=n -mid-shared-library -mno-id-shared-library}
@emph{M68hc1x Options}
@gccoptlist{-m6811 -m6812 -m68hc11 -m68hc12 -m68hcs12 @gol
compilation. This also enforces the coding style convention
that methods and selectors must be declared before being used.
-@c not documented because only avail via -Wp
-@c @item -print-objc-runtime-info
+@item -print-objc-runtime-info
+@opindex -print-objc-runtime-info
+Generate C header describing the largest structure that is passed by
+value, if any.
@end table
several functions, @option{-Wformat} also implies @option{-Wnonnull}.
@option{-Wformat} is included in @option{-Wall}. For more control over some
-aspects of format checking, the options @option{-Wno-format-y2k},
+aspects of format checking, the options @option{-Wformat-y2k},
@option{-Wno-format-extra-args}, @option{-Wno-format-zero-length},
@option{-Wformat-nonliteral}, @option{-Wformat-security}, and
@option{-Wformat=2} are available, but are not included in @option{-Wall}.
-@item -Wno-format-y2k
-@opindex Wno-format-y2k
-If @option{-Wformat} is specified, do not warn about @code{strftime}
+@item -Wformat-y2k
+@opindex Wformat-y2k
+If @option{-Wformat} is specified, also warn about @code{strftime}
formats which may yield only a two-digit year.
@item -Wno-format-extra-args
@opindex Wformat=2
Enable @option{-Wformat} plus format checks not included in
@option{-Wformat}. Currently equivalent to @samp{-Wformat
--Wformat-nonliteral -Wformat-security}.
+-Wformat-nonliteral -Wformat-security -Wformat-y2k}.
@item -Wnonnull
@opindex Wnonnull
the @var{dumpname}. @var{dumpname} is generated from the name of the
output file, if explicitly specified and it is not an executable,
otherwise it is the basename of the source file. In both cases any
-suffix is removed (e.g. @file{foo.00.rtl} or @file{foo.01.sibling}).
+suffix is removed (e.g. @file{foo.01.rtl} or @file{foo.02.sibling}).
Here are the possible letters for use in @var{letters}, and their
meanings:
Annotate the assembler output with miscellaneous debugging information.
@item b
@opindex db
-Dump after computing branch probabilities, to @file{@var{file}.16.bp}.
+Dump after computing branch probabilities, to @file{@var{file}.12.bp}.
@item B
@opindex dB
-Dump after block reordering, to @file{@var{file}.32.bbro}.
+Dump after block reordering, to @file{@var{file}.30.bbro}.
@item c
@opindex dc
-Dump after instruction combination, to the file @file{@var{file}.22.combine}.
+Dump after instruction combination, to the file @file{@var{file}.20.combine}.
@item C
@opindex dC
-Dump after the first if conversion, to the file @file{@var{file}.17.ce1}.
-Also dump after the second if conversion, to the file @file{@var{file}.23.ce2}.
+Dump after the first if conversion, to the file @file{@var{file}.14.ce1}.
+Also dump after the second if conversion, to the file @file{@var{file}.21.ce2}.
@item d
@opindex dd
-Dump after branch target load optimization, to to @file{@var{file}.34.btl}.
-Also dump after delayed branch scheduling, to @file{@var{file}.37.dbr}.
+Dump after branch target load optimization, to to @file{@var{file}.32.btl}.
+Also dump after delayed branch scheduling, to @file{@var{file}.36.dbr}.
@item D
@opindex dD
Dump all macro definitions, at the end of preprocessing, in addition to
normal output.
-@item e
-@opindex de
-Dump after SSA optimizations, to @file{@var{file}.05.ssa} and
-@file{@var{file}.010.ussa}.
@item E
@opindex dE
-Dump after the second if conversion, to @file{@var{file}.33.ce3}.
+Dump after the second if conversion, to @file{@var{file}.31.ce3}.
@item f
@opindex df
-Dump after control and data flow analysis, to @file{@var{file}.15.cfg}.
-Also dump after life analysis, to @file{@var{file}.21.life}.
+Dump after control and data flow analysis, to @file{@var{file}.11.cfg}.
+Also dump after life analysis, to @file{@var{file}.19.life}.
@item F
@opindex dF
-Dump after purging @code{ADDRESSOF} codes, to @file{@var{file}.11.addressof}.
+Dump after purging @code{ADDRESSOF} codes, to @file{@var{file}.07.addressof}.
@item g
@opindex dg
-Dump after global register allocation, to @file{@var{file}.27.greg}.
+Dump after global register allocation, to @file{@var{file}.25.greg}.
@item G
@opindex dG
-Dump after GCSE, to @file{@var{file}.12.gcse}.
+Dump after GCSE, to @file{@var{file}.08.gcse}.
Also dump after jump bypassing and control flow optimizations, to
-@file{@var{file}.14.bypass}.
+@file{@var{file}.10.bypass}.
@item h
@opindex dh
Dump after finalization of EH handling code, to @file{@var{file}.03.eh}.
Dump after the first jump optimization, to @file{@var{file}.04.jump}.
@item k
@opindex dk
-Dump after conversion from registers to stack, to @file{@var{file}.36.stack}.
+Dump after conversion from registers to stack, to @file{@var{file}.34.stack}.
@item l
@opindex dl
-Dump after local register allocation, to @file{@var{file}.26.lreg}.
+Dump after local register allocation, to @file{@var{file}.24.lreg}.
@item L
@opindex dL
-Dump after loop optimization passes, to @file{@var{file}.13.loop} and
-@file{@var{file}.19.loop2}.
+Dump after loop optimization passes, to @file{@var{file}.09.loop} and
+@file{@var{file}.16.loop2}.
@item M
@opindex dM
Dump after performing the machine dependent reorganization pass, to
-@file{@var{file}.37.mach}.
+@file{@var{file}.35.mach}.
@item n
@opindex dn
-Dump after register renumbering, to @file{@var{file}.31.rnreg}.
+Dump after register renumbering, to @file{@var{file}.29.rnreg}.
@item N
@opindex dN
-Dump after the register move pass, to @file{@var{file}.24.regmove}.
+Dump after the register move pass, to @file{@var{file}.22.regmove}.
@item o
@opindex do
-Dump after post-reload optimizations, to @file{@var{file}.28.postreload}.
+Dump after post-reload optimizations, to @file{@var{file}.26.postreload}.
@item r
@opindex dr
Dump after RTL generation, to @file{@var{file}.01.rtl}.
@item R
@opindex dR
-Dump after the second scheduling pass, to @file{@var{file}.35.sched2}.
+Dump after the second scheduling pass, to @file{@var{file}.33.sched2}.
@item s
@opindex ds
Dump after CSE (including the jump optimization that sometimes follows
-CSE), to @file{@var{file}.019.cse}.
+CSE), to @file{@var{file}.06.cse}.
@item S
@opindex dS
-Dump after the first scheduling pass, to @file{@var{file}.25.sched}.
+Dump after the first scheduling pass, to @file{@var{file}.23.sched}.
@item t
@opindex dt
Dump after the second CSE pass (including the jump optimization that
-sometimes follows CSE), to @file{@var{file}.20.cse2}.
+sometimes follows CSE), to @file{@var{file}.18.cse2}.
@item T
@opindex dT
-Dump after running tracer, to @file{@var{file}.18.tracer}.
+Dump after running tracer, to @file{@var{file}.15.tracer}.
@item u
@opindex du
-Dump after null pointer elimination pass to @file{@var{file}.018.null}.
+Dump after null pointer elimination pass to @file{@var{file}.05.null}.
@item U
@opindex dU
Dump callgraph and unit-at-a-time optimization @file{@var{file}.00.unit}.
+@item V
+@opindex dV
+Dump after the value profile transformations, to @file{@var{file}.13.vpt}.
@item w
@opindex dw
-Dump after the second flow pass, to @file{@var{file}.29.flow2}.
-@item W
-@opindex dW
-Dump after SSA conditional constant propagation, to
-@file{@var{file}.06.ssaccp}.
-@item X
-@opindex dX
-Dump after SSA dead code elimination, to @file{@var{file}.07.ssadce}.
+Dump after the second flow pass, to @file{@var{file}.27.flow2}.
@item z
@opindex dz
-Dump after the peephole pass, to @file{@var{file}.30.peephole2}.
+Dump after the peephole pass, to @file{@var{file}.28.peephole2}.
+@item Z
+@opindex dZ
+Dump after constructing the web, to @file{@var{file}.17.web}.
@item a
@opindex da
Produce all the dumps listed above.
-fpeephole2 @gol
-freorder-blocks -freorder-functions @gol
-fstrict-aliasing @gol
--funit-at-a-time -fweb @gol
+-funit-at-a-time @gol
-falign-functions -falign-jumps @gol
-falign-loops -falign-labels}
as follows:
@table @gcctabopt
- @item max-inline-insns
- is set to @var{n}.
@item max-inline-insns-single
is set to @var{n}/2.
@item max-inline-insns-auto
is set to @var{n}.
@end table
-Using @option{-finline-limit=600} thus results in the default settings
-for these parameters. See below for a documentation of the individual
+See below for a documentation of the individual
parameters controlling inlining.
@emph{Note:} pseudo instruction represents, in this particular context, an
specify this option and you may have problems with debugging if
you specify both this option and @option{-g}.
-@item -fssa
-@opindex fssa
-Perform optimizations in static single assignment form. Each function's
-flow graph is translated into SSA form, optimizations are performed, and
-the flow graph is translated back from SSA form. Users should not
-specify this option, since it is not yet ready for production use.
-
-@item -fssa-ccp
-@opindex fssa-ccp
-Perform Sparse Conditional Constant Propagation in SSA form. Requires
-@option{-fssa}. Like @option{-fssa}, this is an experimental feature.
-
-@item -fssa-dce
-@opindex fssa-dce
-Perform aggressive dead-code elimination in SSA form. Requires @option{-fssa}.
-Like @option{-fssa}, this is an experimental feature.
-
@item -fbranch-target-load-optimize
@opindex fbranch-target-load-optimize
Perform branch target register load optimization before prologue / epilogue
Perform branch target register load optimization after prologue / epilogue
threading.
-
-
-
@item --param @var{name}=@var{value}
@opindex param
In some places, GCC uses various constants to control the amount of
be applied.
The default value is 150.
-@item max-inline-insns
-The tree inliner does decrease the allowable size for single functions
-to be inlined after we already inlined the number of instructions
-given here by repeated inlining. This number should be a factor of
-two or more larger than the single function limit.
-Higher numbers result in better runtime performance, but incur higher
-compile-time resource (CPU time, memory) requirements and result in
-larger binaries. Very high values are not advisable, as too large
-binaries may adversely affect runtime performance.
-The default value is 200.
-
-@item max-inline-slope
-After exceeding the maximum number of inlined instructions by repeated
-inlining, a linear function is used to decrease the allowable size
-for single functions. The slope of that function is the negative
-reciprocal of the number specified here.
-This parameter is ignored when @option{-funit-at-a-time} is used.
-The default value is 32.
-
-@item min-inline-insns
-The repeated inlining is throttled more and more by the linear function
-after exceeding the limit. To avoid too much throttling, a minimum for
-this function is specified here to allow repeated inlining for very small
-functions even when a lot of repeated inlining already has been done.
-This parameter is ignored when @option{-funit-at-a-time} is used.
-The default value is 10.
-
@item large-function-insns
The limit specifying really large functions. For functions greater than this
limit inlining is constrained by @option{--param large-function-growth}.
in RTL instructions) for the RTL inliner with this parameter.
The default value is 600.
-
@item max-unrolled-insns
The maximum number of instructions that a loop should have if that loop
is unrolled, and if the loop is unrolled, it determines how many times
Do not (do) assume that unaligned memory references will be handled by
the system.
+@item -msep-data
+Generate code that allows the data segment to be located in a different
+area of memory from the text segment. This allows for execute in place in
+an environment without virtual memory management. This option implies -fPIC.
+
+@item -mno-sep-data
+Generate code that assumes that the data segment follows the text segment.
+This is the default.
+
+@item -mid-shared-library
+Generate code that supports shared libraries via the library ID method.
+This allows for execute in place and shared libraries in an environment
+without virtual memory management. This option implies -fPIC.
+
+@item -mno-id-shared-library
+Generate code that doesn't assume ID based shared libraries are being used.
+This is the default.
+
+@item -mshared-library-id=n
+Specified the identification number of the ID based shared library being
+compiled. Specifying a value of 0 will generate more compact code, specifying
+other values will force the allocation of that number to the current
+library but is no more space or time efficient than omitting this option.
+
@end table
@node M68hc1x Options
@samp{arm7500}, @samp{arm7500fe}, @samp{arm7tdmi}, @samp{arm8},
@samp{strongarm}, @samp{strongarm110}, @samp{strongarm1100},
@samp{arm8}, @samp{arm810}, @samp{arm9}, @samp{arm9e}, @samp{arm920},
-@samp{arm920t}, @samp{arm940t}, @samp{arm9tdmi}, @samp{arm10tdmi},
-@samp{arm1020t}, @samp{xscale}, @samp{iwmmxt}, @samp{ep9312}.
+@samp{arm920t}, @samp{arm926ejs}, @samp{arm940t}, @samp{arm9tdmi},
+@samp{arm10tdmi}, @samp{arm1020t}, @samp{arm1026ejs},
+@samp{arm1136js}, @samp{arm1136jfs} ,@samp{xscale}, @samp{iwmmxt},
+@samp{ep9312}.
@itemx -mtune=@var{name}
@opindex mtune
assembly code. This option can be used in conjunction with or instead
of the @option{-mcpu=} option. Permissible names are: @samp{armv2},
@samp{armv2a}, @samp{armv3}, @samp{armv3m}, @samp{armv4}, @samp{armv4t},
-@samp{armv5}, @samp{armv5t}, @samp{armv5te}, @samp{iwmmxt}, @samp{ep9312}.
+@samp{armv5}, @samp{armv5t}, @samp{armv5te}, @samp{armv6j},
+@samp{iwmmxt}, @samp{ep9312}.
@item -mfpe=@var{number}
@itemx -mfp=@var{number}
Supported values for @var{cpu_type} are @samp{rios}, @samp{rios1},
@samp{rsc}, @samp{rios2}, @samp{rs64a}, @samp{601}, @samp{602},
@samp{603}, @samp{603e}, @samp{604}, @samp{604e}, @samp{620},
-@samp{630}, @samp{740}, @samp{7400}, @samp{7450}, @samp{750},
-@samp{power}, @samp{power2}, @samp{powerpc}, @samp{403}, @samp{505},
-@samp{801}, @samp{821}, @samp{823}, and @samp{860} and @samp{common}.
+@samp{630}, @samp{740}, @samp{7400}, @samp{7450}, @samp{G4},
+@samp{750}, @samp{G3}, @samp{power}, @samp{power2}, @samp{powerpc},
+@samp{403}, @samp{505}, @samp{801}, @samp{821}, @samp{823}, @samp{860},
+@samp{970}, @samp{G5} and @samp{common}.
@option{-mcpu=common} selects a completely generic processor. Code
generated under this option will run on any POWER or PowerPC processor.
@itemx 740
@itemx 7400
@itemx 7450
+@itemx G4
@itemx 750
+@itemx G3
@itemx 505
+@itemx 970
+@itemx G5
@option{-mno-power}, @option{-mpowerpc}, @option{-mnew-mnemonics}
@item 601
@opindex mrelax
Shorten some address references at link time, when possible; uses the
linker option @option{-relax}. @xref{H8/300,, @code{ld} and the H8/300,
-ld.info, Using ld}, for a fuller description.
+ld, Using ld}, for a fuller description.
@item -mh
@opindex mh
A precompiled header file will be searched for when @code{#include} is
seen in the compilation. As it searches for the included file
-(@pxref{Search Path,,Search Path,cpp.info,The C Preprocessor}) the
+(@pxref{Search Path,,Search Path,cpp,The C Preprocessor}) the
compiler looks for a precompiled header in each directory just before it
looks for the include file in that directory. The name searched for is
the name specified in the @code{#include} with @samp{.gch} appended. If
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