-;;- Machine description for Hitachi / SuperH SH.
-;; Copyright (C) 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003
-;; Free Software Foundation, Inc.
+;;- Machine description for Renesas / SuperH SH.
+;; Copyright (C) 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
+;; 2003, 2004 Free Software Foundation, Inc.
;; Contributed by Steve Chamberlain (sac@cygnus.com).
;; Improved by Jim Wilson (wilson@cygnus.com).
-;; This file is part of GNU CC.
+;; This file is part of GCC.
-;; GNU CC is free software; you can redistribute it and/or modify
+;; GCC is free software; you can redistribute it and/or modify
;; it under the terms of the GNU General Public License as published by
;; the Free Software Foundation; either version 2, or (at your option)
;; any later version.
-;; GNU CC is distributed in the hope that it will be useful,
+;; GCC is distributed in the hope that it will be useful,
;; but WITHOUT ANY WARRANTY; without even the implied warranty of
;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
;; GNU General Public License for more details.
;; You should have received a copy of the GNU General Public License
-;; along with GNU CC; see the file COPYING. If not, write to
+;; along with GCC; see the file COPYING. If not, write to
;; the Free Software Foundation, 59 Temple Place - Suite 330,
;; Boston, MA 02111-1307, USA.
(UNSPEC_NSB 17)
(UNSPEC_ALLOCO 18)
(UNSPEC_EH_RETURN 19)
+ (UNSPEC_TLSGD 20)
+ (UNSPEC_TLSLDM 21)
+ (UNSPEC_TLSIE 22)
+ (UNSPEC_DTPOFF 23)
+ (UNSPEC_GOTTPOFF 24)
+ (UNSPEC_TPOFF 25)
+ (UNSPEC_RA 26)
;; These are used with unspec_volatile.
(UNSPECV_BLOCKAGE 0)
(UNSPECV_CONST8 6)
(UNSPECV_WINDOW_END 10)
(UNSPECV_CONST_END 11)
-])
+])
;; -------------------------------------------------------------------------
;; Attributes
;; Target CPU.
(define_attr "cpu"
- "sh1,sh2,sh2e,sh3,sh3e,sh4,sh5"
+ "sh1,sh2,sh2e,sh2a,sh3,sh3e,sh4,sh4a,sh5"
(const (symbol_ref "sh_cpu_attr")))
(define_attr "endian" "big,little"
;; ftrc_s fix_truncsfsi2_i4
;; dfdiv double precision floating point divide (or square root)
;; cwb ic_invalidate_line_i
+;; movua SH4a unaligned load
+;; fsrra square root reciprocal approximate
+;; fsca sine and cosine approximate
+;; tls_load load TLS related address
;; arith_media SHmedia arithmetic, logical, and shift instructions
;; cbranch_media SHmedia conditional branch instructions
;; cmp_media SHmedia compare instructions
;; nil no-op move, will be deleted.
(define_attr "type"
- "mt_group,cbranch,jump,jump_ind,arith,arith3,arith3b,dyn_shift,load,load_si,fload,store,move,fmove,smpy,dmpy,return,pload,prset,pstore,prget,pcload,pcload_si,pcfload,rte,sfunc,call,fp,fdiv,ftrc_s,dfp_arith,dfp_cmp,dfp_conv,dfdiv,gp_fpul,fpul_gp,mac_gp,mem_fpscr,gp_fpscr,cwb,arith_media,cbranch_media,cmp_media,dfdiv_media,dfmul_media,dfparith_media,dfpconv_media,dmpy_media,fcmp_media,fdiv_media,fload_media,fmove_media,fparith_media,fpconv_media,fstore_media,gettr_media,invalidate_line_media,jump_media,load_media,pt_media,ptabs_media,store_media,mcmp_media,mac_media,d2mpy_media,atrans_media,ustore_media,nil,other"
+ "mt_group,cbranch,jump,jump_ind,arith,arith3,arith3b,dyn_shift,load,load_si,fload,store,move,fmove,smpy,dmpy,return,pload,prset,pstore,prget,pcload,pcload_si,pcfload,rte,sfunc,call,fp,fdiv,ftrc_s,dfp_arith,dfp_cmp,dfp_conv,dfdiv,gp_fpul,fpul_gp,mac_gp,mem_fpscr,gp_fpscr,cwb,movua,fsrra,fsca,tls_load,arith_media,cbranch_media,cmp_media,dfdiv_media,dfmul_media,dfparith_media,dfpconv_media,dmpy_media,fcmp_media,fdiv_media,fload_media,fmove_media,fparith_media,fpconv_media,fstore_media,gettr_media,invalidate_line_media,jump_media,load_media,pt_media,ptabs_media,store_media,mcmp_media,mac_media,d2mpy_media,atrans_media,ustore_media,nil,other"
(const_string "other"))
;; We define a new attribute namely "insn_class".We use
(define_attr "fp_mode" "single,double,none" (const_string "none"))
+;; Indicate if the fpu mode is set by this instruction
+;; "unknown" must have the value as "none" in fp_mode, and means
+;; that the instruction/abi has left the processor in an unknown
+;; state.
+;; "none" means that nothing has changed and no mode is set.
+;; This attribute is only used for the Renesas ABI.
+(define_attr "fp_set" "single,double,unknown,none" (const_string "none"))
+
; If a conditional branch destination is within -252..258 bytes away
; from the instruction it can be 2 bytes long. Something in the
; range -4090..4100 bytes can be 6 bytes long. All other conditional
(eq_attr "type" "jump")
(cond [(eq_attr "med_branch_p" "yes")
(const_int 2)
- (and (eq (symbol_ref "GET_CODE (PREV_INSN (insn))")
- (symbol_ref "INSN"))
- (eq (symbol_ref "INSN_CODE (PREV_INSN (insn))")
- (symbol_ref "code_for_indirect_jump_scratch")))
- (if_then_else (eq_attr "braf_branch_p" "yes")
- (const_int 6)
- (const_int 10))
+ (and (eq (symbol_ref "GET_CODE (prev_nonnote_insn (insn))")
+ (symbol_ref "INSN"))
+ (eq (symbol_ref "INSN_CODE (prev_nonnote_insn (insn))")
+ (symbol_ref "code_for_indirect_jump_scratch")))
+ (cond [(eq_attr "braf_branch_p" "yes")
+ (const_int 6)
+ (eq (symbol_ref "flag_pic") (const_int 0))
+ (const_int 10)
+ (ne (symbol_ref "TARGET_SH2") (const_int 0))
+ (const_int 10)] (const_int 18))
(eq_attr "braf_branch_p" "yes")
(const_int 10)
;; ??? using pc is not computed transitively.
(const_int 4)
(const_int 2))))
-;; (define_function_unit {name} {num-units} {n-users} {test}
-;; {ready-delay} {issue-delay} [{conflict-list}])
-
-;; Load and store instructions save a cycle if they are aligned on a
-;; four byte boundary. Using a function unit for stores encourages
-;; gcc to separate load and store instructions by one instruction,
-;; which makes it more likely that the linker will be able to word
-;; align them when relaxing.
-
-;; Loads have a latency of two.
-;; However, call insns can have a delay slot, so that we want one more
-;; insn to be scheduled between the load of the function address and the call.
-;; This is equivalent to a latency of three.
-;; We cannot use a conflict list for this, because we need to distinguish
-;; between the actual call address and the function arguments.
-;; ADJUST_COST can only properly handle reductions of the cost, so we
-;; use a latency of three here.
-;; We only do this for SImode loads of general registers, to make the work
-;; for ADJUST_COST easier.
-(define_function_unit "memory" 1 0
- (and (eq_attr "pipe_model" "sh1")
- (eq_attr "type" "load_si,pcload_si"))
- 3 2)
-(define_function_unit "memory" 1 0
- (and (eq_attr "pipe_model" "sh1")
- (eq_attr "type" "load,pcload,pload,store,pstore"))
- 2 2)
-
-(define_function_unit "int" 1 0
- (and (eq_attr "pipe_model" "sh1") (eq_attr "type" "arith3,arith3b")) 3 3)
-
-(define_function_unit "int" 1 0
- (and (eq_attr "pipe_model" "sh1") (eq_attr "type" "dyn_shift")) 2 2)
-
-(define_function_unit "int" 1 0
- (and (eq_attr "pipe_model" "sh1") (eq_attr "type" "!arith3,arith3b,dyn_shift")) 1 1)
-
-;; ??? These are approximations.
-(define_function_unit "mpy" 1 0
- (and (eq_attr "pipe_model" "sh1") (eq_attr "type" "smpy")) 2 2)
-(define_function_unit "mpy" 1 0
- (and (eq_attr "pipe_model" "sh1") (eq_attr "type" "dmpy")) 3 3)
-
-(define_function_unit "fp" 1 0
- (and (eq_attr "pipe_model" "sh1") (eq_attr "type" "fp,fmove")) 2 1)
-(define_function_unit "fp" 1 0
- (and (eq_attr "pipe_model" "sh1") (eq_attr "type" "fdiv")) 13 12)
-
-
-;; SH-5 SHmedia scheduling
-;; When executing SHmedia code, the SH-5 is a fairly straightforward
-;; single-issue machine. It has four pipelines, the branch unit (br),
-;; the integer and multimedia unit (imu), the load/store unit (lsu), and
-;; the floating point unit (fpu).
-;; Here model the instructions with a latency greater than one cycle.
-
-;; Every instruction on SH-5 occupies the issue resource for at least one
-;; cycle.
-(define_function_unit "sh5issue" 1 0
- (and (eq_attr "pipe_model" "sh5media")
- (eq_attr "type" "!pt_media,ptabs_media,invalidate_line_media,dmpy_media,load_media,fload_media,fcmp_media,fmove_media,fparith_media,dfparith_media,fpconv_media,dfpconv_media,dfmul_media,store_media,fstore_media,mcmp_media,mac_media,d2mpy_media,atrans_media,ustore_media")) 1 1)
-
-;; Specify the various types of instruction which have latency > 1
-(define_function_unit "sh5issue" 1 0
- (and (eq_attr "pipe_model" "sh5media")
- (eq_attr "type" "mcmp_media")) 2 1)
-
-(define_function_unit "sh5issue" 1 0
- (and (eq_attr "pipe_model" "sh5media")
- (eq_attr "type" "dmpy_media,load_media,fcmp_media,mac_media")) 3 1)
-;; but see sh_adjust_cost for mac_media exception.
-
-(define_function_unit "sh5issue" 1 0
- (and (eq_attr "pipe_model" "sh5media")
- (eq_attr "type" "fload_media,fmove_media")) 4 1)
-
-(define_function_unit "sh5issue" 1 0
- (and (eq_attr "pipe_model" "sh5media")
- (eq_attr "type" "d2mpy_media")) 4 2)
-
-(define_function_unit "sh5issue" 1 0
- (and (eq_attr "pipe_model" "sh5media")
- (eq_attr "type" "pt_media,ptabs_media")) 5 1)
-
-(define_function_unit "sh5issue" 1 0
- (and (eq_attr "pipe_model" "sh5media")
- (eq_attr "type" "fparith_media,dfparith_media,fpconv_media,dfpconv_media")) 6 1)
-
-(define_function_unit "sh5issue" 1 0
- (and (eq_attr "pipe_model" "sh5media")
- (eq_attr "type" "invalidate_line_media")) 7 7)
-
-(define_function_unit "sh5issue" 1 0
- (and (eq_attr "pipe_model" "sh5media") (eq_attr "type" "dfmul_media")) 9 4)
-
-(define_function_unit "sh5issue" 1 0
- (and (eq_attr "pipe_model" "sh5media") (eq_attr "type" "atrans_media")) 10 5)
-
-;; Floating-point divide and square-root occupy an additional resource,
-;; which is not internally pipelined. However, other instructions
-;; can continue to issue.
-(define_function_unit "sh5fds" 1 0
- (and (eq_attr "pipe_model" "sh5media") (eq_attr "type" "fdiv_media")) 19 19)
-
-(define_function_unit "sh5fds" 1 0
- (and (eq_attr "pipe_model" "sh5media") (eq_attr "type" "dfdiv_media")) 35 35)
-
-; Definitions for filling branch delay slots.
+;; DFA descriptions for the pipelines
+
+(include "sh1.md")
+(include "shmedia.md")
+(include "sh4.md")
+
+;; Definitions for filling delay slots
(define_attr "needs_delay_slot" "yes,no" (const_string "no"))
;; Say that we have annulled true branches, since this gives smaller and
;; faster code when branches are predicted as not taken.
+;; ??? The non-annulled condition should really be "in_delay_slot",
+;; but insns that can be filled in non-annulled get priority over insns
+;; that can only be filled in anulled.
+
(define_delay
(and (eq_attr "type" "cbranch")
(ne (symbol_ref "TARGET_SH2") (const_int 0)))
;; SH2e has a hardware bug that pretty much prohibits the use of
;; annuled delay slots.
- [(eq_attr "in_delay_slot" "yes") (and (eq_attr "cond_delay_slot" "yes")
+ [(eq_attr "cond_delay_slot" "yes") (and (eq_attr "cond_delay_slot" "yes")
(not (eq_attr "cpu" "sh2e"))) (nil)])
\f
;; -------------------------------------------------------------------------
(define_insn ""
[(set (reg:SI T_REG)
(eq:SI (and:SI (match_operand:SI 0 "arith_reg_operand" "z,r")
- (match_operand:SI 1 "arith_operand" "L,r"))
+ (match_operand:SI 1 "arith_operand" "K08,r"))
(const_int 0)))]
"TARGET_SH1"
"tst %1,%0"
(define_insn "cmpeqsi_t"
[(set (reg:SI T_REG)
(eq:SI (match_operand:SI 0 "arith_reg_operand" "r,z,r")
- (match_operand:SI 1 "arith_operand" "N,rI,r")))]
+ (match_operand:SI 1 "arith_operand" "N,rI08,r")))]
"TARGET_SH1"
"@
tst %0,%0
(define_expand "cmpsi"
[(set (reg:SI T_REG)
- (compare (match_operand:SI 0 "arith_operand" "")
+ (compare (match_operand:SI 0 "cmpsi_operand" "")
(match_operand:SI 1 "arith_operand" "")))]
"TARGET_SH1"
"
{
+ if (GET_CODE (operands[0]) == REG && REGNO (operands[0]) == T_REG
+ && GET_CODE (operands[1]) != CONST_INT)
+ operands[0] = copy_to_mode_reg (SImode, operands[0]);
sh_compare_op0 = operands[0];
sh_compare_op1 = operands[1];
DONE;
if ((GET_CODE (operands[1]) == EQ || GET_CODE (operands[1]) == NE)
&& GET_MODE (sh_compare_op0) == DImode
&& sh_compare_op1 == const0_rtx)
- operands[1] = gen_rtx (GET_CODE (operands[1]), VOIDmode,
- sh_compare_op0, sh_compare_op1);
+ operands[1] = gen_rtx_fmt_ee (GET_CODE (operands[1]), VOIDmode,
+ sh_compare_op0, sh_compare_op1);
else
{
rtx tmp;
{
case EQ:
emit_insn (gen_seq (tmp));
- operands[1] = gen_rtx (NE, VOIDmode, tmp, const0_rtx);
+ operands[1] = gen_rtx_NE (VOIDmode, tmp, const0_rtx);
break;
case NE:
emit_insn (gen_seq (tmp));
- operands[1] = gen_rtx (EQ, VOIDmode, tmp, const0_rtx);
+ operands[1] = gen_rtx_EQ (VOIDmode, tmp, const0_rtx);
break;
case GT:
emit_insn (gen_sgt (tmp));
- operands[1] = gen_rtx (NE, VOIDmode, tmp, const0_rtx);
+ operands[1] = gen_rtx_NE (VOIDmode, tmp, const0_rtx);
break;
case LT:
emit_insn (gen_slt (tmp));
- operands[1] = gen_rtx (NE, VOIDmode, tmp, const0_rtx);
+ operands[1] = gen_rtx_NE (VOIDmode, tmp, const0_rtx);
break;
case GE:
emit_insn (gen_slt (tmp));
- operands[1] = gen_rtx (EQ, VOIDmode, tmp, const0_rtx);
+ operands[1] = gen_rtx_EQ (VOIDmode, tmp, const0_rtx);
break;
case LE:
emit_insn (gen_sgt (tmp));
- operands[1] = gen_rtx (EQ, VOIDmode, tmp, const0_rtx);
+ operands[1] = gen_rtx_EQ (VOIDmode, tmp, const0_rtx);
break;
case GTU:
emit_insn (gen_sgtu (tmp));
- operands[1] = gen_rtx (NE, VOIDmode, tmp, const0_rtx);
+ operands[1] = gen_rtx_NE (VOIDmode, tmp, const0_rtx);
break;
case LTU:
emit_insn (gen_sltu (tmp));
- operands[1] = gen_rtx (NE, VOIDmode, tmp, const0_rtx);
+ operands[1] = gen_rtx_NE (VOIDmode, tmp, const0_rtx);
break;
case GEU:
emit_insn (gen_sltu (tmp));
- operands[1] = gen_rtx (EQ, VOIDmode, tmp, const0_rtx);
+ operands[1] = gen_rtx_EQ (VOIDmode, tmp, const0_rtx);
break;
case LEU:
emit_insn (gen_sgtu (tmp));
- operands[1] = gen_rtx (EQ, VOIDmode, tmp, const0_rtx);
+ operands[1] = gen_rtx_EQ (VOIDmode, tmp, const0_rtx);
break;
case UNORDERED:
emit_insn (gen_sunordered (tmp));
- operands[1] = gen_rtx (NE, VOIDmode, tmp, const0_rtx);
+ operands[1] = gen_rtx_NE (VOIDmode, tmp, const0_rtx);
break;
case ORDERED:
emit_insn (gen_sunordered (tmp));
- operands[1] = gen_rtx (EQ, VOIDmode, tmp, const0_rtx);
+ operands[1] = gen_rtx_EQ (VOIDmode, tmp, const0_rtx);
break;
case UNEQ:
(define_insn "*adddi3_media"
[(set (match_operand:DI 0 "arith_reg_operand" "=r,r")
(plus:DI (match_operand:DI 1 "arith_reg_operand" "%r,r")
- (match_operand:DI 2 "arith_operand" "r,P")))]
+ (match_operand:DI 2 "arith_operand" "r,I10")))]
"TARGET_SHMEDIA"
"@
add %1, %2, %0
[(set_attr "type" "arith_media")])
(define_insn "adddi3_compact"
- [(set (match_operand:DI 0 "arith_reg_operand" "=r")
+ [(set (match_operand:DI 0 "arith_reg_operand" "=&r")
(plus:DI (match_operand:DI 1 "arith_reg_operand" "%0")
(match_operand:DI 2 "arith_reg_operand" "r")))
(clobber (reg:SI T_REG))]
(define_insn "addsi3_media"
[(set (match_operand:SI 0 "arith_reg_operand" "=r,r")
(plus:SI (match_operand:SI 1 "extend_reg_operand" "%r,r")
- (match_operand:SI 2 "arith_operand" "r,P")))]
+ (match_operand:SI 2 "arith_operand" "r,I10")))]
"TARGET_SHMEDIA"
"@
add.l %1, %2, %0
(define_insn "*addsi3_compact"
[(set (match_operand:SI 0 "arith_reg_operand" "=r")
(plus:SI (match_operand:SI 1 "arith_operand" "%0")
- (match_operand:SI 2 "arith_operand" "rI")))]
+ (match_operand:SI 2 "arith_operand" "rI08")))]
"TARGET_SH1"
"add %2,%0"
[(set_attr "type" "arith")])
[(set_attr "type" "arith_media")])
(define_insn "subdi3_compact"
- [(set (match_operand:DI 0 "arith_reg_operand" "=r")
+ [(set (match_operand:DI 0 "arith_reg_operand" "=&r")
(minus:DI (match_operand:DI 1 "arith_reg_operand" "0")
(match_operand:DI 2 "arith_reg_operand" "r")))
(clobber (reg:SI T_REG))]
(match_operand:SI 2 "arith_reg_operand" "r"))
(reg:SI T_REG)))
(set (reg:SI T_REG)
- (gtu:SI (minus:SI (match_dup 1) (match_dup 2)) (match_dup 1)))]
+ (gtu:SI (minus:SI (minus:SI (match_dup 1) (match_dup 2))
+ (reg:SI T_REG))
+ (match_dup 1)))]
"TARGET_SH1"
"subc %2,%0"
[(set_attr "type" "arith")])
(define_insn "use_sfunc_addr"
[(set (reg:SI PR_REG)
(unspec:SI [(match_operand:SI 0 "register_operand" "r")] UNSPEC_SFUNC))]
- "TARGET_SH1"
+ "TARGET_SH1 && check_use_sfunc_addr (insn, operands[0])"
""
[(set_attr "length" "0")])
+(define_insn "udivsi3_sh2a"
+ [(set (match_operand:SI 0 "arith_reg_operand" "=r")
+ (udiv:SI (match_operand:SI 1 "arith_reg_operand" "0")
+ (match_operand:SI 2 "arith_reg_operand" "z")))]
+ "TARGET_SH2A"
+ "divu %2,%1"
+ [(set_attr "type" "arith")
+ (set_attr "in_delay_slot" "no")])
+
;; We must use a pseudo-reg forced to reg 0 in the SET_DEST rather than
;; hard register 0. If we used hard register 0, then the next instruction
;; would be a move from hard register 0 to a pseudo-reg. If the pseudo-reg
/* Emit the move of the address to a pseudo outside of the libcall. */
if (TARGET_HARD_SH4 && TARGET_SH2E)
{
- emit_move_insn (operands[3],
- gen_rtx_SYMBOL_REF (SImode, \"__udivsi3_i4\"));
+ emit_move_insn (operands[3], function_symbol (\"__udivsi3_i4\"));
if (TARGET_FPU_SINGLE)
last = gen_udivsi3_i4_single (operands[0], operands[3]);
else
emit_insn (gen_udivsi3_i4_media (operands[0], operands[1], operands[2]));
DONE;
}
+ else if (TARGET_SH2A)
+ {
+ operands[1] = force_reg (SImode, operands[1]);
+ operands[2] = force_reg (SImode, operands[2]);
+ emit_insn (gen_udivsi3_sh2a (operands[0], operands[1], operands[2]));
+ DONE;
+ }
else if (TARGET_SH5)
{
emit_move_insn (operands[3],
- gen_rtx_SYMBOL_REF (Pmode,
- (TARGET_FPU_ANY
- ? \"__udivsi3_i4\"
- : \"__udivsi3\")));
+ function_symbol (TARGET_FPU_ANY
+ ? \"__udivsi3_i4\"
+ : \"__udivsi3\"));
if (TARGET_SHMEDIA)
last = gen_udivsi3_i1_media (operands[0],
}
else
{
- emit_move_insn (operands[3],
- gen_rtx_SYMBOL_REF (SImode, \"__udivsi3\"));
+ emit_move_insn (operands[3], function_symbol (\"__udivsi3\"));
last = gen_udivsi3_i1 (operands[0], operands[3]);
}
first = emit_move_insn (gen_rtx_REG (SImode, 4), operands[1]);
DONE;
}")
+(define_insn "divsi3_sh2a"
+ [(set (match_operand:SI 0 "arith_reg_operand" "=r")
+ (div:SI (match_operand:SI 1 "arith_reg_operand" "0")
+ (match_operand:SI 2 "arith_reg_operand" "z")))]
+ "TARGET_SH2A"
+ "divs %2,%1"
+ [(set_attr "type" "arith")
+ (set_attr "in_delay_slot" "no")])
+
(define_insn "divsi3_i1"
[(set (match_operand:SI 0 "register_operand" "=z")
(div:SI (reg:SI R4_REG) (reg:SI R5_REG)))
/* Emit the move of the address to a pseudo outside of the libcall. */
if (TARGET_HARD_SH4 && TARGET_SH2E)
{
- emit_move_insn (operands[3],
- gen_rtx_SYMBOL_REF (SImode, \"__sdivsi3_i4\"));
+ emit_move_insn (operands[3], function_symbol (\"__sdivsi3_i4\"));
if (TARGET_FPU_SINGLE)
last = gen_divsi3_i4_single (operands[0], operands[3]);
else
last = gen_divsi3_i4 (operands[0], operands[3]);
}
+ else if (TARGET_SH2A)
+ {
+ operands[1] = force_reg (SImode, operands[1]);
+ operands[2] = force_reg (SImode, operands[2]);
+ emit_insn (gen_divsi3_sh2a (operands[0], operands[1], operands[2]));
+ DONE;
+ }
else if (TARGET_SHMEDIA_FPU)
{
operands[1] = force_reg (SImode, operands[1]);
else if (TARGET_SH5)
{
emit_move_insn (operands[3],
- gen_rtx_SYMBOL_REF (Pmode,
- (TARGET_FPU_ANY
- ? \"__sdivsi3_i4\"
- : \"__sdivsi3\")));
+ function_symbol (TARGET_FPU_ANY
+ ? \"__sdivsi3_i4\"
+ : \"__sdivsi3\"));
if (TARGET_SHMEDIA)
last = gen_divsi3_i1_media (operands[0],
}
else
{
- emit_move_insn (operands[3], gen_rtx_SYMBOL_REF (SImode, \"__sdivsi3\"));
+ emit_move_insn (operands[3], function_symbol (\"__sdivsi3\"));
last = gen_divsi3_i1 (operands[0], operands[3]);
}
first = emit_move_insn (gen_rtx_REG (SImode, 4), operands[1]);
"TARGET_SH1"
"")
+(define_insn "mul_r"
+ [(set (match_operand:SI 0 "arith_reg_operand" "=r")
+ (mult:SI (match_operand:SI 1 "arith_reg_operand" "0")
+ (match_operand:SI 2 "arith_reg_operand" "z")))]
+ "TARGET_SH2A"
+ "mulr %2,%0"
+ [(set_attr "type" "dmpy")])
+
(define_insn "mul_l"
[(set (reg:SI MACL_REG)
(mult:SI (match_operand:SI 0 "arith_reg_operand" "r")
{
/* The address must be set outside the libcall,
since it goes into a pseudo. */
- rtx sym = gen_rtx_SYMBOL_REF (SImode, \"__mulsi3\");
+ rtx sym = function_symbol (\"__mulsi3\");
rtx addr = force_reg (SImode, sym);
rtx insns = gen_mulsi3_call (operands[0], operands[1],
operands[2], addr);
(define_insn "*andsi3_compact"
[(set (match_operand:SI 0 "arith_reg_operand" "=r,z")
(and:SI (match_operand:SI 1 "arith_reg_operand" "%0,0")
- (match_operand:SI 2 "logical_operand" "r,L")))]
+ (match_operand:SI 2 "logical_operand" "r,K08")))]
"TARGET_SH1"
"and %2,%0"
[(set_attr "type" "arith")])
(define_insn_and_split "anddi3"
[(set (match_operand:DI 0 "arith_reg_operand" "=r,r,r")
(and:DI (match_operand:DI 1 "arith_reg_operand" "%r,r,r")
- (match_operand:DI 2 "and_operand" "r,P,Z")))]
+ (match_operand:DI 2 "and_operand" "r,I10,J16")))]
"TARGET_SHMEDIA"
"@
and %1, %2, %0
(define_insn "iorsi3"
[(set (match_operand:SI 0 "arith_reg_operand" "=r,z")
(ior:SI (match_operand:SI 1 "arith_reg_operand" "%0,0")
- (match_operand:SI 2 "logical_operand" "r,L")))]
+ (match_operand:SI 2 "logical_operand" "r,K08")))]
"TARGET_SH1"
"or %2,%0"
[(set_attr "type" "arith")])
(define_insn "iordi3"
[(set (match_operand:DI 0 "arith_reg_operand" "=r,r")
(ior:DI (match_operand:DI 1 "arith_reg_operand" "%r,r")
- (match_operand:DI 2 "logical_operand" "r,P")))]
+ (match_operand:DI 2 "logical_operand" "r,I10")))]
"TARGET_SHMEDIA"
"@
or %1, %2, %0
(define_insn "xorsi3"
[(set (match_operand:SI 0 "arith_reg_operand" "=z,r")
(xor:SI (match_operand:SI 1 "arith_reg_operand" "%0,0")
- (match_operand:SI 2 "logical_operand" "L,r")))]
+ (match_operand:SI 2 "logical_operand" "K08,r")))]
"TARGET_SH1"
"xor %2,%0"
[(set_attr "type" "arith")])
(define_insn "xordi3"
[(set (match_operand:DI 0 "arith_reg_operand" "=r,r")
(xor:DI (match_operand:DI 1 "arith_reg_operand" "%r,r")
- (match_operand:DI 2 "shmedia_6bit_operand" "r,O")))]
+ (match_operand:DI 2 "shmedia_6bit_operand" "r,I06")))]
"TARGET_SHMEDIA"
"@
xor %1, %2, %0
"
{
enum machine_mode inmode = GET_MODE (operands[1]);
- int regno, offset = 0;
+ int offset = 0;
if (GET_CODE (operands[0]) == SUBREG)
{
parts[0] = gen_reg_rtx (SImode);
parts[1] = gen_reg_rtx (SImode);
emit_insn (gen_rotlsi3_16 (parts[2-choice], operands[1]));
- parts[choice-1] = operands[1];
+ emit_move_insn (parts[choice-1], operands[1]);
emit_insn (gen_ashlsi3 (parts[0], parts[0], GEN_INT (8)));
emit_insn (gen_lshrsi3 (parts[1], parts[1], GEN_INT (8)));
emit_insn (gen_iorsi3 (operands[0], parts[0], parts[1]));
;;
;; shift left
+(define_insn "ashlsi3_sh2a"
+ [(set (match_operand:SI 0 "arith_reg_operand" "=r")
+ (ashift:SI (match_operand:SI 1 "arith_reg_operand" "0")
+ (match_operand:SI 2 "arith_reg_operand" "r")))]
+ "TARGET_SH2A"
+ "shad %2,%0"
+ [(set_attr "type" "arith")
+ (set_attr "length" "4")])
+
;; This pattern is used by init_expmed for computing the costs of shift
;; insns.
(define_insn_and_split "ashlsi3_std"
[(set (match_operand:SI 0 "arith_reg_operand" "=r,r,r,r")
(ashift:SI (match_operand:SI 1 "arith_reg_operand" "0,0,0,0")
- (match_operand:SI 2 "nonmemory_operand" "r,M,K,?ri")))
+ (match_operand:SI 2 "nonmemory_operand" "r,M,P27,?ri")))
(clobber (match_scratch:SI 3 "=X,X,X,&r"))]
"TARGET_SH3
|| (TARGET_SH1 && GET_CODE (operands[2]) == CONST_INT
- && CONST_OK_FOR_K (INTVAL (operands[2])))"
+ && CONST_OK_FOR_P27 (INTVAL (operands[2])))"
"@
shld %2,%0
add %0,%0
"TARGET_SH3
&& reload_completed
&& GET_CODE (operands[2]) == CONST_INT
- && ! CONST_OK_FOR_K (INTVAL (operands[2]))"
+ && ! CONST_OK_FOR_P27 (INTVAL (operands[2]))"
[(set (match_dup 3) (match_dup 2))
(parallel
[(set (match_dup 0) (ashift:SI (match_dup 1) (match_dup 3)))
(define_insn "ashlhi3_k"
[(set (match_operand:HI 0 "arith_reg_operand" "=r,r")
(ashift:HI (match_operand:HI 1 "arith_reg_operand" "0,0")
- (match_operand:HI 2 "const_int_operand" "M,K")))]
- "TARGET_SH1 && CONST_OK_FOR_K (INTVAL (operands[2]))"
+ (match_operand:HI 2 "const_int_operand" "M,P27")))]
+ "TARGET_SH1 && CONST_OK_FOR_P27 (INTVAL (operands[2]))"
"@
add %0,%0
shll%O2 %0"
; arithmetic shift right
;
+(define_insn "ashrsi3_sh2a"
+ [(set (match_operand:SI 0 "arith_reg_operand" "=r")
+ (ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
+ (neg:SI (match_operand:SI 2 "arith_reg_operand" "r"))))]
+ "TARGET_SH2A"
+ "shad %2,%0"
+ [(set_attr "type" "dyn_shift")
+ (set_attr "length" "4")])
+
(define_insn "ashrsi3_k"
[(set (match_operand:SI 0 "arith_reg_operand" "=r")
(ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
;; logical shift right
+(define_insn "lshrsi3_sh2a"
+ [(set (match_operand:SI 0 "arith_reg_operand" "=r")
+ (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
+ (neg:SI (match_operand:SI 2 "arith_reg_operand" "r"))))]
+ "TARGET_SH2A"
+ "shld %2,%0"
+ [(set_attr "type" "dyn_shift")
+ (set_attr "length" "4")])
+
(define_insn "lshrsi3_d"
[(set (match_operand:SI 0 "arith_reg_operand" "=r")
(lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
(define_insn "lshrsi3_k"
[(set (match_operand:SI 0 "arith_reg_operand" "=r")
(lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
- (match_operand:SI 2 "const_int_operand" "K")))]
- "TARGET_SH1 && CONST_OK_FOR_K (INTVAL (operands[2]))
+ (match_operand:SI 2 "const_int_operand" "P27")))]
+ "TARGET_SH1 && CONST_OK_FOR_P27 (INTVAL (operands[2]))
&& ! CONST_OK_FOR_M (INTVAL (operands[2]))"
"shlr%O2 %0"
[(set_attr "type" "arith")])
operands[1] = XEXP (operands[1], 0);
}")
-;; ??? when a truncated input to a zero_extrend is reloaded, reload will
-;; reload the entrire truncate expression.
+;; ??? when a truncated input to a zero_extend is reloaded, reload will
+;; reload the entire truncate expression.
(define_insn_and_split "*loaddi_trunc"
[(set (match_operand 0 "int_gpr_dest" "=r")
(truncate (match_operand:DI 1 "memory_operand" "m")))]
(define_expand "extendhisi2"
[(set (match_operand:SI 0 "arith_reg_operand" "=r,r")
- (sign_extend:SI (match_operand:HI 1 "general_extend_operand" "r,m")))]
+ (sign_extend:SI (match_operand:HI 1 "general_extend_operand" "r,m")))]
""
"")
"TARGET_SH1"
"@
exts.w %1,%0
- mov.w %1,%0"
+ mov.w %1,%0"
[(set_attr "type" "arith,load")])
(define_insn "*extendhisi2_media"
(truncate:QI (match_operand:DI 1 "register_operand" "r,r")))]
"TARGET_SHMEDIA"
"@
- and %1, 255, %0
+ andi %1, 255, %0
st%M0.b %m0, %1"
[(set_attr "type" "arith_media,store")])
(define_expand "push_fpscr"
[(const_int 0)]
- "TARGET_SH3E"
+ "TARGET_SH2E"
"
{
- rtx insn = emit_insn (gen_fpu_switch (gen_rtx (MEM, PSImode,
- gen_rtx (PRE_DEC, Pmode,
+ rtx insn = emit_insn (gen_fpu_switch (gen_rtx_MEM (PSImode,
+ gen_rtx_PRE_DEC (Pmode,
stack_pointer_rtx)),
get_fpscr_rtx ()));
- REG_NOTES (insn) = gen_rtx (EXPR_LIST, REG_INC, stack_pointer_rtx, NULL_RTX);
+ REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_INC, stack_pointer_rtx, NULL_RTX);
DONE;
}")
(define_expand "pop_fpscr"
[(const_int 0)]
- "TARGET_SH3E"
+ "TARGET_SH2E"
"
{
rtx insn = emit_insn (gen_fpu_switch (get_fpscr_rtx (),
- gen_rtx (MEM, PSImode,
- gen_rtx (POST_INC, Pmode,
+ gen_rtx_MEM (PSImode,
+ gen_rtx_POST_INC (Pmode,
stack_pointer_rtx))));
- REG_NOTES (insn) = gen_rtx (EXPR_LIST, REG_INC, stack_pointer_rtx, NULL_RTX);
+ REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_INC, stack_pointer_rtx, NULL_RTX);
DONE;
}")
;; (set (subreg:SI (mem:QI (plus:SI (reg:SI SP_REG) (const_int 12)) 0) 0)
;; (made from (set (subreg:SI (reg:QI ###) 0) ) into T.
(define_insn "movsi_i"
- [(set (match_operand:SI 0 "general_movdst_operand" "=r,r,t,r,r,r,r,m,<,<,x,l,x,l,r")
- (match_operand:SI 1 "general_movsrc_operand" "Q,rI,r,mr,x,l,t,r,x,l,r,r,>,>,i"))]
+ [(set (match_operand:SI 0 "general_movdst_operand"
+ "=r,r,t,r,r,r,r,m,<,<,x,l,x,l,r")
+ (match_operand:SI 1 "general_movsrc_operand"
+ "Q,rI08,r,mr,x,l,t,r,x,l,r,r,>,>,i"))]
"TARGET_SH1
&& ! TARGET_SH2E
+ && ! TARGET_SH2A
&& (register_operand (operands[0], SImode)
|| register_operand (operands[1], SImode))"
"@
;; ??? We can't include f/f because we need the proper FPSCR setting when
;; TARGET_FMOVD is in effect, and mode switching is done before reload.
(define_insn "movsi_ie"
- [(set (match_operand:SI 0 "general_movdst_operand" "=r,r,t,r,r,r,r,m,<,<,x,l,x,l,y,<,r,y,r,*f,y,*f,y")
- (match_operand:SI 1 "general_movsrc_operand" "Q,rI,r,mr,x,l,t,r,x,l,r,r,>,>,>,y,i,r,y,y,*f,*f,y"))]
- "TARGET_SH2E
+ [(set (match_operand:SI 0 "general_movdst_operand"
+ "=r,r,r,t,r,r,r,r,m,<,<,x,l,x,l,y,<,r,y,r,*f,y,*f,y")
+ (match_operand:SI 1 "general_movsrc_operand"
+ "Q,rI08,I20,r,mr,x,l,t,r,x,l,r,r,>,>,>,y,i,r,y,y,*f,*f,y"))]
+ "(TARGET_SH2E || TARGET_SH2A)
&& (register_operand (operands[0], SImode)
|| register_operand (operands[1], SImode))"
"@
mov.l %1,%0
mov %1,%0
+ movi20 %1,%0
cmp/pl %1
mov.l %1,%0
sts %1,%0
flds %1,fpul
fmov %1,%0
! move optimized away"
- [(set_attr "type" "pcload_si,move,*,load_si,mac_gp,prget,move,store,store,pstore,move,prset,load,pload,load,store,pcload_si,gp_fpul,fpul_gp,fmove,fmove,fmove,nil")
- (set_attr "late_fp_use" "*,*,*,*,*,*,*,*,*,*,*,*,*,*,*,yes,*,*,yes,*,*,*,*")
- (set_attr "length" "*,*,*,*,*,*,*,*,*,*,*,*,*,*,*,*,*,*,*,*,*,*,0")])
+ [(set_attr "type" "pcload_si,move,move,*,load_si,mac_gp,prget,move,store,store,pstore,move,prset,load,pload,load,store,pcload_si,gp_fpul,fpul_gp,fmove,fmove,fmove,nil")
+ (set_attr "late_fp_use" "*,*,*,*,*,*,*,*,*,*,*,*,*,*,*,*,yes,*,*,yes,*,*,*,*")
+ (set_attr "length" "*,*,4,*,4,*,*,*,4,*,*,*,*,*,*,*,*,*,*,*,*,*,*,0")])
(define_insn "movsi_i_lowpart"
[(set (strict_low_part (match_operand:SI 0 "general_movdst_operand" "+r,r,r,r,r,r,m,r"))
- (match_operand:SI 1 "general_movsrc_operand" "Q,rI,mr,x,l,t,r,i"))]
+ (match_operand:SI 1 "general_movsrc_operand" "Q,rI08,mr,x,l,t,r,i"))]
"TARGET_SH1
&& (register_operand (operands[0], SImode)
|| register_operand (operands[1], SImode))"
fake %1,%0"
[(set_attr "type" "pcload,move,load,move,prget,move,store,pcload")])
+(define_insn_and_split "load_ra"
+ [(set (match_operand:SI 0 "general_movdst_operand" "")
+ (unspec:SI [(match_operand 1 "register_operand" "")] UNSPEC_RA))]
+ "TARGET_SH1"
+ "#"
+ "&& ! currently_expanding_to_rtl"
+ [(set (match_dup 0) (match_dup 1))]
+ "
+{
+ if (TARGET_SHCOMPACT && current_function_has_nonlocal_label)
+ operands[1] = gen_rtx_MEM (SImode, return_address_pointer_rtx);
+}")
+
(define_insn "*movsi_media"
- [(set (match_operand:SI 0 "general_movdst_operand" "=r,r,r,r,m,f,m,f,r,f,*b,r,b")
- (match_operand:SI 1 "general_movsrc_operand" "r,JS,ns,m,rU,m,f,rU,f,f,r,*b,T"))]
+ [(set (match_operand:SI 0 "general_movdst_operand"
+ "=r,r,r,r,m,f,m,f,r,f,*b,r,b")
+ (match_operand:SI 1 "general_movsrc_operand"
+ "r,I16C16,nCpg,m,rZ,m,f,rZ,f,f,r,*b,Csy"))]
"TARGET_SHMEDIA_FPU
&& (register_operand (operands[0], SImode)
|| sh_register_operand (operands[1], SImode))"
(set_attr "length" "4,4,8,4,4,4,4,4,4,4,4,4,12")])
(define_insn "*movsi_media_nofpu"
- [(set (match_operand:SI 0 "general_movdst_operand" "=r,r,r,r,m,*b,r,b")
- (match_operand:SI 1 "general_movsrc_operand" "r,JS,ns,m,rU,r,*b,T"))]
+ [(set (match_operand:SI 0 "general_movdst_operand"
+ "=r,r,r,r,m,*b,r,b")
+ (match_operand:SI 1 "general_movsrc_operand"
+ "r,I16C16,nCpg,m,rZ,r,*b,Csy"))]
"TARGET_SHMEDIA
&& (register_operand (operands[0], SImode)
|| sh_register_operand (operands[1], SImode))"
(match_operand:SI 1 "immediate_operand" ""))]
"TARGET_SHMEDIA && reload_completed
&& ((GET_CODE (operands[1]) == CONST_INT
- && ! CONST_OK_FOR_J (INTVAL (operands[1])))
+ && ! CONST_OK_FOR_I16 (INTVAL (operands[1])))
|| GET_CODE (operands[1]) == CONST_DOUBLE)"
[(set (subreg:DI (match_dup 0) 0) (match_dup 1))])
}
else if (TARGET_SHCOMPACT)
{
- operands[1] = gen_rtx_SYMBOL_REF (Pmode, \"__ic_invalidate\");
+ operands[1] = function_symbol (\"__ic_invalidate\");
operands[1] = force_reg (Pmode, operands[1]);
emit_insn (gen_ic_invalidate_line_compact (operands[0], operands[1]));
DONE;
}
+ else if (TARGET_SH4A_ARCH)
+ {
+ emit_insn (gen_ic_invalidate_line_sh4a (operands[0]));
+ DONE;
+ }
operands[0] = force_reg (Pmode, operands[0]);
operands[1] = force_reg (Pmode, GEN_INT (trunc_int_for_mode (0xf0000008,
Pmode)));
[(set_attr "length" "8")
(set_attr "type" "cwb")])
+(define_insn "ic_invalidate_line_sh4a"
+ [(unspec_volatile [(match_operand:SI 0 "register_operand" "r")]
+ UNSPEC_ICACHE)]
+ "TARGET_SH4A_ARCH"
+ "ocbwb\\t@%0\;synco\;icbi\\t@%0"
+ [(set_attr "length" "16")
+ (set_attr "type" "cwb")])
+
;; ??? could make arg 0 an offsettable memory operand to allow to save
;; an add in the code that calculates the address.
(define_insn "ic_invalidate_line_media"
rtx sfun, tramp;
tramp = force_reg (Pmode, operands[0]);
- sfun = force_reg (Pmode, gen_rtx_SYMBOL_REF (Pmode, \"__init_trampoline\"));
+ sfun = force_reg (Pmode, function_symbol (\"__init_trampoline\"));
emit_move_insn (gen_rtx_REG (SImode, R2_REG), operands[1]);
emit_move_insn (gen_rtx_REG (SImode, R3_REG), operands[2]);
(define_insn "*movqi_media"
[(set (match_operand:QI 0 "general_movdst_operand" "=r,r,r,m")
- (match_operand:QI 1 "general_movsrc_operand" "r,JS,m,rU"))]
+ (match_operand:QI 1 "general_movsrc_operand" "r,I16C16,m,rZ"))]
"TARGET_SHMEDIA
&& (arith_reg_operand (operands[0], QImode)
|| arith_reg_or_0_operand (operands[1], QImode))"
[(set (match_operand:SI 2 "" "=&r")
(match_operand:QI 1 "inqhi_operand" ""))
(set (match_operand:QI 0 "arith_reg_operand" "=r")
- (truncate:HI (match_dup 3)))]
+ (truncate:QI (match_dup 3)))]
"TARGET_SHMEDIA"
"
{
operands[3] = gen_rtx_REG (DImode, REGNO (operands[2]));
}")
+/* When storing r0, we have to avoid reg+reg addressing. */
(define_insn "movhi_i"
- [(set (match_operand:HI 0 "general_movdst_operand" "=r,r,r,r,m,r,l,r")
- (match_operand:HI 1 "general_movsrc_operand" "Q,rI,m,t,r,l,r,i"))]
+ [(set (match_operand:HI 0 "general_movdst_operand" "=r,r,r,r,m,r,l,r")
+ (match_operand:HI 1 "general_movsrc_operand" "Q,rI08,m,t,r,l,r,i"))]
"TARGET_SH1
&& (arith_reg_operand (operands[0], HImode)
- || arith_reg_operand (operands[1], HImode))"
+ || arith_reg_operand (operands[1], HImode))
+ && (GET_CODE (operands[0]) != MEM
+ || GET_CODE (XEXP (operands[0], 0)) != PLUS
+ || GET_CODE (XEXP (XEXP (operands[0], 0), 1)) != REG
+ || ! refers_to_regno_p (R0_REG, R0_REG + 1, operands[1], (rtx *)0))"
"@
mov.w %1,%0
mov %1,%0
[(set_attr "type" "pcload,move,load,move,store,move,move,pcload")])
(define_insn "*movhi_media"
- [(set (match_operand:HI 0 "general_movdst_operand" "=r,r,r,r,m")
- (match_operand:HI 1 "general_movsrc_operand" "r,JS,n,m,rU"))]
+ [(set (match_operand:HI 0 "general_movdst_operand" "=r,r,r,r,m")
+ (match_operand:HI 1 "general_movsrc_operand" "r,I16C16,n,m,rZ"))]
"TARGET_SHMEDIA
&& (arith_reg_operand (operands[0], HImode)
|| arith_reg_or_0_operand (operands[1], HImode))"
[(set (match_operand:HI 0 "register_operand" "")
(match_operand:HI 1 "immediate_operand" ""))]
"TARGET_SHMEDIA && reload_completed
- && ! CONST_OK_FOR_J (INTVAL (operands[1]))"
+ && ! CONST_OK_FOR_I16 (INTVAL (operands[1]))"
[(set (subreg:DI (match_dup 0) 0) (match_dup 1))])
(define_expand "movhi"
;; compiled with -m2 -ml -O3 -funroll-loops
(define_insn "*movdi_i"
[(set (match_operand:DI 0 "general_movdst_operand" "=r,r,r,m,r,r,r,*!x")
- (match_operand:DI 1 "general_movsrc_operand" "Q,r,m,r,I,i,x,r"))]
+ (match_operand:DI 1 "general_movsrc_operand" "Q,r,m,r,I08,i,x,r"))]
"TARGET_SH1
&& (arith_reg_operand (operands[0], DImode)
|| arith_reg_operand (operands[1], DImode))"
}")
(define_insn "*movdi_media"
- [(set (match_operand:DI 0 "general_movdst_operand" "=r,r,r,rl,m,f,m,f,r,f,*b,r,b")
- (match_operand:DI 1 "general_movsrc_operand" "r,JS,iF,m,rlU,m,f,rU,f,f,r,*b,T"))]
+ [(set (match_operand:DI 0 "general_movdst_operand"
+ "=r,r,r,rl,m,f,m,f,r,f,*b,r,b")
+ (match_operand:DI 1 "general_movsrc_operand"
+ "r,I16C16,nCpgF,m,rlZ,m,f,rZ,f,f,r,*b,Csy"))]
"TARGET_SHMEDIA_FPU
&& (register_operand (operands[0], DImode)
|| sh_register_operand (operands[1], DImode))"
(define_insn "*movdi_media_nofpu"
[(set (match_operand:DI 0 "general_movdst_operand" "=r,r,r,rl,m,*b,r,b")
- (match_operand:DI 1 "general_movsrc_operand" "r,JS,iF,m,rlU,r,*b,T"))]
+ (match_operand:DI 1 "general_movsrc_operand" "r,I16C16,nCpgF,m,rlZ,r,*b,Csy"))]
"TARGET_SHMEDIA
&& (register_operand (operands[0], DImode)
|| sh_register_operand (operands[1], DImode))"
(match_operand:DI 1 "immediate_operand" ""))]
"TARGET_SHMEDIA && reload_completed
&& GET_CODE (operands[1]) == CONST_INT
- && ! CONST_OK_FOR_J (INTVAL (operands[1]))"
+ && ! CONST_OK_FOR_I16 (INTVAL (operands[1]))"
[(set (match_dup 0) (match_dup 2))
(match_dup 1)]
"
{
/* If we can't generate the constant with a two-insn movi / shori
sequence, try some other strategies. */
- if (! CONST_OK_FOR_J (high))
+ if (! CONST_OK_FOR_I16 (high))
{
/* Try constant load / left shift. We know VAL != 0. */
val2 = val ^ (val-1);
{
int trailing_zeroes = exact_log2 ((val2 >> 16) + 1) + 15;
- if (CONST_OK_FOR_J (val >> trailing_zeroes)
- || (! CONST_OK_FOR_J (high >> 16)
- && CONST_OK_FOR_J (val >> (trailing_zeroes + 16))))
+ if (CONST_OK_FOR_I16 (val >> trailing_zeroes)
+ || (! CONST_OK_FOR_I16 (high >> 16)
+ && CONST_OK_FOR_I16 (val >> (trailing_zeroes + 16))))
{
val2 = (HOST_WIDE_INT) val >> trailing_zeroes;
operands[1] = gen_ashldi3_media (operands[0], operands[0],
int shift = 49 - exact_log2 (val2);
val2 = trunc_int_for_mode (val << shift, DImode);
- if (CONST_OK_FOR_J (val2))
+ if (CONST_OK_FOR_I16 (val2))
{
operands[1] = gen_lshrdi3_media (operands[0], operands[0],
GEN_INT (shift));
}
/* Try movi / mshflo.l */
val2 = (HOST_WIDE_INT) val >> 32;
- if (val2 == trunc_int_for_mode (val, SImode))
+ if (val2 == ((unsigned HOST_WIDE_INT)
+ trunc_int_for_mode (val, SImode)))
{
operands[1] = gen_mshflo_l_di (operands[0], operands[0],
operands[0]);
}
/* Try movi / mshflo.l w/ r63. */
val2 = val + ((HOST_WIDE_INT) -1 << 32);
- if ((HOST_WIDE_INT) val2 < 0 && CONST_OK_FOR_J (val2))
+ if ((HOST_WIDE_INT) val2 < 0 && CONST_OK_FOR_I16 (val2))
{
operands[1] = gen_mshflo_l_di (operands[0], operands[0],
- GEN_INT (0));
+ const0_rtx);
break;
}
}
(const_int 16))
(zero_extend:DI
(truncate:HI
- (match_operand:DI 2 "immediate_operand" "JS,nF")))))]
+ (match_operand:DI 2 "immediate_operand" "I16C16,nF")))))]
"TARGET_SHMEDIA"
"@
shori %u2, %0
(define_insn "movdf_media"
[(set (match_operand:DF 0 "general_movdst_operand" "=f,f,r,r,r,f,m,r,m")
- (match_operand:DF 1 "general_movsrc_operand" "f,rU,f,r,F,m,f,m,rU"))]
+ (match_operand:DF 1 "general_movsrc_operand" "f,rZ,f,r,F,m,f,m,rZ"))]
"TARGET_SHMEDIA_FPU
&& (register_operand (operands[0], DFmode)
|| sh_register_operand (operands[1], DFmode))"
(define_insn "movdf_media_nofpu"
[(set (match_operand:DF 0 "general_movdst_operand" "=r,r,r,m")
- (match_operand:DF 1 "general_movsrc_operand" "r,F,m,rU"))]
+ (match_operand:DF 1 "general_movsrc_operand" "r,F,m,rZ"))]
"TARGET_SHMEDIA
&& (register_operand (operands[0], DFmode)
|| sh_register_operand (operands[1], DFmode))"
[(set (match_operand:DF 0 "general_movdst_operand" "=r,r,r,m")
(match_operand:DF 1 "general_movsrc_operand" "r,FQ,m,r"))]
"TARGET_SH1
- && (! TARGET_SH4 || reload_completed
+ && (! (TARGET_SH4 || TARGET_SH2A_DOUBLE) || reload_completed
/* ??? We provide some insn so that direct_{load,store}[DFmode] get set */
|| (GET_CODE (operands[0]) == REG && REGNO (operands[0]) == 3)
|| (GET_CODE (operands[1]) == REG && REGNO (operands[1]) == 3))
(match_operand:DF 1 "general_movsrc_operand" "d,r,F,m,d,FQ,m,r,d,r"))
(use (match_operand:PSI 2 "fpscr_operand" "c,c,c,c,c,c,c,c,c,c"))
(clobber (match_scratch:SI 3 "=X,X,&z,X,X,X,X,X,X,X"))]
- "TARGET_SH4
+ "(TARGET_SH4 || TARGET_SH2A_DOUBLE)
&& (arith_reg_operand (operands[0], DFmode)
|| arith_reg_operand (operands[1], DFmode))"
"@
[(if_then_else (eq_attr "fmovd" "yes") (const_int 2) (const_int 4))
(const_int 4)
(if_then_else (eq_attr "fmovd" "yes") (const_int 4) (const_int 6))
- (if_then_else (eq_attr "fmovd" "yes") (const_int 2) (const_int 6))
- (if_then_else (eq_attr "fmovd" "yes") (const_int 2) (const_int 6))
+ (if_then_else (eq_attr "fmovd" "yes") (const_int 4) (const_int 6))
+ (if_then_else (eq_attr "fmovd" "yes") (const_int 4) (const_int 6))
(const_int 4)
(const_int 8) (const_int 8) ;; these need only 8 bytes for @(r0,rn)
;; We can't use 4-byte push/pop on SHcompact, so we have to
(match_operand:DF 1 "register_operand" ""))
(use (match_operand:PSI 2 "fpscr_operand" ""))
(clobber (match_scratch:SI 3 "=X"))]
- "TARGET_SH4 && reload_completed
+ "(TARGET_SH4 || TARGET_SH2A_DOUBLE) && reload_completed
&& (true_regnum (operands[0]) < 16) != (true_regnum (operands[1]) < 16)"
[(const_int 0)]
"
tos = gen_rtx_MEM (DFmode, stack_pointer_rtx);
}
else
- tos = gen_rtx (MEM, DFmode, gen_rtx (PRE_DEC, Pmode, stack_pointer_rtx));
+ tos = gen_rtx_MEM (DFmode, gen_rtx_PRE_DEC (Pmode, stack_pointer_rtx));
insn = emit_insn (gen_movdf_i4 (tos, operands[1], operands[2]));
if (! (TARGET_SH5 && true_regnum (operands[1]) < 16))
- REG_NOTES (insn) = gen_rtx (EXPR_LIST, REG_INC, stack_pointer_rtx, NULL_RTX);
+ REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_INC, stack_pointer_rtx, NULL_RTX);
if (TARGET_SH5 && true_regnum (operands[0]) < 16)
tos = gen_rtx_MEM (DFmode, stack_pointer_rtx);
else
- tos = gen_rtx (MEM, DFmode, gen_rtx (POST_INC, Pmode, stack_pointer_rtx));
+ tos = gen_rtx_MEM (DFmode, gen_rtx_POST_INC (Pmode, stack_pointer_rtx));
insn = emit_insn (gen_movdf_i4 (operands[0], tos, operands[2]));
if (TARGET_SH5 && true_regnum (operands[0]) < 16)
emit_move_insn (stack_pointer_rtx, plus_constant (stack_pointer_rtx, 8));
else
- REG_NOTES (insn) = gen_rtx (EXPR_LIST, REG_INC, stack_pointer_rtx, NULL_RTX);
+ REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_INC, stack_pointer_rtx, NULL_RTX);
DONE;
}")
(match_operand:DF 1 "general_movsrc_operand" ""))
(use (match_operand:PSI 2 "fpscr_operand" ""))
(clobber (match_scratch:SI 3 ""))]
- "TARGET_SH4
+ "(TARGET_SH4 || TARGET_SH2A_DOUBLE)
&& reload_completed
&& true_regnum (operands[0]) < 16
&& true_regnum (operands[1]) < 16"
&& GET_CODE (XEXP (addr, 1)) == REG)
{
int offset;
- rtx reg0 = gen_rtx (REG, Pmode, 0);
+ rtx reg0 = gen_rtx_REG (Pmode, 0);
rtx regop = operands[store_p], word0 ,word1;
if (GET_CODE (regop) == SUBREG)
offset = 4;
mem = copy_rtx (mem);
PUT_MODE (mem, SImode);
- word0 = gen_rtx (SUBREG, SImode, regop, 0);
+ word0 = gen_rtx_SUBREG (SImode, regop, 0);
alter_subreg (&word0);
- word1 = gen_rtx (SUBREG, SImode, regop, 4);
+ word1 = gen_rtx_SUBREG (SImode, regop, 4);
alter_subreg (&word1);
if (store_p || ! refers_to_regno_p (REGNO (word0),
REGNO (word0) + 1, addr, 0))
(match_operand:DF 1 "memory_operand" ""))
(use (match_operand:PSI 2 "fpscr_operand" ""))
(clobber (reg:SI R0_REG))]
- "TARGET_SH4 && reload_completed"
+ "(TARGET_SH4 || TARGET_SH2A_DOUBLE) && reload_completed"
[(parallel [(set (match_dup 0) (match_dup 1))
(use (match_dup 2))
(clobber (scratch:SI))])]
[(set (match_operand:SF 0 "register_operand" "")
(match_operand:SF 1 "register_operand" ""))
(use (match_operand:PSI 2 "fpscr_operand" ""))
- (clobber (match_scratch:SI 3 "X"))]
+ (clobber (match_scratch:SI 3 ""))]
"TARGET_SH2E && reload_completed
&& true_regnum (operands[0]) == true_regnum (operands[1])"
[(set (match_dup 0) (match_dup 0))]
[(set (match_operand:DF 0 "register_operand" "")
(match_operand:DF 1 "register_operand" ""))
(use (match_operand:PSI 2 "fpscr_operand" ""))
- (clobber (match_scratch:SI 3 "X"))]
+ (clobber (match_scratch:SI 3 ""))]
"TARGET_SH4 && ! TARGET_FMOVD && reload_completed
&& FP_OR_XD_REGISTER_P (true_regnum (operands[0]))
&& FP_OR_XD_REGISTER_P (true_regnum (operands[1]))"
"
{
int dst = true_regnum (operands[0]), src = true_regnum (operands[1]);
- emit_insn (gen_movsf_ie (gen_rtx (REG, SFmode, dst),
- gen_rtx (REG, SFmode, src), operands[2]));
- emit_insn (gen_movsf_ie (gen_rtx (REG, SFmode, dst + 1),
- gen_rtx (REG, SFmode, src + 1), operands[2]));
+ emit_insn (gen_movsf_ie (gen_rtx_REG (SFmode, dst),
+ gen_rtx_REG (SFmode, src), operands[2]));
+ emit_insn (gen_movsf_ie (gen_rtx_REG (SFmode, dst + 1),
+ gen_rtx_REG (SFmode, src + 1), operands[2]));
DONE;
}")
(mem:DF (match_operand:SI 1 "register_operand" "")))
(use (match_operand:PSI 2 "fpscr_operand" ""))
(clobber (match_scratch:SI 3 ""))]
- "TARGET_SH4 && ! TARGET_FMOVD && reload_completed
+ "(TARGET_SH4 || TARGET_SH2A_DOUBLE) && ! TARGET_FMOVD && reload_completed
&& FP_OR_XD_REGISTER_P (true_regnum (operands[0]))
&& find_regno_note (insn, REG_DEAD, true_regnum (operands[1]))"
[(const_int 0)]
{
int regno = true_regnum (operands[0]);
rtx insn;
- rtx mem2 = gen_rtx (MEM, SFmode, gen_rtx (POST_INC, Pmode, operands[1]));
+ rtx mem2 = gen_rtx_MEM (SFmode, gen_rtx_POST_INC (Pmode, operands[1]));
- insn = emit_insn (gen_movsf_ie (gen_rtx (REG, SFmode,
+ insn = emit_insn (gen_movsf_ie (gen_rtx_REG (SFmode,
regno + !! TARGET_LITTLE_ENDIAN),
mem2, operands[2]));
- REG_NOTES (insn) = gen_rtx (EXPR_LIST, REG_INC, operands[1], NULL_RTX);
- insn = emit_insn (gen_movsf_ie (gen_rtx (REG, SFmode,
+ REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_INC, operands[1], NULL_RTX);
+ insn = emit_insn (gen_movsf_ie (gen_rtx_REG (SFmode,
regno + ! TARGET_LITTLE_ENDIAN),
- gen_rtx (MEM, SFmode, operands[1]),
+ gen_rtx_MEM (SFmode, operands[1]),
operands[2]));
DONE;
}")
(match_operand:DF 1 "memory_operand" ""))
(use (match_operand:PSI 2 "fpscr_operand" ""))
(clobber (match_scratch:SI 3 ""))]
- "TARGET_SH4 && ! TARGET_FMOVD && reload_completed
+ "(TARGET_SH4 || TARGET_SH2A_DOUBLE) && ! TARGET_FMOVD && reload_completed
&& FP_OR_XD_REGISTER_P (true_regnum (operands[0]))"
[(const_int 0)]
"
(match_operand:DF 1 "register_operand" ""))
(use (match_operand:PSI 2 "fpscr_operand" ""))
(clobber (match_scratch:SI 3 ""))]
- "TARGET_SH4 && ! TARGET_FMOVD && reload_completed
+ "(TARGET_SH4 || TARGET_SH2A_DOUBLE) && ! TARGET_FMOVD && reload_completed
&& FP_OR_XD_REGISTER_P (true_regnum (operands[1]))"
[(const_int 0)]
"
operands[0] = copy_rtx (operands[0]);
PUT_MODE (operands[0], SFmode);
insn = emit_insn (gen_movsf_ie (operands[0],
- gen_rtx (REG, SFmode,
+ gen_rtx_REG (SFmode,
regno + ! TARGET_LITTLE_ENDIAN),
operands[2]));
operands[0] = copy_rtx (operands[0]);
{
adjust = gen_addsi3 (addr, addr, GEN_INT (4));
emit_insn_before (adjust, insn);
- XEXP (operands[0], 0) = addr = gen_rtx (PRE_DEC, SImode, addr);
+ XEXP (operands[0], 0) = addr = gen_rtx_PRE_DEC (SImode, addr);
}
addr = XEXP (addr, 0);
if (! adjust)
- REG_NOTES (insn) = gen_rtx (EXPR_LIST, REG_INC, addr, NULL_RTX);
+ REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_INC, addr, NULL_RTX);
insn = emit_insn (gen_movsf_ie (operands[0],
- gen_rtx (REG, SFmode,
+ gen_rtx_REG (SFmode,
regno + !! TARGET_LITTLE_ENDIAN),
operands[2]));
- REG_NOTES (insn) = gen_rtx (EXPR_LIST, REG_INC, addr, NULL_RTX);
+ REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_INC, addr, NULL_RTX);
DONE;
}")
emit_insn (gen_movdf_media_nofpu (operands[0], operands[1]));
DONE;
}
- if (TARGET_SH4)
+ if (TARGET_SH4 || TARGET_SH2A_DOUBLE)
{
emit_df_insn (gen_movdf_i4 (operands[0], operands[1], get_fpscr_rtx ()));
DONE;
(define_insn_and_split "movv2sf_i"
[(set (match_operand:V2SF 0 "general_movdst_operand" "=f,rf,r,m,mf")
- (match_operand:V2SF 1 "general_operand" "fm,rfm?,F?,f,rfU?"))]
+ (match_operand:V2SF 1 "general_operand" "fm,rfm?,F?,f,rfZ?"))]
"TARGET_SHMEDIA_FPU"
"#"
"TARGET_SHMEDIA_FPU && reload_completed"
(define_insn_and_split "*movv4sf_i"
[(set (match_operand:V4SF 0 "nonimmediate_operand" "=f,f,m")
- (match_operand:V4SF 1 "general_operand" "fU,m,fU"))]
+ (match_operand:V4SF 1 "general_operand" "fZ,m,fZ"))]
"TARGET_SHMEDIA_FPU"
"#"
"&& reload_completed"
i * GET_MODE_SIZE (V2SFmode)));
else
{
- x = gen_rtx_SUBREG (V2SFmode, operands[0], i * 2);
+ x = gen_rtx_SUBREG (V2SFmode, operands[0], i * 8);
alter_subreg (&x);
}
i * GET_MODE_SIZE (V2SFmode)));
else
{
- y = gen_rtx_SUBREG (V2SFmode, operands[1], i * 2);
+ y = gen_rtx_SUBREG (V2SFmode, operands[1], i * 8);
alter_subreg (&y);
}
(define_insn "movsf_media"
[(set (match_operand:SF 0 "general_movdst_operand" "=f,f,r,r,r,f,m,r,m")
- (match_operand:SF 1 "general_movsrc_operand" "f,rU,f,r,F,m,f,m,rU"))]
+ (match_operand:SF 1 "general_movsrc_operand" "f,rZ,f,r,F,m,f,m,rZ"))]
"TARGET_SHMEDIA_FPU
&& (register_operand (operands[0], SFmode)
|| sh_register_operand (operands[1], SFmode))"
(define_insn "movsf_media_nofpu"
[(set (match_operand:SF 0 "general_movdst_operand" "=r,r,r,m")
- (match_operand:SF 1 "general_movsrc_operand" "r,F,m,rU"))]
+ (match_operand:SF 1 "general_movsrc_operand" "r,F,m,rZ"))]
"TARGET_SHMEDIA
&& (register_operand (operands[0], SFmode)
|| sh_register_operand (operands[1], SFmode))"
(define_insn "movsf_i"
[(set (match_operand:SF 0 "general_movdst_operand" "=r,r,r,r,m,l,r")
- (match_operand:SF 1 "general_movsrc_operand" "r,I,FQ,mr,r,r,l"))]
+ (match_operand:SF 1 "general_movsrc_operand" "r,G,FQ,mr,r,r,l"))]
"TARGET_SH1
&& (! TARGET_SH2E
/* ??? We provide some insn so that direct_{load,store}[SFmode] get set */
|| arith_reg_operand (operands[1], SFmode))"
"@
mov %1,%0
- mov %1,%0
+ mov #0,%0
mov.l %1,%0
mov.l %1,%0
mov.l %1,%0
(match_operand:SF 1 "general_movsrc_operand"
"f,r,G,H,FQ,mf,f,FQ,mr,r,y,f,>,fr,y,r,y,>,y"))
(use (match_operand:PSI 2 "fpscr_operand" "c,c,c,c,c,c,c,c,c,c,c,c,c,c,c,c,c,c,c"))
- (clobber (match_scratch:SI 3 "=X,X,X,X,&z,X,X,X,X,X,X,X,X,y,X,X,X,X,X"))]
+ (clobber (match_scratch:SI 3 "=X,X,Bsc,Bsc,&z,X,X,X,X,X,X,X,X,y,X,X,X,X,X"))]
"TARGET_SH2E
&& (arith_reg_operand (operands[0], SFmode)
! move optimized away"
[(set_attr "type" "fmove,move,fmove,fmove,pcfload,fload,store,pcload,load,store,fmove,fmove,load,*,fpul_gp,gp_fpul,store,load,nil")
(set_attr "late_fp_use" "*,*,*,*,*,*,yes,*,*,*,*,*,*,*,yes,*,yes,*,*")
- (set_attr "length" "*,*,*,*,4,*,*,*,*,*,2,2,2,4,2,2,2,2,0")
+ (set_attr "length" "*,*,*,*,4,4,4,*,*,*,2,2,2,4,2,2,2,2,0")
(set (attr "fp_mode") (if_then_else (eq_attr "fmovd" "yes")
(const_string "single")
(const_string "none")))])
(define_insn "*movsi_y"
[(set (match_operand:SI 0 "register_operand" "=y,y")
- (match_operand:SI 1 "immediate_operand" "Qi,I"))
+ (match_operand:SI 1 "immediate_operand" "Qi,I08"))
(clobber (match_scratch:SI 2 "=&z,r"))]
"TARGET_SH2E
&& (reload_in_progress || reload_completed)"
;; This one has the additional purpose to record a possible scratch register
;; for the following branch.
+;; ??? Unfortunately, just setting the scratch register is not good enough,
+;; because the insn then might be deemed dead and deleted. And we can't
+;; make the use in the jump insn explicit because that would disable
+;; delay slot scheduling from the target.
(define_insn "indirect_jump_scratch"
[(set (match_operand:SI 0 "register_operand" "=r")
- (unspec:SI [(match_operand 1 "const_int_operand" "")] UNSPEC_BBR))]
+ (unspec:SI [(match_operand 1 "const_int_operand" "")] UNSPEC_BBR))
+ (set (pc) (unspec [(const_int 0)] UNSPEC_BBR))]
"TARGET_SH1"
""
[(set_attr "length" "0")])
(define_expand "beq_media"
[(set (pc)
(if_then_else (eq (match_operand:DI 1 "arith_reg_operand" "r,r")
- (match_operand:DI 2 "arith_operand" "r,O"))
+ (match_operand:DI 2 "arith_operand" "r,I06"))
(label_ref:DI (match_operand 0 "" ""))
(pc)))]
"TARGET_SHMEDIA"
[(set (pc)
(if_then_else (match_operator 3 "equality_comparison_operator"
[(match_operand:DI 1 "arith_reg_operand" "r,r")
- (match_operand:DI 2 "arith_operand" "r,O")])
+ (match_operand:DI 2 "arith_operand" "r,I06")])
(match_operand:DI 0 "target_operand" "b,b")
(pc)))]
"TARGET_SHMEDIA"
(define_expand "bne_media"
[(set (pc)
(if_then_else (ne (match_operand:DI 1 "arith_reg_operand" "r,r")
- (match_operand:DI 2 "arith_operand" "r,O"))
+ (match_operand:DI 2 "arith_operand" "r,I06"))
(label_ref:DI (match_operand 0 "" ""))
(pc)))]
"TARGET_SHMEDIA"
[(set_attr "type" "jump")
(set_attr "needs_delay_slot" "yes")])
+;; ??? It would be much saner to explicitly use the scratch register
+;; in the jump insn, and have indirect_jump_scratch only set it,
+;; but fill_simple_delay_slots would refuse to do delay slot filling
+;; from the target then, as it uses simplejump_p.
+;;(define_insn "jump_compact_far"
+;; [(set (pc)
+;; (label_ref (match_operand 0 "" "")))
+;; (use (match_operand 1 "register_operand" "r")]
+;; "TARGET_SH1"
+;; "* return output_far_jump(insn, operands[0], operands[1]);"
+;; [(set_attr "type" "jump")
+;; (set_attr "needs_delay_slot" "yes")])
+
(define_insn "jump_media"
[(set (pc)
(match_operand:DI 0 "target_operand" "b"))]
(set (attr "fp_mode")
(if_then_else (eq_attr "fpu_single" "yes")
(const_string "single") (const_string "double")))
- (set_attr "needs_delay_slot" "yes")])
+ (set_attr "needs_delay_slot" "yes")
+ (set_attr "fp_set" "unknown")])
;; This is a pc-rel call, using bsrf, for use with PIC.
(set (attr "fp_mode")
(if_then_else (eq_attr "fpu_single" "yes")
(const_string "single") (const_string "double")))
- (set_attr "needs_delay_slot" "yes")])
+ (set_attr "needs_delay_slot" "yes")
+ (set_attr "fp_set" "unknown")])
(define_insn_and_split "call_pcrel"
[(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" ""))
{
rtx lab = PATTERN (gen_call_site ());
- if (SYMBOL_REF_FLAG (operands[0]))
+ if (SYMBOL_REF_LOCAL_P (operands[0]))
emit_insn (gen_sym_label2reg (operands[2], operands[0], lab));
else
emit_insn (gen_symPLT_label2reg (operands[2], operands[0], lab));
(set (attr "fp_mode")
(if_then_else (eq_attr "fpu_single" "yes")
(const_string "single") (const_string "double")))
- (set_attr "needs_delay_slot" "yes")])
+ (set_attr "needs_delay_slot" "yes")
+ (set_attr "fp_set" "unknown")])
(define_insn "call_compact"
[(call (mem:SI (match_operand:SI 0 "arith_reg_operand" "r"))
(set (attr "fp_mode")
(if_then_else (eq_attr "fpu_single" "yes")
(const_string "single") (const_string "double")))
- (set_attr "needs_delay_slot" "yes")])
+ (set_attr "needs_delay_slot" "yes")
+ (set_attr "fp_set" "unknown")])
(define_insn "call_valuei_pcrel"
[(set (match_operand 0 "" "=rf")
(set (attr "fp_mode")
(if_then_else (eq_attr "fpu_single" "yes")
(const_string "single") (const_string "double")))
- (set_attr "needs_delay_slot" "yes")])
+ (set_attr "needs_delay_slot" "yes")
+ (set_attr "fp_set" "unknown")])
(define_insn_and_split "call_value_pcrel"
[(set (match_operand 0 "" "=rf")
{
rtx lab = PATTERN (gen_call_site ());
- if (SYMBOL_REF_FLAG (operands[1]))
+ if (SYMBOL_REF_LOCAL_P (operands[1]))
emit_insn (gen_sym_label2reg (operands[3], operands[1], lab));
else
emit_insn (gen_symPLT_label2reg (operands[3], operands[1], lab));
(set (attr "fp_mode")
(if_then_else (eq_attr "fpu_single" "yes")
(const_string "single") (const_string "double")))
- (set_attr "needs_delay_slot" "yes")])
+ (set_attr "needs_delay_slot" "yes")
+ (set_attr "fp_set" "unknown")])
(define_insn "call_value_compact"
[(set (match_operand 0 "" "=rf")
operands[0] = XEXP (operands[0], 0);
if (flag_pic && GET_CODE (operands[0]) == SYMBOL_REF)
{
- if (! SYMBOL_REF_FLAG (operands[0]))
+ if (! SYMBOL_REF_LOCAL_P (operands[0]))
{
rtx reg = gen_reg_rtx (Pmode);
if (GET_MODE (operands[0]) != DImode)
operands[0] = gen_rtx_SUBREG (DImode, operands[0], 0);
}
- else
+ else if (TARGET_SHMEDIA64)
{
operands[0] = shallow_copy_rtx (operands[0]);
PUT_MODE (operands[0], DImode);
}
+ else
+ {
+ rtx reg = gen_reg_rtx (DImode);
+
+ operands[0] = copy_to_mode_reg (SImode, operands[0]);
+ emit_insn (gen_extendsidi2 (reg, operands[0]));
+ operands[0] = reg;
+ }
}
if (! target_reg_operand (operands[0], DImode))
operands[0] = copy_to_mode_reg (DImode, operands[0]);
if (flag_pic)
{
- if (GET_CODE (func) == SYMBOL_REF && ! SYMBOL_REF_FLAG (func))
+ if (GET_CODE (func) == SYMBOL_REF && ! SYMBOL_REF_LOCAL_P (func))
{
rtx reg = gen_reg_rtx (Pmode);
run out of registers when adjusting fpscr for the call. */
emit_insn (gen_force_mode_for_call ());
- operands[0] = gen_rtx_SYMBOL_REF (SImode,
- \"__GCC_shcompact_call_trampoline\");
+ operands[0] = function_symbol (\"__GCC_shcompact_call_trampoline\");
if (flag_pic)
{
rtx reg = gen_reg_rtx (Pmode);
}
else if (TARGET_SHCOMPACT && flag_pic
&& GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF
- && ! SYMBOL_REF_FLAG (XEXP (operands[0], 0)))
+ && ! SYMBOL_REF_LOCAL_P (XEXP (operands[0], 0)))
{
rtx reg = gen_reg_rtx (Pmode);
DONE;
}
else
+ {
operands[0] = force_reg (SImode, XEXP (operands[0], 0));
+ operands[1] = operands[2];
+ }
emit_call_insn (gen_calli (operands[0], operands[1]));
DONE;
if (flag_pic)
{
- if (GET_CODE (func) == SYMBOL_REF && ! SYMBOL_REF_FLAG (func))
+ if (GET_CODE (func) == SYMBOL_REF && ! SYMBOL_REF_LOCAL_P (func))
{
rtx reg = gen_reg_rtx (Pmode);
run out of registers when adjusting fpscr for the call. */
emit_insn (gen_force_mode_for_call ());
- operands[0] = gen_rtx_SYMBOL_REF (SImode,
- \"__GCC_shcompact_call_trampoline\");
+ operands[0] = function_symbol (\"__GCC_shcompact_call_trampoline\");
if (flag_pic)
{
rtx reg = gen_reg_rtx (Pmode);
operands[1] = XEXP (operands[1], 0);
if (flag_pic && GET_CODE (operands[1]) == SYMBOL_REF)
{
- if (! SYMBOL_REF_FLAG (operands[1]))
+ if (! SYMBOL_REF_LOCAL_P (operands[1]))
{
rtx reg = gen_reg_rtx (Pmode);
if (GET_MODE (operands[1]) != DImode)
operands[1] = gen_rtx_SUBREG (DImode, operands[1], 0);
}
- else
+ else if (TARGET_SHMEDIA64)
{
operands[1] = shallow_copy_rtx (operands[1]);
PUT_MODE (operands[1], DImode);
}
+ else
+ {
+ rtx reg = gen_reg_rtx (DImode);
+
+ operands[1] = copy_to_mode_reg (SImode, operands[1]);
+ emit_insn (gen_extendsidi2 (reg, operands[1]));
+ operands[1] = reg;
+ }
}
if (! target_reg_operand (operands[1], DImode))
operands[1] = copy_to_mode_reg (DImode, operands[1]);
if (flag_pic)
{
- if (GET_CODE (func) == SYMBOL_REF && ! SYMBOL_REF_FLAG (func))
+ if (GET_CODE (func) == SYMBOL_REF && ! SYMBOL_REF_LOCAL_P (func))
{
rtx reg = gen_reg_rtx (Pmode);
run out of registers when adjusting fpscr for the call. */
emit_insn (gen_force_mode_for_call ());
- operands[1] = gen_rtx_SYMBOL_REF (SImode,
- \"__GCC_shcompact_call_trampoline\");
+ operands[1] = function_symbol (\"__GCC_shcompact_call_trampoline\");
if (flag_pic)
{
rtx reg = gen_reg_rtx (Pmode);
}
else if (TARGET_SHCOMPACT && flag_pic
&& GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
- && ! SYMBOL_REF_FLAG (XEXP (operands[1], 0)))
+ && ! SYMBOL_REF_LOCAL_P (XEXP (operands[1], 0)))
{
rtx reg = gen_reg_rtx (Pmode);
(define_insn "sibcall_media"
[(call (mem:DI (match_operand:DI 0 "target_reg_operand" "k"))
(match_operand 1 "" ""))
+ (use (reg:SI PR_MEDIA_REG))
(return)]
"TARGET_SHMEDIA"
"blink %0, r63"
operands[0] = XEXP (operands[0], 0);
if (flag_pic && GET_CODE (operands[0]) == SYMBOL_REF)
{
- if (! SYMBOL_REF_FLAG (operands[0]))
+ if (! SYMBOL_REF_LOCAL_P (operands[0]))
{
rtx reg = gen_reg_rtx (Pmode);
if (flag_pic)
{
- if (GET_CODE (func) == SYMBOL_REF && ! SYMBOL_REF_FLAG (func))
+ if (GET_CODE (func) == SYMBOL_REF && ! SYMBOL_REF_LOCAL_P (func))
{
rtx reg = gen_reg_rtx (Pmode);
run out of registers when adjusting fpscr for the call. */
emit_insn (gen_force_mode_for_call ());
- operands[0] = gen_rtx_SYMBOL_REF (SImode,
- \"__GCC_shcompact_call_trampoline\");
+ operands[0] = function_symbol (\"__GCC_shcompact_call_trampoline\");
if (flag_pic)
{
rtx reg = gen_reg_rtx (Pmode);
}
else if (TARGET_SHCOMPACT && flag_pic
&& GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF
- && ! SYMBOL_REF_FLAG (XEXP (operands[0], 0)))
+ && ! SYMBOL_REF_LOCAL_P (XEXP (operands[0], 0)))
{
rtx reg = gen_reg_rtx (Pmode);
/* The PLT needs the PIC register, but the epilogue would have
to restore it, so we can only use PC-relative PIC calls for
static functions. */
- && SYMBOL_REF_FLAG (XEXP (operands[0], 0)))
+ && SYMBOL_REF_LOCAL_P (XEXP (operands[0], 0)))
{
emit_call_insn (gen_sibcall_pcrel (XEXP (operands[0], 0), operands[1]));
DONE;
if (flag_pic)
{
- if (GET_CODE (func) == SYMBOL_REF && ! SYMBOL_REF_FLAG (func))
+ if (GET_CODE (func) == SYMBOL_REF && ! SYMBOL_REF_LOCAL_P (func))
{
rtx reg = gen_reg_rtx (Pmode);
run out of registers when adjusting fpscr for the call. */
emit_insn (gen_force_mode_for_call ());
- operands[1] = gen_rtx_SYMBOL_REF (SImode,
- \"__GCC_shcompact_call_trampoline\");
+ operands[1] = function_symbol (\"__GCC_shcompact_call_trampoline\");
if (flag_pic)
{
rtx reg = gen_reg_rtx (Pmode);
""
"
{
- sh_expand_epilogue ();
+ sh_expand_epilogue (1);
if (TARGET_SHCOMPACT)
{
rtx insn, set;
(const_int 0))
(match_operand 1 "" "")
(match_operand 2 "" "")])]
- "TARGET_SH2E || TARGET_SHMEDIA"
+ "(TARGET_SH2E || TARGET_SH2A) || TARGET_SHMEDIA"
"
{
int i;
[(set_attr "in_delay_slot" "no")
(set_attr "type" "arith")])
-;; machine_dependent_reorg() will make this a `mova'.
+;; machine_dependent_reorg will make this a `mova'.
(define_insn "mova_const"
[(set (reg:SI R0_REG)
(unspec:SI [(match_operand 0 "immediate_operand" "i")] UNSPEC_MOVA))]
emit_insn (gen_ptrel (tr, dipic, lab));
if (GET_MODE (operands[0]) != GET_MODE (tr))
- tr = gen_rtx_SUBREG (GET_MODE (operands[0]), tr, 0);
+ tr = gen_lowpart (GET_MODE (operands[0]), tr);
insn = emit_move_insn (operands[0], tr);
}
")
-;; When generating PIC, we must match label_refs especially, because
-;; they do not satisfy LEGITIMATE_PIC_OPERAND_P(), and we don't want
-;; them to do, because they can't be loaded directly into
-;; non-branch-target registers.
-(define_insn "*pt"
- [(set (match_operand:DI 0 "target_reg_operand" "=b")
- (match_operand:DI 1 "" "T"))]
- "TARGET_SHMEDIA && flag_pic
- && EXTRA_CONSTRAINT_T (operands[1])"
- "pt %1, %0"
- [(set_attr "type" "pt_media")
- (set_attr "length" "*")])
-
(define_insn "*ptb"
[(set (match_operand:DI 0 "target_reg_operand" "=b")
- (const:DI (unspec:DI [(match_operand:DI 1 "" "T")]
+ (const:DI (unspec:DI [(match_operand:DI 1 "" "Csy")]
UNSPEC_DATALABEL)))]
"TARGET_SHMEDIA && flag_pic
- && EXTRA_CONSTRAINT_T (operands[1])"
+ && EXTRA_CONSTRAINT_Csy (operands[1])"
"ptb/u datalabel %1, %0"
[(set_attr "type" "pt_media")
(set_attr "length" "*")])
PUT_MODE (gotsym, Pmode);
insn = emit_insn (gen_symGOT_load (operands[0], gotsym));
- RTX_UNCHANGING_P (SET_SRC (PATTERN (insn))) = 1;
+ MEM_READONLY_P (SET_SRC (PATTERN (insn))) = 1;
DONE;
}")
""
"")
+;; TLS code generation.
+;; ??? this should be a define_insn_and_split
+;; See the thread [PATCH/RFA] SH TLS support on gcc-patches
+;; <http://gcc.gnu.org/ml/gcc-patches/2003-02/msg01898.html>
+;; for details.
+
+(define_insn "tls_global_dynamic"
+ [(set (match_operand:SI 0 "register_operand" "=&z")
+ (call (mem:SI (unspec:SI [(match_operand:SI 1 "" "")]
+ UNSPEC_TLSGD))
+ (const_int 0)))
+ (use (reg:PSI FPSCR_REG))
+ (use (reg:SI PIC_REG))
+ (clobber (reg:SI PR_REG))
+ (clobber (scratch:SI))]
+ "TARGET_SH1"
+ "*
+{
+ return \"\\
+mov.l\\t1f,r4\\n\\
+\\tmova\\t2f,r0\\n\\
+\\tmov.l\\t2f,r1\\n\\
+\\tadd\\tr0,r1\\n\\
+\\tjsr\\t@r1\\n\\
+\\tadd\\tr12,r4\\n\\
+\\tbra\\t3f\\n\\
+\\tnop\\n\\
+\\t.align\\t2\\n\\
+1:\\t.long\\t%a1@TLSGD\\n\\
+2:\\t.long\\t__tls_get_addr@PLT\\n\\
+3:\";
+}"
+ [(set_attr "type" "tls_load")
+ (set_attr "length" "26")])
+
+(define_insn "tls_local_dynamic"
+ [(set (match_operand:SI 0 "register_operand" "=&z")
+ (call (mem:SI (unspec:SI [(match_operand:SI 1 "" "")]
+ UNSPEC_TLSLDM))
+ (const_int 0)))
+ (use (reg:PSI FPSCR_REG))
+ (use (reg:SI PIC_REG))
+ (clobber (reg:SI PR_REG))
+ (clobber (scratch:SI))]
+ "TARGET_SH1"
+ "*
+{
+ return \"\\
+mov.l\\t1f,r4\\n\\
+\\tmova\\t2f,r0\\n\\
+\\tmov.l\\t2f,r1\\n\\
+\\tadd\\tr0,r1\\n\\
+\\tjsr\\t@r1\\n\\
+\\tadd\\tr12,r4\\n\\
+\\tbra\\t3f\\n\\
+\\tnop\\n\\
+\\t.align\\t2\\n\\
+1:\\t.long\\t%a1@TLSLDM\\n\\
+2:\\t.long\\t__tls_get_addr@PLT\\n\\
+3:\";
+}"
+ [(set_attr "type" "tls_load")
+ (set_attr "length" "26")])
+
+(define_expand "sym2DTPOFF"
+ [(const (unspec [(match_operand 0 "" "")] UNSPEC_DTPOFF))]
+ ""
+ "")
+
+(define_expand "symDTPOFF2reg"
+ [(match_operand 0 "" "") (match_operand 1 "" "") (match_operand 2 "" "")]
+ ""
+ "
+{
+ rtx dtpoffsym, insn;
+ rtx t = no_new_pseudos ? operands[0] : gen_reg_rtx (GET_MODE (operands[0]));
+
+ dtpoffsym = gen_sym2DTPOFF (operands[1]);
+ PUT_MODE (dtpoffsym, Pmode);
+ emit_move_insn (t, dtpoffsym);
+ insn = emit_move_insn (operands[0],
+ gen_rtx_PLUS (Pmode, t, operands[2]));
+ DONE;
+}")
+
+(define_expand "sym2GOTTPOFF"
+ [(const (unspec [(match_operand 0 "" "")] UNSPEC_GOTTPOFF))]
+ ""
+ "")
+
+(define_insn "tls_initial_exec"
+ [(set (match_operand:SI 0 "register_operand" "=&r")
+ (unspec:SI [(match_operand:SI 1 "" "")]
+ UNSPEC_TLSIE))
+ (use (reg:SI GBR_REG))
+ (use (reg:SI PIC_REG))
+ (clobber (reg:SI R0_REG))]
+ ""
+ "*
+{
+ return \"\\
+mov.l\\t1f,r0\\n\\
+\\tstc\\tgbr,%0\\n\\
+\\tmov.l\\t@(r0,r12),r0\\n\\
+\\tbra\\t2f\\n\\
+\\tadd\\tr0,%0\\n\\
+\\t.align\\t2\\n\\
+1:\\t.long\\t%a1\\n\\
+2:\";
+}"
+ [(set_attr "type" "tls_load")
+ (set_attr "length" "16")])
+
+(define_expand "sym2TPOFF"
+ [(const (unspec [(match_operand 0 "" "")] UNSPEC_TPOFF))]
+ ""
+ "")
+
+(define_expand "symTPOFF2reg"
+ [(match_operand 0 "" "") (match_operand 1 "" "")]
+ ""
+ "
+{
+ rtx tpoffsym, insn;
+
+ tpoffsym = gen_sym2TPOFF (operands[1]);
+ PUT_MODE (tpoffsym, Pmode);
+ insn = emit_move_insn (operands[0], tpoffsym);
+ DONE;
+}")
+
+(define_insn "load_gbr"
+ [(set (match_operand:SI 0 "register_operand" "") (reg:SI GBR_REG))
+ (use (reg:SI GBR_REG))]
+ ""
+ "stc gbr,%0"
+ [(set_attr "type" "tls_load")])
+
;; case instruction for switch statements.
;; Operand 0 is index
(clobber (match_dup 3))])]
"if (GET_CODE (operands[2]) == CODE_LABEL) LABEL_NUSES (operands[2])++;")
-(define_insn "*casesi_worker"
+(define_insn "casesi_worker_1"
[(set (match_operand:SI 0 "register_operand" "=r,r")
(unspec:SI [(reg:SI R0_REG)
(match_operand:SI 1 "register_operand" "0,r")
}"
[(set_attr "length" "4")])
+(define_insn "casesi_worker_2"
+ [(set (match_operand:SI 0 "register_operand" "=r,r")
+ (unspec:SI [(reg:SI R0_REG)
+ (match_operand:SI 1 "register_operand" "0,r")
+ (label_ref (match_operand 2 "" ""))
+ (label_ref (match_operand 3 "" ""))] UNSPEC_CASESI))
+ (clobber (match_operand:SI 4 "" "=X,1"))]
+ "TARGET_SH2 && reload_completed && flag_pic"
+ "*
+{
+ rtx diff_vec = PATTERN (next_real_insn (operands[2]));
+ const char *load;
+
+ if (GET_CODE (diff_vec) != ADDR_DIFF_VEC)
+ abort ();
+
+ switch (GET_MODE (diff_vec))
+ {
+ case SImode:
+ output_asm_insn (\"shll2 %1\", operands);
+ load = \"mov.l @(r0,%1),%0\"; break;
+ case HImode:
+ output_asm_insn (\"add %1,%1\", operands);
+ load = \"mov.w @(r0,%1),%0\"; break;
+ case QImode:
+ if (ADDR_DIFF_VEC_FLAGS (diff_vec).offset_unsigned)
+ load = \"mov.b @(r0,%1),%0\;extu.b %0,%0\";
+ else
+ load = \"mov.b @(r0,%1),%0\";
+ break;
+ default:
+ abort ();
+ }
+ output_asm_insn (\"add\tr0,%1\;mova\t%O3,r0\\n\", operands);
+ return load;
+}"
+ [(set_attr "length" "8")])
+
(define_insn "casesi_shift_media"
[(set (match_operand:DI 0 "arith_reg_operand" "=r")
(ashift:DI (match_operand:DI 1 "arith_reg_operand" "r")
"
{
rtx reg = gen_rtx_REG (Pmode, R0_REG);
- rtx sym = gen_rtx_SYMBOL_REF (Pmode,
- \"__GCC_shcompact_return_trampoline\");
+ rtx sym = function_symbol (\"__GCC_shcompact_return_trampoline\");
if (flag_pic)
emit_insn (gen_symGOTPLT2reg (reg, sym));
"blink %0, r63"
[(set_attr "type" "jump_media")])
+(define_insn "return_media_rte"
+ [(return)]
+ "TARGET_SHMEDIA && reload_completed && current_function_interrupt"
+ "rte"
+ [(set_attr "type" "jump_media")])
+
(define_expand "return_media"
[(return)]
"TARGET_SHMEDIA && reload_completed"
int tr_regno = sh_media_register_for_return ();
rtx tr;
+ if (current_function_interrupt)
+ {
+ emit_jump_insn (gen_return_media_rte ());
+ DONE;
+ }
if (tr_regno < 0)
{
rtx r18 = gen_rtx_REG (DImode, PR_MEDIA_REG);
+ if (! call_really_used_regs[TR0_REG] || fixed_regs[TR0_REG])
+ abort ();
tr_regno = TR0_REG;
tr = gen_rtx_REG (DImode, tr_regno);
emit_move_insn (tr, r18);
""
"
{
- sh_expand_epilogue ();
+ sh_expand_epilogue (0);
emit_jump_insn (gen_return ());
DONE;
}")
(define_expand "eh_return"
- [(use (match_operand 0 "register_operand" ""))
- (use (match_operand 1 "register_operand" ""))]
+ [(use (match_operand 0 "register_operand" ""))]
""
{
- rtx tmp, sa = operands[0], ra = operands[1];
+ rtx ra = operands[0];
if (TARGET_SHMEDIA64)
emit_insn (gen_eh_set_ra_di (ra));
else
emit_insn (gen_eh_set_ra_si (ra));
- emit_move_insn (EH_RETURN_STACKADJ_RTX, sa);
DONE;
})
}
DONE;
}
+ if (sh_expand_t_scc (EQ, operands[0]))
+ DONE;
+ if (! currently_expanding_to_rtl)
+ FAIL;
operands[1] = prepare_scc_operands (EQ);
}")
}
DONE;
}
+ if (! currently_expanding_to_rtl)
+ FAIL;
operands[1] = prepare_scc_operands (LT);
}")
}
DONE;
}
+ if (! currently_expanding_to_rtl)
+ FAIL;
operands[1] = prepare_scc_operands (GT);
}")
DONE;
}
+ if (! currently_expanding_to_rtl)
+ FAIL;
if (GET_MODE_CLASS (GET_MODE (sh_compare_op0)) == MODE_FLOAT)
{
if (TARGET_IEEE)
sh_compare_op0, sh_compare_op1));
DONE;
}
+ if (! currently_expanding_to_rtl)
+ FAIL;
operands[1] = prepare_scc_operands (GTU);
}")
sh_compare_op1, sh_compare_op0));
DONE;
}
+ if (! currently_expanding_to_rtl)
+ FAIL;
operands[1] = prepare_scc_operands (LTU);
}")
DONE;
}
+ if (! currently_expanding_to_rtl)
+ FAIL;
operands[1] = prepare_scc_operands (LEU);
}")
DONE;
}
+ if (! currently_expanding_to_rtl)
+ FAIL;
operands[1] = prepare_scc_operands (GEU);
}")
DONE;
}
- operands[1] = prepare_scc_operands (EQ);
- operands[2] = gen_reg_rtx (SImode);
+ if (sh_expand_t_scc (NE, operands[0]))
+ DONE;
+ if (! currently_expanding_to_rtl)
+ FAIL;
+ operands[1] = prepare_scc_operands (EQ);
+ operands[2] = gen_reg_rtx (SImode);
}")
(define_expand "sunordered"
;; String/block move insn.
-(define_expand "movstrsi"
+(define_expand "movmemsi"
[(parallel [(set (mem:BLK (match_operand:BLK 0 "" ""))
(mem:BLK (match_operand:BLK 1 "" "")))
(use (match_operand:SI 2 "nonmemory_operand" ""))
(define_expand "fpu_switch0"
[(set (match_operand:SI 0 "" "") (match_dup 2))
(set (match_dup 1) (mem:PSI (match_dup 0)))]
- "TARGET_SH4"
+ "(TARGET_SH4 || TARGET_SH2A_DOUBLE)"
"
{
operands[1] = get_fpscr_rtx ();
[(set (match_operand:SI 0 "" "") (match_dup 2))
(set (match_dup 3) (plus:SI (match_dup 0) (const_int 4)))
(set (match_dup 1) (mem:PSI (match_dup 3)))]
- "TARGET_SH4"
+ "(TARGET_SH4 || TARGET_SH2A_DOUBLE)"
"
{
operands[1] = get_fpscr_rtx ();
(define_expand "movpsi"
[(set (match_operand:PSI 0 "register_operand" "")
(match_operand:PSI 1 "general_movsrc_operand" ""))]
- "TARGET_SH4"
+ "(TARGET_SH4 || TARGET_SH2A_DOUBLE)"
"")
;; The c / m alternative is a fake to guide reload to load directly into
(define_insn "fpu_switch"
[(set (match_operand:PSI 0 "general_movdst_operand" "=c,c,r,c,c,r,m,r,<")
(match_operand:PSI 1 "general_movsrc_operand" "c,>,m,m,r,r,r,!c,c"))]
- "TARGET_SH3E
+ "TARGET_SH2E
&& (! reload_completed
|| true_regnum (operands[0]) != FPSCR_REG
|| GET_CODE (operands[1]) != MEM
(define_split
[(set (reg:PSI FPSCR_REG)
(mem:PSI (match_operand:SI 0 "register_operand" "")))]
- "TARGET_SH4 && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))"
+ "(TARGET_SH4 || TARGET_SH2A_DOUBLE) && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))"
[(set (match_dup 0) (match_dup 0))]
"
{
rtx insn = emit_insn (gen_fpu_switch (get_fpscr_rtx (),
- gen_rtx (MEM, PSImode,
- gen_rtx (POST_INC, Pmode,
+ gen_rtx_MEM (PSImode,
+ gen_rtx_POST_INC (Pmode,
operands[0]))));
- REG_NOTES (insn) = gen_rtx (EXPR_LIST, REG_INC, operands[0], NULL_RTX);
+ REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_INC, operands[0], NULL_RTX);
}")
(define_split
[(set (reg:PSI FPSCR_REG)
(mem:PSI (match_operand:SI 0 "register_operand" "")))]
- "TARGET_SH4"
+ "(TARGET_SH4 || TARGET_SH2A_DOUBLE)"
[(set (match_dup 0) (plus:SI (match_dup 0) (const_int -4)))]
"
{
rtx insn = emit_insn (gen_fpu_switch (get_fpscr_rtx (),
- gen_rtx (MEM, PSImode,
- gen_rtx (POST_INC, Pmode,
+ gen_rtx_MEM (PSImode,
+ gen_rtx_POST_INC (Pmode,
operands[0]))));
- REG_NOTES (insn) = gen_rtx (EXPR_LIST, REG_INC, operands[0], NULL_RTX);
+ REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_INC, operands[0], NULL_RTX);
}")
;; ??? This uses the fp unit, but has no type indicating that.
(define_insn "toggle_sz"
[(set (reg:PSI FPSCR_REG)
(xor:PSI (reg:PSI FPSCR_REG) (const_int 1048576)))]
- "TARGET_SH4"
- "fschg")
+ "(TARGET_SH4 || TARGET_SH2A_DOUBLE)"
+ "fschg"
+ [(set_attr "type" "fp") (set_attr "fp_set" "unknown")])
+
+;; There's no way we can use it today, since optimize mode switching
+;; doesn't enable us to know from which mode we're switching to the
+;; mode it requests, to tell whether we can use a relative mode switch
+;; (like toggle_pr) or an absolute switch (like loading fpscr from
+;; memory).
+(define_insn "toggle_pr"
+ [(set (reg:PSI FPSCR_REG)
+ (xor:PSI (reg:PSI FPSCR_REG) (const_int 524288)))]
+ "TARGET_SH4A_FP && ! TARGET_FPU_SINGLE"
+ "fpchg"
+ [(set_attr "type" "fp")])
(define_expand "addsf3"
[(set (match_operand:SF 0 "arith_reg_operand" "")
operands[7] = gen_rtx_REG (SFmode,
(true_regnum (operands[0])
+ (INTVAL (operands[3]) ^ endian)));
- operands[6] = gen_rtx (GET_CODE (operands[2]), SFmode, op1);
+ operands[6] = gen_rtx_fmt_e (GET_CODE (operands[2]), SFmode, op1);
}"
[(set_attr "type" "fparith_media")])
(vec_concat:V2SF
(vec_select:SF
(match_dup 0)
- (parallel [(not:BI (match_operand 4 "const_int_operand" "n"))]))
+ (parallel [(match_operand 7 "const_int_operand" "n")]))
(match_operator:SF 3 "binary_float_operator"
[(vec_select:SF (match_operand:V2SF 1 "fp_arith_reg_operand" "f")
(parallel [(match_operand 5
(vec_select:SF (match_operand:V2SF 2 "fp_arith_reg_operand" "f")
(parallel [(match_operand 6
"const_int_operand" "n")]))]))
- (parallel [(not:BI (match_dup 4)) (match_dup 4)])))]
- "TARGET_SHMEDIA_FPU"
+ (parallel [(match_dup 7) (match_operand 4 "const_int_operand" "n")])))]
+ "TARGET_SHMEDIA_FPU && INTVAL (operands[4]) != INTVAL (operands[7])"
"#"
- "TARGET_SHMEDIA_FPU && reload_completed"
- [(set (match_dup 7) (match_dup 8))]
+ "&& reload_completed"
+ [(set (match_dup 8) (match_dup 9))]
"
{
int endian = TARGET_LITTLE_ENDIAN ? 0 : 1;
(true_regnum (operands[2])
+ (INTVAL (operands[6]) ^ endian)));
- operands[7] = gen_rtx_REG (SFmode,
+ operands[8] = gen_rtx_REG (SFmode,
(true_regnum (operands[0])
+ (INTVAL (operands[4]) ^ endian)));
- operands[8] = gen_rtx (GET_CODE (operands[3]), SFmode, op1, op2);
+ operands[9] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SFmode, op1, op2);
}"
[(set_attr "type" "fparith_media")])
"TARGET_SH2E || TARGET_SHMEDIA_FPU"
"
{
- if (TARGET_SH4)
+ if (TARGET_SH4 || TARGET_SH2A_SINGLE)
expand_sf_binop (&gen_mulsf3_i4, operands);
else if (TARGET_SH2E)
emit_insn (gen_mulsf3_ie (operands[0], operands[1], operands[2]));
[(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
(mult:SF (match_operand:SF 1 "fp_arith_reg_operand" "%0")
(match_operand:SF 2 "fp_arith_reg_operand" "f")))]
- "TARGET_SH2E && ! TARGET_SH4"
+ "TARGET_SH2E && ! (TARGET_SH4 || TARGET_SH2A_SINGLE)"
"fmul %2,%0"
[(set_attr "type" "fp")])
"TARGET_SH2E || TARGET_SHMEDIA_FPU"
"
{
- if (TARGET_SH4)
+ if (TARGET_SH4 || TARGET_SH2A_SINGLE)
{
emit_sf_insn (gen_floatsisf2_i4 (operands[0], operands[1], get_fpscr_rtx ()));
DONE;
[(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
(float:SF (match_operand:SI 1 "fpul_operand" "y")))
(use (match_operand:PSI 2 "fpscr_operand" "c"))]
- "TARGET_SH4"
+ "(TARGET_SH4 || TARGET_SH2A_SINGLE)"
"float %1,%0"
[(set_attr "type" "fp")
(set_attr "fp_mode" "single")])
(define_insn "*floatsisf2_ie"
[(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
(float:SF (match_operand:SI 1 "fpul_operand" "y")))]
- "TARGET_SH2E && ! TARGET_SH4"
+ "TARGET_SH2E && ! (TARGET_SH4 || TARGET_SH2A_SINGLE)"
"float %1,%0"
[(set_attr "type" "fp")])
"TARGET_SH2E || TARGET_SHMEDIA_FPU"
"
{
- if (TARGET_SH4)
+ if (TARGET_SH4 || TARGET_SH2A_SINGLE)
{
emit_sf_insn (gen_fix_truncsfsi2_i4 (operands[0], operands[1], get_fpscr_rtx ()));
DONE;
[(set (match_operand:SI 0 "fpul_operand" "=y")
(fix:SI (match_operand:SF 1 "fp_arith_reg_operand" "f")))
(use (match_operand:PSI 2 "fpscr_operand" "c"))]
- "TARGET_SH4"
+ "(TARGET_SH4 || TARGET_SH2A_SINGLE)"
"ftrc %1,%0"
[(set_attr "type" "ftrc_s")
(set_attr "fp_mode" "single")])
(define_insn "*fixsfsi"
[(set (match_operand:SI 0 "fpul_operand" "=y")
(fix:SI (match_operand:SF 1 "fp_arith_reg_operand" "f")))]
- "TARGET_SH2E && ! TARGET_SH4"
+ "TARGET_SH2E && ! (TARGET_SH4 || TARGET_SH2A_SINGLE)"
"ftrc %1,%0"
[(set_attr "type" "fp")])
[(set (reg:SI T_REG)
(gt:SI (match_operand:SF 0 "fp_arith_reg_operand" "f")
(match_operand:SF 1 "fp_arith_reg_operand" "f")))]
- "TARGET_SH2E && ! TARGET_SH4"
+ "TARGET_SH2E && ! (TARGET_SH4 || TARGET_SH2A_SINGLE)"
"fcmp/gt %1,%0"
[(set_attr "type" "fp")
(set_attr "fp_mode" "single")])
[(set (reg:SI T_REG)
(eq:SI (match_operand:SF 0 "fp_arith_reg_operand" "f")
(match_operand:SF 1 "fp_arith_reg_operand" "f")))]
- "TARGET_SH2E && ! TARGET_SH4"
+ "TARGET_SH2E && ! (TARGET_SH4 || TARGET_SH2A_SINGLE)"
"fcmp/eq %1,%0"
[(set_attr "type" "fp")
(set_attr "fp_mode" "single")])
(ior:SI (reg:SI T_REG)
(eq:SI (match_operand:SF 0 "fp_arith_reg_operand" "f")
(match_operand:SF 1 "fp_arith_reg_operand" "f"))))]
- "TARGET_SH2E && TARGET_IEEE && ! TARGET_SH4"
+ "TARGET_SH2E && TARGET_IEEE && ! (TARGET_SH4 || TARGET_SH2A_SINGLE)"
"* return output_ieee_ccmpeq (insn, operands);"
[(set_attr "length" "4")])
(gt:SI (match_operand:SF 0 "fp_arith_reg_operand" "f")
(match_operand:SF 1 "fp_arith_reg_operand" "f")))
(use (match_operand:PSI 2 "fpscr_operand" "c"))]
- "TARGET_SH4"
+ "(TARGET_SH4 || TARGET_SH2A_SINGLE)"
"fcmp/gt %1,%0"
[(set_attr "type" "fp")
(set_attr "fp_mode" "single")])
(eq:SI (match_operand:SF 0 "fp_arith_reg_operand" "f")
(match_operand:SF 1 "fp_arith_reg_operand" "f")))
(use (match_operand:PSI 2 "fpscr_operand" "c"))]
- "TARGET_SH4"
+ "(TARGET_SH4 || TARGET_SH2A_SINGLE)"
"fcmp/eq %1,%0"
[(set_attr "type" "fp")
(set_attr "fp_mode" "single")])
(eq:SI (match_operand:SF 0 "fp_arith_reg_operand" "f")
(match_operand:SF 1 "fp_arith_reg_operand" "f"))))
(use (match_operand:PSI 2 "fpscr_operand" "c"))]
- "TARGET_IEEE && TARGET_SH4"
+ "TARGET_IEEE && (TARGET_SH4 || TARGET_SH2A_SINGLE)"
"* return output_ieee_ccmpeq (insn, operands);"
[(set_attr "length" "4")
(set_attr "fp_mode" "single")])
[(set_attr "type" "fdiv")
(set_attr "fp_mode" "single")])
+(define_insn "rsqrtsf2"
+ [(set (match_operand:SF 0 "register_operand" "=f")
+ (div:SF (match_operand:SF 1 "immediate_operand" "i")
+ (sqrt:SF (match_operand:SF 2 "register_operand" "0"))))
+ (use (match_operand:PSI 3 "fpscr_operand" "c"))]
+ "TARGET_SH4A_FP && flag_unsafe_math_optimizations
+ && operands[1] == CONST1_RTX (SFmode)"
+ "fsrra %0"
+ [(set_attr "type" "fsrra")
+ (set_attr "fp_mode" "single")])
+
+(define_insn "fsca"
+ [(set (match_operand:V2SF 0 "fp_arith_reg_operand" "=f")
+ (vec_concat:V2SF
+ (unspec:SF [(mult:SF
+ (float:SF (match_operand:SI 1 "fpul_operand" "y"))
+ (match_operand:SF 2 "immediate_operand" "i"))
+ ] UNSPEC_FSINA)
+ (unspec:SF [(mult:SF (float:SF (match_dup 1)) (match_dup 2))
+ ] UNSPEC_FCOSA)))
+ (use (match_operand:PSI 3 "fpscr_operand" "c"))]
+ "TARGET_SH4A_FP && flag_unsafe_math_optimizations
+ && operands[2] == sh_fsca_int2sf ()"
+ "fsca fpul,%d0"
+ [(set_attr "type" "fsca")
+ (set_attr "fp_mode" "single")])
+
+(define_expand "sinsf2"
+ [(set (match_operand:SF 0 "nonimmediate_operand" "")
+ (unspec:SF [(match_operand:SF 1 "fp_arith_reg_operand" "")]
+ UNSPEC_FSINA))]
+ "TARGET_SH4A_FP && flag_unsafe_math_optimizations"
+ "
+{
+ rtx scaled = gen_reg_rtx (SFmode);
+ rtx truncated = gen_reg_rtx (SImode);
+ rtx fsca = gen_reg_rtx (V2SFmode);
+ rtx scale_reg = force_reg (SFmode, sh_fsca_sf2int ());
+
+ emit_sf_insn (gen_mulsf3 (scaled, operands[1], scale_reg));
+ emit_sf_insn (gen_fix_truncsfsi2 (truncated, scaled));
+ emit_sf_insn (gen_fsca (fsca, truncated, sh_fsca_int2sf (),
+ get_fpscr_rtx ()));
+ emit_move_insn (operands[0], gen_rtx_SUBREG (SFmode, fsca, 0));
+ DONE;
+}")
+
+(define_expand "cossf2"
+ [(set (match_operand:SF 0 "nonimmediate_operand" "")
+ (unspec:SF [(match_operand:SF 1 "fp_arith_reg_operand" "")]
+ UNSPEC_FCOSA))]
+ "TARGET_SH4A_FP && flag_unsafe_math_optimizations"
+ "
+{
+ rtx scaled = gen_reg_rtx (SFmode);
+ rtx truncated = gen_reg_rtx (SImode);
+ rtx fsca = gen_reg_rtx (V2SFmode);
+ rtx scale_reg = force_reg (SFmode, sh_fsca_sf2int ());
+
+ emit_sf_insn (gen_mulsf3 (scaled, operands[1], scale_reg));
+ emit_sf_insn (gen_fix_truncsfsi2 (truncated, scaled));
+ emit_sf_insn (gen_fsca (fsca, truncated, sh_fsca_int2sf (),
+ get_fpscr_rtx ()));
+ emit_move_insn (operands[0], gen_rtx_SUBREG (SFmode, fsca, 4));
+ DONE;
+}")
+
+(define_expand "sindf2"
+ [(set (match_operand:DF 0 "fp_arith_reg_operand" "")
+ (unspec:DF [(match_operand:DF 1 "fp_arith_reg_operand" "")]
+ UNSPEC_FSINA))]
+ "TARGET_SH4A_FP && ! TARGET_FPU_SINGLE && flag_unsafe_math_optimizations"
+ "
+{
+ rtx scaled = gen_reg_rtx (DFmode);
+ rtx truncated = gen_reg_rtx (SImode);
+ rtx fsca = gen_reg_rtx (V2SFmode);
+ rtx scale_reg = force_reg (DFmode, sh_fsca_df2int ());
+ rtx sfresult = gen_reg_rtx (SFmode);
+
+ emit_df_insn (gen_muldf3 (scaled, operands[1], scale_reg));
+ emit_df_insn (gen_fix_truncdfsi2 (truncated, scaled));
+ emit_sf_insn (gen_fsca (fsca, truncated, sh_fsca_int2sf (),
+ get_fpscr_rtx ()));
+ emit_move_insn (sfresult, gen_rtx_SUBREG (SFmode, fsca, 0));
+ emit_df_insn (gen_extendsfdf2 (operands[0], sfresult));
+ DONE;
+}")
+
+(define_expand "cosdf2"
+ [(set (match_operand:DF 0 "fp_arith_reg_operand" "")
+ (unspec:DF [(match_operand:DF 1 "fp_arith_reg_operand" "")]
+ UNSPEC_FCOSA))]
+ "TARGET_SH4A_FP && ! TARGET_FPU_SINGLE && flag_unsafe_math_optimizations"
+ "
+{
+ rtx scaled = gen_reg_rtx (DFmode);
+ rtx truncated = gen_reg_rtx (SImode);
+ rtx fsca = gen_reg_rtx (V2SFmode);
+ rtx scale_reg = force_reg (DFmode, sh_fsca_df2int ());
+ rtx sfresult = gen_reg_rtx (SFmode);
+
+ emit_df_insn (gen_muldf3 (scaled, operands[1], scale_reg));
+ emit_df_insn (gen_fix_truncdfsi2 (truncated, scaled));
+ emit_sf_insn (gen_fsca (fsca, truncated, sh_fsca_int2sf (),
+ get_fpscr_rtx ()));
+ emit_move_insn (sfresult, gen_rtx_SUBREG (SFmode, fsca, 4));
+ emit_df_insn (gen_extendsfdf2 (operands[0], sfresult));
+ DONE;
+}")
+
(define_expand "abssf2"
[(set (match_operand:SF 0 "fp_arith_reg_operand" "")
(abs:SF (match_operand:SF 1 "fp_arith_reg_operand" "")))]
[(set (match_operand:DF 0 "fp_arith_reg_operand" "")
(plus:DF (match_operand:DF 1 "fp_arith_reg_operand" "")
(match_operand:DF 2 "fp_arith_reg_operand" "")))]
- "TARGET_SH4 || TARGET_SHMEDIA_FPU"
+ "(TARGET_SH4 || TARGET_SH2A_DOUBLE) || TARGET_SHMEDIA_FPU"
"
{
- if (TARGET_SH4)
+ if (TARGET_SH4 || TARGET_SH2A_DOUBLE)
{
expand_df_binop (&gen_adddf3_i, operands);
DONE;
(plus:DF (match_operand:DF 1 "fp_arith_reg_operand" "%0")
(match_operand:DF 2 "fp_arith_reg_operand" "f")))
(use (match_operand:PSI 3 "fpscr_operand" "c"))]
- "TARGET_SH4"
+ "(TARGET_SH4 || TARGET_SH2A_DOUBLE)"
"fadd %2,%0"
[(set_attr "type" "dfp_arith")
(set_attr "fp_mode" "double")])
[(set (match_operand:DF 0 "fp_arith_reg_operand" "")
(minus:DF (match_operand:DF 1 "fp_arith_reg_operand" "")
(match_operand:DF 2 "fp_arith_reg_operand" "")))]
- "TARGET_SH4 || TARGET_SHMEDIA_FPU"
+ "(TARGET_SH4 || TARGET_SH2A_DOUBLE) || TARGET_SHMEDIA_FPU"
"
{
- if (TARGET_SH4)
+ if (TARGET_SH4 || TARGET_SH2A_DOUBLE)
{
expand_df_binop (&gen_subdf3_i, operands);
DONE;
(minus:DF (match_operand:DF 1 "fp_arith_reg_operand" "0")
(match_operand:DF 2 "fp_arith_reg_operand" "f")))
(use (match_operand:PSI 3 "fpscr_operand" "c"))]
- "TARGET_SH4"
+ "(TARGET_SH4 || TARGET_SH2A_DOUBLE)"
"fsub %2,%0"
[(set_attr "type" "dfp_arith")
(set_attr "fp_mode" "double")])
[(set (match_operand:DF 0 "fp_arith_reg_operand" "")
(mult:DF (match_operand:DF 1 "fp_arith_reg_operand" "")
(match_operand:DF 2 "fp_arith_reg_operand" "")))]
- "TARGET_SH4 || TARGET_SHMEDIA_FPU"
+ "(TARGET_SH4 || TARGET_SH2A_DOUBLE) || TARGET_SHMEDIA_FPU"
"
{
- if (TARGET_SH4)
+ if (TARGET_SH4 || TARGET_SH2A_DOUBLE)
{
expand_df_binop (&gen_muldf3_i, operands);
DONE;
(mult:DF (match_operand:DF 1 "fp_arith_reg_operand" "%0")
(match_operand:DF 2 "fp_arith_reg_operand" "f")))
(use (match_operand:PSI 3 "fpscr_operand" "c"))]
- "TARGET_SH4"
+ "(TARGET_SH4 || TARGET_SH2A_DOUBLE)"
"fmul %2,%0"
[(set_attr "type" "dfp_arith")
(set_attr "fp_mode" "double")])
[(set (match_operand:DF 0 "fp_arith_reg_operand" "")
(div:DF (match_operand:DF 1 "fp_arith_reg_operand" "")
(match_operand:DF 2 "fp_arith_reg_operand" "")))]
- "TARGET_SH4 || TARGET_SHMEDIA_FPU"
+ "(TARGET_SH4 || TARGET_SH2A_DOUBLE) || TARGET_SHMEDIA_FPU"
"
{
- if (TARGET_SH4)
+ if (TARGET_SH4 || TARGET_SH2A_DOUBLE)
{
expand_df_binop (&gen_divdf3_i, operands);
DONE;
(div:DF (match_operand:DF 1 "fp_arith_reg_operand" "0")
(match_operand:DF 2 "fp_arith_reg_operand" "f")))
(use (match_operand:PSI 3 "fpscr_operand" "c"))]
- "TARGET_SH4"
+ "(TARGET_SH4 || TARGET_SH2A_DOUBLE)"
"fdiv %2,%0"
[(set_attr "type" "dfdiv")
(set_attr "fp_mode" "double")])
(define_expand "floatsidf2"
[(set (match_operand:DF 0 "fp_arith_reg_operand" "")
(float:DF (match_operand:SI 1 "fpul_operand" "")))]
- "TARGET_SH4 || TARGET_SHMEDIA_FPU"
+ "(TARGET_SH4 || TARGET_SH2A_DOUBLE) || TARGET_SHMEDIA_FPU"
"
{
- if (TARGET_SH4)
+ if (TARGET_SH4 || TARGET_SH2A_DOUBLE)
{
emit_df_insn (gen_floatsidf2_i (operands[0], operands[1],
get_fpscr_rtx ()));
[(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
(float:DF (match_operand:SI 1 "fpul_operand" "y")))
(use (match_operand:PSI 2 "fpscr_operand" "c"))]
- "TARGET_SH4"
+ "(TARGET_SH4 || TARGET_SH2A_DOUBLE)"
"float %1,%0"
[(set_attr "type" "dfp_conv")
(set_attr "fp_mode" "double")])
(define_expand "fix_truncdfsi2"
[(set (match_operand:SI 0 "fpul_operand" "")
(fix:SI (match_operand:DF 1 "fp_arith_reg_operand" "")))]
- "TARGET_SH4 || TARGET_SHMEDIA_FPU"
+ "(TARGET_SH4 || TARGET_SH2A_DOUBLE) || TARGET_SHMEDIA_FPU"
"
{
- if (TARGET_SH4)
+ if (TARGET_SH4 || TARGET_SH2A_DOUBLE)
{
emit_df_insn (gen_fix_truncdfsi2_i (operands[0], operands[1],
get_fpscr_rtx ()));
[(set (match_operand:SI 0 "fpul_operand" "=y")
(fix:SI (match_operand:DF 1 "fp_arith_reg_operand" "f")))
(use (match_operand:PSI 2 "fpscr_operand" "c"))]
- "TARGET_SH4"
+ "(TARGET_SH4 || TARGET_SH2A_DOUBLE)"
"ftrc %1,%0"
[(set_attr "type" "dfp_conv")
(set_attr "dfp_comp" "no")
(gt:SI (match_operand:DF 0 "arith_reg_operand" "f")
(match_operand:DF 1 "arith_reg_operand" "f")))
(use (match_operand:PSI 2 "fpscr_operand" "c"))]
- "TARGET_SH4"
+ "(TARGET_SH4 || TARGET_SH2A_DOUBLE)"
"fcmp/gt %1,%0"
[(set_attr "type" "dfp_cmp")
(set_attr "fp_mode" "double")])
(eq:SI (match_operand:DF 0 "arith_reg_operand" "f")
(match_operand:DF 1 "arith_reg_operand" "f")))
(use (match_operand:PSI 2 "fpscr_operand" "c"))]
- "TARGET_SH4"
+ "(TARGET_SH4 || TARGET_SH2A_DOUBLE)"
"fcmp/eq %1,%0"
[(set_attr "type" "dfp_cmp")
(set_attr "fp_mode" "double")])
(eq:SI (match_operand:DF 0 "arith_reg_operand" "f")
(match_operand:DF 1 "arith_reg_operand" "f"))))
(use (match_operand:PSI 2 "fpscr_operand" "c"))]
- "TARGET_IEEE && TARGET_SH4"
+ "TARGET_IEEE && (TARGET_SH4 || TARGET_SH2A_DOUBLE)"
"* return output_ieee_ccmpeq (insn, operands);"
[(set_attr "length" "4")
(set_attr "fp_mode" "double")])
[(set (reg:SI T_REG)
(compare (match_operand:DF 0 "arith_operand" "")
(match_operand:DF 1 "arith_operand" "")))]
- "TARGET_SH4 || TARGET_SHMEDIA_FPU"
+ "(TARGET_SH4 || TARGET_SH2A_DOUBLE) || TARGET_SHMEDIA_FPU"
"
{
sh_compare_op0 = operands[0];
(define_expand "negdf2"
[(set (match_operand:DF 0 "arith_reg_operand" "")
(neg:DF (match_operand:DF 1 "arith_reg_operand" "")))]
- "TARGET_SH4 || TARGET_SHMEDIA_FPU"
+ "(TARGET_SH4 || TARGET_SH2A_DOUBLE) || TARGET_SHMEDIA_FPU"
"
{
- if (TARGET_SH4)
+ if (TARGET_SH4 || TARGET_SH2A_DOUBLE)
{
expand_df_unop (&gen_negdf2_i, operands);
DONE;
[(set (match_operand:DF 0 "arith_reg_operand" "=f")
(neg:DF (match_operand:DF 1 "arith_reg_operand" "0")))
(use (match_operand:PSI 2 "fpscr_operand" "c"))]
- "TARGET_SH4"
+ "(TARGET_SH4 || TARGET_SH2A_DOUBLE)"
"fneg %0"
[(set_attr "type" "fmove")
(set_attr "fp_mode" "double")])
(define_expand "sqrtdf2"
[(set (match_operand:DF 0 "arith_reg_operand" "")
(sqrt:DF (match_operand:DF 1 "arith_reg_operand" "")))]
- "TARGET_SH4 || TARGET_SHMEDIA_FPU"
+ "(TARGET_SH4 || TARGET_SH2A_DOUBLE) || TARGET_SHMEDIA_FPU"
"
{
- if (TARGET_SH4)
+ if (TARGET_SH4 || TARGET_SH2A_DOUBLE)
{
expand_df_unop (&gen_sqrtdf2_i, operands);
DONE;
[(set (match_operand:DF 0 "arith_reg_operand" "=f")
(sqrt:DF (match_operand:DF 1 "arith_reg_operand" "0")))
(use (match_operand:PSI 2 "fpscr_operand" "c"))]
- "TARGET_SH4"
+ "(TARGET_SH4 || TARGET_SH2A_DOUBLE)"
"fsqrt %0"
[(set_attr "type" "dfdiv")
(set_attr "fp_mode" "double")])
(define_expand "absdf2"
[(set (match_operand:DF 0 "arith_reg_operand" "")
(abs:DF (match_operand:DF 1 "arith_reg_operand" "")))]
- "TARGET_SH4 || TARGET_SHMEDIA_FPU"
+ "(TARGET_SH4 || TARGET_SH2A_DOUBLE) || TARGET_SHMEDIA_FPU"
"
{
- if (TARGET_SH4)
+ if (TARGET_SH4 || TARGET_SH2A_DOUBLE)
{
expand_df_unop (&gen_absdf2_i, operands);
DONE;
[(set (match_operand:DF 0 "arith_reg_operand" "=f")
(abs:DF (match_operand:DF 1 "arith_reg_operand" "0")))
(use (match_operand:PSI 2 "fpscr_operand" "c"))]
- "TARGET_SH4"
+ "(TARGET_SH4 || TARGET_SH2A_DOUBLE)"
"fabs %0"
[(set_attr "type" "fmove")
(set_attr "fp_mode" "double")])
(define_expand "extendsfdf2"
[(set (match_operand:DF 0 "fp_arith_reg_operand" "")
(float_extend:DF (match_operand:SF 1 "fpul_operand" "")))]
- "TARGET_SH4 || TARGET_SHMEDIA_FPU"
+ "(TARGET_SH4 || TARGET_SH2A_DOUBLE) || TARGET_SHMEDIA_FPU"
"
{
- if (TARGET_SH4)
+ if (TARGET_SH4 || TARGET_SH2A_DOUBLE)
{
emit_df_insn (gen_extendsfdf2_i4 (operands[0], operands[1],
get_fpscr_rtx ()));
[(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
(float_extend:DF (match_operand:SF 1 "fpul_operand" "y")))
(use (match_operand:PSI 2 "fpscr_operand" "c"))]
- "TARGET_SH4"
+ "(TARGET_SH4 || TARGET_SH2A_DOUBLE)"
"fcnvsd %1,%0"
[(set_attr "type" "fp")
(set_attr "fp_mode" "double")])
(define_expand "truncdfsf2"
[(set (match_operand:SF 0 "fpul_operand" "")
(float_truncate:SF (match_operand:DF 1 "fp_arith_reg_operand" "")))]
- "TARGET_SH4 || TARGET_SHMEDIA_FPU"
+ "(TARGET_SH4 || TARGET_SH2A_DOUBLE) || TARGET_SHMEDIA_FPU"
"
{
- if (TARGET_SH4)
+ if (TARGET_SH4 || TARGET_SH2A_DOUBLE)
{
emit_df_insn (gen_truncdfsf2_i4 (operands[0], operands[1],
get_fpscr_rtx ()));
[(set (match_operand:SF 0 "fpul_operand" "=y")
(float_truncate:SF (match_operand:DF 1 "fp_arith_reg_operand" "f")))
(use (match_operand:PSI 2 "fpscr_operand" "c"))]
- "TARGET_SH4"
+ "(TARGET_SH4 || TARGET_SH2A_DOUBLE)"
"fcnvds %1,%0"
[(set_attr "type" "fp")
(set_attr "fp_mode" "double")])
"
{
rtx addr_target, orig_address, shift_reg, qi_val;
- HOST_WIDE_INT bitsize, size, v;
+ HOST_WIDE_INT bitsize, size, v = 0;
rtx x = operands[3];
/* ??? expmed doesn't care for non-register predicates. */
emit_insn (gen_lshrsi3_k (shift_reg, shift_reg, GEN_INT (8)));
qi_val = gen_rtx_SUBREG (QImode, shift_reg, 3);
}
- emit_insn (gen_addsi3 (addr_target, addr_target, GEN_INT (-1)));
+ emit_insn (gen_addsi3 (addr_target, addr_target, constm1_rtx));
emit_insn (gen_movqi (operands[0], qi_val));
}
DONE;
}")
+
+(define_insn "movua"
+ [(set (match_operand:SI 0 "register_operand" "=z")
+ (sign_extract:SI (match_operand:SI 1 "unaligned_load_operand" "Sua>")
+ (const_int 32) (const_int 0)))]
+ "TARGET_SH4A_ARCH"
+ "movua.l %1,%0"
+ [(set_attr "type" "movua")])
+
+;; We shouldn't need this, but cse replaces increments with references
+;; to other regs before flow has a chance to create post_inc
+;; addressing modes, and only postreload's cse_move2add brings the
+;; increments back to a usable form.
+(define_peephole2
+ [(set (match_operand:SI 0 "register_operand" "")
+ (sign_extract:SI (mem:SI (match_operand:SI 1 "register_operand" ""))
+ (const_int 32) (const_int 0)))
+ (set (match_dup 1) (plus:SI (match_dup 1) (const_int 4)))]
+ "TARGET_SH4A_ARCH && REGNO (operands[0]) != REGNO (operands[1])"
+ [(set (match_operand:SI 0 "register_operand" "")
+ (sign_extract:SI (mem:SI (post_inc:SI
+ (match_operand:SI 1 "register_operand" "")))
+ (const_int 32) (const_int 0)))]
+ "")
+
+(define_expand "extv"
+ [(set (match_operand:SI 0 "register_operand" "")
+ (sign_extract:SI (match_operand:QI 1 "unaligned_load_operand" "")
+ (match_operand 2 "const_int_operand" "")
+ (match_operand 3 "const_int_operand" "")))]
+ "TARGET_SH4A_ARCH"
+{
+ if (TARGET_SH4A_ARCH
+ && INTVAL (operands[2]) == 32
+ && INTVAL (operands[3]) == -24 * (BITS_BIG_ENDIAN != BYTES_BIG_ENDIAN)
+ && GET_CODE (operands[1]) == MEM && MEM_ALIGN (operands[1]) < 32)
+ {
+ emit_insn (gen_movua (operands[0],
+ adjust_address (operands[1], SImode, 0)));
+ DONE;
+ }
+
+ FAIL;
+})
+
+(define_expand "extzv"
+ [(set (match_operand:SI 0 "register_operand" "")
+ (zero_extract:SI (match_operand:QI 1 "unaligned_load_operand" "")
+ (match_operand 2 "const_int_operand" "")
+ (match_operand 3 "const_int_operand" "")))]
+ "TARGET_SH4A_ARCH"
+{
+ if (TARGET_SH4A_ARCH
+ && INTVAL (operands[2]) == 32
+ && INTVAL (operands[3]) == -24 * (BITS_BIG_ENDIAN != BYTES_BIG_ENDIAN)
+ && GET_CODE (operands[1]) == MEM && MEM_ALIGN (operands[1]) < 32)
+ {
+ emit_insn (gen_movua (operands[0],
+ adjust_address (operands[1], SImode, 0)));
+ DONE;
+ }
+
+ FAIL;
+})
+
\f
;; -------------------------------------------------------------------------
;; Peepholes
(define_insn "movv8qi_i"
[(set (match_operand:V8QI 0 "general_movdst_operand" "=r,r,r,rl,m")
- (match_operand:V8QI 1 "general_movsrc_operand" "r,JSU,nW,m,rlU"))]
+ (match_operand:V8QI 1 "general_movsrc_operand" "r,I16C16Z,nW,m,rlZ"))]
"TARGET_SHMEDIA
&& (register_operand (operands[0], V8QImode)
|| sh_register_operand (operands[1], V8QImode))"
(match_operand 1 "sh_rep_vec" ""))]
"TARGET_SHMEDIA && reload_completed
&& GET_MODE (operands[0]) == GET_MODE (operands[1])
- && VECTOR_MODE_SUPPORTED_P (GET_MODE (operands[0]))
+ && sh_vector_mode_supported_p (GET_MODE (operands[0]))
&& GET_MODE_SIZE (GET_MODE (operands[0])) == 8
&& (XVECEXP (operands[1], 0, 0) != const0_rtx
|| XVECEXP (operands[1], 0, 1) != const0_rtx)
if (unit_size < 2)
{
if (GET_CODE (operands[1]) == CONST_INT && GET_CODE (elt1) == CONST_INT)
- operands[1] = GEN_INT (TARGET_LITTLE_ENDIAN
- ? INTVAL (operands[1]) + (INTVAL (elt1) << 8)
- : (INTVAL (operands[1]) << 8) + INTVAL (elt1));
+ operands[1]
+ = GEN_INT (TARGET_LITTLE_ENDIAN
+ ? (INTVAL (operands[1]) & 0xff) + (INTVAL (elt1) << 8)
+ : (INTVAL (operands[1]) << 8) + (INTVAL (elt1) & 0xff));
else
{
operands[0] = gen_rtx_REG (V2QImode, true_regnum (operands[0]));
(match_operand 1 "sh_const_vec" ""))]
"TARGET_SHMEDIA && reload_completed
&& GET_MODE (operands[0]) == GET_MODE (operands[1])
- && VECTOR_MODE_SUPPORTED_P (GET_MODE (operands[0]))
+ && sh_vector_mode_supported_p (GET_MODE (operands[0]))
&& operands[1] != CONST0_RTX (GET_MODE (operands[1]))"
[(set (match_dup 0) (match_dup 1))]
"
(define_insn "movv2hi_i"
[(set (match_operand:V2HI 0 "general_movdst_operand" "=r,r,r,rl,m")
- (match_operand:V2HI 1 "general_movsrc_operand" "r,JSU,nW,m,rlU"))]
+ (match_operand:V2HI 1 "general_movsrc_operand" "r,I16C16Z,nW,m,rlZ"))]
"TARGET_SHMEDIA
&& (register_operand (operands[0], V2HImode)
|| sh_register_operand (operands[1], V2HImode))"
(define_insn "movv4hi_i"
[(set (match_operand:V4HI 0 "general_movdst_operand" "=r,r,r,rl,m")
- (match_operand:V4HI 1 "general_movsrc_operand" "r,JSU,nW,m,rlU"))]
+ (match_operand:V4HI 1 "general_movsrc_operand" "r,I16C16Z,nW,m,rlZ"))]
"TARGET_SHMEDIA
&& (register_operand (operands[0], V4HImode)
|| sh_register_operand (operands[1], V4HImode))"
(define_insn "movv2si_i"
[(set (match_operand:V2SI 0 "general_movdst_operand" "=r,r,r,rl,m")
- (match_operand:V2SI 1 "general_movsrc_operand" "r,JSU,nW,m,rlU"))]
+ (match_operand:V2SI 1 "general_movsrc_operand" "r,I16C16Z,nW,m,rlZ"))]
"TARGET_SHMEDIA
&& (register_operand (operands[0], V2SImode)
|| sh_register_operand (operands[1], V2SImode))"
(define_insn "negcmpeqv8qi"
[(set (match_operand:V8QI 0 "arith_reg_dest" "=r")
- (neg:V8QI (eq:V8QI (match_operand:V8QI 1 "arith_reg_or_0_operand" "%rU")
- (match_operand:V8QI 2 "arith_reg_or_0_operand" "rU"))))]
+ (neg:V8QI (eq:V8QI (match_operand:V8QI 1 "arith_reg_or_0_operand" "%rZ")
+ (match_operand:V8QI 2 "arith_reg_or_0_operand" "rZ"))))]
"TARGET_SHMEDIA"
"mcmpeq.b %N1, %N2, %0"
[(set_attr "type" "mcmp_media")])
(define_insn "negcmpeqv2si"
[(set (match_operand:V2SI 0 "arith_reg_dest" "=r")
- (neg:V2SI (eq:V2SI (match_operand:V2SI 1 "arith_reg_or_0_operand" "%rU")
- (match_operand:V2SI 2 "arith_reg_or_0_operand" "rU"))))]
+ (neg:V2SI (eq:V2SI (match_operand:V2SI 1 "arith_reg_or_0_operand" "%rZ")
+ (match_operand:V2SI 2 "arith_reg_or_0_operand" "rZ"))))]
"TARGET_SHMEDIA"
"mcmpeq.l %N1, %N2, %0"
[(set_attr "type" "mcmp_media")])
(define_insn "negcmpeqv4hi"
[(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
- (neg:V4HI (eq:V4HI (match_operand:V4HI 1 "arith_reg_or_0_operand" "%rU")
- (match_operand:V4HI 2 "arith_reg_or_0_operand" "rU"))))]
+ (neg:V4HI (eq:V4HI (match_operand:V4HI 1 "arith_reg_or_0_operand" "%rZ")
+ (match_operand:V4HI 2 "arith_reg_or_0_operand" "rZ"))))]
"TARGET_SHMEDIA"
"mcmpeq.w %N1, %N2, %0"
[(set_attr "type" "mcmp_media")])
(define_insn "negcmpgtuv8qi"
[(set (match_operand:V8QI 0 "arith_reg_dest" "=r")
- (neg:V8QI (gtu:V8QI (match_operand:V8QI 1 "arith_reg_or_0_operand" "%rU")
- (match_operand:V8QI 2 "arith_reg_or_0_operand" "rU"))))]
+ (neg:V8QI (gtu:V8QI (match_operand:V8QI 1 "arith_reg_or_0_operand" "%rZ")
+ (match_operand:V8QI 2 "arith_reg_or_0_operand" "rZ"))))]
"TARGET_SHMEDIA"
"mcmpgt.ub %N1, %N2, %0"
[(set_attr "type" "mcmp_media")])
(define_insn "negcmpgtv2si"
[(set (match_operand:V2SI 0 "arith_reg_dest" "=r")
- (neg:V2SI (gt:V2SI (match_operand:V2SI 1 "arith_reg_or_0_operand" "%rU")
- (match_operand:V2SI 2 "arith_reg_or_0_operand" "rU"))))]
+ (neg:V2SI (gt:V2SI (match_operand:V2SI 1 "arith_reg_or_0_operand" "%rZ")
+ (match_operand:V2SI 2 "arith_reg_or_0_operand" "rZ"))))]
"TARGET_SHMEDIA"
"mcmpgt.l %N1, %N2, %0"
[(set_attr "type" "mcmp_media")])
(define_insn "negcmpgtv4hi"
[(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
- (neg:V4HI (gt:V4HI (match_operand:V4HI 1 "arith_reg_or_0_operand" "%rU")
- (match_operand:V4HI 2 "arith_reg_or_0_operand" "rU"))))]
+ (neg:V4HI (gt:V4HI (match_operand:V4HI 1 "arith_reg_or_0_operand" "%rZ")
+ (match_operand:V4HI 2 "arith_reg_or_0_operand" "rZ"))))]
"TARGET_SHMEDIA"
"mcmpgt.w %N1, %N2, %0"
[(set_attr "type" "mcmp_media")])
(define_insn "mcmv"
[(set (match_operand:DI 0 "arith_reg_dest" "=r")
- (ior:DI (and:DI (match_operand:DI 1 "arith_reg_or_0_operand" "rU")
+ (ior:DI (and:DI (match_operand:DI 1 "arith_reg_or_0_operand" "rZ")
(match_operand:DI 2 "arith_reg_operand" "r"))
(and:DI (match_operand:DI 3 "arith_reg_operand" "0")
(not:DI (match_dup 2)))))]
(define_insn "mcnvs_lw"
[(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
(vec_concat:V4HI
- (ss_truncate:V2HI (match_operand:V2SI 1 "arith_reg_or_0_operand" "rU"))
- (ss_truncate:V2HI (match_operand:V2SI 2 "arith_reg_or_0_operand" "rU"))))]
+ (ss_truncate:V2HI (match_operand:V2SI 1 "arith_reg_or_0_operand" "rZ"))
+ (ss_truncate:V2HI (match_operand:V2SI 2 "arith_reg_or_0_operand" "rZ"))))]
"TARGET_SHMEDIA"
"mcnvs.lw %N1, %N2, %0"
[(set_attr "type" "mcmp_media")])
(define_insn "mcnvs_wb"
[(set (match_operand:V8QI 0 "arith_reg_dest" "=r")
(vec_concat:V8QI
- (ss_truncate:V4QI (match_operand:V4HI 1 "arith_reg_or_0_operand" "rU"))
- (ss_truncate:V4QI (match_operand:V4HI 2 "arith_reg_or_0_operand" "rU"))))]
+ (ss_truncate:V4QI (match_operand:V4HI 1 "arith_reg_or_0_operand" "rZ"))
+ (ss_truncate:V4QI (match_operand:V4HI 2 "arith_reg_or_0_operand" "rZ"))))]
"TARGET_SHMEDIA"
"mcnvs.wb %N1, %N2, %0"
[(set_attr "type" "mcmp_media")])
(define_insn "mcnvs_wub"
[(set (match_operand:V8QI 0 "arith_reg_dest" "=r")
(vec_concat:V8QI
- (us_truncate:V4QI (match_operand:V4HI 1 "arith_reg_or_0_operand" "rU"))
- (us_truncate:V4QI (match_operand:V4HI 2 "arith_reg_or_0_operand" "rU"))))]
+ (us_truncate:V4QI (match_operand:V4HI 1 "arith_reg_or_0_operand" "rZ"))
+ (us_truncate:V4QI (match_operand:V4HI 2 "arith_reg_or_0_operand" "rZ"))))]
"TARGET_SHMEDIA"
"mcnvs.wub %N1, %N2, %0"
[(set_attr "type" "mcmp_media")])
(define_insn "mextr_rl"
[(set (match_operand:DI 0 "arith_reg_dest" "=r")
- (ior:DI (lshiftrt:DI (match_operand:DI 1 "arith_reg_or_0_operand" "rU")
+ (ior:DI (lshiftrt:DI (match_operand:DI 1 "arith_reg_or_0_operand" "rZ")
(match_operand:HI 3 "mextr_bit_offset" "i"))
- (ashift:DI (match_operand:DI 2 "arith_reg_or_0_operand" "rU")
+ (ashift:DI (match_operand:DI 2 "arith_reg_or_0_operand" "rZ")
(match_operand:HI 4 "mextr_bit_offset" "i"))))]
"TARGET_SHMEDIA && INTVAL (operands[3]) + INTVAL (operands[4]) == 64"
"*
(define_insn "*mextr_lr"
[(set (match_operand:DI 0 "arith_reg_dest" "=r")
- (ior:DI (ashift:DI (match_operand:DI 1 "arith_reg_or_0_operand" "rU")
+ (ior:DI (ashift:DI (match_operand:DI 1 "arith_reg_or_0_operand" "rZ")
(match_operand:HI 3 "mextr_bit_offset" "i"))
- (lshiftrt:DI (match_operand:DI 2 "arith_reg_or_0_operand" "rU")
+ (lshiftrt:DI (match_operand:DI 2 "arith_reg_or_0_operand" "rZ")
(match_operand:HI 4 "mextr_bit_offset" "i"))))]
"TARGET_SHMEDIA && INTVAL (operands[3]) + INTVAL (operands[4]) == 64"
"*
; vector then varies depending on endianness.
(define_expand "mextr1"
[(match_operand:DI 0 "arith_reg_dest" "")
- (match_operand:DI 1 "arith_reg_or_0_operand" "rU")
- (match_operand:DI 2 "arith_reg_or_0_operand" "rU")]
+ (match_operand:DI 1 "arith_reg_or_0_operand" "rZ")
+ (match_operand:DI 2 "arith_reg_or_0_operand" "rZ")]
"TARGET_SHMEDIA"
"
{
(define_expand "mextr2"
[(match_operand:DI 0 "arith_reg_dest" "")
- (match_operand:DI 1 "arith_reg_or_0_operand" "rU")
- (match_operand:DI 2 "arith_reg_or_0_operand" "rU")]
+ (match_operand:DI 1 "arith_reg_or_0_operand" "rZ")
+ (match_operand:DI 2 "arith_reg_or_0_operand" "rZ")]
"TARGET_SHMEDIA"
"
{
(define_expand "mextr3"
[(match_operand:DI 0 "arith_reg_dest" "")
- (match_operand:DI 1 "arith_reg_or_0_operand" "rU")
- (match_operand:DI 2 "arith_reg_or_0_operand" "rU")]
+ (match_operand:DI 1 "arith_reg_or_0_operand" "rZ")
+ (match_operand:DI 2 "arith_reg_or_0_operand" "rZ")]
"TARGET_SHMEDIA"
"
{
(define_expand "mextr4"
[(match_operand:DI 0 "arith_reg_dest" "")
- (match_operand:DI 1 "arith_reg_or_0_operand" "rU")
- (match_operand:DI 2 "arith_reg_or_0_operand" "rU")]
+ (match_operand:DI 1 "arith_reg_or_0_operand" "rZ")
+ (match_operand:DI 2 "arith_reg_or_0_operand" "rZ")]
"TARGET_SHMEDIA"
"
{
(define_expand "mextr5"
[(match_operand:DI 0 "arith_reg_dest" "")
- (match_operand:DI 1 "arith_reg_or_0_operand" "rU")
- (match_operand:DI 2 "arith_reg_or_0_operand" "rU")]
+ (match_operand:DI 1 "arith_reg_or_0_operand" "rZ")
+ (match_operand:DI 2 "arith_reg_or_0_operand" "rZ")]
"TARGET_SHMEDIA"
"
{
(define_expand "mextr6"
[(match_operand:DI 0 "arith_reg_dest" "")
- (match_operand:DI 1 "arith_reg_or_0_operand" "rU")
- (match_operand:DI 2 "arith_reg_or_0_operand" "rU")]
+ (match_operand:DI 1 "arith_reg_or_0_operand" "rZ")
+ (match_operand:DI 2 "arith_reg_or_0_operand" "rZ")]
"TARGET_SHMEDIA"
"
{
(define_expand "mextr7"
[(match_operand:DI 0 "arith_reg_dest" "")
- (match_operand:DI 1 "arith_reg_or_0_operand" "rU")
- (match_operand:DI 2 "arith_reg_or_0_operand" "rU")]
+ (match_operand:DI 1 "arith_reg_or_0_operand" "rZ")
+ (match_operand:DI 2 "arith_reg_or_0_operand" "rZ")]
"TARGET_SHMEDIA"
"
{
(define_expand "mperm_w"
[(match_operand:V4HI 0 "arith_reg_dest" "=r")
(match_operand:V4HI 1 "arith_reg_operand" "r")
- (match_operand:QI 2 "extend_reg_or_0_operand" "rU")]
+ (match_operand:QI 2 "extend_reg_or_0_operand" "rZ")]
"TARGET_SHMEDIA"
"
{
(vec_select:V4HI
(match_operand:V4HI 1 "arith_reg_operand" "r")
(parallel
- [(zero_extract:QI (match_operand:QI 2 "extend_reg_or_0_operand" "rU")
+ [(zero_extract:QI (match_operand:QI 2 "extend_reg_or_0_operand" "rZ")
(const_int 2) (const_int 0))
(zero_extract:QI (match_dup 2) (const_int 2) (const_int 2))
(zero_extract:QI (match_dup 2) (const_int 2) (const_int 4))
(match_operand:V4HI 1 "arith_reg_operand" "r")
(parallel
[(zero_extract:QI (not:QI (match_operand:QI 2
- "extend_reg_or_0_operand" "rU"))
+ "extend_reg_or_0_operand" "rZ"))
(const_int 2) (const_int 0))
(zero_extract:QI (not:QI (match_dup 2)) (const_int 2) (const_int 2))
(zero_extract:QI (not:QI (match_dup 2)) (const_int 2) (const_int 4))
(abs:DI (vec_select:DI
(minus:V8DI
(zero_extend:V8DI
- (match_operand:V8QI 2 "arith_reg_or_0_operand" "r"))
+ (match_operand:V8QI 2 "arith_reg_or_0_operand" "rZ"))
(zero_extend:V8DI
- (match_operand:V8QI 3 "arith_reg_or_0_operand" "r")))
+ (match_operand:V8QI 3 "arith_reg_or_0_operand" "rZ")))
(parallel [(const_int 0)]))))
(abs:DI (vec_select:DI (minus:V8DI (zero_extend:V8DI (match_dup 2))
(zero_extend:V8DI (match_dup 3)))
[(set (match_operand:HI 0 "arith_reg_dest" "=r")
(ss_truncate:HI
(ashiftrt:DI (match_operand:DI 1 "arith_reg_operand" "r")
- (match_operand:DI 2 "arith_reg_or_0_operand" "rU"))))]
+ (match_operand:DI 2 "arith_reg_or_0_operand" "rZ"))))]
"TARGET_SHMEDIA"
"mshards.q %1, %N2, %0"
[(set_attr "type" "mcmp_media")])
(define_expand "mshfhi_b"
[(match_operand:V8QI 0 "arith_reg_dest" "")
- (match_operand:V8QI 1 "arith_reg_or_0_operand" "rU")
- (match_operand:V8QI 2 "arith_reg_or_0_operand" "rU")]
+ (match_operand:V8QI 1 "arith_reg_or_0_operand" "rZ")
+ (match_operand:V8QI 2 "arith_reg_or_0_operand" "rZ")]
"TARGET_SHMEDIA"
"
{
(define_expand "mshflo_b"
[(match_operand:V8QI 0 "arith_reg_dest" "")
- (match_operand:V8QI 1 "arith_reg_or_0_operand" "rU")
- (match_operand:V8QI 2 "arith_reg_or_0_operand" "rU")]
+ (match_operand:V8QI 1 "arith_reg_or_0_operand" "rZ")
+ (match_operand:V8QI 2 "arith_reg_or_0_operand" "rZ")]
"TARGET_SHMEDIA"
"
{
[(set
(match_operand:V8QI 0 "arith_reg_dest" "=r")
(vec_select:V8QI
- (vec_concat:V16QI (match_operand:V8QI 1 "arith_reg_or_0_operand" "rU")
- (match_operand:V8QI 2 "arith_reg_or_0_operand" "rU"))
+ (vec_concat:V16QI (match_operand:V8QI 1 "arith_reg_or_0_operand" "rZ")
+ (match_operand:V8QI 2 "arith_reg_or_0_operand" "rZ"))
(parallel [(const_int 4) (const_int 12) (const_int 5) (const_int 13)
(const_int 6) (const_int 14) (const_int 7) (const_int 15)])))]
"TARGET_SHMEDIA"
[(set
(match_operand:V8QI 0 "arith_reg_dest" "=r")
(vec_select:V8QI
- (vec_concat:V16QI (match_operand:V8QI 1 "arith_reg_or_0_operand" "rU")
- (match_operand:V8QI 2 "arith_reg_or_0_operand" "rU"))
+ (vec_concat:V16QI (match_operand:V8QI 1 "arith_reg_or_0_operand" "rZ")
+ (match_operand:V8QI 2 "arith_reg_or_0_operand" "rZ"))
(parallel [(const_int 0) (const_int 8) (const_int 1) (const_int 9)
(const_int 2) (const_int 10) (const_int 3) (const_int 11)])))]
"TARGET_SHMEDIA"
(define_expand "mshfhi_l"
[(match_operand:V2SI 0 "arith_reg_dest" "")
- (match_operand:V2SI 1 "arith_reg_or_0_operand" "rU")
- (match_operand:V2SI 2 "arith_reg_or_0_operand" "rU")]
+ (match_operand:V2SI 1 "arith_reg_or_0_operand" "rZ")
+ (match_operand:V2SI 2 "arith_reg_or_0_operand" "rZ")]
"TARGET_SHMEDIA"
"
{
(define_expand "mshflo_l"
[(match_operand:V2SI 0 "arith_reg_dest" "")
- (match_operand:V2SI 1 "arith_reg_or_0_operand" "rU")
- (match_operand:V2SI 2 "arith_reg_or_0_operand" "rU")]
+ (match_operand:V2SI 1 "arith_reg_or_0_operand" "rZ")
+ (match_operand:V2SI 2 "arith_reg_or_0_operand" "rZ")]
"TARGET_SHMEDIA"
"
{
(define_insn "mshf4_l"
[(set (match_operand:V2SI 0 "arith_reg_dest" "=r")
(vec_select:V2SI
- (vec_concat:V4SI (match_operand:V2SI 1 "arith_reg_or_0_operand" "rU")
- (match_operand:V2SI 2 "arith_reg_or_0_operand" "rU"))
+ (vec_concat:V4SI (match_operand:V2SI 1 "arith_reg_or_0_operand" "rZ")
+ (match_operand:V2SI 2 "arith_reg_or_0_operand" "rZ"))
(parallel [(const_int 1) (const_int 3)])))]
"TARGET_SHMEDIA"
"* return (TARGET_LITTLE_ENDIAN
(define_insn "mshf0_l"
[(set (match_operand:V2SI 0 "arith_reg_dest" "=r")
(vec_select:V2SI
- (vec_concat:V4SI (match_operand:V2SI 1 "arith_reg_or_0_operand" "rU")
- (match_operand:V2SI 2 "arith_reg_or_0_operand" "rU"))
+ (vec_concat:V4SI (match_operand:V2SI 1 "arith_reg_or_0_operand" "rZ")
+ (match_operand:V2SI 2 "arith_reg_or_0_operand" "rZ"))
(parallel [(const_int 0) (const_int 2)])))]
"TARGET_SHMEDIA"
"* return (TARGET_LITTLE_ENDIAN
(define_expand "mshfhi_w"
[(match_operand:V4HI 0 "arith_reg_dest" "")
- (match_operand:V4HI 1 "arith_reg_or_0_operand" "rU")
- (match_operand:V4HI 2 "arith_reg_or_0_operand" "rU")]
+ (match_operand:V4HI 1 "arith_reg_or_0_operand" "rZ")
+ (match_operand:V4HI 2 "arith_reg_or_0_operand" "rZ")]
"TARGET_SHMEDIA"
"
{
(define_expand "mshflo_w"
[(match_operand:V4HI 0 "arith_reg_dest" "")
- (match_operand:V4HI 1 "arith_reg_or_0_operand" "rU")
- (match_operand:V4HI 2 "arith_reg_or_0_operand" "rU")]
+ (match_operand:V4HI 1 "arith_reg_or_0_operand" "rZ")
+ (match_operand:V4HI 2 "arith_reg_or_0_operand" "rZ")]
"TARGET_SHMEDIA"
"
{
(define_insn "mshf4_w"
[(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
(vec_select:V4HI
- (vec_concat:V8HI (match_operand:V4HI 1 "arith_reg_or_0_operand" "rU")
- (match_operand:V4HI 2 "arith_reg_or_0_operand" "rU"))
+ (vec_concat:V8HI (match_operand:V4HI 1 "arith_reg_or_0_operand" "rZ")
+ (match_operand:V4HI 2 "arith_reg_or_0_operand" "rZ"))
(parallel [(const_int 2) (const_int 6) (const_int 3) (const_int 7)])))]
"TARGET_SHMEDIA"
"* return (TARGET_LITTLE_ENDIAN
(define_insn "mshf0_w"
[(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
(vec_select:V4HI
- (vec_concat:V8HI (match_operand:V4HI 1 "arith_reg_or_0_operand" "rU")
- (match_operand:V4HI 2 "arith_reg_or_0_operand" "rU"))
+ (vec_concat:V8HI (match_operand:V4HI 1 "arith_reg_or_0_operand" "rZ")
+ (match_operand:V4HI 2 "arith_reg_or_0_operand" "rZ"))
(parallel [(const_int 0) (const_int 4) (const_int 1) (const_int 5)])))]
"TARGET_SHMEDIA"
"* return (TARGET_LITTLE_ENDIAN
(define_insn "mshflo_w_x"
[(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
(vec_select:V4HI
- (vec_concat:V4HI (match_operand:V2HI 1 "extend_reg_or_0_operand" "rU")
- (match_operand:V2HI 2 "extend_reg_or_0_operand" "rU"))
+ (vec_concat:V4HI (match_operand:V2HI 1 "extend_reg_or_0_operand" "rZ")
+ (match_operand:V2HI 2 "extend_reg_or_0_operand" "rZ"))
(parallel [(const_int 2) (const_int 0) (const_int 3) (const_int 1)])))]
"TARGET_SHMEDIA"
"mshflo.w %N1, %N2, %0"
/* These are useful to expand ANDs and as combiner patterns. */
(define_insn_and_split "mshfhi_l_di"
[(set (match_operand:DI 0 "arith_reg_dest" "=r,f")
- (ior:DI (lshiftrt:DI (match_operand:DI 1 "arith_reg_or_0_operand" "rU,f")
+ (ior:DI (lshiftrt:DI (match_operand:DI 1 "arith_reg_or_0_operand" "rZ,f")
(const_int 32))
- (and:DI (match_operand:DI 2 "arith_reg_or_0_operand" "rU,?f")
+ (and:DI (match_operand:DI 2 "arith_reg_or_0_operand" "rZ,?f")
(const_int -4294967296))))]
"TARGET_SHMEDIA"
"@
(define_insn "*mshfhi_l_di_rev"
[(set (match_operand:DI 0 "arith_reg_dest" "=r")
- (ior:DI (and:DI (match_operand:DI 1 "arith_reg_or_0_operand" "rU")
+ (ior:DI (and:DI (match_operand:DI 1 "arith_reg_or_0_operand" "rZ")
(const_int -4294967296))
- (lshiftrt:DI (match_operand:DI 2 "arith_reg_or_0_operand" "rU")
+ (lshiftrt:DI (match_operand:DI 2 "arith_reg_or_0_operand" "rZ")
(const_int 32))))]
"TARGET_SHMEDIA"
"mshfhi.l %N2, %N1, %0"
(define_insn "mshflo_l_di"
[(set (match_operand:DI 0 "arith_reg_dest" "=r")
- (ior:DI (and:DI (match_operand:DI 1 "arith_reg_or_0_operand" "rU")
+ (ior:DI (and:DI (match_operand:DI 1 "arith_reg_or_0_operand" "rZ")
(const_int 4294967295))
- (ashift:DI (match_operand:DI 2 "arith_reg_or_0_operand" "rU")
+ (ashift:DI (match_operand:DI 2 "arith_reg_or_0_operand" "rZ")
(const_int 32))))]
-
+
"TARGET_SHMEDIA"
"mshflo.l %N1, %N2, %0"
[(set_attr "type" "arith_media")])
(define_insn "*mshflo_l_di_rev"
[(set (match_operand:DI 0 "arith_reg_dest" "=r")
- (ior:DI (ashift:DI (match_operand:DI 1 "arith_reg_or_0_operand" "rU")
+ (ior:DI (ashift:DI (match_operand:DI 1 "arith_reg_or_0_operand" "rZ")
(const_int 32))
- (and:DI (match_operand:DI 2 "arith_reg_or_0_operand" "rU")
+ (and:DI (match_operand:DI 2 "arith_reg_or_0_operand" "rZ")
(const_int 4294967295))))]
-
+
"TARGET_SHMEDIA"
"mshflo.l %N2, %N1, %0"
[(set_attr "type" "arith_media")])
(define_insn "*mshflo_l_di_x"
[(set (match_operand:DI 0 "arith_reg_dest" "=r")
(ior:DI (zero_extend:DI (match_operand:SI 1 "extend_reg_or_0_operand"
- "rU"))
- (ashift:DI (match_operand:DI 2 "arith_reg_or_0_operand" "rU")
+ "rZ"))
+ (ashift:DI (match_operand:DI 2 "arith_reg_or_0_operand" "rZ")
(const_int 32))))]
-
+
"TARGET_SHMEDIA"
"mshflo.l %N1, %N2, %0"
[(set_attr "type" "arith_media")])
(define_insn_and_split "concat_v2sf"
[(set (match_operand:V2SF 0 "register_operand" "=r,f,f?")
-;; (vec_concat:V2SF (match_operand:SF 1 "register_operand" "rU,0,f")
- (vec_concat:V2SF (match_operand:SF 1 "register_operand" "rU,f,f")
- (match_operand:SF 2 "register_operand" "rU,f,f")))]
-
+;; (vec_concat:V2SF (match_operand:SF 1 "register_operand" "rZ,0,f")
+ (vec_concat:V2SF (match_operand:SF 1 "register_operand" "rZ,f,f")
+ (match_operand:SF 2 "register_operand" "rZ,f,f")))]
+
"TARGET_SHMEDIA"
"@
mshflo.l %N1, %N2, %0
(define_insn "*mshflo_l_di_x_rev"
[(set (match_operand:DI 0 "arith_reg_dest" "=r")
- (ior:DI (ashift:DI (match_operand:DI 1 "arith_reg_or_0_operand" "rU")
+ (ior:DI (ashift:DI (match_operand:DI 1 "arith_reg_or_0_operand" "rZ")
(const_int 32))
- (zero_extend:DI (match_operand:SI 2 "extend_reg_or_0_operand" "rU"))))]
-
+ (zero_extend:DI (match_operand:SI 2 "extend_reg_or_0_operand" "rZ"))))]
+
"TARGET_SHMEDIA"
"mshflo.l %N2, %N1, %0"
[(set_attr "type" "arith_media")])
(define_insn "subv2si3"
[(set (match_operand:V2SI 0 "arith_reg_dest" "=r")
- (minus:V2SI (match_operand:V2SI 1 "arith_reg_or_0_operand" "rU")
+ (minus:V2SI (match_operand:V2SI 1 "arith_reg_or_0_operand" "rZ")
(match_operand:V2SI 2 "arith_reg_operand" "r")))]
"TARGET_SHMEDIA"
"msub.l %N1, %2, %0"
(define_insn "subv4hi3"
[(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
- (minus:V4HI (match_operand:V4HI 1 "arith_reg_or_0_operand" "rU")
+ (minus:V4HI (match_operand:V4HI 1 "arith_reg_or_0_operand" "rZ")
(match_operand:V4HI 2 "arith_reg_operand" "r")))]
"TARGET_SHMEDIA"
"msub.w %N1, %2, %0"
(define_insn "sssubv2si3"
[(set (match_operand:V2SI 0 "arith_reg_dest" "=r")
- (ss_minus:V2SI (match_operand:V2SI 1 "arith_reg_or_0_operand" "rU")
+ (ss_minus:V2SI (match_operand:V2SI 1 "arith_reg_or_0_operand" "rZ")
(match_operand:V2SI 2 "arith_reg_operand" "r")))]
"TARGET_SHMEDIA"
"msubs.l %N1, %2, %0"
(define_insn "sssubv4hi3"
[(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
- (ss_minus:V4HI (match_operand:V4HI 1 "arith_reg_or_0_operand" "rU")
+ (ss_minus:V4HI (match_operand:V4HI 1 "arith_reg_or_0_operand" "rZ")
(match_operand:V4HI 2 "arith_reg_operand" "r")))]
"TARGET_SHMEDIA"
"msubs.w %N1, %2, %0"
(vec_select:SF (mult:V4SF (match_dup 1) (match_dup 2))
(parallel [(const_int 3)])))))]
"TARGET_SHMEDIA"
- "fipr %1, %2, %0"
+ "fipr.s %1, %2, %0"
[(set_attr "type" "fparith_media")])
(define_insn "fsrra_s"
(const_int 14) (const_int 3)]))
(vec_select:V4SF (match_dup 2)
(parallel [(const_int 1) (const_int 2)
- (const_int 3) (const_int 0)]))))
+ (const_int 3) (const_int 0)]))))
(plus:V4SF
(mult:V4SF
(vec_select:V4SF (match_dup 1)
(parallel [(const_int 3) (const_int 0)
(const_int 1) (const_int 2)]))))))]
"TARGET_SHMEDIA"
- "ftrv %1, %2, %0"
+ "ftrv.s %1, %2, %0"
[(set_attr "type" "fparith_media")])
(define_insn "nsb"
rtx scratch = gen_reg_rtx (DImode);
rtx last;
- emit_insn (gen_adddi3 (scratch, operands[1], GEN_INT (-1)));
+ emit_insn (gen_adddi3 (scratch, operands[1], constm1_rtx));
emit_insn (gen_xordi3 (scratch, operands[1], scratch));
emit_insn (gen_lshrdi3_media (scratch, scratch, const1_rtx));
emit_insn (gen_nsbdi (scratch, scratch));
emit_insn (gen_adddi3 (discratch,
simplify_gen_subreg (DImode, operands[1], SImode, 0),
- GEN_INT (-1)));
+ constm1_rtx));
emit_insn (gen_andcdi3 (discratch,
simplify_gen_subreg (DImode, operands[1], SImode, 0),
discratch));
"byterev %1, %0"
[(set_attr "type" "arith_media")])
-;; The following description models the
-;; SH4 pipeline using the DFA based scheduler.
-;; The DFA based description is better way to model
-;; a superscalar pipeline as compared to function unit
-;; reservation model.
-;; 1. The function unit based model is oriented to describe at most one
-;; unit reservation by each insn. It is difficult to model unit reservations in multiple
-;; pipeline units by same insn. This can be done using DFA based description.
-;; 2. The execution performance of DFA based scheduler does not depend on processor complexity.
-;; 3. Writing all unit reservations for an instruction class is more natural description
-;; of the pipeline and makes interface of the hazard recognizer simpler than the
-;; old function unit based model.
-;; 4. The DFA model is richer and is a part of greater overall framework of RCSP.
-
-
-;; Two automata are defined to reduce number of states
-;; which a single large automaton will have.(Factoring)
-
-(define_automaton "inst_pipeline,fpu_pipe")
-
-;; This unit is basically the decode unit of the processor.
-;; Since SH4 is a dual issue machine,it is as if there are two
-;; units so that any insn can be processed by either one
-;; of the decoding unit.
-
-(define_cpu_unit "pipe_01,pipe_02" "inst_pipeline")
-
-
-;; The fixed point arithmetic calculator(?? EX Unit).
-
-(define_cpu_unit "int" "inst_pipeline")
-
-;; f1_1 and f1_2 are floating point units.Actually there is
-;; a f1 unit which can overlap with other f1 unit but
-;; not another F1 unit.It is as though there were two
-;; f1 units.
-
-(define_cpu_unit "f1_1,f1_2" "fpu_pipe")
-
-;; The floating point units (except FS - F2 always precedes it.)
-
-(define_cpu_unit "F0,F1,F2,F3" "fpu_pipe")
-
-;; This is basically the MA unit of SH4
-;; used in LOAD/STORE pipeline.
-
-(define_cpu_unit "memory" "inst_pipeline")
-
-;; However, there are LS group insns that don't use it, even ones that
-;; complete in 0 cycles. So we use an extra unit for the issue of LS insns.
-(define_cpu_unit "load_store" "inst_pipeline")
-
-;; The address calculator used for branch instructions.
-;; This will be reserved after "issue" of branch instructions
-;; and this is to make sure that no two branch instructions
-;; can be issued in parallel.
-
-(define_cpu_unit "pcr_addrcalc" "inst_pipeline")
-
-;; ----------------------------------------------------
-;; This reservation is to simplify the dual issue description.
-
-(define_reservation "issue" "pipe_01|pipe_02")
-
-;; This is to express the locking of D stage.
-;; Note that the issue of a CO group insn also effectively locks the D stage.
-
-(define_reservation "d_lock" "pipe_01+pipe_02")
-
-;; Every FE instruction but fipr / ftrv starts with issue and this.
-(define_reservation "F01" "F0+F1")
-
-;; This is to simplify description where F1,F2,FS
-;; are used simultaneously.
-
-(define_reservation "fpu" "F1+F2")
-
-;; This is to highlight the fact that f1
-;; cannot overlap with F1.
-
-(exclusion_set "f1_1,f1_2" "F1")
-
-(define_insn_reservation "nil" 0 (eq_attr "type" "nil") "nothing")
-
-;; Although reg moves have a latency of zero
-;; we need to highlight that they use D stage
-;; for one cycle.
-
-;; Group: MT
+(define_insn "prefetch_media"
+ [(prefetch (match_operand:QI 0 "address_operand" "p")
+ (match_operand:SI 1 "const_int_operand" "n")
+ (match_operand:SI 2 "const_int_operand" "n"))]
+ "TARGET_SHMEDIA"
+ "*
+{
+ operands[0] = gen_rtx_MEM (QImode, operands[0]);
+ output_asm_insn (\"ld%M0.b %m0,r63\", operands);
+ return \"\";
+}"
+ [(set_attr "type" "other")])
-(define_insn_reservation "reg_mov" 0
- (and (eq_attr "pipe_model" "sh4")
- (eq_attr "type" "move"))
- "issue")
-
-;; Group: LS
+(define_insn "prefetch_i4"
+ [(prefetch (match_operand:SI 0 "register_operand" "r")
+ (match_operand:SI 1 "const_int_operand" "n")
+ (match_operand:SI 2 "const_int_operand" "n"))]
+ "TARGET_HARD_SH4"
+ "*
+{
+ return \"pref @%0\";
+}"
+ [(set_attr "type" "other")])
-(define_insn_reservation "freg_mov" 0
- (and (eq_attr "pipe_model" "sh4")
- (eq_attr "type" "fmove"))
- "issue+load_store")
-
-;; We don't model all pipeline stages; we model the issue ('D') stage
-;; inasmuch as we allow only two instructions to issue simultaneously,
-;; and CO instructions prevent any simultaneous issue of another instruction.
-;; (This uses pipe_01 and pipe_02).
-;; Double issue of EX insns is prevented by using the int unit in the EX stage.
-;; Double issue of EX / BR insns is prevented by using the int unit /
-;; pcr_addrcalc unit in the EX stage.
-;; Double issue of BR / LS instructions is prevented by using the
-;; pcr_addrcalc / load_store unit in the issue cycle.
-;; Double issue of FE instructions is prevented by using F0 in the first
-;; pipeline stage after the first D stage.
-;; There is no need to describe the [ES]X / [MN]A / S stages after a D stage
-;; (except in the cases outlined above), nor to describe the FS stage after
-;; the F2 stage.
-
-;; Other MT group instructions(1 step operations)
-;; Group: MT
-;; Latency: 1
-;; Issue Rate: 1
-
-(define_insn_reservation "mt" 1
- (and (eq_attr "pipe_model" "sh4")
- (eq_attr "type" "mt_group"))
- "issue")
-
-;; Fixed Point Arithmetic Instructions(1 step operations)
-;; Group: EX
-;; Latency: 1
-;; Issue Rate: 1
-
-(define_insn_reservation "sh4_simple_arith" 1
- (and (eq_attr "pipe_model" "sh4")
- (eq_attr "insn_class" "ex_group"))
- "issue,int")
-
-;; Load and store instructions have no alignment peculiarities for the SH4,
-;; but they use the load-store unit, which they share with the fmove type
-;; insns (fldi[01]; fmov frn,frm; flds; fsts; fabs; fneg) .
-;; Loads have a latency of two.
-;; However, call insns can only paired with a preceding insn, and have
-;; a delay slot, so that we want two more insns to be scheduled between the
-;; load of the function address and the call. This is equivalent to a
-;; latency of three.
-;; ADJUST_COST can only properly handle reductions of the cost, so we
-;; use a latency of three here, which gets multiplied by 10 to yield 30.
-;; We only do this for SImode loads of general registers, to make the work
-;; for ADJUST_COST easier.
-
-;; Load Store instructions. (MOV.[BWL]@(d,GBR)
-;; Group: LS
-;; Latency: 2
-;; Issue Rate: 1
-
-(define_insn_reservation "sh4_load" 2
- (and (eq_attr "pipe_model" "sh4")
- (eq_attr "type" "load,pcload"))
- "issue+load_store,nothing,memory")
-
-;; calls / sfuncs need an extra instruction for their delay slot.
-;; Moreover, estimating the latency for SImode loads as 3 will also allow
-;; adjust_cost to meaningfully bump it back up to 3 if they load the shift
-;; count of a dynamic shift.
-(define_insn_reservation "sh4_load_si" 3
- (and (eq_attr "pipe_model" "sh4")
- (eq_attr "type" "load_si,pcload_si"))
- "issue+load_store,nothing,memory")
-
-;; (define_bypass 2 "sh4_load_si" "!sh4_call")
-
-;; The load latency is upped to three higher if the dependent insn does
-;; double precision computation. We want the 'default' latency to reflect
-;; that increased latency because otherwise the insn priorities won't
-;; allow proper scheduling.
-(define_insn_reservation "sh4_fload" 3
- (and (eq_attr "pipe_model" "sh4")
- (eq_attr "type" "fload,pcfload"))
- "issue+load_store,nothing,memory")
-
-;; (define_bypass 2 "sh4_fload" "!")
-
-(define_insn_reservation "sh4_store" 1
- (and (eq_attr "pipe_model" "sh4")
- (eq_attr "type" "store"))
- "issue+load_store,nothing,memory")
-
-;; Load Store instructions.
-;; Group: LS
-;; Latency: 1
-;; Issue Rate: 1
-
-(define_insn_reservation "sh4_gp_fpul" 1
- (and (eq_attr "pipe_model" "sh4")
- (eq_attr "type" "gp_fpul"))
- "issue+load_store")
-
-;; Load Store instructions.
-;; Group: LS
-;; Latency: 3
-;; Issue Rate: 1
-
-(define_insn_reservation "sh4_fpul_gp" 3
- (and (eq_attr "pipe_model" "sh4")
- (eq_attr "type" "fpul_gp"))
- "issue+load_store")
-
-;; Branch (BF,BF/S,BT,BT/S,BRA)
-;; Group: BR
-;; Latency when taken: 2 (or 1)
-;; Issue Rate: 1
-;; The latency is 1 when displacement is 0.
-;; We can't really do much with the latency, even if we could express it,
-;; but the pairing restrictions are useful to take into account.
-;; ??? If the branch is likely, we might want to fill the delay slot;
-;; if the branch is likely, but not very likely, should we pretend to use
-;; a resource that CO instructions use, to get a pairable delay slot insn?
-
-(define_insn_reservation "sh4_branch" 1
- (and (eq_attr "pipe_model" "sh4")
- (eq_attr "type" "cbranch,jump"))
- "issue+pcr_addrcalc")
-
-;; Branch Far (JMP,RTS,BRAF)
-;; Group: CO
-;; Latency: 3
-;; Issue Rate: 2
-;; ??? Scheduling happens before branch shortening, and hence jmp and braf
-;; can't be distinguished from bra for the "jump" pattern.
-
-(define_insn_reservation "sh4_return" 3
- (and (eq_attr "pipe_model" "sh4")
- (eq_attr "type" "return,jump_ind"))
- "d_lock*2")
-
-;; RTE
-;; Group: CO
-;; Latency: 5
-;; Issue Rate: 5
-;; this instruction can be executed in any of the pipelines
-;; and blocks the pipeline for next 4 stages.
-
-(define_insn_reservation "sh4_return_from_exp" 5
- (and (eq_attr "pipe_model" "sh4")
- (eq_attr "type" "rte"))
- "d_lock*5")
-
-;; OCBP, OCBWB
-;; Group: CO
-;; Latency: 1-5
-;; Issue Rate: 1
-
-;; cwb is used for the sequence ocbwb @%0; extu.w %0,%2; or %1,%2; mov.l %0,@%2
-;; ocbwb on its own would be "d_lock,nothing,memory*5"
-(define_insn_reservation "ocbwb" 6
- (and (eq_attr "pipe_model" "sh4")
- (eq_attr "type" "cwb"))
- "d_lock*2,(d_lock+memory)*3,issue+load_store+memory,memory*2")
-
-;; LDS to PR,JSR
-;; Group: CO
-;; Latency: 3
-;; Issue Rate: 2
-;; The SX stage is blocked for last 2 cycles.
-;; OTOH, the only time that has an effect for insns generated by the compiler
-;; is when lds to PR is followed by sts from PR - and that is highly unlikely -
-;; or when we are doing a function call - and we don't do inter-function
-;; scheduling. For the function call case, it's really best that we end with
-;; something that models an rts.
-
-(define_insn_reservation "sh4_lds_to_pr" 3
- (and (eq_attr "pipe_model" "sh4")
- (eq_attr "type" "prset") )
- "d_lock*2")
-
-;; calls introduce a longisch delay that is likely to flush the pipelines
-;; of the caller's instructions. Ordinary functions tend to end with a
-;; load to restore a register (in the delay slot of rts), while sfuncs
-;; tend to end with an EX or MT insn. But that is not actually relevant,
-;; since there are no instructions that contend for memory access early.
-;; We could, of course, provide exact scheduling information for specific
-;; sfuncs, if that should prove useful.
-
-(define_insn_reservation "sh4_call" 16
- (and (eq_attr "pipe_model" "sh4")
- (eq_attr "type" "call,sfunc"))
- "d_lock*16")
-
-;; LDS.L to PR
-;; Group: CO
-;; Latency: 3
-;; Issue Rate: 2
-;; The SX unit is blocked for last 2 cycles.
-
-(define_insn_reservation "ldsmem_to_pr" 3
- (and (eq_attr "pipe_model" "sh4")
- (eq_attr "type" "pload"))
- "d_lock*2")
-
-;; STS from PR
-;; Group: CO
-;; Latency: 2
-;; Issue Rate: 2
-;; The SX unit in second and third cycles.
-
-(define_insn_reservation "sts_from_pr" 2
- (and (eq_attr "pipe_model" "sh4")
- (eq_attr "type" "prget"))
- "d_lock*2")
-
-;; STS.L from PR
-;; Group: CO
-;; Latency: 2
-;; Issue Rate: 2
-
-(define_insn_reservation "sh4_prstore_mem" 2
- (and (eq_attr "pipe_model" "sh4")
- (eq_attr "type" "pstore"))
- "d_lock*2,nothing,memory")
-
-;; LDS to FPSCR
-;; Group: CO
-;; Latency: 4
-;; Issue Rate: 1
-;; F1 is blocked for last three cycles.
-
-(define_insn_reservation "fpscr_load" 4
- (and (eq_attr "pipe_model" "sh4")
- (eq_attr "type" "gp_fpscr"))
- "d_lock,nothing,F1*3")
-
-;; LDS.L to FPSCR
-;; Group: CO
-;; Latency: 1 / 4
-;; Latency to update Rn is 1 and latency to update FPSCR is 4
-;; Issue Rate: 1
-;; F1 is blocked for last three cycles.
-
-(define_insn_reservation "fpscr_load_mem" 4
- (and (eq_attr "pipe_model" "sh4")
- (eq_attr "type" "mem_fpscr"))
- "d_lock,nothing,(F1+memory),F1*2")
+(define_expand "prefetch"
+ [(prefetch (match_operand:QI 0 "address_operand" "p")
+ (match_operand:SI 1 "const_int_operand" "n")
+ (match_operand:SI 2 "const_int_operand" "n"))]
+ "TARGET_SHMEDIA || TARGET_HARD_SH4"
+ "
+{
+ if (TARGET_HARD_SH4 && ! register_operand (operands[0], SImode))
+ {
+ rtx reg = gen_reg_rtx (SImode);
+ emit_move_insn (reg, operands[0]);
+ operands[0] = reg;
+ }
-\f
-;; Fixed point multiplication (DMULS.L DMULU.L MUL.L MULS.W,MULU.W)
-;; Group: CO
-;; Latency: 4 / 4
-;; Issue Rate: 1
-
-(define_insn_reservation "multi" 4
- (and (eq_attr "pipe_model" "sh4")
- (eq_attr "type" "smpy,dmpy"))
- "d_lock,(d_lock+f1_1),(f1_1|f1_2)*3,F2")
-
-;; Fixed STS from MACL / MACH
-;; Group: CO
-;; Latency: 3
-;; Issue Rate: 1
-
-(define_insn_reservation "sh4_mac_gp" 3
- (and (eq_attr "pipe_model" "sh4")
- (eq_attr "type" "mac_gp"))
- "d_lock")
-
-
-;; Single precision floating point computation FCMP/EQ,
-;; FCMP/GT, FADD, FLOAT, FMAC, FMUL, FSUB, FTRC, FRVHG, FSCHG
-;; Group: FE
-;; Latency: 3/4
-;; Issue Rate: 1
-
-(define_insn_reservation "fp_arith" 3
- (and (eq_attr "pipe_model" "sh4")
- (eq_attr "type" "fp"))
- "issue,F01,F2")
-
-(define_insn_reservation "fp_arith_ftrc" 3
- (and (eq_attr "pipe_model" "sh4")
- (eq_attr "type" "ftrc_s"))
- "issue,F01,F2")
-
-(define_bypass 1 "fp_arith_ftrc" "sh4_fpul_gp")
-
-;; Single Precision FDIV/SQRT
-;; Group: FE
-;; Latency: 12/13 (FDIV); 11/12 (FSQRT)
-;; Issue Rate: 1
-;; We describe fdiv here; fsqrt is actually one cycle faster.
-
-(define_insn_reservation "fp_div" 12
- (and (eq_attr "pipe_model" "sh4")
- (eq_attr "type" "fdiv"))
- "issue,F01+F3,F2+F3,F3*7,F1+F3,F2")
-
-;; Double Precision floating point computation
-;; (FCNVDS, FCNVSD, FLOAT, FTRC)
-;; Group: FE
-;; Latency: (3,4)/5
-;; Issue Rate: 1
-
-(define_insn_reservation "dp_float" 4
- (and (eq_attr "pipe_model" "sh4")
- (eq_attr "type" "dfp_conv"))
- "issue,F01,F1+F2,F2")
-
-;; Double-precision floating-point (FADD,FMUL,FSUB)
-;; Group: FE
-;; Latency: (7,8)/9
-;; Issue Rate: 1
-
-(define_insn_reservation "fp_double_arith" 8
- (and (eq_attr "pipe_model" "sh4")
- (eq_attr "type" "dfp_arith"))
- "issue,F01,F1+F2,fpu*4,F2")
-
-;; Double-precision FCMP (FCMP/EQ,FCMP/GT)
-;; Group: CO
-;; Latency: 3/5
-;; Issue Rate: 2
-
-(define_insn_reservation "fp_double_cmp" 3
- (and (eq_attr "pipe_model" "sh4")
- (eq_attr "type" "dfp_cmp"))
- "d_lock,(d_lock+F01),F1+F2,F2")
-
-;; Double precision FDIV/SQRT
-;; Group: FE
-;; Latency: (24,25)/26
-;; Issue Rate: 1
-
-(define_insn_reservation "dp_div" 25
- (and (eq_attr "pipe_model" "sh4")
- (eq_attr "type" "dfdiv"))
- "issue,F01+F3,F1+F2+F3,F2+F3,F3*16,F1+F3,(fpu+F3)*2,F2")
-
-
-;; Use the branch-not-taken case to model arith3 insns. For the branch taken
-;; case, we'd get a d_lock instead of issue at the end.
-(define_insn_reservation "arith3" 3
- (and (eq_attr "pipe_model" "sh4")
- (eq_attr "type" "arith3"))
- "issue,d_lock+pcr_addrcalc,issue")
-
-;; arith3b insns schedule the same no matter if the branch is taken or not.
-(define_insn_reservation "arith3b" 2
- (and (eq_attr "pipe_model" "sh4")
- (eq_attr "type" "arith3"))
- "issue,d_lock+pcr_addrcalc")
+ emit_insn ((TARGET_SHMEDIA ? gen_prefetch_media : gen_prefetch_i4)
+ (operands[0], operands[1], operands[2]));
+ DONE;
+}")
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