-(define_insn_reservation "freg_mov" 0
- (and (eq_attr "pipe_model" "sh4")
- (eq_attr "type" "fmove"))
- "issue+load_store")
-
-;; We don't model all pipeline stages; we model the issue ('D') stage
-;; inasmuch as we allow only two instructions to issue simultaneously,
-;; and CO instructions prevent any simultaneous issue of another instruction.
-;; (This uses pipe_01 and pipe_02).
-;; Double issue of EX insns is prevented by using the int unit in the EX stage.
-;; Double issue of EX / BR insns is prevented by using the int unit /
-;; pcr_addrcalc unit in the EX stage.
-;; Double issue of BR / LS instructions is prevented by using the
-;; pcr_addrcalc / load_store unit in the issue cycle.
-;; Double issue of FE instructions is prevented by using F0 in the first
-;; pipeline stage after the first D stage.
-;; There is no need to describe the [ES]X / [MN]A / S stages after a D stage
-;; (except in the cases outlined above), nor to describe the FS stage after
-;; the F2 stage.
-
-;; Other MT group instructions(1 step operations)
-;; Group: MT
-;; Latency: 1
-;; Issue Rate: 1
-
-(define_insn_reservation "mt" 1
- (and (eq_attr "pipe_model" "sh4")
- (eq_attr "type" "mt_group"))
- "issue")
-
-;; Fixed Point Arithmetic Instructions(1 step operations)
-;; Group: EX
-;; Latency: 1
-;; Issue Rate: 1
-
-(define_insn_reservation "sh4_simple_arith" 1
- (and (eq_attr "pipe_model" "sh4")
- (eq_attr "insn_class" "ex_group"))
- "issue,int")
-
-;; Load and store instructions have no alignment peculiarities for the SH4,
-;; but they use the load-store unit, which they share with the fmove type
-;; insns (fldi[01]; fmov frn,frm; flds; fsts; fabs; fneg) .
-;; Loads have a latency of two.
-;; However, call insns can only paired with a preceding insn, and have
-;; a delay slot, so that we want two more insns to be scheduled between the
-;; load of the function address and the call. This is equivalent to a
-;; latency of three.
-;; ADJUST_COST can only properly handle reductions of the cost, so we
-;; use a latency of three here, which gets multiplied by 10 to yield 30.
-;; We only do this for SImode loads of general registers, to make the work
-;; for ADJUST_COST easier.
-
-;; Load Store instructions. (MOV.[BWL]@(d,GBR)
-;; Group: LS
-;; Latency: 2
-;; Issue Rate: 1
-
-(define_insn_reservation "sh4_load" 2
- (and (eq_attr "pipe_model" "sh4")
- (eq_attr "type" "load,pcload"))
- "issue+load_store,nothing,memory")
-
-;; calls / sfuncs need an extra instruction for their delay slot.
-;; Moreover, estimating the latency for SImode loads as 3 will also allow
-;; adjust_cost to meaningfully bump it back up to 3 if they load the shift
-;; count of a dynamic shift.
-(define_insn_reservation "sh4_load_si" 3
- (and (eq_attr "pipe_model" "sh4")
- (eq_attr "type" "load_si,pcload_si"))
- "issue+load_store,nothing,memory")
-
-;; (define_bypass 2 "sh4_load_si" "!sh4_call")
-
-;; The load latency is upped to three higher if the dependent insn does
-;; double precision computation. We want the 'default' latency to reflect
-;; that increased latency because otherwise the insn priorities won't
-;; allow proper scheduling.
-(define_insn_reservation "sh4_fload" 3
- (and (eq_attr "pipe_model" "sh4")
- (eq_attr "type" "fload,pcfload"))
- "issue+load_store,nothing,memory")
-
-;; (define_bypass 2 "sh4_fload" "!")
-
-(define_insn_reservation "sh4_store" 1
- (and (eq_attr "pipe_model" "sh4")
- (eq_attr "type" "store"))
- "issue+load_store,nothing,memory")
-
-;; Load Store instructions.
-;; Group: LS
-;; Latency: 1
-;; Issue Rate: 1
-
-(define_insn_reservation "sh4_gp_fpul" 1
- (and (eq_attr "pipe_model" "sh4")
- (eq_attr "type" "gp_fpul"))
- "issue+load_store")
-
-;; Load Store instructions.
-;; Group: LS
-;; Latency: 3
-;; Issue Rate: 1
-
-(define_insn_reservation "sh4_fpul_gp" 3
- (and (eq_attr "pipe_model" "sh4")
- (eq_attr "type" "fpul_gp"))
- "issue+load_store")
-
-;; Branch (BF,BF/S,BT,BT/S,BRA)
-;; Group: BR
-;; Latency when taken: 2 (or 1)
-;; Issue Rate: 1
-;; The latency is 1 when displacement is 0.
-;; We can't really do much with the latency, even if we could express it,
-;; but the pairing restrictions are useful to take into account.
-;; ??? If the branch is likely, we might want to fill the delay slot;
-;; if the branch is likely, but not very likely, should we pretend to use
-;; a resource that CO instructions use, to get a pairable delay slot insn?
-
-(define_insn_reservation "sh4_branch" 1
- (and (eq_attr "pipe_model" "sh4")
- (eq_attr "type" "cbranch,jump"))
- "issue+pcr_addrcalc")
-
-;; Branch Far (JMP,RTS,BRAF)
-;; Group: CO
-;; Latency: 3
-;; Issue Rate: 2
-;; ??? Scheduling happens before branch shortening, and hence jmp and braf
-;; can't be distinguished from bra for the "jump" pattern.
-
-(define_insn_reservation "sh4_return" 3
- (and (eq_attr "pipe_model" "sh4")
- (eq_attr "type" "return,jump_ind"))
- "d_lock*2")
-
-;; RTE
-;; Group: CO
-;; Latency: 5
-;; Issue Rate: 5
-;; this instruction can be executed in any of the pipelines
-;; and blocks the pipeline for next 4 stages.
-
-(define_insn_reservation "sh4_return_from_exp" 5
- (and (eq_attr "pipe_model" "sh4")
- (eq_attr "type" "rte"))
- "d_lock*5")
-
-;; OCBP, OCBWB
-;; Group: CO
-;; Latency: 1-5
-;; Issue Rate: 1
-
-;; cwb is used for the sequence ocbwb @%0; extu.w %0,%2; or %1,%2; mov.l %0,@%2
-;; ocbwb on its own would be "d_lock,nothing,memory*5"
-(define_insn_reservation "ocbwb" 6
- (and (eq_attr "pipe_model" "sh4")
- (eq_attr "type" "cwb"))
- "d_lock*2,(d_lock+memory)*3,issue+load_store+memory,memory*2")
-
-;; LDS to PR,JSR
-;; Group: CO
-;; Latency: 3
-;; Issue Rate: 2
-;; The SX stage is blocked for last 2 cycles.
-;; OTOH, the only time that has an effect for insns generated by the compiler
-;; is when lds to PR is followed by sts from PR - and that is highly unlikely -
-;; or when we are doing a function call - and we don't do inter-function
-;; scheduling. For the function call case, it's really best that we end with
-;; something that models an rts.
-
-(define_insn_reservation "sh4_lds_to_pr" 3
- (and (eq_attr "pipe_model" "sh4")
- (eq_attr "type" "prset") )
- "d_lock*2")
-
-;; calls introduce a longisch delay that is likely to flush the pipelines
-;; of the caller's instructions. Ordinary functions tend to end with a
-;; load to restore a register (in the delay slot of rts), while sfuncs
-;; tend to end with an EX or MT insn. But that is not actually relevant,
-;; since there are no instructions that contend for memory access early.
-;; We could, of course, provide exact scheduling information for specific
-;; sfuncs, if that should prove useful.
-
-(define_insn_reservation "sh4_call" 16
- (and (eq_attr "pipe_model" "sh4")
- (eq_attr "type" "call,sfunc"))
- "d_lock*16")
-
-;; LDS.L to PR
-;; Group: CO
-;; Latency: 3
-;; Issue Rate: 2
-;; The SX unit is blocked for last 2 cycles.
-
-(define_insn_reservation "ldsmem_to_pr" 3
- (and (eq_attr "pipe_model" "sh4")
- (eq_attr "type" "pload"))
- "d_lock*2")
-
-;; STS from PR
-;; Group: CO
-;; Latency: 2
-;; Issue Rate: 2
-;; The SX unit in second and third cycles.
-
-(define_insn_reservation "sts_from_pr" 2
- (and (eq_attr "pipe_model" "sh4")
- (eq_attr "type" "prget"))
- "d_lock*2")
-
-;; STS.L from PR
-;; Group: CO
-;; Latency: 2
-;; Issue Rate: 2
-
-(define_insn_reservation "sh4_prstore_mem" 2
- (and (eq_attr "pipe_model" "sh4")
- (eq_attr "type" "pstore"))
- "d_lock*2,nothing,memory")
-
-;; LDS to FPSCR
-;; Group: CO
-;; Latency: 4
-;; Issue Rate: 1
-;; F1 is blocked for last three cycles.
-
-(define_insn_reservation "fpscr_load" 4
- (and (eq_attr "pipe_model" "sh4")
- (eq_attr "type" "gp_fpscr"))
- "d_lock,nothing,F1*3")
-
-;; LDS.L to FPSCR
-;; Group: CO
-;; Latency: 1 / 4
-;; Latency to update Rn is 1 and latency to update FPSCR is 4
-;; Issue Rate: 1
-;; F1 is blocked for last three cycles.
-
-(define_insn_reservation "fpscr_load_mem" 4
- (and (eq_attr "pipe_model" "sh4")
- (eq_attr "type" "mem_fpscr"))
- "d_lock,nothing,(F1+memory),F1*2")