;;- Machine description for GNU compiler -- S/390 / zSeries version.
-;; Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004
+;; Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005
;; Free Software Foundation, Inc.
;; Contributed by Hartmut Penner (hpenner@de.ibm.com) and
;; Ulrich Weigand (uweigand@de.ibm.com).
;; Special constraints for s/390 machine description:
;;
;; a -- Any address register from 1 to 15.
+;; c -- Condition code register 33.
;; d -- Any register from 0 to 15.
+;; f -- Floating point registers.
+;; t -- Access registers 36 and 37.
+;; G -- Const double zero operand
;; I -- An 8-bit constant (0..255).
;; J -- A 12-bit constant (0..4095).
;; K -- A 16-bit constant (-32768..32767).
;; (-524288..524287) for long displacement
;; M -- Constant integer with a value of 0x7fffffff.
;; N -- Multiple letter constraint followed by 4 parameter letters.
-;; 0..9: number of the part counting from most to least significant
-;; H,Q: mode of the part
-;; D,S,H: mode of the containing operand
-;; 0,F: value of the other parts (F - all bits set)
+;; 0..9,x: number of the part counting from most to least significant
+;; H,Q: mode of the part
+;; D,S,H: mode of the containing operand
+;; 0,F: value of the other parts (F - all bits set)
;;
;; The constraint matches if the specified part of a constant
-;; has a value different from its other parts.
+;; has a value different from its other parts. If the letter x
+;; is specified instead of a part number, the constraint matches
+;; if there is any single part with non-default value.
;; Q -- Memory reference without index register and with short displacement.
;; R -- Memory reference with index register and short displacement.
;; S -- Memory reference without index register but with long displacement.
;; T -- Memory reference with index register and long displacement.
+;; A -- Multiple letter constraint followed by Q, R, S, or T:
+;; Offsettable memory reference of type specified by second letter.
+;; B -- Multiple letter constraint followed by Q, R, S, or T:
+;; Memory reference of the type specified by second letter that
+;; does *not* refer to a literal pool entry.
;; U -- Pointer with short displacement.
;; W -- Pointer with long displacement.
;; Y -- Shift count operand.
;; %J: print tls_load/tls_gdcall/tls_ldcall suffix
;; %O: print only the displacement of a memory reference.
;; %R: print only the base register of a memory reference.
+;; %S: print S-type memory reference (base+displacement).
;; %N: print the second word of a DImode operand.
;; %M: print the second word of a TImode operand.
(define_constants
[; Miscellaneous
(UNSPEC_ROUND 1)
+ (UNSPEC_CMPINT 2)
(UNSPEC_SETHIGH 10)
; GOT/PLT and lt-relative accesses
(UNSPEC_RELOAD_BASE 210)
(UNSPEC_MAIN_BASE 211)
(UNSPEC_LTREF 212)
+ (UNSPEC_INSN 213)
+ (UNSPEC_EXECUTE 214)
; TLS relocation specifiers
(UNSPEC_TLSGD 500)
(UNSPEC_INDNTPOFF 505)
; TLS support
- (UNSPEC_TP 510)
(UNSPEC_TLSLDM_NTPOFF 511)
(UNSPEC_TLS_LOAD 512)
; Literal pool
(UNSPECV_POOL 200)
- (UNSPECV_POOL_START 201)
- (UNSPECV_POOL_END 202)
+ (UNSPECV_POOL_SECTION 201)
+ (UNSPECV_POOL_ALIGN 202)
(UNSPECV_POOL_ENTRY 203)
(UNSPECV_MAIN_POOL 300)
(UNSPECV_SET_TP 500)
])
+;;
+;; Registers
+;;
-;; Processor type. This attribute must exactly match the processor_type
-;; enumeration in s390.h. The current machine description does not
-;; distinguish between g5 and g6, but there are differences between the two
-;; CPUs could in theory be modeled.
-
-(define_attr "cpu" "g5,g6,z900,z990"
- (const (symbol_ref "s390_tune")))
-
-;; Define an insn type attribute. This is used in function unit delay
-;; computations.
+(define_constants
+ [
+ ; Sibling call register.
+ (SIBCALL_REGNUM 1)
+ ; Literal pool base register.
+ (BASE_REGNUM 13)
+ ; Return address register.
+ (RETURN_REGNUM 14)
+ ; Condition code register.
+ (CC_REGNUM 33)
+ ; Thread local storage pointer register.
+ (TP_REGNUM 36)
+ ])
-(define_attr "type" "none,integer,load,lr,la,larl,lm,stm,
- cs,vs,store,imul,idiv,
- branch,jsr,fsimpd,fsimps,
- floadd,floads,fstored, fstores,
- fmuld,fmuls,fdivd,fdivs,
- ftoi,itof,fsqrtd,fsqrts,
- other,o2,o3"
- (const_string "integer"))
-;; Operand type. Used to default length attribute values
+;; Instruction operand type as used in the Principles of Operation.
+;; Used to determine defaults for length and other attribute values.
(define_attr "op_type"
"NN,E,RR,RRE,RX,RS,RSI,RI,SI,S,SS,SSE,RXE,RSE,RIL,RIE,RXY,RSY,SIY"
- (const_string "RX"))
+ (const_string "NN"))
+
+;; Instruction type attribute used for scheduling.
-;; Insn are devide in two classes:
-;; agen: Insn using agen
-;; reg: Insn not using agen
+(define_attr "type" "none,integer,load,lr,la,larl,lm,stm,
+ cs,vs,store,idiv,
+ imulhi,imulsi,imuldi,
+ branch,jsr,fsimpdf,fsimpsf,
+ floaddf,floadsf,fstoredf,fstoresf,
+ fmuldf,fmulsf,fdivdf,fdivsf,
+ ftoi,itof,fsqrtdf,fsqrtsf,
+ other"
+ (cond [(eq_attr "op_type" "NN") (const_string "other")
+ (eq_attr "op_type" "SS") (const_string "cs")]
+ (const_string "integer")))
+
+;; Another attribute used for scheduling purposes:
+;; agen: Instruction uses the address generation unit
+;; reg: Instruction does not use the agen unit
(define_attr "atype" "agen,reg"
-(cond [ (eq_attr "op_type" "E") (const_string "reg")
+ (cond [(eq_attr "op_type" "E") (const_string "reg")
(eq_attr "op_type" "RR") (const_string "reg")
(eq_attr "op_type" "RX") (const_string "agen")
(eq_attr "op_type" "RI") (const_string "reg")
(eq_attr "op_type" "RXY") (const_string "agen")
(eq_attr "op_type" "RSY") (const_string "agen")
(eq_attr "op_type" "SIY") (const_string "agen")]
- (const_string "reg")))
-
-;; Pipeline description for z900. For lack of anything better,
-;; this description is also used for the g5 and g6.
-(include "2064.md")
-
-;; Pipeline description for z990.
-(include "2084.md")
+ (const_string "agen")))
;; Length in bytes.
(define_attr "length" ""
-(cond [ (eq_attr "op_type" "E") (const_int 2)
+ (cond [(eq_attr "op_type" "E") (const_int 2)
(eq_attr "op_type" "RR") (const_int 2)
(eq_attr "op_type" "RX") (const_int 4)
(eq_attr "op_type" "RI") (const_int 4)
(eq_attr "op_type" "RXY") (const_int 6)
(eq_attr "op_type" "RSY") (const_int 6)
(eq_attr "op_type" "SIY") (const_int 6)]
- (const_int 4)))
+ (const_int 6)))
-;; Define attributes for `asm' insns.
-(define_asm_attributes [(set_attr "type" "other")
- (set_attr "op_type" "NN")])
+;; Processor type. This attribute must exactly match the processor_type
+;; enumeration in s390.h. The current machine description does not
+;; distinguish between g5 and g6, but there are differences between the two
+;; CPUs could in theory be modeled.
+
+(define_attr "cpu" "g5,g6,z900,z990"
+ (const (symbol_ref "s390_tune")))
-;;
-;; Condition Codes
-;;
-;
-; CCL: Zero Nonzero Zero Nonzero (AL, ALR, SL, SLR, N, NC, NI, NR, O, OC, OI, OR, X, XC, XI, XR)
-; CCA: Zero <Zero >Zero Overflow (A, AR, AH, AHI, S, SR, SH, SHI, LTR, LCR, LNR, LPR, SLA, SLDA, SLA, SRDA)
-; CCU: Equal ULess UGreater -- (CL, CLR, CLI, CLM)
-; CCS: Equal SLess SGreater -- (C, CR, CH, CHI, ICM)
-; CCT: Zero Mixed Mixed Ones (TM, TMH, TML)
+;; Pipeline description for z900. For lack of anything better,
+;; this description is also used for the g5 and g6.
+(include "2064.md")
+
+;; Pipeline description for z990.
+(include "2084.md")
+
+;; Predicates
+(include "predicates.md")
+
+
+;; Macros
+
+;; This mode macro allows DF and SF patterns to be generated from the
+;; same template.
+(define_mode_macro FPR [DF SF])
+
+;; These mode macros allow 31-bit and 64-bit GPR patterns to be generated
+;; from the same template.
+(define_mode_macro GPR [(DI "TARGET_64BIT") SI])
+(define_mode_macro DSI [DI SI])
+
+;; This mode macro allows :P to be used for patterns that operate on
+;; pointer-sized quantities. Exactly one of the two alternatives will match.
+(define_mode_macro P [(DI "TARGET_64BIT") (SI "!TARGET_64BIT")])
+
+;; This mode macro allows the QI and HI patterns to be defined from
+;; the same template.
+(define_mode_macro HQI [HI QI])
+
+;; This mode macro allows the integer patterns to be defined from the
+;; same template.
+(define_mode_macro INT [(DI "TARGET_64BIT") SI HI QI])
+
+;; This macro allows to unify all 'bCOND' expander patterns.
+(define_code_macro COMPARE [eq ne gt gtu lt ltu ge geu le leu unordered
+ ordered uneq unlt ungt unle unge ltgt])
+
+;; This macro allows to unify all 'sCOND' patterns.
+(define_code_macro SCOND [ltu gtu leu geu])
-; CCZ -> CCL / CCZ1
-; CCZ1 -> CCA/CCU/CCS/CCT
-; CCS -> CCA
+;; This macro allows some 'ashift' and 'lshiftrt' pattern to be defined from
+;; the same template.
+(define_code_macro SHIFT [ashift lshiftrt])
-; String: CLC, CLCL, CLCLE, CLST, CUSE, MVCL, MVCLE, MVPG, MVST, SRST
-; Clobber: CKSM, CFC, CS, CDS, CUUTF, CUTFU, PLO, SPM, STCK, STCKE, TS, TRT, TRE, UPT
+
+;; In FPR templates, a string like "lt<de>br" will expand to "ltdbr" in DFmode
+;; and "ltebr" in SFmode.
+(define_mode_attr de [(DF "d") (SF "e")])
+
+;; In FPR templates, a string like "m<dee>br" will expand to "mdbr" in DFmode
+;; and "meebr" in SFmode. This is needed for the 'mul<mode>3' pattern.
+(define_mode_attr dee [(DF "d") (SF "ee")])
+
+;; In SHIFT templates, a string like "s<lr>dl" will expand to "sldl" in
+;; 'ashift' and "srdl" in 'lshiftrt'.
+(define_code_attr lr [(ashift "l") (lshiftrt "r")])
+
+;; In SHIFT templates, this attribute holds the correct standard name for the
+;; pattern itself and the corresponding function calls.
+(define_code_attr shift [(ashift "ashl") (lshiftrt "lshr")])
+
+;; This attribute handles differences in the instruction 'type' and will result
+;; in "RRE" for DImode and "RR" for SImode.
+(define_mode_attr E [(DI "E") (SI "")])
+
+;; In GPR templates, a string like "lc<g>r" will expand to "lcgr" in DImode
+;; and "lcr" in SImode.
+(define_mode_attr g [(DI "g") (SI "")])
+
+;; In GPR templates, a string like "c<gf>dbr" will expand to "cgdbr" in DImode
+;; and "cfdbr" in SImode.
+(define_mode_attr gf [(DI "g") (SI "f")])
+
+;; ICM mask required to load MODE value into the highest subreg
+;; of a SImode register.
+(define_mode_attr icm_hi [(HI "12") (QI "8")])
+
+;; ICM mask required to load MODE value into the lowest subreg
+;; of a SImode register.
+(define_mode_attr icm_lo [(HI "3") (QI "1")])
+
+;; In HQI templates, a string like "llg<hc>" will expand to "llgh" in
+;; HImode and "llgc" in QImode.
+(define_mode_attr hc [(HI "h") (QI "c")])
+
+;; Maximum unsigned integer that fits in MODE.
+(define_mode_attr max_uint [(HI "65535") (QI "255")])
;;
;;- Compare instructions.
;;
-(define_expand "cmpdi"
- [(set (reg:CC 33)
- (compare:CC (match_operand:DI 0 "register_operand" "")
- (match_operand:DI 1 "general_operand" "")))]
- "TARGET_64BIT"
-{
- s390_compare_op0 = operands[0];
- s390_compare_op1 = operands[1];
- DONE;
-})
-
-(define_expand "cmpsi"
- [(set (reg:CC 33)
- (compare:CC (match_operand:SI 0 "register_operand" "")
- (match_operand:SI 1 "general_operand" "")))]
+(define_expand "cmp<mode>"
+ [(set (reg:CC CC_REGNUM)
+ (compare:CC (match_operand:GPR 0 "register_operand" "")
+ (match_operand:GPR 1 "general_operand" "")))]
""
{
s390_compare_op0 = operands[0];
DONE;
})
-(define_expand "cmpdf"
- [(set (reg:CC 33)
- (compare:CC (match_operand:DF 0 "register_operand" "")
- (match_operand:DF 1 "general_operand" "")))]
- "TARGET_HARD_FLOAT"
-{
- s390_compare_op0 = operands[0];
- s390_compare_op1 = operands[1];
- DONE;
-})
-
-(define_expand "cmpsf"
- [(set (reg:CC 33)
- (compare:CC (match_operand:SF 0 "register_operand" "")
- (match_operand:SF 1 "general_operand" "")))]
+(define_expand "cmp<mode>"
+ [(set (reg:CC CC_REGNUM)
+ (compare:CC (match_operand:FPR 0 "register_operand" "")
+ (match_operand:FPR 1 "general_operand" "")))]
"TARGET_HARD_FLOAT"
{
s390_compare_op0 = operands[0];
; Test-under-Mask instructions
(define_insn "*tmqi_mem"
- [(set (reg 33)
+ [(set (reg CC_REGNUM)
(compare (and:QI (match_operand:QI 0 "memory_operand" "Q,S")
(match_operand:QI 1 "immediate_operand" "n,n"))
(match_operand:QI 2 "immediate_operand" "n,n")))]
- "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 0))"
+ "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], false))"
"@
- tm\t%0,%b1
- tmy\t%0,%b1"
+ tm\t%S0,%b1
+ tmy\t%S0,%b1"
[(set_attr "op_type" "SI,SIY")])
(define_insn "*tmdi_reg"
- [(set (reg 33)
+ [(set (reg CC_REGNUM)
(compare (and:DI (match_operand:DI 0 "nonimmediate_operand" "d,d,d,d")
(match_operand:DI 1 "immediate_operand"
"N0HD0,N1HD0,N2HD0,N3HD0"))
(match_operand:DI 2 "immediate_operand" "n,n,n,n")))]
"TARGET_64BIT
- && s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 1))
+ && s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], true))
&& s390_single_part (operands[1], DImode, HImode, 0) >= 0"
"@
tmhh\t%0,%i1
[(set_attr "op_type" "RI")])
(define_insn "*tmsi_reg"
- [(set (reg 33)
+ [(set (reg CC_REGNUM)
(compare (and:SI (match_operand:SI 0 "nonimmediate_operand" "d,d")
(match_operand:SI 1 "immediate_operand" "N0HS0,N1HS0"))
(match_operand:SI 2 "immediate_operand" "n,n")))]
- "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 1))
+ "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], true))
&& s390_single_part (operands[1], SImode, HImode, 0) >= 0"
"@
tmh\t%0,%i1
tml\t%0,%i1"
[(set_attr "op_type" "RI")])
-(define_insn "*tmhi_full"
- [(set (reg 33)
- (compare (match_operand:HI 0 "register_operand" "d")
- (match_operand:HI 1 "immediate_operand" "n")))]
- "s390_match_ccmode (insn, s390_tm_ccmode (constm1_rtx, operands[1], 1))"
- "tml\t%0,65535"
- [(set_attr "op_type" "RX")])
-
-(define_insn "*tmqi_full"
- [(set (reg 33)
- (compare (match_operand:QI 0 "register_operand" "d")
- (match_operand:QI 1 "immediate_operand" "n")))]
- "s390_match_ccmode (insn, s390_tm_ccmode (constm1_rtx, operands[1], 1))"
- "tml\t%0,255"
+(define_insn "*tm<mode>_full"
+ [(set (reg CC_REGNUM)
+ (compare (match_operand:HQI 0 "register_operand" "d")
+ (match_operand:HQI 1 "immediate_operand" "n")))]
+ "s390_match_ccmode (insn, s390_tm_ccmode (constm1_rtx, operands[1], true))"
+ "tml\t%0,<max_uint>"
[(set_attr "op_type" "RI")])
; Load-and-Test instructions
(define_insn "*tstdi_sign"
- [(set (reg 33)
+ [(set (reg CC_REGNUM)
(compare (ashiftrt:DI (ashift:DI (subreg:DI (match_operand:SI 0 "register_operand" "d") 0)
(const_int 32)) (const_int 32))
(match_operand:DI 1 "const0_operand" "")))
[(set_attr "op_type" "RRE")])
(define_insn "*tstdi"
- [(set (reg 33)
+ [(set (reg CC_REGNUM)
(compare (match_operand:DI 0 "register_operand" "d")
(match_operand:DI 1 "const0_operand" "")))
(set (match_operand:DI 2 "register_operand" "=d")
[(set_attr "op_type" "RRE")])
(define_insn "*tstdi_cconly"
- [(set (reg 33)
+ [(set (reg CC_REGNUM)
(compare (match_operand:DI 0 "register_operand" "d")
(match_operand:DI 1 "const0_operand" "")))]
"s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
[(set_attr "op_type" "RRE")])
(define_insn "*tstdi_cconly_31"
- [(set (reg 33)
+ [(set (reg CC_REGNUM)
(compare (match_operand:DI 0 "register_operand" "d")
(match_operand:DI 1 "const0_operand" "")))]
"s390_match_ccmode(insn, CCSmode) && !TARGET_64BIT"
(define_insn "*tstsi"
- [(set (reg 33)
+ [(set (reg CC_REGNUM)
(compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S")
(match_operand:SI 1 "const0_operand" "")))
(set (match_operand:SI 2 "register_operand" "=d,d,d")
"s390_match_ccmode(insn, CCSmode)"
"@
ltr\t%2,%0
- icm\t%2,15,%0
- icmy\t%2,15,%0"
+ icm\t%2,15,%S0
+ icmy\t%2,15,%S0"
[(set_attr "op_type" "RR,RS,RSY")])
(define_insn "*tstsi_cconly"
- [(set (reg 33)
+ [(set (reg CC_REGNUM)
(compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S")
(match_operand:SI 1 "const0_operand" "")))
(clobber (match_scratch:SI 2 "=X,d,d"))]
"s390_match_ccmode(insn, CCSmode)"
"@
ltr\t%0,%0
- icm\t%2,15,%0
- icmy\t%2,15,%0"
+ icm\t%2,15,%S0
+ icmy\t%2,15,%S0"
[(set_attr "op_type" "RR,RS,RSY")])
(define_insn "*tstsi_cconly2"
- [(set (reg 33)
+ [(set (reg CC_REGNUM)
(compare (match_operand:SI 0 "register_operand" "d")
(match_operand:SI 1 "const0_operand" "")))]
"s390_match_ccmode(insn, CCSmode)"
"ltr\t%0,%0"
[(set_attr "op_type" "RR")])
-(define_insn "*tsthiCCT"
- [(set (reg 33)
- (compare (match_operand:HI 0 "nonimmediate_operand" "?Q,?S,d")
- (match_operand:HI 1 "const0_operand" "")))
- (set (match_operand:HI 2 "register_operand" "=d,d,0")
+(define_insn "*tst<mode>CCT"
+ [(set (reg CC_REGNUM)
+ (compare (match_operand:HQI 0 "nonimmediate_operand" "?Q,?S,d")
+ (match_operand:HQI 1 "const0_operand" "")))
+ (set (match_operand:HQI 2 "register_operand" "=d,d,0")
(match_dup 0))]
"s390_match_ccmode(insn, CCTmode)"
"@
- icm\t%2,3,%0
- icmy\t%2,3,%0
- tml\t%0,65535"
+ icm\t%2,<icm_lo>,%S0
+ icmy\t%2,<icm_lo>,%S0
+ tml\t%0,<max_uint>"
[(set_attr "op_type" "RS,RSY,RI")])
(define_insn "*tsthiCCT_cconly"
- [(set (reg 33)
+ [(set (reg CC_REGNUM)
(compare (match_operand:HI 0 "nonimmediate_operand" "Q,S,d")
(match_operand:HI 1 "const0_operand" "")))
(clobber (match_scratch:HI 2 "=d,d,X"))]
"s390_match_ccmode(insn, CCTmode)"
"@
- icm\t%2,3,%0
- icmy\t%2,3,%0
+ icm\t%2,3,%S0
+ icmy\t%2,3,%S0
tml\t%0,65535"
[(set_attr "op_type" "RS,RSY,RI")])
-(define_insn "*tsthi"
- [(set (reg 33)
- (compare (match_operand:HI 0 "s_operand" "Q,S")
- (match_operand:HI 1 "const0_operand" "")))
- (set (match_operand:HI 2 "register_operand" "=d,d")
- (match_dup 0))]
- "s390_match_ccmode(insn, CCSmode)"
- "@
- icm\t%2,3,%0
- icmy\t%2,3,%0"
- [(set_attr "op_type" "RS,RSY")])
-
-(define_insn "*tsthi_cconly"
- [(set (reg 33)
- (compare (match_operand:HI 0 "s_operand" "Q,S")
- (match_operand:HI 1 "const0_operand" "")))
- (clobber (match_scratch:HI 2 "=d,d"))]
- "s390_match_ccmode(insn, CCSmode)"
- "@
- icm\t%2,3,%0
- icmy\t%2,3,%0"
- [(set_attr "op_type" "RS,RSY")])
-
-(define_insn "*tstqiCCT"
- [(set (reg 33)
- (compare (match_operand:QI 0 "nonimmediate_operand" "?Q,?S,d")
- (match_operand:QI 1 "const0_operand" "")))
- (set (match_operand:QI 2 "register_operand" "=d,d,0")
- (match_dup 0))]
- "s390_match_ccmode(insn, CCTmode)"
- "@
- icm\t%2,1,%0
- icmy\t%2,1,%0
- tml\t%0,255"
- [(set_attr "op_type" "RS,RSY,RI")])
-
(define_insn "*tstqiCCT_cconly"
- [(set (reg 33)
+ [(set (reg CC_REGNUM)
(compare (match_operand:QI 0 "nonimmediate_operand" "?Q,?S,d")
(match_operand:QI 1 "const0_operand" "")))]
"s390_match_ccmode(insn, CCTmode)"
"@
- cli\t%0,0
- cliy\t%0,0
+ cli\t%S0,0
+ cliy\t%S0,0
tml\t%0,255"
[(set_attr "op_type" "SI,SIY,RI")])
-(define_insn "*tstqi"
- [(set (reg 33)
- (compare (match_operand:QI 0 "s_operand" "Q,S")
- (match_operand:QI 1 "const0_operand" "")))
- (set (match_operand:QI 2 "register_operand" "=d,d")
+(define_insn "*tst<mode>"
+ [(set (reg CC_REGNUM)
+ (compare (match_operand:HQI 0 "s_operand" "Q,S")
+ (match_operand:HQI 1 "const0_operand" "")))
+ (set (match_operand:HQI 2 "register_operand" "=d,d")
(match_dup 0))]
"s390_match_ccmode(insn, CCSmode)"
"@
- icm\t%2,1,%0
- icmy\t%2,1,%0"
+ icm\t%2,<icm_lo>,%S0
+ icmy\t%2,<icm_lo>,%S0"
[(set_attr "op_type" "RS,RSY")])
-(define_insn "*tstqi_cconly"
- [(set (reg 33)
- (compare (match_operand:QI 0 "s_operand" "Q,S")
- (match_operand:QI 1 "const0_operand" "")))
- (clobber (match_scratch:QI 2 "=d,d"))]
+(define_insn "*tst<mode>_cconly"
+ [(set (reg CC_REGNUM)
+ (compare (match_operand:HQI 0 "s_operand" "Q,S")
+ (match_operand:HQI 1 "const0_operand" "")))
+ (clobber (match_scratch:HQI 2 "=d,d"))]
"s390_match_ccmode(insn, CCSmode)"
"@
- icm\t%2,1,%0
- icmy\t%2,1,%0"
+ icm\t%2,<icm_lo>,%S0
+ icmy\t%2,<icm_lo>,%S0"
[(set_attr "op_type" "RS,RSY")])
+; Compare (equality) instructions
+
+(define_insn "*cmpdi_cct"
+ [(set (reg CC_REGNUM)
+ (compare (match_operand:DI 0 "nonimmediate_operand" "%d,d,d,Q")
+ (match_operand:DI 1 "general_operand" "d,K,m,BQ")))]
+ "s390_match_ccmode (insn, CCTmode) && TARGET_64BIT"
+ "@
+ cgr\t%0,%1
+ cghi\t%0,%h1
+ cg\t%0,%1
+ #"
+ [(set_attr "op_type" "RRE,RI,RXY,SS")])
+
+(define_insn "*cmpsi_cct"
+ [(set (reg CC_REGNUM)
+ (compare (match_operand:SI 0 "nonimmediate_operand" "%d,d,d,d,Q")
+ (match_operand:SI 1 "general_operand" "d,K,R,T,BQ")))]
+ "s390_match_ccmode (insn, CCTmode)"
+ "@
+ cr\t%0,%1
+ chi\t%0,%h1
+ c\t%0,%1
+ cy\t%0,%1
+ #"
+ [(set_attr "op_type" "RR,RI,RX,RXY,SS")])
+
+
; Compare (signed) instructions
(define_insn "*cmpdi_ccs_sign"
- [(set (reg 33)
+ [(set (reg CC_REGNUM)
(compare (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m"))
(match_operand:DI 0 "register_operand" "d,d")))]
"s390_match_ccmode(insn, CCSRmode) && TARGET_64BIT"
[(set_attr "op_type" "RRE,RXY")])
(define_insn "*cmpdi_ccs"
- [(set (reg 33)
+ [(set (reg CC_REGNUM)
(compare (match_operand:DI 0 "register_operand" "d,d,d")
(match_operand:DI 1 "general_operand" "d,K,m")))]
"s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
"@
cgr\t%0,%1
- cghi\t%0,%c1
+ cghi\t%0,%h1
cg\t%0,%1"
[(set_attr "op_type" "RRE,RI,RXY")])
(define_insn "*cmpsi_ccs_sign"
- [(set (reg 33)
+ [(set (reg CC_REGNUM)
(compare (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T"))
(match_operand:SI 0 "register_operand" "d,d")))]
"s390_match_ccmode(insn, CCSRmode)"
[(set_attr "op_type" "RX,RXY")])
(define_insn "*cmpsi_ccs"
- [(set (reg 33)
+ [(set (reg CC_REGNUM)
(compare (match_operand:SI 0 "register_operand" "d,d,d,d")
(match_operand:SI 1 "general_operand" "d,K,R,T")))]
"s390_match_ccmode(insn, CCSmode)"
"@
cr\t%0,%1
- chi\t%0,%c1
+ chi\t%0,%h1
c\t%0,%1
cy\t%0,%1"
[(set_attr "op_type" "RR,RI,RX,RXY")])
; Compare (unsigned) instructions
(define_insn "*cmpdi_ccu_zero"
- [(set (reg 33)
+ [(set (reg CC_REGNUM)
(compare (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m"))
(match_operand:DI 0 "register_operand" "d,d")))]
- "s390_match_ccmode(insn, CCURmode) && TARGET_64BIT"
+ "s390_match_ccmode (insn, CCURmode) && TARGET_64BIT"
"@
clgfr\t%0,%1
clgf\t%0,%1"
[(set_attr "op_type" "RRE,RXY")])
(define_insn "*cmpdi_ccu"
- [(set (reg 33)
- (compare (match_operand:DI 0 "register_operand" "d,d")
- (match_operand:DI 1 "general_operand" "d,m")))]
- "s390_match_ccmode(insn, CCUmode) && TARGET_64BIT"
+ [(set (reg CC_REGNUM)
+ (compare (match_operand:DI 0 "nonimmediate_operand" "d,d,Q,BQ")
+ (match_operand:DI 1 "general_operand" "d,m,BQ,Q")))]
+ "s390_match_ccmode (insn, CCUmode) && TARGET_64BIT"
"@
clgr\t%0,%1
- clg\t%0,%1"
- [(set_attr "op_type" "RRE,RXY")])
+ clg\t%0,%1
+ #
+ #"
+ [(set_attr "op_type" "RRE,RXY,SS,SS")])
(define_insn "*cmpsi_ccu"
- [(set (reg 33)
- (compare (match_operand:SI 0 "register_operand" "d,d,d")
- (match_operand:SI 1 "general_operand" "d,R,T")))]
- "s390_match_ccmode(insn, CCUmode)"
+ [(set (reg CC_REGNUM)
+ (compare (match_operand:SI 0 "nonimmediate_operand" "d,d,d,Q,BQ")
+ (match_operand:SI 1 "general_operand" "d,R,T,BQ,Q")))]
+ "s390_match_ccmode (insn, CCUmode)"
"@
clr\t%0,%1
cl\t%0,%1
- cly\t%0,%1"
- [(set_attr "op_type" "RR,RX,RXY")])
+ cly\t%0,%1
+ #
+ #"
+ [(set_attr "op_type" "RR,RX,RXY,SS,SS")])
(define_insn "*cmphi_ccu"
- [(set (reg 33)
- (compare (match_operand:HI 0 "register_operand" "d,d")
- (match_operand:HI 1 "s_imm_operand" "Q,S")))]
- "s390_match_ccmode(insn, CCUmode)"
- "@
- clm\t%0,3,%1
- clmy\t%0,3,%1"
- [(set_attr "op_type" "RS,RSY")])
+ [(set (reg CC_REGNUM)
+ (compare (match_operand:HI 0 "nonimmediate_operand" "d,d,Q,BQ")
+ (match_operand:HI 1 "general_operand" "Q,S,BQ,Q")))]
+ "s390_match_ccmode (insn, CCUmode)
+ && !register_operand (operands[1], HImode)"
+ "@
+ clm\t%0,3,%S1
+ clmy\t%0,3,%S1
+ #
+ #"
+ [(set_attr "op_type" "RS,RSY,SS,SS")])
(define_insn "*cmpqi_ccu"
- [(set (reg 33)
- (compare (match_operand:QI 0 "register_operand" "d,d")
- (match_operand:QI 1 "s_imm_operand" "Q,S")))]
- "s390_match_ccmode(insn, CCUmode)"
- "@
- clm\t%0,1,%1
- clmy\t%0,1,%1"
- [(set_attr "op_type" "RS,RSY")])
-
-(define_insn "*cli"
- [(set (reg 33)
- (compare (match_operand:QI 0 "memory_operand" "Q,S")
- (match_operand:QI 1 "immediate_operand" "n,n")))]
- "s390_match_ccmode (insn, CCUmode)"
- "@
- cli\t%0,%b1
- cliy\t%0,%b1"
- [(set_attr "op_type" "SI,SIY")])
+ [(set (reg CC_REGNUM)
+ (compare (match_operand:QI 0 "nonimmediate_operand" "d,d,Q,S,Q,BQ")
+ (match_operand:QI 1 "general_operand" "Q,S,n,n,BQ,Q")))]
+ "s390_match_ccmode (insn, CCUmode)
+ && !register_operand (operands[1], QImode)"
+ "@
+ clm\t%0,1,%S1
+ clmy\t%0,1,%S1
+ cli\t%S0,%b1
+ cliy\t%S0,%b1
+ #
+ #"
+ [(set_attr "op_type" "RS,RSY,SI,SIY,SS,SS")])
-(define_insn "*cmpdi_ccu_mem"
- [(set (reg 33)
- (compare (match_operand:DI 0 "s_operand" "Q")
- (match_operand:DI 1 "s_imm_operand" "Q")))]
- "s390_match_ccmode(insn, CCUmode)"
- "clc\t%O0(8,%R0),%1"
- [(set_attr "op_type" "SS")])
-(define_insn "*cmpsi_ccu_mem"
- [(set (reg 33)
- (compare (match_operand:SI 0 "s_operand" "Q")
- (match_operand:SI 1 "s_imm_operand" "Q")))]
- "s390_match_ccmode(insn, CCUmode)"
- "clc\t%O0(4,%R0),%1"
- [(set_attr "op_type" "SS")])
-
-(define_insn "*cmphi_ccu_mem"
- [(set (reg 33)
- (compare (match_operand:HI 0 "s_operand" "Q")
- (match_operand:HI 1 "s_imm_operand" "Q")))]
- "s390_match_ccmode(insn, CCUmode)"
- "clc\t%O0(2,%R0),%1"
- [(set_attr "op_type" "SS")])
+; Block compare (CLC) instruction patterns.
-(define_insn "*cmpqi_ccu_mem"
- [(set (reg 33)
- (compare (match_operand:QI 0 "s_operand" "Q")
- (match_operand:QI 1 "s_imm_operand" "Q")))]
- "s390_match_ccmode(insn, CCUmode)"
- "clc\t%O0(1,%R0),%1"
+(define_insn "*clc"
+ [(set (reg CC_REGNUM)
+ (compare (match_operand:BLK 0 "memory_operand" "Q")
+ (match_operand:BLK 1 "memory_operand" "Q")))
+ (use (match_operand 2 "const_int_operand" "n"))]
+ "s390_match_ccmode (insn, CCUmode)
+ && INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
+ "clc\t%O0(%2,%R0),%S1"
[(set_attr "op_type" "SS")])
+(define_split
+ [(set (reg CC_REGNUM)
+ (compare (match_operand 0 "memory_operand" "")
+ (match_operand 1 "memory_operand" "")))]
+ "reload_completed
+ && s390_match_ccmode (insn, CCUmode)
+ && GET_MODE (operands[0]) == GET_MODE (operands[1])
+ && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
+ [(parallel
+ [(set (match_dup 0) (match_dup 1))
+ (use (match_dup 2))])]
+{
+ operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
+ operands[0] = adjust_address (operands[0], BLKmode, 0);
+ operands[1] = adjust_address (operands[1], BLKmode, 0);
-; DF instructions
-
-(define_insn "*cmpdf_ccs_0"
- [(set (reg 33)
- (compare (match_operand:DF 0 "register_operand" "f")
- (match_operand:DF 1 "const0_operand" "")))]
- "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
- "ltdbr\t%0,%0"
- [(set_attr "op_type" "RRE")
- (set_attr "type" "fsimpd")])
-
-(define_insn "*cmpdf_ccs_0_ibm"
- [(set (reg 33)
- (compare (match_operand:DF 0 "register_operand" "f")
- (match_operand:DF 1 "const0_operand" "")))]
- "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
- "ltdr\t%0,%0"
- [(set_attr "op_type" "RR")
- (set_attr "type" "fsimpd")])
-
-(define_insn "*cmpdf_ccs"
- [(set (reg 33)
- (compare (match_operand:DF 0 "register_operand" "f,f")
- (match_operand:DF 1 "general_operand" "f,R")))]
- "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
- "@
- cdbr\t%0,%1
- cdb\t%0,%1"
- [(set_attr "op_type" "RRE,RXE")
- (set_attr "type" "fsimpd")])
-
-(define_insn "*cmpdf_ccs_ibm"
- [(set (reg 33)
- (compare (match_operand:DF 0 "register_operand" "f,f")
- (match_operand:DF 1 "general_operand" "f,R")))]
- "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
- "@
- cdr\t%0,%1
- cd\t%0,%1"
- [(set_attr "op_type" "RR,RX")
- (set_attr "type" "fsimpd")])
+ operands[1] = gen_rtx_COMPARE (GET_MODE (SET_DEST (PATTERN (curr_insn))),
+ operands[0], operands[1]);
+ operands[0] = SET_DEST (PATTERN (curr_insn));
+})
-; SF instructions
+; (DF|SF) instructions
-(define_insn "*cmpsf_ccs_0"
- [(set (reg 33)
- (compare (match_operand:SF 0 "register_operand" "f")
- (match_operand:SF 1 "const0_operand" "")))]
+(define_insn "*cmp<mode>_ccs_0"
+ [(set (reg CC_REGNUM)
+ (compare (match_operand:FPR 0 "register_operand" "f")
+ (match_operand:FPR 1 "const0_operand" "")))]
"s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
- "ltebr\t%0,%0"
+ "lt<de>br\t%0,%0"
[(set_attr "op_type" "RRE")
- (set_attr "type" "fsimps")])
+ (set_attr "type" "fsimp<mode>")])
-(define_insn "*cmpsf_ccs_0_ibm"
- [(set (reg 33)
- (compare (match_operand:SF 0 "register_operand" "f")
- (match_operand:SF 1 "const0_operand" "")))]
+(define_insn "*cmp<mode>_ccs_0_ibm"
+ [(set (reg CC_REGNUM)
+ (compare (match_operand:FPR 0 "register_operand" "f")
+ (match_operand:FPR 1 "const0_operand" "")))]
"s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
- "lter\t%0,%0"
+ "lt<de>r\t%0,%0"
[(set_attr "op_type" "RR")
- (set_attr "type" "fsimps")])
+ (set_attr "type" "fsimp<mode>")])
-(define_insn "*cmpsf_ccs"
- [(set (reg 33)
- (compare (match_operand:SF 0 "register_operand" "f,f")
- (match_operand:SF 1 "general_operand" "f,R")))]
+(define_insn "*cmp<mode>_ccs"
+ [(set (reg CC_REGNUM)
+ (compare (match_operand:FPR 0 "register_operand" "f,f")
+ (match_operand:FPR 1 "general_operand" "f,R")))]
"s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"@
- cebr\t%0,%1
- ceb\t%0,%1"
+ c<de>br\t%0,%1
+ c<de>b\t%0,%1"
[(set_attr "op_type" "RRE,RXE")
- (set_attr "type" "fsimps")])
+ (set_attr "type" "fsimp<mode>")])
-(define_insn "*cmpsf_ccs"
- [(set (reg 33)
- (compare (match_operand:SF 0 "register_operand" "f,f")
- (match_operand:SF 1 "general_operand" "f,R")))]
+(define_insn "*cmp<mode>_ccs_ibm"
+ [(set (reg CC_REGNUM)
+ (compare (match_operand:FPR 0 "register_operand" "f,f")
+ (match_operand:FPR 1 "general_operand" "f,R")))]
"s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
"@
- cer\t%0,%1
- ce\t%0,%1"
+ c<de>r\t%0,%1
+ c<de>\t%0,%1"
[(set_attr "op_type" "RR,RX")
- (set_attr "type" "fsimps")])
+ (set_attr "type" "fsimp<mode>")])
;;
(match_operand:TI 1 "general_operand" "QS,d,dKm,d,Q"))]
"TARGET_64BIT"
"@
- lmg\t%0,%N0,%1
- stmg\t%1,%N1,%0
+ lmg\t%0,%N0,%S1
+ stmg\t%1,%N1,%S0
#
#
- mvc\t%O0(16,%R0),%1"
- [(set_attr "op_type" "RSY,RSY,NN,NN,SS")
- (set_attr "type" "lm,stm,*,*,cs")])
+ #"
+ [(set_attr "op_type" "RSY,RSY,*,*,SS")
+ (set_attr "type" "lm,stm,*,*,*")])
(define_split
[(set (match_operand:TI 0 "nonimmediate_operand" "")
})
(define_expand "reload_outti"
- [(parallel [(match_operand:TI 0 "memory_operand" "")
+ [(parallel [(match_operand:TI 0 "" "")
(match_operand:TI 1 "register_operand" "d")
(match_operand:DI 2 "register_operand" "=&a")])]
"TARGET_64BIT"
{
- s390_load_address (operands[2], XEXP (operands[0], 0));
+ gcc_assert (MEM_P (operands[0]));
+ s390_load_address (operands[2], find_replacement (&XEXP (operands[0], 0)));
operands[0] = replace_equiv_address (operands[0], operands[2]);
emit_move_insn (operands[0], operands[1]);
DONE;
(define_insn "*movdi_64"
[(set (match_operand:DI 0 "nonimmediate_operand"
- "=d,d,d,d,d,d,d,d,m,!*f,!*f,!*f,!R,!T,?Q")
+ "=d,d,d,d,d,d,d,d,m,!*f,!*f,!*f,!R,!T,d,t,Q,t,?Q")
(match_operand:DI 1 "general_operand"
- "K,N0HD0,N1HD0,N2HD0,N3HD0,L,d,m,d,*f,R,T,*f,*f,?Q"))]
+ "K,N0HD0,N1HD0,N2HD0,N3HD0,L,d,m,d,*f,R,T,*f,*f,t,d,t,Q,?Q"))]
"TARGET_64BIT"
"@
lghi\t%0,%h1
ldy\t%0,%1
std\t%1,%0
stdy\t%1,%0
- mvc\t%O0(8,%R0),%1"
- [(set_attr "op_type" "RI,RI,RI,RI,RI,RXY,RRE,RXY,RXY,RR,RX,RXY,RX,RXY,SS")
- (set_attr "type" "*,*,*,*,*,la,lr,load,store,floadd,floadd,floadd,
- fstored,fstored,cs")])
+ #
+ #
+ stam\t%1,%N1,%S0
+ lam\t%0,%N0,%S1
+ #"
+ [(set_attr "op_type" "RI,RI,RI,RI,RI,RXY,RRE,RXY,RXY,
+ RR,RX,RXY,RX,RXY,*,*,RS,RS,SS")
+ (set_attr "type" "*,*,*,*,*,la,lr,load,store,
+ floaddf,floaddf,floaddf,fstoredf,fstoredf,*,*,*,*,*")])
+
+(define_split
+ [(set (match_operand:DI 0 "register_operand" "")
+ (match_operand:DI 1 "register_operand" ""))]
+ "TARGET_64BIT && ACCESS_REG_P (operands[1])"
+ [(set (match_dup 2) (match_dup 3))
+ (set (match_dup 0) (ashift:DI (match_dup 0) (const_int 32)))
+ (set (strict_low_part (match_dup 2)) (match_dup 4))]
+ "operands[2] = gen_lowpart (SImode, operands[0]);
+ s390_split_access_reg (operands[1], &operands[4], &operands[3]);")
+
+(define_split
+ [(set (match_operand:DI 0 "register_operand" "")
+ (match_operand:DI 1 "register_operand" ""))]
+ "TARGET_64BIT && ACCESS_REG_P (operands[0])
+ && dead_or_set_p (insn, operands[1])"
+ [(set (match_dup 3) (match_dup 2))
+ (set (match_dup 1) (lshiftrt:DI (match_dup 1) (const_int 32)))
+ (set (match_dup 4) (match_dup 2))]
+ "operands[2] = gen_lowpart (SImode, operands[1]);
+ s390_split_access_reg (operands[0], &operands[3], &operands[4]);")
+
+(define_split
+ [(set (match_operand:DI 0 "register_operand" "")
+ (match_operand:DI 1 "register_operand" ""))]
+ "TARGET_64BIT && ACCESS_REG_P (operands[0])
+ && !dead_or_set_p (insn, operands[1])"
+ [(set (match_dup 3) (match_dup 2))
+ (set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32)))
+ (set (match_dup 4) (match_dup 2))
+ (set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32)))]
+ "operands[2] = gen_lowpart (SImode, operands[1]);
+ s390_split_access_reg (operands[0], &operands[3], &operands[4]);")
(define_insn "*movdi_31"
[(set (match_operand:DI 0 "nonimmediate_operand" "=d,Q,d,o,!*f,!*f,!*f,!R,!T,Q")
(match_operand:DI 1 "general_operand" "Q,d,dKm,d,*f,R,T,*f,*f,Q"))]
"!TARGET_64BIT"
"@
- lm\t%0,%N0,%1
- stm\t%1,%N1,%0
+ lm\t%0,%N0,%S1
+ stm\t%1,%N1,%S0
#
#
ldr\t%0,%1
ldy\t%0,%1
std\t%1,%0
stdy\t%1,%0
- mvc\t%O0(8,%R0),%1"
- [(set_attr "op_type" "RS,RS,NN,NN,RR,RX,RXY,RX,RXY,SS")
- (set_attr "type" "lm,stm,*,*,floadd,floadd,floadd,fstored,fstored,cs")])
+ #"
+ [(set_attr "op_type" "RS,RS,*,*,RR,RX,RXY,RX,RXY,SS")
+ (set_attr "type" "lm,stm,*,*,floaddf,floaddf,floaddf,fstoredf,fstoredf,*")])
(define_split
[(set (match_operand:DI 0 "nonimmediate_operand" "")
})
(define_expand "reload_outdi"
- [(parallel [(match_operand:DI 0 "memory_operand" "")
+ [(parallel [(match_operand:DI 0 "" "")
(match_operand:DI 1 "register_operand" "d")
(match_operand:SI 2 "register_operand" "=&a")])]
"!TARGET_64BIT"
{
- s390_load_address (operands[2], XEXP (operands[0], 0));
+ gcc_assert (MEM_P (operands[0]));
+ s390_load_address (operands[2], find_replacement (&XEXP (operands[0], 0)));
operands[0] = replace_equiv_address (operands[0], operands[2]);
emit_move_insn (operands[0], operands[1]);
DONE;
[(parallel
[(set (match_operand:DI 0 "register_operand" "")
(match_operand:QI 1 "address_operand" ""))
- (clobber (reg:CC 33))])]
+ (clobber (reg:CC CC_REGNUM))])]
"TARGET_64BIT
&& preferred_la_operand_p (operands[1], const0_rtx)"
[(set (match_dup 0) (match_dup 1))]
[(set (match_dup 0)
(plus:DI (match_dup 0)
(match_operand:DI 2 "nonmemory_operand" "")))
- (clobber (reg:CC 33))])]
+ (clobber (reg:CC CC_REGNUM))])]
"TARGET_64BIT
&& !reg_overlap_mentioned_p (operands[0], operands[2])
&& preferred_la_operand_p (operands[1], operands[2])"
(define_insn "*movsi_zarch"
[(set (match_operand:SI 0 "nonimmediate_operand"
- "=d,d,d,d,d,d,d,R,T,!*f,!*f,!*f,!R,!T,?Q")
+ "=d,d,d,d,d,d,d,R,T,!*f,!*f,!*f,!R,!T,d,t,Q,t,?Q")
(match_operand:SI 1 "general_operand"
- "K,N0HS0,N1HS0,L,d,R,T,d,d,*f,R,T,*f,*f,?Q"))]
+ "K,N0HS0,N1HS0,L,d,R,T,d,d,*f,R,T,*f,*f,t,d,t,Q,?Q"))]
"TARGET_ZARCH"
"@
lhi\t%0,%h1
ley\t%0,%1
ste\t%1,%0
stey\t%1,%0
- mvc\t%O0(4,%R0),%1"
- [(set_attr "op_type" "RI,RI,RI,RXY,RR,RX,RXY,RX,RXY,RR,RX,RXY,RX,RXY,SS")
- (set_attr "type" "*,*,*,la,lr,load,load,store,store,floads,floads,floads,fstores,fstores,cs")])
+ ear\t%0,%1
+ sar\t%0,%1
+ stam\t%1,%1,%S0
+ lam\t%0,%0,%S1
+ #"
+ [(set_attr "op_type" "RI,RI,RI,RXY,RR,RX,RXY,RX,RXY,
+ RR,RX,RXY,RX,RXY,RRE,RRE,RS,RS,SS")
+ (set_attr "type" "*,*,*,la,lr,load,load,store,store,
+ floadsf,floadsf,floadsf,fstoresf,fstoresf,*,*,*,*,*")])
(define_insn "*movsi_esa"
- [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,R,!*f,!*f,!R,?Q")
- (match_operand:SI 1 "general_operand" "K,d,R,d,*f,R,*f,?Q"))]
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,R,!*f,!*f,!R,d,t,Q,t,?Q")
+ (match_operand:SI 1 "general_operand" "K,d,R,d,*f,R,*f,t,d,t,Q,?Q"))]
"!TARGET_ZARCH"
"@
lhi\t%0,%h1
ler\t%0,%1
le\t%0,%1
ste\t%1,%0
- mvc\t%O0(4,%R0),%1"
- [(set_attr "op_type" "RI,RR,RX,RX,RR,RX,RX,SS")
- (set_attr "type" "*,lr,load,store,floads,floads,fstores,cs")])
+ ear\t%0,%1
+ sar\t%0,%1
+ stam\t%1,%1,%S0
+ lam\t%0,%0,%S1
+ #"
+ [(set_attr "op_type" "RI,RR,RX,RX,RR,RX,RX,RRE,RRE,RS,RS,SS")
+ (set_attr "type" "*,lr,load,store,floadsf,floadsf,fstoresf,*,*,*,*,*")])
(define_peephole2
[(set (match_operand:SI 0 "register_operand" "")
[(parallel
[(set (match_operand:SI 0 "register_operand" "")
(match_operand:QI 1 "address_operand" ""))
- (clobber (reg:CC 33))])]
+ (clobber (reg:CC CC_REGNUM))])]
"!TARGET_64BIT
&& preferred_la_operand_p (operands[1], const0_rtx)"
[(set (match_dup 0) (match_dup 1))]
[(set (match_dup 0)
(plus:SI (match_dup 0)
(match_operand:SI 2 "nonmemory_operand" "")))
- (clobber (reg:CC 33))])]
+ (clobber (reg:CC CC_REGNUM))])]
"!TARGET_64BIT
&& !reg_overlap_mentioned_p (operands[0], operands[2])
&& preferred_la_operand_p (operands[1], operands[2])"
[(set (match_operand:SI 0 "register_operand" "=d")
(and:SI (match_operand:QI 1 "address_operand" "p")
(const_int 2147483647)))
- (clobber (reg:CC 33))]
+ (clobber (reg:CC CC_REGNUM))]
"!TARGET_64BIT"
"#"
"&& reload_completed"
lhy\t%0,%1
sth\t%1,%0
sthy\t%1,%0
- mvc\t%O0(2,%R0),%1"
+ #"
[(set_attr "op_type" "RR,RI,RX,RXY,RX,RXY,SS")
- (set_attr "type" "lr,*,*,*,store,store,cs")])
+ (set_attr "type" "lr,*,*,*,store,store,*")])
(define_peephole2
[(set (match_operand:HI 0 "register_operand" "")
icy\t%0,%1
stc\t%1,%0
stcy\t%1,%0
- mvi\t%0,%b1
- mviy\t%0,%b1
- mvc\t%O0(1,%R0),%1"
+ mvi\t%S0,%b1
+ mviy\t%S0,%b1
+ #"
[(set_attr "op_type" "RR,RI,RX,RXY,RX,RXY,SI,SIY,SS")
- (set_attr "type" "lr,*,*,*,store,store,store,store,cs")])
+ (set_attr "type" "lr,*,*,*,store,store,store,store,*")])
(define_peephole2
[(set (match_operand:QI 0 "nonimmediate_operand" "")
(define_insn "*movstricthi"
[(set (strict_low_part (match_operand:HI 0 "register_operand" "+d,d"))
- (match_operand:HI 1 "s_imm_operand" "Q,S"))
- (clobber (reg:CC 33))]
+ (match_operand:HI 1 "memory_operand" "Q,S"))
+ (clobber (reg:CC CC_REGNUM))]
""
"@
- icm\t%0,3,%1
- icmy\t%0,3,%1"
+ icm\t%0,3,%S1
+ icmy\t%0,3,%S1"
[(set_attr "op_type" "RS,RSY")])
;
;
(define_insn "movstrictsi"
- [(set (strict_low_part (match_operand:SI 0 "register_operand" "+d,d,d"))
- (match_operand:SI 1 "general_operand" "d,R,T"))]
+ [(set (strict_low_part (match_operand:SI 0 "register_operand" "+d,d,d,d"))
+ (match_operand:SI 1 "general_operand" "d,R,T,t"))]
"TARGET_64BIT"
"@
lr\t%0,%1
l\t%0,%1
- ly\t%0,%1"
- [(set_attr "op_type" "RR,RX,RXY")
- (set_attr "type" "lr,load,load")])
+ ly\t%0,%1
+ ear\t%0,%1"
+ [(set_attr "op_type" "RR,RX,RXY,RRE")
+ (set_attr "type" "lr,load,load,*")])
;
; movdf instruction pattern(s).
"")
(define_insn "*movdf_64"
- [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,R,T,d,d,m,?Q")
- (match_operand:DF 1 "general_operand" "f,R,T,f,f,d,m,d,?Q"))]
+ [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,f,R,T,d,d,m,?Q")
+ (match_operand:DF 1 "general_operand" "G,f,R,T,f,f,d,m,d,?Q"))]
"TARGET_64BIT"
"@
+ lzdr\t%0
ldr\t%0,%1
ld\t%0,%1
ldy\t%0,%1
lgr\t%0,%1
lg\t%0,%1
stg\t%1,%0
- mvc\t%O0(8,%R0),%1"
- [(set_attr "op_type" "RR,RX,RXY,RX,RXY,RRE,RXY,RXY,SS")
- (set_attr "type" "floadd,floadd,floadd,fstored,fstored,lr,load,store,cs")])
+ #"
+ [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RRE,RXY,RXY,SS")
+ (set_attr "type" "fsimpdf,floaddf,floaddf,floaddf,fstoredf,fstoredf,lr,load,store,*")])
(define_insn "*movdf_31"
- [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,R,T,d,Q,d,o,Q")
- (match_operand:DF 1 "general_operand" "f,R,T,f,f,Q,d,dKm,d,Q"))]
+ [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,f,R,T,d,Q,d,o,Q")
+ (match_operand:DF 1 "general_operand" "G,f,R,T,f,f,Q,d,dKm,d,Q"))]
"!TARGET_64BIT"
"@
+ lzdr\t%0
ldr\t%0,%1
ld\t%0,%1
ldy\t%0,%1
std\t%1,%0
stdy\t%1,%0
- lm\t%0,%N0,%1
- stm\t%1,%N1,%0
+ lm\t%0,%N0,%S1
+ stm\t%1,%N1,%S0
#
#
- mvc\t%O0(8,%R0),%1"
- [(set_attr "op_type" "RR,RX,RXY,RX,RXY,RS,RS,NN,NN,SS")
- (set_attr "type" "floadd,floadd,floadd,fstored,fstored,lm,stm,*,*,cs")])
+ #"
+ [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RS,RS,*,*,SS")
+ (set_attr "type" "fsimpdf,floaddf,floaddf,floaddf,fstoredf,fstoredf,lm,stm,*,*,*")])
(define_split
[(set (match_operand:DF 0 "nonimmediate_operand" "")
})
(define_expand "reload_outdf"
- [(parallel [(match_operand:DF 0 "memory_operand" "")
+ [(parallel [(match_operand:DF 0 "" "")
(match_operand:DF 1 "register_operand" "d")
(match_operand:SI 2 "register_operand" "=&a")])]
"!TARGET_64BIT"
{
- s390_load_address (operands[2], XEXP (operands[0], 0));
+ gcc_assert (MEM_P (operands[0]));
+ s390_load_address (operands[2], find_replacement (&XEXP (operands[0], 0)));
operands[0] = replace_equiv_address (operands[0], operands[2]);
emit_move_insn (operands[0], operands[1]);
DONE;
;
(define_insn "movsf"
- [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,f,R,T,d,d,d,R,T,?Q")
- (match_operand:SF 1 "general_operand" "f,R,T,f,f,d,R,T,d,d,?Q"))]
+ [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,f,f,R,T,d,d,d,R,T,?Q")
+ (match_operand:SF 1 "general_operand" "G,f,R,T,f,f,d,R,T,d,d,?Q"))]
""
"@
+ lzer\t%0
ler\t%0,%1
le\t%0,%1
ley\t%0,%1
ly\t%0,%1
st\t%1,%0
sty\t%1,%0
- mvc\t%O0(4,%R0),%1"
- [(set_attr "op_type" "RR,RX,RXY,RX,RXY,RR,RX,RXY,RX,RXY,SS")
- (set_attr "type" "floads,floads,floads,fstores,fstores,lr,load,load,store,store,cs")])
+ #"
+ [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RR,RX,RXY,RX,RXY,SS")
+ (set_attr "type" "fsimpsf,floadsf,floadsf,floadsf,fstoresf,fstoresf,
+ lr,load,load,store,store,*")])
+
+;
+; movcc instruction pattern
+;
+
+(define_insn "movcc"
+ [(set (match_operand:CC 0 "nonimmediate_operand" "=d,c,d,d,d,R,T")
+ (match_operand:CC 1 "nonimmediate_operand" "d,d,c,R,T,d,d"))]
+ ""
+ "@
+ lr\t%0,%1
+ tmh\t%1,12288
+ ipm\t%0
+ st\t%0,%1
+ sty\t%0,%1
+ l\t%1,%0
+ ly\t%1,%0"
+ [(set_attr "op_type" "RR,RI,RRE,RX,RXY,RX,RXY")
+ (set_attr "type" "lr,*,*,store,store,load,load")])
+
+;
+; Block move (MVC) patterns.
+;
+
+(define_insn "*mvc"
+ [(set (match_operand:BLK 0 "memory_operand" "=Q")
+ (match_operand:BLK 1 "memory_operand" "Q"))
+ (use (match_operand 2 "const_int_operand" "n"))]
+ "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
+ "mvc\t%O0(%2,%R0),%S1"
+ [(set_attr "op_type" "SS")])
+
+(define_split
+ [(set (match_operand 0 "memory_operand" "")
+ (match_operand 1 "memory_operand" ""))]
+ "reload_completed
+ && GET_MODE (operands[0]) == GET_MODE (operands[1])
+ && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
+ [(parallel
+ [(set (match_dup 0) (match_dup 1))
+ (use (match_dup 2))])]
+{
+ operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
+ operands[0] = adjust_address (operands[0], BLKmode, 0);
+ operands[1] = adjust_address (operands[1], BLKmode, 0);
+})
+
+(define_peephole2
+ [(parallel
+ [(set (match_operand:BLK 0 "memory_operand" "")
+ (match_operand:BLK 1 "memory_operand" ""))
+ (use (match_operand 2 "const_int_operand" ""))])
+ (parallel
+ [(set (match_operand:BLK 3 "memory_operand" "")
+ (match_operand:BLK 4 "memory_operand" ""))
+ (use (match_operand 5 "const_int_operand" ""))])]
+ "s390_offset_p (operands[0], operands[3], operands[2])
+ && s390_offset_p (operands[1], operands[4], operands[2])
+ && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
+ [(parallel
+ [(set (match_dup 6) (match_dup 7))
+ (use (match_dup 8))])]
+ "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
+ operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
+ operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
+
;
; load_multiple pattern(s).
{
int words = XVECLEN (operands[0], 0);
operands[0] = gen_rtx_REG (DImode, REGNO (operands[1]) + words - 1);
- return "lmg\t%1,%0,%2";
+ return "lmg\t%1,%0,%S2";
}
[(set_attr "op_type" "RSY")
(set_attr "type" "lm")])
{
int words = XVECLEN (operands[0], 0);
operands[0] = gen_rtx_REG (SImode, REGNO (operands[1]) + words - 1);
- return which_alternative == 0 ? "lm\t%1,%0,%2" : "lmy\t%1,%0,%2";
+ return which_alternative == 0 ? "lm\t%1,%0,%S2" : "lmy\t%1,%0,%S2";
}
[(set_attr "op_type" "RS,RSY")
(set_attr "type" "lm")])
{
int words = XVECLEN (operands[0], 0);
operands[0] = gen_rtx_REG (DImode, REGNO (operands[2]) + words - 1);
- return "stmg\t%2,%0,%1";
+ return "stmg\t%2,%0,%S1";
}
[(set_attr "op_type" "RSY")
(set_attr "type" "stm")])
{
int words = XVECLEN (operands[0], 0);
operands[0] = gen_rtx_REG (SImode, REGNO (operands[2]) + words - 1);
- return which_alternative == 0 ? "stm\t%2,%0,%1" : "stmy\t%2,%0,%1";
+ return which_alternative == 0 ? "stm\t%2,%0,%S1" : "stmy\t%2,%0,%S1";
}
[(set_attr "op_type" "RS,RSY")
(set_attr "type" "stm")])
;; String instructions.
;;
+(define_insn "*execute"
+ [(match_parallel 0 ""
+ [(unspec [(match_operand 1 "register_operand" "a")
+ (match_operand:BLK 2 "memory_operand" "R")
+ (match_operand 3 "" "")] UNSPEC_EXECUTE)])]
+ "GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
+ && GET_MODE_SIZE (GET_MODE (operands[1])) <= UNITS_PER_WORD"
+ "ex\t%1,%2"
+ [(set_attr "op_type" "RX")
+ (set_attr "type" "cs")])
+
+
;
; strlenM instruction pattern(s).
;
-(define_expand "strlendi"
- [(set (reg:QI 0) (match_operand:QI 2 "immediate_operand" ""))
- (parallel
- [(set (match_dup 4)
- (unspec:DI [(const_int 0)
- (match_operand:BLK 1 "memory_operand" "")
- (reg:QI 0)
- (match_operand 3 "immediate_operand" "")] UNSPEC_SRST))
- (clobber (scratch:DI))
- (clobber (reg:CC 33))])
- (parallel
- [(set (match_operand:DI 0 "register_operand" "")
- (minus:DI (match_dup 4) (match_dup 5)))
- (clobber (reg:CC 33))])]
- "TARGET_64BIT"
-{
- operands[4] = gen_reg_rtx (DImode);
- operands[5] = gen_reg_rtx (DImode);
- emit_move_insn (operands[5], force_operand (XEXP (operands[1], 0), NULL_RTX));
- operands[1] = replace_equiv_address (operands[1], operands[5]);
-})
-
-(define_insn "*strlendi"
- [(set (match_operand:DI 0 "register_operand" "=a")
- (unspec:DI [(match_operand:DI 2 "general_operand" "0")
- (mem:BLK (match_operand:DI 3 "register_operand" "1"))
- (reg:QI 0)
- (match_operand 4 "immediate_operand" "")] UNSPEC_SRST))
- (clobber (match_scratch:DI 1 "=a"))
- (clobber (reg:CC 33))]
- "TARGET_64BIT"
- "srst\t%0,%1\;jo\t.-4"
- [(set_attr "op_type" "NN")
- (set_attr "type" "vs")
- (set_attr "length" "8")])
-
-(define_expand "strlensi"
+(define_expand "strlen<mode>"
[(set (reg:QI 0) (match_operand:QI 2 "immediate_operand" ""))
(parallel
[(set (match_dup 4)
- (unspec:SI [(const_int 0)
+ (unspec:P [(const_int 0)
(match_operand:BLK 1 "memory_operand" "")
(reg:QI 0)
(match_operand 3 "immediate_operand" "")] UNSPEC_SRST))
- (clobber (scratch:SI))
- (clobber (reg:CC 33))])
+ (clobber (scratch:P))
+ (clobber (reg:CC CC_REGNUM))])
(parallel
- [(set (match_operand:SI 0 "register_operand" "")
- (minus:SI (match_dup 4) (match_dup 5)))
- (clobber (reg:CC 33))])]
- "!TARGET_64BIT"
+ [(set (match_operand:P 0 "register_operand" "")
+ (minus:P (match_dup 4) (match_dup 5)))
+ (clobber (reg:CC CC_REGNUM))])]
+ ""
{
- operands[4] = gen_reg_rtx (SImode);
- operands[5] = gen_reg_rtx (SImode);
+ operands[4] = gen_reg_rtx (Pmode);
+ operands[5] = gen_reg_rtx (Pmode);
emit_move_insn (operands[5], force_operand (XEXP (operands[1], 0), NULL_RTX));
operands[1] = replace_equiv_address (operands[1], operands[5]);
})
-(define_insn "*strlensi"
- [(set (match_operand:SI 0 "register_operand" "=a")
- (unspec:SI [(match_operand:SI 2 "general_operand" "0")
- (mem:BLK (match_operand:SI 3 "register_operand" "1"))
+(define_insn "*strlen<mode>"
+ [(set (match_operand:P 0 "register_operand" "=a")
+ (unspec:P [(match_operand:P 2 "general_operand" "0")
+ (mem:BLK (match_operand:P 3 "register_operand" "1"))
(reg:QI 0)
(match_operand 4 "immediate_operand" "")] UNSPEC_SRST))
- (clobber (match_scratch:SI 1 "=a"))
- (clobber (reg:CC 33))]
- "!TARGET_64BIT"
+ (clobber (match_scratch:P 1 "=a"))
+ (clobber (reg:CC CC_REGNUM))]
+ ""
"srst\t%0,%1\;jo\t.-4"
- [(set_attr "op_type" "NN")
- (set_attr "type" "vs")
- (set_attr "length" "8")])
+ [(set_attr "length" "8")
+ (set_attr "type" "vs")])
;
; movmemM instruction pattern(s).
;
-(define_expand "movmemdi"
- [(set (match_operand:BLK 0 "memory_operand" "")
- (match_operand:BLK 1 "memory_operand" ""))
- (use (match_operand:DI 2 "general_operand" ""))
- (match_operand 3 "" "")]
- "TARGET_64BIT"
- "s390_expand_movmem (operands[0], operands[1], operands[2]); DONE;")
-
-(define_expand "movmemsi"
+(define_expand "movmem<mode>"
[(set (match_operand:BLK 0 "memory_operand" "")
(match_operand:BLK 1 "memory_operand" ""))
- (use (match_operand:SI 2 "general_operand" ""))
+ (use (match_operand:GPR 2 "general_operand" ""))
(match_operand 3 "" "")]
""
"s390_expand_movmem (operands[0], operands[1], operands[2]); DONE;")
[(set (match_operand:BLK 0 "memory_operand" "")
(match_operand:BLK 1 "memory_operand" ""))
(use (match_operand 2 "nonmemory_operand" ""))
+ (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
(clobber (match_dup 3))])]
""
"operands[3] = gen_rtx_SCRATCH (Pmode);")
(define_insn "*movmem_short"
- [(set (match_operand:BLK 0 "memory_operand" "=Q,Q")
- (match_operand:BLK 1 "memory_operand" "Q,Q"))
- (use (match_operand 2 "nonmemory_operand" "n,a"))
- (clobber (match_scratch 3 "=X,&a"))]
+ [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q")
+ (match_operand:BLK 1 "memory_operand" "Q,Q,Q"))
+ (use (match_operand 2 "nonmemory_operand" "n,a,a"))
+ (use (match_operand 3 "immediate_operand" "X,R,X"))
+ (clobber (match_scratch 4 "=X,X,&a"))]
"(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode)
- && GET_MODE (operands[3]) == Pmode"
-{
- switch (which_alternative)
- {
- case 0:
- return "mvc\t%O0(%b2+1,%R0),%1";
+ && GET_MODE (operands[4]) == Pmode"
+ "#"
+ [(set_attr "type" "cs")])
- case 1:
- output_asm_insn ("bras\t%3,.+10", operands);
- output_asm_insn ("mvc\t%O0(1,%R0),%1", operands);
- return "ex\t%2,0(%3)";
+(define_split
+ [(set (match_operand:BLK 0 "memory_operand" "")
+ (match_operand:BLK 1 "memory_operand" ""))
+ (use (match_operand 2 "const_int_operand" ""))
+ (use (match_operand 3 "immediate_operand" ""))
+ (clobber (scratch))]
+ "reload_completed"
+ [(parallel
+ [(set (match_dup 0) (match_dup 1))
+ (use (match_dup 2))])]
+ "operands[2] = GEN_INT ((INTVAL (operands[2]) & 0xff) + 1);")
- default:
- abort ();
- }
-}
- [(set_attr "op_type" "SS,NN")
- (set_attr "type" "cs,cs")
- (set_attr "atype" "*,agen")
- (set_attr "length" "*,14")])
+(define_split
+ [(set (match_operand:BLK 0 "memory_operand" "")
+ (match_operand:BLK 1 "memory_operand" ""))
+ (use (match_operand 2 "register_operand" ""))
+ (use (match_operand 3 "memory_operand" ""))
+ (clobber (scratch))]
+ "reload_completed"
+ [(parallel
+ [(unspec [(match_dup 2) (match_dup 3)
+ (const_int 0)] UNSPEC_EXECUTE)
+ (set (match_dup 0) (match_dup 1))
+ (use (const_int 1))])]
+ "")
+
+(define_split
+ [(set (match_operand:BLK 0 "memory_operand" "")
+ (match_operand:BLK 1 "memory_operand" ""))
+ (use (match_operand 2 "register_operand" ""))
+ (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
+ (clobber (match_operand 3 "register_operand" ""))]
+ "reload_completed && TARGET_CPU_ZARCH"
+ [(set (match_dup 3) (label_ref (match_dup 4)))
+ (parallel
+ [(unspec [(match_dup 2) (mem:BLK (match_dup 3))
+ (label_ref (match_dup 4))] UNSPEC_EXECUTE)
+ (set (match_dup 0) (match_dup 1))
+ (use (const_int 1))])]
+ "operands[4] = gen_label_rtx ();")
; Move a block of arbitrary length.
(match_operand:BLK 1 "memory_operand" ""))
(use (match_operand 2 "general_operand" ""))
(use (match_dup 3))
- (clobber (reg:CC 33))])]
+ (clobber (reg:CC CC_REGNUM))])]
""
{
enum machine_mode dword_mode = word_mode == DImode ? TImode : DImode;
(mem:BLK (subreg:DI (match_operand:TI 3 "register_operand" "1") 0)))
(use (match_dup 2))
(use (match_dup 3))
- (clobber (reg:CC 33))]
+ (clobber (reg:CC CC_REGNUM))]
"TARGET_64BIT"
"mvcle\t%0,%1,0\;jo\t.-4"
- [(set_attr "op_type" "NN")
- (set_attr "type" "vs")
- (set_attr "length" "8")])
+ [(set_attr "length" "8")
+ (set_attr "type" "vs")])
(define_insn "*movmem_long_31"
[(clobber (match_operand:DI 0 "register_operand" "=d"))
(mem:BLK (subreg:SI (match_operand:DI 3 "register_operand" "1") 0)))
(use (match_dup 2))
(use (match_dup 3))
- (clobber (reg:CC 33))]
+ (clobber (reg:CC CC_REGNUM))]
"!TARGET_64BIT"
"mvcle\t%0,%1,0\;jo\t.-4"
- [(set_attr "op_type" "NN")
- (set_attr "type" "vs")
- (set_attr "length" "8")])
+ [(set_attr "length" "8")
+ (set_attr "type" "vs")])
;
; clrmemM instruction pattern(s).
;
-(define_expand "clrmemdi"
- [(set (match_operand:BLK 0 "memory_operand" "")
- (const_int 0))
- (use (match_operand:DI 1 "general_operand" ""))
- (match_operand 2 "" "")]
- "TARGET_64BIT"
- "s390_expand_clrmem (operands[0], operands[1]); DONE;")
-
-(define_expand "clrmemsi"
+(define_expand "clrmem<mode>"
[(set (match_operand:BLK 0 "memory_operand" "")
(const_int 0))
- (use (match_operand:SI 1 "general_operand" ""))
+ (use (match_operand:GPR 1 "general_operand" ""))
(match_operand 2 "" "")]
""
"s390_expand_clrmem (operands[0], operands[1]); DONE;")
[(set (match_operand:BLK 0 "memory_operand" "")
(const_int 0))
(use (match_operand 1 "nonmemory_operand" ""))
+ (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
(clobber (match_dup 2))
- (clobber (reg:CC 33))])]
+ (clobber (reg:CC CC_REGNUM))])]
""
"operands[2] = gen_rtx_SCRATCH (Pmode);")
(define_insn "*clrmem_short"
- [(set (match_operand:BLK 0 "memory_operand" "=Q,Q")
+ [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q")
(const_int 0))
- (use (match_operand 1 "nonmemory_operand" "n,a"))
- (clobber (match_scratch 2 "=X,&a"))
- (clobber (reg:CC 33))]
+ (use (match_operand 1 "nonmemory_operand" "n,a,a"))
+ (use (match_operand 2 "immediate_operand" "X,R,X"))
+ (clobber (match_scratch 3 "=X,X,&a"))
+ (clobber (reg:CC CC_REGNUM))]
"(GET_MODE (operands[1]) == Pmode || GET_MODE (operands[1]) == VOIDmode)
- && GET_MODE (operands[2]) == Pmode"
-{
- switch (which_alternative)
- {
- case 0:
- return "xc\t%O0(%b1+1,%R0),%0";
+ && GET_MODE (operands[3]) == Pmode"
+ "#"
+ [(set_attr "type" "cs")])
+
+(define_split
+ [(set (match_operand:BLK 0 "memory_operand" "")
+ (const_int 0))
+ (use (match_operand 1 "const_int_operand" ""))
+ (use (match_operand 2 "immediate_operand" ""))
+ (clobber (scratch))
+ (clobber (reg:CC CC_REGNUM))]
+ "reload_completed"
+ [(parallel
+ [(set (match_dup 0) (const_int 0))
+ (use (match_dup 1))
+ (clobber (reg:CC CC_REGNUM))])]
+ "operands[1] = GEN_INT ((INTVAL (operands[1]) & 0xff) + 1);")
- case 1:
- output_asm_insn ("bras\t%2,.+10", operands);
- output_asm_insn ("xc\t%O0(1,%R0),%0", operands);
- return "ex\t%1,0(%2)";
+(define_split
+ [(set (match_operand:BLK 0 "memory_operand" "")
+ (const_int 0))
+ (use (match_operand 1 "register_operand" ""))
+ (use (match_operand 2 "memory_operand" ""))
+ (clobber (scratch))
+ (clobber (reg:CC CC_REGNUM))]
+ "reload_completed"
+ [(parallel
+ [(unspec [(match_dup 1) (match_dup 2)
+ (const_int 0)] UNSPEC_EXECUTE)
+ (set (match_dup 0) (const_int 0))
+ (use (const_int 1))
+ (clobber (reg:CC CC_REGNUM))])]
+ "")
- default:
- abort ();
- }
-}
- [(set_attr "op_type" "SS,NN")
- (set_attr "type" "cs,cs")
- (set_attr "atype" "*,agen")
- (set_attr "length" "*,14")])
+(define_split
+ [(set (match_operand:BLK 0 "memory_operand" "")
+ (const_int 0))
+ (use (match_operand 1 "register_operand" ""))
+ (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
+ (clobber (match_operand 2 "register_operand" ""))
+ (clobber (reg:CC CC_REGNUM))]
+ "reload_completed && TARGET_CPU_ZARCH"
+ [(set (match_dup 2) (label_ref (match_dup 3)))
+ (parallel
+ [(unspec [(match_dup 1) (mem:BLK (match_dup 2))
+ (label_ref (match_dup 3))] UNSPEC_EXECUTE)
+ (set (match_dup 0) (const_int 0))
+ (use (const_int 1))
+ (clobber (reg:CC CC_REGNUM))])]
+ "operands[3] = gen_label_rtx ();")
; Clear a block of arbitrary length.
(const_int 0))
(use (match_operand 1 "general_operand" ""))
(use (match_dup 2))
- (clobber (reg:CC 33))])]
+ (clobber (reg:CC CC_REGNUM))])]
""
{
enum machine_mode dword_mode = word_mode == DImode ? TImode : DImode;
(const_int 0))
(use (match_dup 2))
(use (match_operand:TI 1 "register_operand" "d"))
- (clobber (reg:CC 33))]
+ (clobber (reg:CC CC_REGNUM))]
"TARGET_64BIT"
"mvcle\t%0,%1,0\;jo\t.-4"
- [(set_attr "op_type" "NN")
- (set_attr "type" "vs")
- (set_attr "length" "8")])
+ [(set_attr "length" "8")
+ (set_attr "type" "vs")])
(define_insn "*clrmem_long_31"
[(clobber (match_operand:DI 0 "register_operand" "=d"))
(const_int 0))
(use (match_dup 2))
(use (match_operand:DI 1 "register_operand" "d"))
- (clobber (reg:CC 33))]
+ (clobber (reg:CC CC_REGNUM))]
"!TARGET_64BIT"
"mvcle\t%0,%1,0\;jo\t.-4"
- [(set_attr "op_type" "NN")
- (set_attr "type" "vs")
- (set_attr "length" "8")])
+ [(set_attr "length" "8")
+ (set_attr "type" "vs")])
;
; cmpmemM instruction pattern(s).
;
-(define_expand "cmpmemdi"
- [(set (match_operand:DI 0 "register_operand" "")
- (compare:DI (match_operand:BLK 1 "memory_operand" "")
- (match_operand:BLK 2 "memory_operand" "") ) )
- (use (match_operand:DI 3 "general_operand" ""))
- (use (match_operand:DI 4 "" ""))]
- "TARGET_64BIT"
- "s390_expand_cmpmem (operands[0], operands[1],
- operands[2], operands[3]); DONE;")
-
(define_expand "cmpmemsi"
[(set (match_operand:SI 0 "register_operand" "")
(compare:SI (match_operand:BLK 1 "memory_operand" "")
(define_expand "cmpmem_short"
[(parallel
- [(set (reg:CCS 33)
- (compare:CCS (match_operand:BLK 0 "memory_operand" "")
+ [(set (reg:CCU CC_REGNUM)
+ (compare:CCU (match_operand:BLK 0 "memory_operand" "")
(match_operand:BLK 1 "memory_operand" "")))
(use (match_operand 2 "nonmemory_operand" ""))
+ (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
(clobber (match_dup 3))])]
""
"operands[3] = gen_rtx_SCRATCH (Pmode);")
(define_insn "*cmpmem_short"
- [(set (reg:CCS 33)
- (compare:CCS (match_operand:BLK 0 "memory_operand" "=Q,Q")
- (match_operand:BLK 1 "memory_operand" "Q,Q")))
- (use (match_operand 2 "nonmemory_operand" "n,a"))
- (clobber (match_scratch 3 "=X,&a"))]
+ [(set (reg:CCU CC_REGNUM)
+ (compare:CCU (match_operand:BLK 0 "memory_operand" "Q,Q,Q")
+ (match_operand:BLK 1 "memory_operand" "Q,Q,Q")))
+ (use (match_operand 2 "nonmemory_operand" "n,a,a"))
+ (use (match_operand 3 "immediate_operand" "X,R,X"))
+ (clobber (match_scratch 4 "=X,X,&a"))]
"(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode)
- && GET_MODE (operands[3]) == Pmode"
-{
- switch (which_alternative)
- {
- case 0:
- return "clc\t%O0(%b2+1,%R0),%1";
+ && GET_MODE (operands[4]) == Pmode"
+ "#"
+ [(set_attr "type" "cs")])
- case 1:
- output_asm_insn ("bras\t%3,.+10", operands);
- output_asm_insn ("clc\t%O0(1,%R0),%1", operands);
- return "ex\t%2,0(%3)";
+(define_split
+ [(set (reg:CCU CC_REGNUM)
+ (compare:CCU (match_operand:BLK 0 "memory_operand" "")
+ (match_operand:BLK 1 "memory_operand" "")))
+ (use (match_operand 2 "const_int_operand" ""))
+ (use (match_operand 3 "immediate_operand" ""))
+ (clobber (scratch))]
+ "reload_completed"
+ [(parallel
+ [(set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
+ (use (match_dup 2))])]
+ "operands[2] = GEN_INT ((INTVAL (operands[2]) & 0xff) + 1);")
- default:
- abort ();
- }
-}
- [(set_attr "op_type" "SS,NN")
- (set_attr "type" "cs,cs")
- (set_attr "atype" "*,agen")
- (set_attr "length" "*,14")])
+(define_split
+ [(set (reg:CCU CC_REGNUM)
+ (compare:CCU (match_operand:BLK 0 "memory_operand" "")
+ (match_operand:BLK 1 "memory_operand" "")))
+ (use (match_operand 2 "register_operand" ""))
+ (use (match_operand 3 "memory_operand" ""))
+ (clobber (scratch))]
+ "reload_completed"
+ [(parallel
+ [(unspec [(match_dup 2) (match_dup 3)
+ (const_int 0)] UNSPEC_EXECUTE)
+ (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
+ (use (const_int 1))])]
+ "")
+
+(define_split
+ [(set (reg:CCU CC_REGNUM)
+ (compare:CCU (match_operand:BLK 0 "memory_operand" "")
+ (match_operand:BLK 1 "memory_operand" "")))
+ (use (match_operand 2 "register_operand" ""))
+ (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
+ (clobber (match_operand 3 "register_operand" ""))]
+ "reload_completed && TARGET_CPU_ZARCH"
+ [(set (match_dup 3) (label_ref (match_dup 4)))
+ (parallel
+ [(unspec [(match_dup 2) (mem:BLK (match_dup 3))
+ (label_ref (match_dup 4))] UNSPEC_EXECUTE)
+ (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
+ (use (const_int 1))])]
+ "operands[4] = gen_label_rtx ();")
; Compare a block of arbitrary length.
[(parallel
[(clobber (match_dup 2))
(clobber (match_dup 3))
- (set (reg:CCS 33)
- (compare:CCS (match_operand:BLK 0 "memory_operand" "")
+ (set (reg:CCU CC_REGNUM)
+ (compare:CCU (match_operand:BLK 0 "memory_operand" "")
(match_operand:BLK 1 "memory_operand" "")))
(use (match_operand 2 "general_operand" ""))
(use (match_dup 3))])]
(define_insn "*cmpmem_long_64"
[(clobber (match_operand:TI 0 "register_operand" "=d"))
(clobber (match_operand:TI 1 "register_operand" "=d"))
- (set (reg:CCS 33)
- (compare:CCS (mem:BLK (subreg:DI (match_operand:TI 2 "register_operand" "0") 0))
+ (set (reg:CCU CC_REGNUM)
+ (compare:CCU (mem:BLK (subreg:DI (match_operand:TI 2 "register_operand" "0") 0))
(mem:BLK (subreg:DI (match_operand:TI 3 "register_operand" "1") 0))))
(use (match_dup 2))
(use (match_dup 3))]
"TARGET_64BIT"
"clcle\t%0,%1,0\;jo\t.-4"
- [(set_attr "op_type" "NN")
- (set_attr "type" "vs")
- (set_attr "length" "8")])
+ [(set_attr "length" "8")
+ (set_attr "type" "vs")])
(define_insn "*cmpmem_long_31"
[(clobber (match_operand:DI 0 "register_operand" "=d"))
(clobber (match_operand:DI 1 "register_operand" "=d"))
- (set (reg:CCS 33)
- (compare:CCS (mem:BLK (subreg:SI (match_operand:DI 2 "register_operand" "0") 0))
+ (set (reg:CCU CC_REGNUM)
+ (compare:CCU (mem:BLK (subreg:SI (match_operand:DI 2 "register_operand" "0") 0))
(mem:BLK (subreg:SI (match_operand:DI 3 "register_operand" "1") 0))))
(use (match_dup 2))
(use (match_dup 3))]
"!TARGET_64BIT"
"clcle\t%0,%1,0\;jo\t.-4"
- [(set_attr "op_type" "NN")
- (set_attr "type" "vs")
- (set_attr "length" "8")])
+ [(set_attr "length" "8")
+ (set_attr "type" "vs")])
-; Convert condition code to integer in range (-1, 0, 1)
+; Convert CCUmode condition code to integer.
+; Result is zero if EQ, positive if LTU, negative if GTU.
-(define_insn "cmpint_si"
+(define_insn_and_split "cmpint"
[(set (match_operand:SI 0 "register_operand" "=d")
- (compare:SI (reg:CCS 33) (const_int 0)))]
+ (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
+ UNSPEC_CMPINT))
+ (clobber (reg:CC CC_REGNUM))]
""
+ "#"
+ "reload_completed"
+ [(set (match_dup 0) (ashift:SI (match_dup 0) (const_int 2)))
+ (parallel
+ [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 30)))
+ (clobber (reg:CC CC_REGNUM))])])
+
+(define_insn_and_split "*cmpint_cc"
+ [(set (reg CC_REGNUM)
+ (compare (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
+ UNSPEC_CMPINT)
+ (const_int 0)))
+ (set (match_operand:SI 0 "register_operand" "=d")
+ (unspec:SI [(match_dup 1)] UNSPEC_CMPINT))]
+ "s390_match_ccmode (insn, CCSmode)"
+ "#"
+ "&& reload_completed"
+ [(set (match_dup 0) (ashift:SI (match_dup 0) (const_int 2)))
+ (parallel
+ [(set (match_dup 2) (match_dup 3))
+ (set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 30)))])]
{
- output_asm_insn ("lhi\t%0,1", operands);
- output_asm_insn ("jh\t.+12", operands);
- output_asm_insn ("jl\t.+6", operands);
- output_asm_insn ("sr\t%0,%0", operands);
- return "lcr\t%0,%0";
-}
- [(set_attr "op_type" "NN")
- (set_attr "length" "16")
- (set_attr "type" "other")])
+ rtx result = gen_rtx_ASHIFTRT (SImode, operands[0], GEN_INT (30));
+ operands[2] = SET_DEST (XVECEXP (PATTERN (curr_insn), 0, 0));
+ operands[3] = gen_rtx_COMPARE (GET_MODE (operands[2]), result, const0_rtx);
+})
-(define_insn "cmpint_di"
+(define_insn_and_split "*cmpint_sign"
[(set (match_operand:DI 0 "register_operand" "=d")
- (compare:DI (reg:CCS 33) (const_int 0)))]
+ (sign_extend:DI (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
+ UNSPEC_CMPINT)))
+ (clobber (reg:CC CC_REGNUM))]
"TARGET_64BIT"
+ "#"
+ "&& reload_completed"
+ [(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34)))
+ (parallel
+ [(set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 62)))
+ (clobber (reg:CC CC_REGNUM))])])
+
+(define_insn_and_split "*cmpint_sign_cc"
+ [(set (reg CC_REGNUM)
+ (compare (ashiftrt:DI (ashift:DI (subreg:DI
+ (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
+ UNSPEC_CMPINT) 0)
+ (const_int 32)) (const_int 32))
+ (const_int 0)))
+ (set (match_operand:DI 0 "register_operand" "=d")
+ (sign_extend:DI (unspec:SI [(match_dup 1)] UNSPEC_CMPINT)))]
+ "s390_match_ccmode (insn, CCSmode) && TARGET_64BIT"
+ "#"
+ "&& reload_completed"
+ [(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34)))
+ (parallel
+ [(set (match_dup 2) (match_dup 3))
+ (set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 62)))])]
{
- output_asm_insn ("lghi\t%0,1", operands);
- output_asm_insn ("jh\t.+16", operands);
- output_asm_insn ("jl\t.+8", operands);
- output_asm_insn ("sgr\t%0,%0", operands);
- return "lcgr\t%0,%0";
-}
- [(set_attr "op_type" "NN")
- (set_attr "length" "20")
- (set_attr "type" "other")])
+ rtx result = gen_rtx_ASHIFTRT (DImode, operands[0], GEN_INT (62));
+ operands[2] = SET_DEST (XVECEXP (PATTERN (curr_insn), 0, 0));
+ operands[3] = gen_rtx_COMPARE (GET_MODE (operands[2]), result, const0_rtx);
+})
;;
;;- Conversion instructions.
;;
-(define_insn "*sethighqisi"
- [(set (match_operand:SI 0 "register_operand" "=d,d")
- (unspec:SI [(match_operand:QI 1 "s_operand" "Q,S")] UNSPEC_SETHIGH))
- (clobber (reg:CC 33))]
- ""
- "@
- icm\t%0,8,%1
- icmy\t%0,8,%1"
- [(set_attr "op_type" "RS,RSY")])
-(define_insn "*sethighhisi"
+(define_insn "*sethigh<mode>si"
[(set (match_operand:SI 0 "register_operand" "=d,d")
- (unspec:SI [(match_operand:HI 1 "s_operand" "Q,S")] UNSPEC_SETHIGH))
- (clobber (reg:CC 33))]
+ (unspec:SI [(match_operand:HQI 1 "s_operand" "Q,S")] UNSPEC_SETHIGH))
+ (clobber (reg:CC CC_REGNUM))]
""
"@
- icm\t%0,12,%1
- icmy\t%0,12,%1"
+ icm\t%0,<icm_hi>,%S1
+ icmy\t%0,<icm_hi>,%S1"
[(set_attr "op_type" "RS,RSY")])
(define_insn "*sethighqidi_64"
[(set (match_operand:DI 0 "register_operand" "=d")
(unspec:DI [(match_operand:QI 1 "s_operand" "QS")] UNSPEC_SETHIGH))
- (clobber (reg:CC 33))]
+ (clobber (reg:CC CC_REGNUM))]
"TARGET_64BIT"
- "icmh\t%0,8,%1"
+ "icmh\t%0,8,%S1"
[(set_attr "op_type" "RSY")])
(define_insn "*sethighqidi_31"
[(set (match_operand:DI 0 "register_operand" "=d,d")
(unspec:DI [(match_operand:QI 1 "s_operand" "Q,S")] UNSPEC_SETHIGH))
- (clobber (reg:CC 33))]
+ (clobber (reg:CC CC_REGNUM))]
"!TARGET_64BIT"
"@
- icm\t%0,8,%1
- icmy\t%0,8,%1"
+ icm\t%0,8,%S1
+ icmy\t%0,8,%S1"
[(set_attr "op_type" "RS,RSY")])
(define_insn_and_split "*extractqi"
(zero_extract:SI (match_operand:QI 1 "s_operand" "Q")
(match_operand 2 "const_int_operand" "n")
(const_int 0)))
- (clobber (reg:CC 33))]
+ (clobber (reg:CC CC_REGNUM))]
"!TARGET_64BIT
&& INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 8"
"#"
"&& reload_completed"
[(parallel
[(set (match_dup 0) (unspec:SI [(match_dup 1)] UNSPEC_SETHIGH))
- (clobber (reg:CC 33))])
+ (clobber (reg:CC CC_REGNUM))])
(set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 2)))]
{
operands[2] = GEN_INT (32 - INTVAL (operands[2]));
operands[1] = change_address (operands[1], QImode, 0);
-}
- [(set_attr "atype" "agen")])
+})
(define_insn_and_split "*extracthi"
[(set (match_operand:SI 0 "register_operand" "=d")
(zero_extract:SI (match_operand:QI 1 "s_operand" "Q")
(match_operand 2 "const_int_operand" "n")
(const_int 0)))
- (clobber (reg:CC 33))]
+ (clobber (reg:CC CC_REGNUM))]
"!TARGET_64BIT
&& INTVAL (operands[2]) >= 8 && INTVAL (operands[2]) < 16"
"#"
"&& reload_completed"
[(parallel
[(set (match_dup 0) (unspec:SI [(match_dup 1)] UNSPEC_SETHIGH))
- (clobber (reg:CC 33))])
+ (clobber (reg:CC CC_REGNUM))])
(set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 2)))]
{
operands[2] = GEN_INT (32 - INTVAL (operands[2]));
operands[1] = change_address (operands[1], HImode, 0);
-}
- [(set_attr "atype" "agen")])
+})
;
; extendsidi2 instruction pattern(s).
[(set_attr "op_type" "RRE,RXY")])
;
-; extendhidi2 instruction pattern(s).
+; extend(hi|qi)di2 instruction pattern(s).
;
-(define_expand "extendhidi2"
+(define_expand "extend<mode>di2"
[(set (match_operand:DI 0 "register_operand" "")
- (sign_extend:DI (match_operand:HI 1 "register_operand" "")))]
+ (sign_extend:DI (match_operand:HQI 1 "register_operand" "")))]
""
"
{
if (!TARGET_64BIT)
{
rtx tmp = gen_reg_rtx (SImode);
- emit_insn (gen_extendhisi2 (tmp, operands[1]));
+ emit_insn (gen_extend<mode>si2 (tmp, operands[1]));
emit_insn (gen_extendsidi2 (operands[0], tmp));
DONE;
}
else
{
+ rtx bitcount = GEN_INT (GET_MODE_BITSIZE (DImode) -
+ GET_MODE_BITSIZE (<MODE>mode));
operands[1] = gen_lowpart (DImode, operands[1]);
- emit_insn (gen_ashldi3 (operands[0], operands[1], GEN_INT (48)));
- emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (48)));
+ emit_insn (gen_ashldi3 (operands[0], operands[1], bitcount));
+ emit_insn (gen_ashrdi3 (operands[0], operands[0], bitcount));
DONE;
}
}
"lgh\t%0,%1"
[(set_attr "op_type" "RXY")])
-;
-; extendqidi2 instruction pattern(s).
-;
-
-(define_expand "extendqidi2"
- [(set (match_operand:DI 0 "register_operand" "")
- (sign_extend:DI (match_operand:QI 1 "register_operand" "")))]
- ""
- "
-{
- if (!TARGET_64BIT)
- {
- rtx tmp = gen_reg_rtx (SImode);
- emit_insn (gen_extendqisi2 (tmp, operands[1]));
- emit_insn (gen_extendsidi2 (operands[0], tmp));
- DONE;
- }
- else
- {
- operands[1] = gen_lowpart (DImode, operands[1]);
- emit_insn (gen_ashldi3 (operands[0], operands[1], GEN_INT (56)));
- emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (56)));
- DONE;
- }
-}
-")
-
(define_insn "*extendqidi2"
[(set (match_operand:DI 0 "register_operand" "=d")
(sign_extend:DI (match_operand:QI 1 "memory_operand" "m")))]
(define_insn_and_split "*extendqidi2_short_displ"
[(set (match_operand:DI 0 "register_operand" "=d")
(sign_extend:DI (match_operand:QI 1 "s_operand" "Q")))
- (clobber (reg:CC 33))]
+ (clobber (reg:CC CC_REGNUM))]
"TARGET_64BIT && !TARGET_LONG_DISPLACEMENT"
"#"
"&& reload_completed"
[(parallel
[(set (match_dup 0) (unspec:DI [(match_dup 1)] UNSPEC_SETHIGH))
- (clobber (reg:CC 33))])
+ (clobber (reg:CC CC_REGNUM))])
(parallel
[(set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 56)))
- (clobber (reg:CC 33))])]
+ (clobber (reg:CC CC_REGNUM))])]
"")
;
-; extendhisi2 instruction pattern(s).
+; extend(hi|qi)si2 instruction pattern(s).
;
-(define_expand "extendhisi2"
+(define_expand "extend<mode>si2"
[(set (match_operand:SI 0 "register_operand" "")
- (sign_extend:SI (match_operand:HI 1 "register_operand" "")))]
+ (sign_extend:SI (match_operand:HQI 1 "register_operand" "")))]
""
"
{
+ rtx bitcount = GEN_INT (GET_MODE_BITSIZE(SImode) -
+ GET_MODE_BITSIZE(<MODE>mode));
operands[1] = gen_lowpart (SImode, operands[1]);
- emit_insn (gen_ashlsi3 (operands[0], operands[1], GEN_INT (16)));
- emit_insn (gen_ashrsi3 (operands[0], operands[0], GEN_INT (16)));
+ emit_insn (gen_ashlsi3 (operands[0], operands[1], bitcount));
+ emit_insn (gen_ashrsi3 (operands[0], operands[0], bitcount));
DONE;
}
")
lhy\t%0,%1"
[(set_attr "op_type" "RX,RXY")])
-;
-; extendqisi2 instruction pattern(s).
-;
-
-(define_expand "extendqisi2"
- [(set (match_operand:SI 0 "register_operand" "")
- (sign_extend:SI (match_operand:QI 1 "register_operand" "")))]
- ""
- "
-{
- operands[1] = gen_lowpart (SImode, operands[1]);
- emit_insn (gen_ashlsi3 (operands[0], operands[1], GEN_INT (24)));
- emit_insn (gen_ashrsi3 (operands[0], operands[0], GEN_INT (24)));
- DONE;
-}
-")
-
(define_insn "*extendqisi2"
[(set (match_operand:SI 0 "register_operand" "=d")
(sign_extend:SI (match_operand:QI 1 "memory_operand" "m")))]
(define_insn_and_split "*extendqisi2_short_displ"
[(set (match_operand:SI 0 "register_operand" "=d")
(sign_extend:SI (match_operand:QI 1 "s_operand" "Q")))
- (clobber (reg:CC 33))]
+ (clobber (reg:CC CC_REGNUM))]
"!TARGET_LONG_DISPLACEMENT"
"#"
"&& reload_completed"
[(parallel
[(set (match_dup 0) (unspec:SI [(match_dup 1)] UNSPEC_SETHIGH))
- (clobber (reg:CC 33))])
+ (clobber (reg:CC CC_REGNUM))])
(parallel
[(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 24)))
- (clobber (reg:CC 33))])]
+ (clobber (reg:CC CC_REGNUM))])]
"")
;
[(set_attr "op_type" "RRE,RXY")])
;
-; zero_extendhidi2 instruction pattern(s).
+; zero_extend(hi|qi)di2 instruction pattern(s).
;
-(define_expand "zero_extendhidi2"
+(define_expand "zero_extend<mode>di2"
[(set (match_operand:DI 0 "register_operand" "")
- (zero_extend:DI (match_operand:HI 1 "register_operand" "")))]
+ (zero_extend:DI (match_operand:HQI 1 "register_operand" "")))]
""
"
{
if (!TARGET_64BIT)
{
rtx tmp = gen_reg_rtx (SImode);
- emit_insn (gen_zero_extendhisi2 (tmp, operands[1]));
+ emit_insn (gen_zero_extend<mode>si2 (tmp, operands[1]));
emit_insn (gen_zero_extendsidi2 (operands[0], tmp));
DONE;
}
else
{
+ rtx bitcount = GEN_INT (GET_MODE_BITSIZE(DImode) -
+ GET_MODE_BITSIZE(<MODE>mode));
operands[1] = gen_lowpart (DImode, operands[1]);
- emit_insn (gen_ashldi3 (operands[0], operands[1], GEN_INT (48)));
- emit_insn (gen_lshrdi3 (operands[0], operands[0], GEN_INT (48)));
+ emit_insn (gen_ashldi3 (operands[0], operands[1], bitcount));
+ emit_insn (gen_lshrdi3 (operands[0], operands[0], bitcount));
DONE;
}
}
")
-(define_insn "*zero_extendhidi2"
+(define_insn "*zero_extend<mode>di2"
[(set (match_operand:DI 0 "register_operand" "=d")
- (zero_extend:DI (match_operand:HI 1 "memory_operand" "m")))]
+ (zero_extend:DI (match_operand:HQI 1 "memory_operand" "m")))]
"TARGET_64BIT"
- "llgh\t%0,%1"
+ "llg<hc>\t%0,%1"
[(set_attr "op_type" "RXY")])
;
; LLGT-type instructions (zero-extend from 31 bit to 64 bit).
;
+(define_insn "*llgt_sidi"
+ [(set (match_operand:DI 0 "register_operand" "=d")
+ (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "m") 0)
+ (const_int 2147483647)))]
+ "TARGET_64BIT"
+ "llgt\t%0,%1"
+ [(set_attr "op_type" "RXE")])
+
+(define_insn_and_split "*llgt_sidi_split"
+ [(set (match_operand:DI 0 "register_operand" "=d")
+ (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "m") 0)
+ (const_int 2147483647)))
+ (clobber (reg:CC CC_REGNUM))]
+ "TARGET_64BIT"
+ "#"
+ "&& reload_completed"
+ [(set (match_dup 0)
+ (and:DI (subreg:DI (match_dup 1) 0)
+ (const_int 2147483647)))]
+ "")
+
(define_insn "*llgt_sisi"
[(set (match_operand:SI 0 "register_operand" "=d,d")
(and:SI (match_operand:SI 1 "nonimmediate_operand" "d,m")
llgt\t%0,%1"
[(set_attr "op_type" "RRE,RXE")])
-(define_split
- [(set (match_operand:SI 0 "register_operand" "")
- (and:SI (match_operand:SI 1 "nonimmediate_operand" "")
- (const_int 2147483647)))
- (clobber (reg:CC 33))]
- "TARGET_64BIT && reload_completed"
- [(set (match_dup 0)
- (and:SI (match_dup 1)
- (const_int 2147483647)))]
- "")
-
(define_insn "*llgt_didi"
[(set (match_operand:DI 0 "register_operand" "=d,d")
(and:DI (match_operand:DI 1 "nonimmediate_operand" "d,o")
[(set_attr "op_type" "RRE,RXE")])
(define_split
- [(set (match_operand:DI 0 "register_operand" "")
- (and:DI (match_operand:DI 1 "nonimmediate_operand" "")
- (const_int 2147483647)))
- (clobber (reg:CC 33))]
+ [(set (match_operand:GPR 0 "register_operand" "")
+ (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "")
+ (const_int 2147483647)))
+ (clobber (reg:CC CC_REGNUM))]
"TARGET_64BIT && reload_completed"
[(set (match_dup 0)
- (and:DI (match_dup 1)
- (const_int 2147483647)))]
+ (and:GPR (match_dup 1)
+ (const_int 2147483647)))]
"")
-(define_insn "*llgt_sidi"
- [(set (match_operand:DI 0 "register_operand" "=d")
- (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "m") 0)
- (const_int 2147483647)))]
- "TARGET_64BIT"
- "llgt\t%0,%1"
- [(set_attr "op_type" "RXE")])
-
-(define_insn_and_split "*llgt_sidi_split"
- [(set (match_operand:DI 0 "register_operand" "=d")
- (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "m") 0)
- (const_int 2147483647)))
- (clobber (reg:CC 33))]
- "TARGET_64BIT"
- "#"
- "&& reload_completed"
- [(set (match_dup 0)
- (and:DI (subreg:DI (match_dup 1) 0)
- (const_int 2147483647)))]
- "")
-
-;
-; zero_extendqidi2 instruction pattern(s)
-;
-
-(define_expand "zero_extendqidi2"
- [(set (match_operand:DI 0 "register_operand" "")
- (zero_extend:DI (match_operand:QI 1 "register_operand" "")))]
- ""
- "
-{
- if (!TARGET_64BIT)
- {
- rtx tmp = gen_reg_rtx (SImode);
- emit_insn (gen_zero_extendqisi2 (tmp, operands[1]));
- emit_insn (gen_zero_extendsidi2 (operands[0], tmp));
- DONE;
- }
- else
- {
- operands[1] = gen_lowpart (DImode, operands[1]);
- emit_insn (gen_ashldi3 (operands[0], operands[1], GEN_INT (56)));
- emit_insn (gen_lshrdi3 (operands[0], operands[0], GEN_INT (56)));
- DONE;
- }
-}
-")
-
-(define_insn "*zero_extendqidi2"
- [(set (match_operand:DI 0 "register_operand" "=d")
- (zero_extend:DI (match_operand:QI 1 "memory_operand" "m")))]
- "TARGET_64BIT"
- "llgc\t%0,%1"
- [(set_attr "op_type" "RXY")])
-
;
-; zero_extendhisi2 instruction pattern(s).
+; zero_extend(hi|qi)si2 instruction pattern(s).
;
-(define_expand "zero_extendhisi2"
+(define_expand "zero_extend<mode>si2"
[(set (match_operand:SI 0 "register_operand" "")
- (zero_extend:SI (match_operand:HI 1 "register_operand" "")))]
+ (zero_extend:SI (match_operand:HQI 1 "register_operand" "")))]
""
"
{
operands[1] = gen_lowpart (SImode, operands[1]);
- emit_insn (gen_andsi3 (operands[0], operands[1], GEN_INT (0xffff)));
+ emit_insn (gen_andsi3 (operands[0], operands[1],
+ GEN_INT ((1 << GET_MODE_BITSIZE(<MODE>mode)) - 1)));
DONE;
}
")
-(define_insn "*zero_extendhisi2_64"
+(define_insn "*zero_extend<mode>si2_64"
[(set (match_operand:SI 0 "register_operand" "=d")
- (zero_extend:SI (match_operand:HI 1 "memory_operand" "m")))]
- "TARGET_64BIT"
- "llgh\t%0,%1"
+ (zero_extend:SI (match_operand:HQI 1 "memory_operand" "m")))]
+ "TARGET_ZARCH"
+ "llg<hc>\t%0,%1"
[(set_attr "op_type" "RXY")])
(define_insn_and_split "*zero_extendhisi2_31"
[(set (match_operand:SI 0 "register_operand" "=&d")
(zero_extend:SI (match_operand:HI 1 "s_operand" "QS")))
- (clobber (reg:CC 33))]
- "!TARGET_64BIT"
+ (clobber (reg:CC CC_REGNUM))]
+ "!TARGET_ZARCH"
"#"
"&& reload_completed"
[(set (match_dup 0) (const_int 0))
(parallel
[(set (strict_low_part (match_dup 2)) (match_dup 1))
- (clobber (reg:CC 33))])]
- "operands[2] = gen_lowpart (HImode, operands[0]);"
- [(set_attr "atype" "agen")])
-
-;
-; zero_extendqisi2 instruction pattern(s).
-;
-
-(define_expand "zero_extendqisi2"
- [(set (match_operand:SI 0 "register_operand" "")
- (zero_extend:SI (match_operand:QI 1 "register_operand" "")))]
- ""
- "
-{
- operands[1] = gen_lowpart (SImode, operands[1]);
- emit_insn (gen_andsi3 (operands[0], operands[1], GEN_INT (0xff)));
- DONE;
-}
-")
-
-(define_insn "*zero_extendqisi2_64"
- [(set (match_operand:SI 0 "register_operand" "=d")
- (zero_extend:SI (match_operand:QI 1 "memory_operand" "m")))]
- "TARGET_ZARCH"
- "llgc\t%0,%1"
- [(set_attr "op_type" "RXY")])
+ (clobber (reg:CC CC_REGNUM))])]
+ "operands[2] = gen_lowpart (HImode, operands[0]);")
(define_insn_and_split "*zero_extendqisi2_31"
[(set (match_operand:SI 0 "register_operand" "=&d")
"&& reload_completed"
[(set (match_dup 0) (const_int 0))
(set (strict_low_part (match_dup 2)) (match_dup 1))]
- "operands[2] = gen_lowpart (QImode, operands[0]);"
- [(set_attr "atype" "agen")])
+ "operands[2] = gen_lowpart (QImode, operands[0]);")
;
; zero_extendqihi2 instruction pattern(s).
"&& reload_completed"
[(set (match_dup 0) (const_int 0))
(set (strict_low_part (match_dup 2)) (match_dup 1))]
- "operands[2] = gen_lowpart (QImode, operands[0]);"
- [(set_attr "atype" "agen")])
+ "operands[2] = gen_lowpart (QImode, operands[0]);")
;
-; fixuns_truncdfdi2 and fix_truncdfsi2 instruction pattern(s).
+; fixuns_trunc(sf|df)(si|di)2 and fix_trunc(sf|df)(si|di)2 instruction pattern(s).
;
-(define_expand "fixuns_truncdfdi2"
- [(set (match_operand:DI 0 "register_operand" "")
- (unsigned_fix:DI (match_operand:DF 1 "register_operand" "")))]
- "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
+(define_expand "fixuns_trunc<FPR:mode><GPR:mode>2"
+ [(set (match_operand:GPR 0 "register_operand" "")
+ (unsigned_fix:GPR (match_operand:FPR 1 "register_operand" "")))]
+ "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
{
rtx label1 = gen_label_rtx ();
rtx label2 = gen_label_rtx ();
- rtx temp = gen_reg_rtx (DFmode);
- operands[1] = force_reg (DFmode, operands[1]);
-
- emit_insn (gen_cmpdf (operands[1],
- CONST_DOUBLE_FROM_REAL_VALUE (
- REAL_VALUE_ATOF ("9223372036854775808.0", DFmode), DFmode)));
+ rtx temp = gen_reg_rtx (<FPR:MODE>mode);
+ REAL_VALUE_TYPE cmp, sub;
+
+ operands[1] = force_reg (<FPR:MODE>mode, operands[1]);
+ real_2expN (&cmp, GET_MODE_BITSIZE(<GPR:MODE>mode) - 1);
+ real_2expN (&sub, GET_MODE_BITSIZE(<GPR:MODE>mode));
+
+ emit_insn (gen_cmp<FPR:mode> (operands[1],
+ CONST_DOUBLE_FROM_REAL_VALUE (cmp, <FPR:MODE>mode)));
emit_jump_insn (gen_blt (label1));
- emit_insn (gen_subdf3 (temp, operands[1],
- CONST_DOUBLE_FROM_REAL_VALUE (
- REAL_VALUE_ATOF ("18446744073709551616.0", DFmode), DFmode)));
- emit_insn (gen_fix_truncdfdi2_ieee (operands[0], temp, GEN_INT(7)));
+ emit_insn (gen_sub<FPR:mode>3 (temp, operands[1],
+ CONST_DOUBLE_FROM_REAL_VALUE (sub, <FPR:MODE>mode)));
+ emit_insn (gen_fix_trunc<FPR:mode><GPR:mode>2_ieee (operands[0], temp,
+ GEN_INT(7)));
emit_jump (label2);
emit_label (label1);
- emit_insn (gen_fix_truncdfdi2_ieee (operands[0], operands[1], GEN_INT(5)));
+ emit_insn (gen_fix_trunc<FPR:mode><GPR:mode>2_ieee (operands[0],
+ operands[1], GEN_INT(5)));
emit_label (label2);
DONE;
})
-(define_expand "fix_truncdfdi2"
+(define_expand "fix_trunc<FPR:mode>di2"
[(set (match_operand:DI 0 "register_operand" "")
- (fix:DI (match_operand:DF 1 "nonimmediate_operand" "")))]
+ (fix:DI (match_operand:FPR 1 "nonimmediate_operand" "")))]
"TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
{
- operands[1] = force_reg (DFmode, operands[1]);
- emit_insn (gen_fix_truncdfdi2_ieee (operands[0], operands[1], GEN_INT(5)));
+ operands[1] = force_reg (<FPR:MODE>mode, operands[1]);
+ emit_insn (gen_fix_trunc<FPR:mode>di2_ieee (operands[0], operands[1],
+ GEN_INT(5)));
DONE;
})
-(define_insn "fix_truncdfdi2_ieee"
- [(set (match_operand:DI 0 "register_operand" "=d")
- (fix:DI (match_operand:DF 1 "register_operand" "f")))
- (unspec:DI [(match_operand:DI 2 "immediate_operand" "K")] UNSPEC_ROUND)
- (clobber (reg:CC 33))]
- "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
- "cgdbr\t%0,%h2,%1"
+(define_insn "fix_trunc<FPR:mode><GPR:mode>2_ieee"
+ [(set (match_operand:GPR 0 "register_operand" "=d")
+ (fix:GPR (match_operand:FPR 1 "register_operand" "f")))
+ (unspec:GPR [(match_operand:GPR 2 "immediate_operand" "K")] UNSPEC_ROUND)
+ (clobber (reg:CC CC_REGNUM))]
+ "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
+ "c<GPR:gf><FPR:de>br\t%0,%h2,%1"
[(set_attr "op_type" "RRE")
(set_attr "type" "ftoi")])
;
-; fixuns_truncdfsi2 and fix_truncdfsi2 instruction pattern(s).
+; fix_truncdfsi2 instruction pattern(s).
;
-(define_expand "fixuns_truncdfsi2"
- [(set (match_operand:SI 0 "register_operand" "")
- (unsigned_fix:SI (match_operand:DF 1 "register_operand" "")))]
- "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
-{
- rtx label1 = gen_label_rtx ();
- rtx label2 = gen_label_rtx ();
- rtx temp = gen_reg_rtx (DFmode);
-
- operands[1] = force_reg (DFmode,operands[1]);
- emit_insn (gen_cmpdf (operands[1],
- CONST_DOUBLE_FROM_REAL_VALUE (
- REAL_VALUE_ATOF ("2147483648.0", DFmode), DFmode)));
- emit_jump_insn (gen_blt (label1));
- emit_insn (gen_subdf3 (temp, operands[1],
- CONST_DOUBLE_FROM_REAL_VALUE (
- REAL_VALUE_ATOF ("4294967296.0", DFmode), DFmode)));
- emit_insn (gen_fix_truncdfsi2_ieee (operands[0], temp, GEN_INT (7)));
- emit_jump (label2);
-
- emit_label (label1);
- emit_insn (gen_fix_truncdfsi2_ieee (operands[0], operands[1], GEN_INT (5)));
- emit_label (label2);
- DONE;
-})
-
(define_expand "fix_truncdfsi2"
[(set (match_operand:SI 0 "register_operand" "")
(fix:SI (match_operand:DF 1 "nonimmediate_operand" "")))]
DONE;
})
-(define_insn "fix_truncdfsi2_ieee"
- [(set (match_operand:SI 0 "register_operand" "=d")
- (fix:SI (match_operand:DF 1 "register_operand" "f")))
- (unspec:SI [(match_operand:SI 2 "immediate_operand" "K")] UNSPEC_ROUND)
- (clobber (reg:CC 33))]
- "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
- "cfdbr\t%0,%h2,%1"
- [(set_attr "op_type" "RRE")
- (set_attr "type" "other" )])
-
(define_insn "fix_truncdfsi2_ibm"
[(set (match_operand:SI 0 "register_operand" "=d")
(fix:SI (match_operand:DF 1 "nonimmediate_operand" "+f")))
(use (match_operand:DI 2 "immediate_operand" "m"))
(use (match_operand:DI 3 "immediate_operand" "m"))
(use (match_operand:BLK 4 "memory_operand" "m"))
- (clobber (reg:CC 33))]
+ (clobber (reg:CC CC_REGNUM))]
"TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
{
output_asm_insn ("sd\t%1,%2", operands);
output_asm_insn ("xi\t%N4,128", operands);
return "l\t%0,%N4";
}
- [(set_attr "op_type" "NN")
- (set_attr "type" "ftoi")
- (set_attr "atype" "agen")
- (set_attr "length" "20")])
+ [(set_attr "length" "20")])
;
-; fixuns_truncsfdi2 and fix_truncsfdi2 instruction pattern(s).
+; fix_truncsfsi2 instruction pattern(s).
;
-(define_expand "fixuns_truncsfdi2"
- [(set (match_operand:DI 0 "register_operand" "")
- (unsigned_fix:DI (match_operand:SF 1 "register_operand" "")))]
- "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
-{
- rtx label1 = gen_label_rtx ();
- rtx label2 = gen_label_rtx ();
- rtx temp = gen_reg_rtx (SFmode);
-
- operands[1] = force_reg (SFmode, operands[1]);
- emit_insn (gen_cmpsf (operands[1],
- CONST_DOUBLE_FROM_REAL_VALUE (
- REAL_VALUE_ATOF ("9223372036854775808.0", SFmode), SFmode)));
- emit_jump_insn (gen_blt (label1));
-
- emit_insn (gen_subsf3 (temp, operands[1],
- CONST_DOUBLE_FROM_REAL_VALUE (
- REAL_VALUE_ATOF ("18446744073709551616.0", SFmode), SFmode)));
- emit_insn (gen_fix_truncsfdi2_ieee (operands[0], temp, GEN_INT(7)));
- emit_jump (label2);
-
- emit_label (label1);
- emit_insn (gen_fix_truncsfdi2_ieee (operands[0], operands[1], GEN_INT(5)));
- emit_label (label2);
- DONE;
-})
-
-(define_expand "fix_truncsfdi2"
- [(set (match_operand:DI 0 "register_operand" "")
- (fix:DI (match_operand:SF 1 "nonimmediate_operand" "")))]
- "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
-{
- operands[1] = force_reg (SFmode, operands[1]);
- emit_insn (gen_fix_truncsfdi2_ieee (operands[0], operands[1], GEN_INT(5)));
- DONE;
-})
-
-(define_insn "fix_truncsfdi2_ieee"
- [(set (match_operand:DI 0 "register_operand" "=d")
- (fix:DI (match_operand:SF 1 "register_operand" "f")))
- (unspec:DI [(match_operand:DI 2 "immediate_operand" "K")] UNSPEC_ROUND)
- (clobber (reg:CC 33))]
- "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
- "cgebr\t%0,%h2,%1"
- [(set_attr "op_type" "RRE")
- (set_attr "type" "ftoi")])
-
-;
-; fixuns_truncsfsi2 and fix_truncsfsi2 instruction pattern(s).
-;
-
-(define_expand "fixuns_truncsfsi2"
- [(set (match_operand:SI 0 "register_operand" "")
- (unsigned_fix:SI (match_operand:SF 1 "register_operand" "")))]
- "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
-{
- rtx label1 = gen_label_rtx ();
- rtx label2 = gen_label_rtx ();
- rtx temp = gen_reg_rtx (SFmode);
-
- operands[1] = force_reg (SFmode, operands[1]);
- emit_insn (gen_cmpsf (operands[1],
- CONST_DOUBLE_FROM_REAL_VALUE (
- REAL_VALUE_ATOF ("2147483648.0", SFmode), SFmode)));
- emit_jump_insn (gen_blt (label1));
- emit_insn (gen_subsf3 (temp, operands[1],
- CONST_DOUBLE_FROM_REAL_VALUE (
- REAL_VALUE_ATOF ("4294967296.0", SFmode), SFmode)));
- emit_insn (gen_fix_truncsfsi2_ieee (operands[0], temp, GEN_INT (7)));
- emit_jump (label2);
-
- emit_label (label1);
- emit_insn (gen_fix_truncsfsi2_ieee (operands[0], operands[1], GEN_INT (5)));
- emit_label (label2);
- DONE;
-})
-
(define_expand "fix_truncsfsi2"
[(set (match_operand:SI 0 "register_operand" "")
(fix:SI (match_operand:SF 1 "nonimmediate_operand" "")))]
DONE;
})
-(define_insn "fix_truncsfsi2_ieee"
- [(set (match_operand:SI 0 "register_operand" "=d")
- (fix:SI (match_operand:SF 1 "register_operand" "f")))
- (unspec:SI [(match_operand:SI 2 "immediate_operand" "K")] UNSPEC_ROUND)
- (clobber (reg:CC 33))]
- "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
- "cfebr\t%0,%h2,%1"
- [(set_attr "op_type" "RRE")
- (set_attr "type" "ftoi")])
-
;
-; floatdidf2 instruction pattern(s).
+; floatdi(df|sf)2 instruction pattern(s).
;
-(define_insn "floatdidf2"
- [(set (match_operand:DF 0 "register_operand" "=f")
- (float:DF (match_operand:DI 1 "register_operand" "d")))
- (clobber (reg:CC 33))]
+(define_insn "floatdi<mode>2"
+ [(set (match_operand:FPR 0 "register_operand" "=f")
+ (float:FPR (match_operand:DI 1 "register_operand" "d")))]
"TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
- "cdgbr\t%0,%1"
- [(set_attr "op_type" "RRE")
- (set_attr "type" "itof" )])
-
-;
-; floatdisf2 instruction pattern(s).
-;
-
-(define_insn "floatdisf2"
- [(set (match_operand:SF 0 "register_operand" "=f")
- (float:SF (match_operand:DI 1 "register_operand" "d")))
- (clobber (reg:CC 33))]
- "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
- "cegbr\t%0,%1"
+ "c<de>gbr\t%0,%1"
[(set_attr "op_type" "RRE")
(set_attr "type" "itof" )])
;
(define_expand "floatsidf2"
- [(parallel
- [(set (match_operand:DF 0 "register_operand" "")
- (float:DF (match_operand:SI 1 "register_operand" "")))
- (clobber (reg:CC 33))])]
+ [(set (match_operand:DF 0 "register_operand" "")
+ (float:DF (match_operand:SI 1 "register_operand" "")))]
"TARGET_HARD_FLOAT"
{
if (TARGET_IBM_FLOAT)
(define_insn "floatsidf2_ieee"
[(set (match_operand:DF 0 "register_operand" "=f")
- (float:DF (match_operand:SI 1 "register_operand" "d")))
- (clobber (reg:CC 33))]
+ (float:DF (match_operand:SI 1 "register_operand" "d")))]
"TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"cdfbr\t%0,%1"
[(set_attr "op_type" "RRE")
(float:DF (match_operand:SI 1 "register_operand" "d")))
(use (match_operand:DI 2 "immediate_operand" "m"))
(use (match_operand:BLK 3 "memory_operand" "m"))
- (clobber (reg:CC 33))]
+ (clobber (reg:CC CC_REGNUM))]
"TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
{
output_asm_insn ("st\t%1,%N3", operands);
output_asm_insn ("ld\t%0,%3", operands);
return "sd\t%0,%2";
}
- [(set_attr "op_type" "NN")
- (set_attr "type" "other" )
- (set_attr "atype" "agen")
- (set_attr "length" "20")])
+ [(set_attr "length" "20")])
;
; floatsisf2 instruction pattern(s).
;
(define_expand "floatsisf2"
- [(parallel
- [(set (match_operand:SF 0 "register_operand" "")
- (float:SF (match_operand:SI 1 "register_operand" "")))
- (clobber (reg:CC 33))])]
+ [(set (match_operand:SF 0 "register_operand" "")
+ (float:SF (match_operand:SI 1 "register_operand" "")))]
"TARGET_HARD_FLOAT"
{
if (TARGET_IBM_FLOAT)
(define_insn "floatsisf2_ieee"
[(set (match_operand:SF 0 "register_operand" "=f")
- (float:SF (match_operand:SI 1 "register_operand" "d")))
- (clobber (reg:CC 33))]
+ (float:SF (match_operand:SI 1 "register_operand" "d")))]
"TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"cefbr\t%0,%1"
[(set_attr "op_type" "RRE")
(define_expand "truncdfsf2"
[(set (match_operand:SF 0 "register_operand" "")
- (float_truncate:SF (match_operand:DF 1 "general_operand" "")))]
+ (float_truncate:SF (match_operand:DF 1 "register_operand" "")))]
"TARGET_HARD_FLOAT"
"")
(define_insn "truncdfsf2_ieee"
[(set (match_operand:SF 0 "register_operand" "=f")
- (float_truncate:SF (match_operand:DF 1 "general_operand" "f")))]
+ (float_truncate:SF (match_operand:DF 1 "register_operand" "f")))]
"TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"ledbr\t%0,%1"
[(set_attr "op_type" "RRE")])
(define_insn "truncdfsf2_ibm"
[(set (match_operand:SF 0 "register_operand" "=f,f")
- (float_truncate:SF (match_operand:DF 1 "general_operand" "f,R")))]
+ (float_truncate:SF (match_operand:DF 1 "nonimmediate_operand" "f,R")))]
"TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
"@
- lrer\t%0,%1
+ ler\t%0,%1
le\t%0,%1"
[(set_attr "op_type" "RR,RX")
- (set_attr "type" "floads,floads")])
+ (set_attr "type" "floadsf")])
;
; extendsfdf2 instruction pattern(s).
ldebr\t%0,%1
ldeb\t%0,%1"
[(set_attr "op_type" "RRE,RXE")
- (set_attr "type" "floads,floads")])
+ (set_attr "type" "floadsf")])
(define_insn "extendsfdf2_ibm"
[(set (match_operand:DF 0 "register_operand" "=f,f")
(float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,R")))
- (clobber (reg:CC 33))]
+ (clobber (reg:CC CC_REGNUM))]
"TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
"@
sdr\t%0,%0\;ler\t%0,%1
sdr\t%0,%0\;le\t%0,%1"
- [(set_attr "op_type" "NN,NN")
- (set_attr "atype" "reg,agen")
- (set_attr "length" "4,6")
- (set_attr "type" "o2,o2")])
+ [(set_attr "length" "4,6")
+ (set_attr "type" "floadsf")])
;;
[(set (match_operand:TI 0 "register_operand" "=&d")
(plus:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
(match_operand:TI 2 "general_operand" "do") ) )
- (clobber (reg:CC 33))]
+ (clobber (reg:CC CC_REGNUM))]
"TARGET_64BIT"
"#"
"&& reload_completed"
[(parallel
- [(set (reg:CCL1 33)
+ [(set (reg:CCL1 CC_REGNUM)
(compare:CCL1 (plus:DI (match_dup 7) (match_dup 8))
(match_dup 7)))
(set (match_dup 6) (plus:DI (match_dup 7) (match_dup 8)))])
(parallel
[(set (match_dup 3) (plus:DI (plus:DI (match_dup 4) (match_dup 5))
- (ltu:DI (reg:CCL1 33) (const_int 0))))
- (clobber (reg:CC 33))])]
+ (ltu:DI (reg:CCL1 CC_REGNUM) (const_int 0))))
+ (clobber (reg:CC CC_REGNUM))])]
"operands[3] = operand_subword (operands[0], 0, 0, TImode);
operands[4] = operand_subword (operands[1], 0, 0, TImode);
operands[5] = operand_subword (operands[2], 0, 0, TImode);
operands[6] = operand_subword (operands[0], 1, 0, TImode);
operands[7] = operand_subword (operands[1], 1, 0, TImode);
- operands[8] = operand_subword (operands[2], 1, 0, TImode);"
- [(set_attr "op_type" "NN")])
+ operands[8] = operand_subword (operands[2], 1, 0, TImode);")
;
; adddi3 instruction pattern(s).
[(set (match_operand:DI 0 "register_operand" "=d,d")
(plus:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,m"))
(match_operand:DI 1 "register_operand" "0,0")))
- (clobber (reg:CC 33))]
+ (clobber (reg:CC CC_REGNUM))]
"TARGET_64BIT"
"@
agfr\t%0,%2
[(set_attr "op_type" "RRE,RXY")])
(define_insn "*adddi3_zero_cc"
- [(set (reg 33)
+ [(set (reg CC_REGNUM)
(compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))
(match_operand:DI 1 "register_operand" "0,0"))
(const_int 0)))
[(set_attr "op_type" "RRE,RXY")])
(define_insn "*adddi3_zero_cconly"
- [(set (reg 33)
+ [(set (reg CC_REGNUM)
(compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))
(match_operand:DI 1 "register_operand" "0,0"))
(const_int 0)))
[(set (match_operand:DI 0 "register_operand" "=d,d")
(plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))
(match_operand:DI 1 "register_operand" "0,0")))
- (clobber (reg:CC 33))]
+ (clobber (reg:CC CC_REGNUM))]
"TARGET_64BIT"
"@
algfr\t%0,%2
[(set_attr "op_type" "RRE,RXY")])
(define_insn "*adddi3_imm_cc"
- [(set (reg 33)
+ [(set (reg CC_REGNUM)
(compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "0")
(match_operand:DI 2 "const_int_operand" "K"))
(const_int 0)))
[(set_attr "op_type" "RI")])
(define_insn "*adddi3_carry1_cc"
- [(set (reg 33)
+ [(set (reg CC_REGNUM)
(compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
(match_operand:DI 2 "general_operand" "d,m"))
(match_dup 1)))
[(set_attr "op_type" "RRE,RXY")])
(define_insn "*adddi3_carry1_cconly"
- [(set (reg 33)
+ [(set (reg CC_REGNUM)
(compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
(match_operand:DI 2 "general_operand" "d,m"))
(match_dup 1)))
[(set_attr "op_type" "RRE,RXY")])
(define_insn "*adddi3_carry2_cc"
- [(set (reg 33)
+ [(set (reg CC_REGNUM)
(compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
(match_operand:DI 2 "general_operand" "d,m"))
(match_dup 2)))
[(set_attr "op_type" "RRE,RXY")])
(define_insn "*adddi3_carry2_cconly"
- [(set (reg 33)
+ [(set (reg CC_REGNUM)
(compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
(match_operand:DI 2 "general_operand" "d,m"))
(match_dup 2)))
[(set_attr "op_type" "RRE,RXY")])
(define_insn "*adddi3_cc"
- [(set (reg 33)
+ [(set (reg CC_REGNUM)
(compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
(match_operand:DI 2 "general_operand" "d,m"))
(const_int 0)))
[(set_attr "op_type" "RRE,RXY")])
(define_insn "*adddi3_cconly"
- [(set (reg 33)
+ [(set (reg CC_REGNUM)
(compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
(match_operand:DI 2 "general_operand" "d,m"))
(const_int 0)))
[(set_attr "op_type" "RRE,RXY")])
(define_insn "*adddi3_cconly2"
- [(set (reg 33)
+ [(set (reg CC_REGNUM)
(compare (match_operand:DI 1 "nonimmediate_operand" "%0,0")
(neg:SI (match_operand:DI 2 "general_operand" "d,m"))))
(clobber (match_scratch:DI 0 "=d,d"))]
[(set (match_operand:DI 0 "register_operand" "=d,d,d")
(plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0")
(match_operand:DI 2 "general_operand" "d,K,m") ) )
- (clobber (reg:CC 33))]
+ (clobber (reg:CC CC_REGNUM))]
"TARGET_64BIT"
"@
agr\t%0,%2
[(set (match_operand:DI 0 "register_operand" "=&d")
(plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
(match_operand:DI 2 "general_operand" "do") ) )
- (clobber (reg:CC 33))]
+ (clobber (reg:CC CC_REGNUM))]
"!TARGET_64BIT && TARGET_CPU_ZARCH"
"#"
"&& reload_completed"
[(parallel
- [(set (reg:CCL1 33)
+ [(set (reg:CCL1 CC_REGNUM)
(compare:CCL1 (plus:SI (match_dup 7) (match_dup 8))
(match_dup 7)))
(set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))])
(parallel
[(set (match_dup 3) (plus:SI (plus:SI (match_dup 4) (match_dup 5))
- (ltu:SI (reg:CCL1 33) (const_int 0))))
- (clobber (reg:CC 33))])]
+ (ltu:SI (reg:CCL1 CC_REGNUM) (const_int 0))))
+ (clobber (reg:CC CC_REGNUM))])]
"operands[3] = operand_subword (operands[0], 0, 0, DImode);
operands[4] = operand_subword (operands[1], 0, 0, DImode);
operands[5] = operand_subword (operands[2], 0, 0, DImode);
operands[6] = operand_subword (operands[0], 1, 0, DImode);
operands[7] = operand_subword (operands[1], 1, 0, DImode);
- operands[8] = operand_subword (operands[2], 1, 0, DImode);"
- [(set_attr "op_type" "NN")])
+ operands[8] = operand_subword (operands[2], 1, 0, DImode);")
(define_insn_and_split "*adddi3_31"
[(set (match_operand:DI 0 "register_operand" "=&d")
(plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
(match_operand:DI 2 "general_operand" "do") ) )
- (clobber (reg:CC 33))]
+ (clobber (reg:CC CC_REGNUM))]
"!TARGET_CPU_ZARCH"
"#"
"&& reload_completed"
[(parallel
[(set (match_dup 3) (plus:SI (match_dup 4) (match_dup 5)))
- (clobber (reg:CC 33))])
+ (clobber (reg:CC CC_REGNUM))])
(parallel
- [(set (reg:CCL1 33)
+ [(set (reg:CCL1 CC_REGNUM)
(compare:CCL1 (plus:SI (match_dup 7) (match_dup 8))
(match_dup 7)))
(set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))])
(set (pc)
- (if_then_else (ltu (reg:CCL1 33) (const_int 0))
+ (if_then_else (ltu (reg:CCL1 CC_REGNUM) (const_int 0))
(pc)
(label_ref (match_dup 9))))
(parallel
[(set (match_dup 3) (plus:SI (match_dup 3) (const_int 1)))
- (clobber (reg:CC 33))])
+ (clobber (reg:CC CC_REGNUM))])
(match_dup 9)]
"operands[3] = operand_subword (operands[0], 0, 0, DImode);
operands[4] = operand_subword (operands[1], 0, 0, DImode);
operands[6] = operand_subword (operands[0], 1, 0, DImode);
operands[7] = operand_subword (operands[1], 1, 0, DImode);
operands[8] = operand_subword (operands[2], 1, 0, DImode);
- operands[9] = gen_label_rtx ();"
- [(set_attr "op_type" "NN")])
+ operands[9] = gen_label_rtx ();")
(define_expand "adddi3"
[(parallel
[(set (match_operand:DI 0 "register_operand" "")
(plus:DI (match_operand:DI 1 "nonimmediate_operand" "")
(match_operand:DI 2 "general_operand" "")))
- (clobber (reg:CC 33))])]
+ (clobber (reg:CC CC_REGNUM))])]
""
"")
;
(define_insn "*addsi3_imm_cc"
- [(set (reg 33)
+ [(set (reg CC_REGNUM)
(compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "0")
(match_operand:SI 2 "const_int_operand" "K"))
(const_int 0)))
[(set_attr "op_type" "RI")])
(define_insn "*addsi3_carry1_cc"
- [(set (reg 33)
+ [(set (reg CC_REGNUM)
(compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
(match_operand:SI 2 "general_operand" "d,R,T"))
(match_dup 1)))
[(set_attr "op_type" "RR,RX,RXY")])
(define_insn "*addsi3_carry1_cconly"
- [(set (reg 33)
+ [(set (reg CC_REGNUM)
(compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
(match_operand:SI 2 "general_operand" "d,R,T"))
(match_dup 1)))
[(set_attr "op_type" "RR,RX,RXY")])
(define_insn "*addsi3_carry2_cc"
- [(set (reg 33)
+ [(set (reg CC_REGNUM)
(compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
(match_operand:SI 2 "general_operand" "d,R,T"))
(match_dup 2)))
[(set_attr "op_type" "RR,RX,RXY")])
(define_insn "*addsi3_carry2_cconly"
- [(set (reg 33)
+ [(set (reg CC_REGNUM)
(compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
(match_operand:SI 2 "general_operand" "d,R,T"))
(match_dup 2)))
[(set_attr "op_type" "RR,RX,RXY")])
(define_insn "*addsi3_cc"
- [(set (reg 33)
+ [(set (reg CC_REGNUM)
(compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
(match_operand:SI 2 "general_operand" "d,R,T"))
(const_int 0)))
[(set_attr "op_type" "RR,RX,RXY")])
(define_insn "*addsi3_cconly"
- [(set (reg 33)
+ [(set (reg CC_REGNUM)
(compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
(match_operand:SI 2 "general_operand" "d,R,T"))
(const_int 0)))
[(set_attr "op_type" "RR,RX,RXY")])
(define_insn "*addsi3_cconly2"
- [(set (reg 33)
+ [(set (reg CC_REGNUM)
(compare (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
(neg:SI (match_operand:SI 2 "general_operand" "d,R,T"))))
(clobber (match_scratch:SI 0 "=d,d,d"))]
(define_insn "*addsi3_sign"
[(set (match_operand:SI 0 "register_operand" "=d,d")
- (plus:SI (match_operand:SI 1 "register_operand" "0,0")
- (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T"))))
- (clobber (reg:CC 33))]
+ (plus:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T"))
+ (match_operand:SI 1 "register_operand" "0,0")))
+ (clobber (reg:CC CC_REGNUM))]
""
"@
ah\t%0,%2
[(set (match_operand:SI 0 "register_operand" "=d,d,d,d")
(plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
(match_operand:SI 2 "general_operand" "d,K,R,T")))
- (clobber (reg:CC 33))]
+ (clobber (reg:CC CC_REGNUM))]
""
"@
ar\t%0,%2
[(set_attr "op_type" "RR,RI,RX,RXY")])
;
-; adddf3 instruction pattern(s).
-;
-
-(define_expand "adddf3"
- [(parallel
- [(set (match_operand:DF 0 "register_operand" "=f,f")
- (plus:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0")
- (match_operand:DF 2 "general_operand" "f,R")))
- (clobber (reg:CC 33))])]
- "TARGET_HARD_FLOAT"
- "")
-
-(define_insn "*adddf3"
- [(set (match_operand:DF 0 "register_operand" "=f,f")
- (plus:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0")
- (match_operand:DF 2 "general_operand" "f,R")))
- (clobber (reg:CC 33))]
- "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
- "@
- adbr\t%0,%2
- adb\t%0,%2"
- [(set_attr "op_type" "RRE,RXE")
- (set_attr "type" "fsimpd,fsimpd")])
-
-(define_insn "*adddf3_cc"
- [(set (reg 33)
- (compare (plus:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0")
- (match_operand:DF 2 "general_operand" "f,R"))
- (match_operand:DF 3 "const0_operand" "")))
- (set (match_operand:DF 0 "register_operand" "=f,f")
- (plus:DF (match_dup 1) (match_dup 2)))]
- "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
- "@
- adbr\t%0,%2
- adb\t%0,%2"
- [(set_attr "op_type" "RRE,RXE")
- (set_attr "type" "fsimpd,fsimpd")])
-
-(define_insn "*adddf3_cconly"
- [(set (reg 33)
- (compare (plus:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0")
- (match_operand:DF 2 "general_operand" "f,R"))
- (match_operand:DF 3 "const0_operand" "")))
- (clobber (match_scratch:DF 0 "=f,f"))]
- "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
- "@
- adbr\t%0,%2
- adb\t%0,%2"
- [(set_attr "op_type" "RRE,RXE")
- (set_attr "type" "fsimpd,fsimpd")])
-
-(define_insn "*adddf3_ibm"
- [(set (match_operand:DF 0 "register_operand" "=f,f")
- (plus:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0")
- (match_operand:DF 2 "general_operand" "f,R")))
- (clobber (reg:CC 33))]
- "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
- "@
- adr\t%0,%2
- ad\t%0,%2"
- [(set_attr "op_type" "RR,RX")
- (set_attr "type" "fsimpd,fsimpd")])
-
-;
-; addsf3 instruction pattern(s).
+; add(df|sf)3 instruction pattern(s).
;
-(define_expand "addsf3"
+(define_expand "add<mode>3"
[(parallel
- [(set (match_operand:SF 0 "register_operand" "=f,f")
- (plus:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0")
- (match_operand:SF 2 "general_operand" "f,R")))
- (clobber (reg:CC 33))])]
+ [(set (match_operand:FPR 0 "register_operand" "=f,f")
+ (plus:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
+ (match_operand:FPR 2 "general_operand" "f,R")))
+ (clobber (reg:CC CC_REGNUM))])]
"TARGET_HARD_FLOAT"
"")
-(define_insn "*addsf3"
- [(set (match_operand:SF 0 "register_operand" "=f,f")
- (plus:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0")
- (match_operand:SF 2 "general_operand" "f,R")))
- (clobber (reg:CC 33))]
+(define_insn "*add<mode>3"
+ [(set (match_operand:FPR 0 "register_operand" "=f,f")
+ (plus:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
+ (match_operand:FPR 2 "general_operand" "f,R")))
+ (clobber (reg:CC CC_REGNUM))]
"TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"@
- aebr\t%0,%2
- aeb\t%0,%2"
+ a<de>br\t%0,%2
+ a<de>b\t%0,%2"
[(set_attr "op_type" "RRE,RXE")
- (set_attr "type" "fsimps,fsimps")])
-
-(define_insn "*addsf3_cc"
- [(set (reg 33)
- (compare (plus:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0")
- (match_operand:SF 2 "general_operand" "f,R"))
- (match_operand:SF 3 "const0_operand" "")))
- (set (match_operand:SF 0 "register_operand" "=f,f")
- (plus:SF (match_dup 1) (match_dup 2)))]
+ (set_attr "type" "fsimp<mode>")])
+
+(define_insn "*add<mode>3_cc"
+ [(set (reg CC_REGNUM)
+ (compare (plus:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
+ (match_operand:FPR 2 "general_operand" "f,R"))
+ (match_operand:FPR 3 "const0_operand" "")))
+ (set (match_operand:FPR 0 "register_operand" "=f,f")
+ (plus:FPR (match_dup 1) (match_dup 2)))]
"s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"@
- aebr\t%0,%2
- aeb\t%0,%2"
+ a<de>br\t%0,%2
+ a<de>b\t%0,%2"
[(set_attr "op_type" "RRE,RXE")
- (set_attr "type" "fsimps,fsimps")])
-
-(define_insn "*addsf3_cconly"
- [(set (reg 33)
- (compare (plus:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0")
- (match_operand:SF 2 "general_operand" "f,R"))
- (match_operand:SF 3 "const0_operand" "")))
- (clobber (match_scratch:SF 0 "=f,f"))]
+ (set_attr "type" "fsimp<mode>")])
+
+(define_insn "*add<mode>3_cconly"
+ [(set (reg CC_REGNUM)
+ (compare (plus:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
+ (match_operand:FPR 2 "general_operand" "f,R"))
+ (match_operand:FPR 3 "const0_operand" "")))
+ (clobber (match_scratch:FPR 0 "=f,f"))]
"s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"@
- aebr\t%0,%2
- aeb\t%0,%2"
+ a<de>br\t%0,%2
+ a<de>b\t%0,%2"
[(set_attr "op_type" "RRE,RXE")
- (set_attr "type" "fsimps,fsimps")])
+ (set_attr "type" "fsimp<mode>")])
-(define_insn "*addsf3"
- [(set (match_operand:SF 0 "register_operand" "=f,f")
- (plus:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0")
- (match_operand:SF 2 "general_operand" "f,R")))
- (clobber (reg:CC 33))]
+(define_insn "*add<mode>3_ibm"
+ [(set (match_operand:FPR 0 "register_operand" "=f,f")
+ (plus:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
+ (match_operand:FPR 2 "general_operand" "f,R")))
+ (clobber (reg:CC CC_REGNUM))]
"TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
"@
- aer\t%0,%2
- ae\t%0,%2"
+ a<de>r\t%0,%2
+ a<de>\t%0,%2"
[(set_attr "op_type" "RR,RX")
- (set_attr "type" "fsimps,fsimps")])
+ (set_attr "type" "fsimp<mode>")])
;;
[(set (match_operand:TI 0 "register_operand" "=&d")
(minus:TI (match_operand:TI 1 "register_operand" "0")
(match_operand:TI 2 "general_operand" "do") ) )
- (clobber (reg:CC 33))]
+ (clobber (reg:CC CC_REGNUM))]
"TARGET_64BIT"
"#"
"&& reload_completed"
[(parallel
- [(set (reg:CCL2 33)
+ [(set (reg:CCL2 CC_REGNUM)
(compare:CCL2 (minus:DI (match_dup 7) (match_dup 8))
(match_dup 7)))
(set (match_dup 6) (minus:DI (match_dup 7) (match_dup 8)))])
(parallel
[(set (match_dup 3) (minus:DI (minus:DI (match_dup 4) (match_dup 5))
- (gtu:DI (reg:CCL2 33) (const_int 0))))
- (clobber (reg:CC 33))])]
+ (gtu:DI (reg:CCL2 CC_REGNUM) (const_int 0))))
+ (clobber (reg:CC CC_REGNUM))])]
"operands[3] = operand_subword (operands[0], 0, 0, TImode);
operands[4] = operand_subword (operands[1], 0, 0, TImode);
operands[5] = operand_subword (operands[2], 0, 0, TImode);
operands[6] = operand_subword (operands[0], 1, 0, TImode);
operands[7] = operand_subword (operands[1], 1, 0, TImode);
- operands[8] = operand_subword (operands[2], 1, 0, TImode);"
- [(set_attr "op_type" "NN")])
+ operands[8] = operand_subword (operands[2], 1, 0, TImode);")
;
; subdi3 instruction pattern(s).
[(set (match_operand:DI 0 "register_operand" "=d,d")
(minus:DI (match_operand:DI 1 "register_operand" "0,0")
(sign_extend:DI (match_operand:SI 2 "general_operand" "d,m"))))
- (clobber (reg:CC 33))]
+ (clobber (reg:CC CC_REGNUM))]
"TARGET_64BIT"
"@
sgfr\t%0,%2
[(set_attr "op_type" "RRE,RXY")])
(define_insn "*subdi3_zero_cc"
- [(set (reg 33)
+ [(set (reg CC_REGNUM)
(compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
(zero_extend:DI (match_operand:SI 2 "general_operand" "d,m")))
(const_int 0)))
[(set_attr "op_type" "RRE,RXY")])
(define_insn "*subdi3_zero_cconly"
- [(set (reg 33)
+ [(set (reg CC_REGNUM)
(compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
(zero_extend:DI (match_operand:SI 2 "general_operand" "d,m")))
(const_int 0)))
[(set (match_operand:DI 0 "register_operand" "=d,d")
(minus:DI (match_operand:DI 1 "register_operand" "0,0")
(zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))))
- (clobber (reg:CC 33))]
+ (clobber (reg:CC CC_REGNUM))]
"TARGET_64BIT"
"@
slgfr\t%0,%2
[(set_attr "op_type" "RRE,RXY")])
(define_insn "*subdi3_borrow_cc"
- [(set (reg 33)
+ [(set (reg CC_REGNUM)
(compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
(match_operand:DI 2 "general_operand" "d,m"))
(match_dup 1)))
[(set_attr "op_type" "RRE,RXY")])
(define_insn "*subdi3_borrow_cconly"
- [(set (reg 33)
+ [(set (reg CC_REGNUM)
(compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
(match_operand:DI 2 "general_operand" "d,m"))
(match_dup 1)))
[(set_attr "op_type" "RRE,RXY")])
(define_insn "*subdi3_cc"
- [(set (reg 33)
+ [(set (reg CC_REGNUM)
(compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
(match_operand:DI 2 "general_operand" "d,m"))
(const_int 0)))
[(set_attr "op_type" "RRE,RXY")])
(define_insn "*subdi3_cc2"
- [(set (reg 33)
+ [(set (reg CC_REGNUM)
(compare (match_operand:DI 1 "register_operand" "0,0")
(match_operand:DI 2 "general_operand" "d,m")))
(set (match_operand:DI 0 "register_operand" "=d,d")
[(set_attr "op_type" "RRE,RXY")])
(define_insn "*subdi3_cconly"
- [(set (reg 33)
+ [(set (reg CC_REGNUM)
(compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
(match_operand:DI 2 "general_operand" "d,m"))
(const_int 0)))
[(set_attr "op_type" "RRE,RXY")])
(define_insn "*subdi3_cconly2"
- [(set (reg 33)
+ [(set (reg CC_REGNUM)
(compare (match_operand:DI 1 "register_operand" "0,0")
(match_operand:DI 2 "general_operand" "d,m")))
(clobber (match_scratch:DI 0 "=d,d"))]
[(set (match_operand:DI 0 "register_operand" "=d,d")
(minus:DI (match_operand:DI 1 "register_operand" "0,0")
(match_operand:DI 2 "general_operand" "d,m") ) )
- (clobber (reg:CC 33))]
+ (clobber (reg:CC CC_REGNUM))]
"TARGET_64BIT"
"@
sgr\t%0,%2
[(set (match_operand:DI 0 "register_operand" "=&d")
(minus:DI (match_operand:DI 1 "register_operand" "0")
(match_operand:DI 2 "general_operand" "do") ) )
- (clobber (reg:CC 33))]
+ (clobber (reg:CC CC_REGNUM))]
"!TARGET_64BIT && TARGET_CPU_ZARCH"
"#"
"&& reload_completed"
[(parallel
- [(set (reg:CCL2 33)
+ [(set (reg:CCL2 CC_REGNUM)
(compare:CCL2 (minus:SI (match_dup 7) (match_dup 8))
(match_dup 7)))
(set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))])
(parallel
[(set (match_dup 3) (minus:SI (minus:SI (match_dup 4) (match_dup 5))
- (gtu:SI (reg:CCL2 33) (const_int 0))))
- (clobber (reg:CC 33))])]
+ (gtu:SI (reg:CCL2 CC_REGNUM) (const_int 0))))
+ (clobber (reg:CC CC_REGNUM))])]
"operands[3] = operand_subword (operands[0], 0, 0, DImode);
operands[4] = operand_subword (operands[1], 0, 0, DImode);
operands[5] = operand_subword (operands[2], 0, 0, DImode);
operands[6] = operand_subword (operands[0], 1, 0, DImode);
operands[7] = operand_subword (operands[1], 1, 0, DImode);
- operands[8] = operand_subword (operands[2], 1, 0, DImode);"
- [(set_attr "op_type" "NN")])
+ operands[8] = operand_subword (operands[2], 1, 0, DImode);")
(define_insn_and_split "*subdi3_31"
[(set (match_operand:DI 0 "register_operand" "=&d")
(minus:DI (match_operand:DI 1 "register_operand" "0")
(match_operand:DI 2 "general_operand" "do") ) )
- (clobber (reg:CC 33))]
+ (clobber (reg:CC CC_REGNUM))]
"!TARGET_CPU_ZARCH"
"#"
"&& reload_completed"
[(parallel
[(set (match_dup 3) (minus:SI (match_dup 4) (match_dup 5)))
- (clobber (reg:CC 33))])
+ (clobber (reg:CC CC_REGNUM))])
(parallel
- [(set (reg:CCL2 33)
+ [(set (reg:CCL2 CC_REGNUM)
(compare:CCL2 (minus:SI (match_dup 7) (match_dup 8))
(match_dup 7)))
(set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))])
(set (pc)
- (if_then_else (gtu (reg:CCL2 33) (const_int 0))
+ (if_then_else (gtu (reg:CCL2 CC_REGNUM) (const_int 0))
(pc)
(label_ref (match_dup 9))))
(parallel
[(set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))
- (clobber (reg:CC 33))])
+ (clobber (reg:CC CC_REGNUM))])
(match_dup 9)]
"operands[3] = operand_subword (operands[0], 0, 0, DImode);
operands[4] = operand_subword (operands[1], 0, 0, DImode);
operands[6] = operand_subword (operands[0], 1, 0, DImode);
operands[7] = operand_subword (operands[1], 1, 0, DImode);
operands[8] = operand_subword (operands[2], 1, 0, DImode);
- operands[9] = gen_label_rtx ();"
- [(set_attr "op_type" "NN")])
+ operands[9] = gen_label_rtx ();")
(define_expand "subdi3"
[(parallel
[(set (match_operand:DI 0 "register_operand" "")
(minus:DI (match_operand:DI 1 "register_operand" "")
(match_operand:DI 2 "general_operand" "")))
- (clobber (reg:CC 33))])]
+ (clobber (reg:CC CC_REGNUM))])]
""
"")
;
(define_insn "*subsi3_borrow_cc"
- [(set (reg 33)
+ [(set (reg CC_REGNUM)
(compare (minus:SI (match_operand:SI 1 "register_operand" "0,0,0")
(match_operand:SI 2 "general_operand" "d,R,T"))
(match_dup 1)))
[(set_attr "op_type" "RR,RX,RXY")])
(define_insn "*subsi3_borrow_cconly"
- [(set (reg 33)
+ [(set (reg CC_REGNUM)
(compare (minus:SI (match_operand:SI 1 "register_operand" "0,0,0")
(match_operand:SI 2 "general_operand" "d,R,T"))
(match_dup 1)))
[(set_attr "op_type" "RR,RX,RXY")])
(define_insn "*subsi3_cc"
- [(set (reg 33)
+ [(set (reg CC_REGNUM)
(compare (minus:SI (match_operand:SI 1 "register_operand" "0,0,0")
(match_operand:SI 2 "general_operand" "d,R,T"))
(const_int 0)))
[(set_attr "op_type" "RR,RX,RXY")])
(define_insn "*subsi3_cc2"
- [(set (reg 33)
+ [(set (reg CC_REGNUM)
(compare (match_operand:SI 1 "register_operand" "0,0,0")
(match_operand:SI 2 "general_operand" "d,R,T")))
(set (match_operand:SI 0 "register_operand" "=d,d,d")
[(set_attr "op_type" "RR,RX,RXY")])
(define_insn "*subsi3_cconly"
- [(set (reg 33)
+ [(set (reg CC_REGNUM)
(compare (minus:SI (match_operand:SI 1 "register_operand" "0,0,0")
(match_operand:SI 2 "general_operand" "d,R,T"))
(const_int 0)))
[(set_attr "op_type" "RR,RX,RXY")])
(define_insn "*subsi3_cconly2"
- [(set (reg 33)
+ [(set (reg CC_REGNUM)
(compare (match_operand:SI 1 "register_operand" "0,0,0")
(match_operand:SI 2 "general_operand" "d,R,T")))
(clobber (match_scratch:SI 0 "=d,d,d"))]
[(set (match_operand:SI 0 "register_operand" "=d,d")
(minus:SI (match_operand:SI 1 "register_operand" "0,0")
(sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T"))))
- (clobber (reg:CC 33))]
+ (clobber (reg:CC CC_REGNUM))]
""
"@
sh\t%0,%2
[(set (match_operand:SI 0 "register_operand" "=d,d,d")
(minus:SI (match_operand:SI 1 "register_operand" "0,0,0")
(match_operand:SI 2 "general_operand" "d,R,T")))
- (clobber (reg:CC 33))]
+ (clobber (reg:CC CC_REGNUM))]
""
"@
sr\t%0,%2
;
-; subdf3 instruction pattern(s).
-;
-
-(define_expand "subdf3"
- [(parallel
- [(set (match_operand:DF 0 "register_operand" "=f,f")
- (minus:DF (match_operand:DF 1 "register_operand" "0,0")
- (match_operand:DF 2 "general_operand" "f,R")))
- (clobber (reg:CC 33))])]
- "TARGET_HARD_FLOAT"
- "")
-
-(define_insn "*subdf3"
- [(set (match_operand:DF 0 "register_operand" "=f,f")
- (minus:DF (match_operand:DF 1 "register_operand" "0,0")
- (match_operand:DF 2 "general_operand" "f,R")))
- (clobber (reg:CC 33))]
- "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
- "@
- sdbr\t%0,%2
- sdb\t%0,%2"
- [(set_attr "op_type" "RRE,RXE")
- (set_attr "type" "fsimpd,fsimpd")])
-
-(define_insn "*subdf3_cc"
- [(set (reg 33)
- (compare (minus:DF (match_operand:DF 1 "nonimmediate_operand" "0,0")
- (match_operand:DF 2 "general_operand" "f,R"))
- (match_operand:DF 3 "const0_operand" "")))
- (set (match_operand:DF 0 "register_operand" "=f,f")
- (plus:DF (match_dup 1) (match_dup 2)))]
- "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
- "@
- sdbr\t%0,%2
- sdb\t%0,%2"
- [(set_attr "op_type" "RRE,RXE")
- (set_attr "type" "fsimpd,fsimpd")])
-
-(define_insn "*subdf3_cconly"
- [(set (reg 33)
- (compare (minus:DF (match_operand:DF 1 "nonimmediate_operand" "0,0")
- (match_operand:DF 2 "general_operand" "f,R"))
- (match_operand:DF 3 "const0_operand" "")))
- (clobber (match_scratch:DF 0 "=f,f"))]
- "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
- "@
- sdbr\t%0,%2
- sdb\t%0,%2"
- [(set_attr "op_type" "RRE,RXE")
- (set_attr "type" "fsimpd,fsimpd")])
-
-(define_insn "*subdf3_ibm"
- [(set (match_operand:DF 0 "register_operand" "=f,f")
- (minus:DF (match_operand:DF 1 "register_operand" "0,0")
- (match_operand:DF 2 "general_operand" "f,R")))
- (clobber (reg:CC 33))]
- "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
- "@
- sdr\t%0,%2
- sd\t%0,%2"
- [(set_attr "op_type" "RR,RX")
- (set_attr "type" "fsimpd,fsimpd")])
-
-;
-; subsf3 instruction pattern(s).
+; sub(df|sf)3 instruction pattern(s).
;
-(define_expand "subsf3"
+(define_expand "sub<mode>3"
[(parallel
- [(set (match_operand:SF 0 "register_operand" "=f,f")
- (minus:SF (match_operand:SF 1 "register_operand" "0,0")
- (match_operand:SF 2 "general_operand" "f,R")))
- (clobber (reg:CC 33))])]
+ [(set (match_operand:FPR 0 "register_operand" "=f,f")
+ (minus:FPR (match_operand:FPR 1 "register_operand" "0,0")
+ (match_operand:FPR 2 "general_operand" "f,R")))
+ (clobber (reg:CC CC_REGNUM))])]
"TARGET_HARD_FLOAT"
"")
-(define_insn "*subsf3"
- [(set (match_operand:SF 0 "register_operand" "=f,f")
- (minus:SF (match_operand:SF 1 "register_operand" "0,0")
- (match_operand:SF 2 "general_operand" "f,R")))
- (clobber (reg:CC 33))]
+(define_insn "*sub<mode>3"
+ [(set (match_operand:FPR 0 "register_operand" "=f,f")
+ (minus:FPR (match_operand:FPR 1 "register_operand" "0,0")
+ (match_operand:FPR 2 "general_operand" "f,R")))
+ (clobber (reg:CC CC_REGNUM))]
"TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"@
- sebr\t%0,%2
- seb\t%0,%2"
+ s<de>br\t%0,%2
+ s<de>b\t%0,%2"
[(set_attr "op_type" "RRE,RXE")
- (set_attr "type" "fsimps,fsimps")])
-
-(define_insn "*subsf3_cc"
- [(set (reg 33)
- (compare (minus:SF (match_operand:SF 1 "nonimmediate_operand" "0,0")
- (match_operand:SF 2 "general_operand" "f,R"))
- (match_operand:SF 3 "const0_operand" "")))
- (set (match_operand:SF 0 "register_operand" "=f,f")
- (minus:SF (match_dup 1) (match_dup 2)))]
+ (set_attr "type" "fsimp<mode>")])
+
+(define_insn "*sub<mode>3_cc"
+ [(set (reg CC_REGNUM)
+ (compare (minus:FPR (match_operand:FPR 1 "nonimmediate_operand" "0,0")
+ (match_operand:FPR 2 "general_operand" "f,R"))
+ (match_operand:FPR 3 "const0_operand" "")))
+ (set (match_operand:FPR 0 "register_operand" "=f,f")
+ (minus:FPR (match_dup 1) (match_dup 2)))]
"s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"@
- sebr\t%0,%2
- seb\t%0,%2"
+ s<de>br\t%0,%2
+ s<de>b\t%0,%2"
[(set_attr "op_type" "RRE,RXE")
- (set_attr "type" "fsimps,fsimps")])
-
-(define_insn "*subsf3_cconly"
- [(set (reg 33)
- (compare (minus:SF (match_operand:SF 1 "nonimmediate_operand" "0,0")
- (match_operand:SF 2 "general_operand" "f,R"))
- (match_operand:SF 3 "const0_operand" "")))
- (clobber (match_scratch:SF 0 "=f,f"))]
+ (set_attr "type" "fsimp<mode>")])
+
+(define_insn "*sub<mode>3_cconly"
+ [(set (reg CC_REGNUM)
+ (compare (minus:FPR (match_operand:FPR 1 "nonimmediate_operand" "0,0")
+ (match_operand:FPR 2 "general_operand" "f,R"))
+ (match_operand:FPR 3 "const0_operand" "")))
+ (clobber (match_scratch:FPR 0 "=f,f"))]
"s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"@
- sebr\t%0,%2
- seb\t%0,%2"
+ s<de>br\t%0,%2
+ s<de>b\t%0,%2"
[(set_attr "op_type" "RRE,RXE")
- (set_attr "type" "fsimps,fsimps")])
-
-(define_insn "*subsf3_ibm"
- [(set (match_operand:SF 0 "register_operand" "=f,f")
- (minus:SF (match_operand:SF 1 "register_operand" "0,0")
- (match_operand:SF 2 "general_operand" "f,R")))
- (clobber (reg:CC 33))]
- "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
- "@
- ser\t%0,%2
- se\t%0,%2"
- [(set_attr "op_type" "RR,RX")
- (set_attr "type" "fsimps,fsimps")])
-
-
-;;
-;;- Conditional add/subtract instructions.
-;;
-
-;
-; adddicc instruction pattern(s).
-;
-
-(define_insn "*adddi3_alc_cc"
- [(set (reg 33)
- (compare
- (plus:DI (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
- (match_operand:DI 2 "general_operand" "d,m"))
- (match_operand:DI 3 "s390_alc_comparison" ""))
- (const_int 0)))
- (set (match_operand:DI 0 "register_operand" "=d,d")
- (plus:DI (plus:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
- "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
- "@
- alcgr\\t%0,%2
- alcg\\t%0,%2"
- [(set_attr "op_type" "RRE,RXY")])
-
-(define_insn "*adddi3_alc"
- [(set (match_operand:DI 0 "register_operand" "=d,d")
- (plus:DI (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
- (match_operand:DI 2 "general_operand" "d,m"))
- (match_operand:DI 3 "s390_alc_comparison" "")))
- (clobber (reg:CC 33))]
- "TARGET_64BIT"
- "@
- alcgr\\t%0,%2
- alcg\\t%0,%2"
- [(set_attr "op_type" "RRE,RXY")])
-
-(define_insn "*subdi3_slb_cc"
- [(set (reg 33)
- (compare
- (minus:DI (minus:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
- (match_operand:DI 2 "general_operand" "d,m"))
- (match_operand:DI 3 "s390_slb_comparison" ""))
- (const_int 0)))
- (set (match_operand:DI 0 "register_operand" "=d,d")
- (minus:DI (minus:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
- "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
- "@
- slbgr\\t%0,%2
- slbg\\t%0,%2"
- [(set_attr "op_type" "RRE,RXY")])
-
-(define_insn "*subdi3_slb"
- [(set (match_operand:DI 0 "register_operand" "=d,d")
- (minus:DI (minus:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
- (match_operand:DI 2 "general_operand" "d,m"))
- (match_operand:DI 3 "s390_slb_comparison" "")))
- (clobber (reg:CC 33))]
- "TARGET_64BIT"
+ (set_attr "type" "fsimp<mode>")])
+
+(define_insn "*sub<mode>3_ibm"
+ [(set (match_operand:FPR 0 "register_operand" "=f,f")
+ (minus:FPR (match_operand:FPR 1 "register_operand" "0,0")
+ (match_operand:FPR 2 "general_operand" "f,R")))
+ (clobber (reg:CC CC_REGNUM))]
+ "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
"@
- slbgr\\t%0,%2
- slbg\\t%0,%2"
- [(set_attr "op_type" "RRE,RXY")])
+ s<de>r\t%0,%2
+ s<de>\t%0,%2"
+ [(set_attr "op_type" "RR,RX")
+ (set_attr "type" "fsimp<mode>")])
-(define_expand "adddicc"
- [(match_operand:DI 0 "register_operand" "")
- (match_operand 1 "comparison_operator" "")
- (match_operand:DI 2 "register_operand" "")
- (match_operand:DI 3 "const_int_operand" "")]
- "TARGET_64BIT"
- "if (!s390_expand_addcc (GET_CODE (operands[1]),
- s390_compare_op0, s390_compare_op1,
- operands[0], operands[2],
- operands[3])) FAIL; DONE;")
+
+;;
+;;- Conditional add/subtract instructions.
+;;
;
-; addsicc instruction pattern(s).
+; add(di|si)cc instruction pattern(s).
;
-(define_insn "*addsi3_alc_cc"
- [(set (reg 33)
+(define_insn "*add<mode>3_alc_cc"
+ [(set (reg CC_REGNUM)
(compare
- (plus:SI (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
- (match_operand:SI 2 "general_operand" "d,m"))
- (match_operand:SI 3 "s390_alc_comparison" ""))
+ (plus:GPR (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0")
+ (match_operand:GPR 2 "general_operand" "d,m"))
+ (match_operand:GPR 3 "s390_alc_comparison" ""))
(const_int 0)))
- (set (match_operand:SI 0 "register_operand" "=d,d")
- (plus:SI (plus:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
+ (set (match_operand:GPR 0 "register_operand" "=d,d")
+ (plus:GPR (plus:GPR (match_dup 1) (match_dup 2)) (match_dup 3)))]
"s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH"
"@
- alcr\\t%0,%2
- alc\\t%0,%2"
+ alc<g>r\t%0,%2
+ alc<g>\t%0,%2"
[(set_attr "op_type" "RRE,RXY")])
-(define_insn "*addsi3_alc"
- [(set (match_operand:SI 0 "register_operand" "=d,d")
- (plus:SI (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
- (match_operand:SI 2 "general_operand" "d,m"))
- (match_operand:SI 3 "s390_alc_comparison" "")))
- (clobber (reg:CC 33))]
+(define_insn "*add<mode>3_alc"
+ [(set (match_operand:GPR 0 "register_operand" "=d,d")
+ (plus:GPR (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0")
+ (match_operand:GPR 2 "general_operand" "d,m"))
+ (match_operand:GPR 3 "s390_alc_comparison" "")))
+ (clobber (reg:CC CC_REGNUM))]
"TARGET_CPU_ZARCH"
"@
- alcr\\t%0,%2
- alc\\t%0,%2"
+ alc<g>r\t%0,%2
+ alc<g>\t%0,%2"
[(set_attr "op_type" "RRE,RXY")])
-(define_insn "*subsi3_slb_cc"
- [(set (reg 33)
+(define_insn "*sub<mode>3_slb_cc"
+ [(set (reg CC_REGNUM)
(compare
- (minus:SI (minus:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
- (match_operand:SI 2 "general_operand" "d,m"))
- (match_operand:SI 3 "s390_slb_comparison" ""))
+ (minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0")
+ (match_operand:GPR 2 "general_operand" "d,m"))
+ (match_operand:GPR 3 "s390_slb_comparison" ""))
(const_int 0)))
- (set (match_operand:SI 0 "register_operand" "=d,d")
- (minus:SI (minus:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
+ (set (match_operand:GPR 0 "register_operand" "=d,d")
+ (minus:GPR (minus:GPR (match_dup 1) (match_dup 2)) (match_dup 3)))]
"s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH"
"@
- slbr\\t%0,%2
- slb\\t%0,%2"
+ slb<g>r\t%0,%2
+ slb<g>\t%0,%2"
[(set_attr "op_type" "RRE,RXY")])
-(define_insn "*subsi3_slb"
- [(set (match_operand:SI 0 "register_operand" "=d,d")
- (minus:SI (minus:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
- (match_operand:SI 2 "general_operand" "d,m"))
- (match_operand:SI 3 "s390_slb_comparison" "")))
- (clobber (reg:CC 33))]
+(define_insn "*sub<mode>3_slb"
+ [(set (match_operand:GPR 0 "register_operand" "=d,d")
+ (minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0")
+ (match_operand:GPR 2 "general_operand" "d,m"))
+ (match_operand:GPR 3 "s390_slb_comparison" "")))
+ (clobber (reg:CC CC_REGNUM))]
"TARGET_CPU_ZARCH"
"@
- slbr\\t%0,%2
- slb\\t%0,%2"
+ slb<g>r\t%0,%2
+ slb<g>\t%0,%2"
[(set_attr "op_type" "RRE,RXY")])
-(define_expand "addsicc"
- [(match_operand:SI 0 "register_operand" "")
+(define_expand "add<mode>cc"
+ [(match_operand:GPR 0 "register_operand" "")
(match_operand 1 "comparison_operator" "")
- (match_operand:SI 2 "register_operand" "")
- (match_operand:SI 3 "const_int_operand" "")]
+ (match_operand:GPR 2 "register_operand" "")
+ (match_operand:GPR 3 "const_int_operand" "")]
"TARGET_CPU_ZARCH"
"if (!s390_expand_addcc (GET_CODE (operands[1]),
s390_compare_op0, s390_compare_op1,
; scond instruction pattern(s).
;
-(define_insn_and_split "*sconddi"
- [(set (match_operand:DI 0 "register_operand" "=&d")
- (match_operand:DI 1 "s390_alc_comparison" ""))
- (clobber (reg:CC 33))]
- "TARGET_64BIT"
- "#"
- "&& reload_completed"
- [(set (match_dup 0) (const_int 0))
- (parallel
- [(set (match_dup 0) (plus:DI (plus:DI (match_dup 0) (match_dup 0))
- (match_dup 1)))
- (clobber (reg:CC 33))])]
- ""
- [(set_attr "op_type" "NN")])
-
-(define_insn_and_split "*scondsi"
- [(set (match_operand:SI 0 "register_operand" "=&d")
- (match_operand:SI 1 "s390_alc_comparison" ""))
- (clobber (reg:CC 33))]
+(define_insn_and_split "*scond<mode>"
+ [(set (match_operand:GPR 0 "register_operand" "=&d")
+ (match_operand:GPR 1 "s390_alc_comparison" ""))
+ (clobber (reg:CC CC_REGNUM))]
"TARGET_CPU_ZARCH"
"#"
"&& reload_completed"
[(set (match_dup 0) (const_int 0))
(parallel
- [(set (match_dup 0) (plus:SI (plus:SI (match_dup 0) (match_dup 0))
- (match_dup 1)))
- (clobber (reg:CC 33))])]
- ""
- [(set_attr "op_type" "NN")])
-
-(define_insn_and_split "*sconddi_neg"
- [(set (match_operand:DI 0 "register_operand" "=&d")
- (match_operand:DI 1 "s390_slb_comparison" ""))
- (clobber (reg:CC 33))]
- "TARGET_64BIT"
- "#"
- "&& reload_completed"
- [(set (match_dup 0) (const_int 0))
- (parallel
- [(set (match_dup 0) (minus:DI (minus:DI (match_dup 0) (match_dup 0))
+ [(set (match_dup 0) (plus:GPR (plus:GPR (match_dup 0) (match_dup 0))
(match_dup 1)))
- (clobber (reg:CC 33))])
- (parallel
- [(set (match_dup 0) (neg:DI (match_dup 0)))
- (clobber (reg:CC 33))])]
- ""
- [(set_attr "op_type" "NN")])
+ (clobber (reg:CC CC_REGNUM))])]
+ "")
-(define_insn_and_split "*scondsi_neg"
- [(set (match_operand:SI 0 "register_operand" "=&d")
- (match_operand:SI 1 "s390_slb_comparison" ""))
- (clobber (reg:CC 33))]
+(define_insn_and_split "*scond<mode>_neg"
+ [(set (match_operand:GPR 0 "register_operand" "=&d")
+ (match_operand:GPR 1 "s390_slb_comparison" ""))
+ (clobber (reg:CC CC_REGNUM))]
"TARGET_CPU_ZARCH"
"#"
"&& reload_completed"
[(set (match_dup 0) (const_int 0))
(parallel
- [(set (match_dup 0) (minus:SI (minus:SI (match_dup 0) (match_dup 0))
- (match_dup 1)))
- (clobber (reg:CC 33))])
+ [(set (match_dup 0) (minus:GPR (minus:GPR (match_dup 0) (match_dup 0))
+ (match_dup 1)))
+ (clobber (reg:CC CC_REGNUM))])
(parallel
- [(set (match_dup 0) (neg:SI (match_dup 0)))
- (clobber (reg:CC 33))])]
- ""
- [(set_attr "op_type" "NN")])
-
-(define_expand "sltu"
- [(match_operand:SI 0 "register_operand" "")]
- "TARGET_CPU_ZARCH"
- "if (!s390_expand_addcc (LTU, s390_compare_op0, s390_compare_op1,
- operands[0], const0_rtx, const1_rtx)) FAIL; DONE;")
-
-(define_expand "sgtu"
- [(match_operand:SI 0 "register_operand" "")]
- "TARGET_CPU_ZARCH"
- "if (!s390_expand_addcc (GTU, s390_compare_op0, s390_compare_op1,
- operands[0], const0_rtx, const1_rtx)) FAIL; DONE;")
+ [(set (match_dup 0) (neg:GPR (match_dup 0)))
+ (clobber (reg:CC CC_REGNUM))])]
+ "")
-(define_expand "sleu"
- [(match_operand:SI 0 "register_operand" "")]
- "TARGET_CPU_ZARCH"
- "if (!s390_expand_addcc (LEU, s390_compare_op0, s390_compare_op1,
- operands[0], const0_rtx, const1_rtx)) FAIL; DONE;")
-(define_expand "sgeu"
- [(match_operand:SI 0 "register_operand" "")]
+(define_expand "s<code>"
+ [(set (match_operand:SI 0 "register_operand" "")
+ (SCOND (match_dup 0)
+ (match_dup 0)))]
"TARGET_CPU_ZARCH"
- "if (!s390_expand_addcc (GEU, s390_compare_op0, s390_compare_op1,
+ "if (!s390_expand_addcc (<CODE>, s390_compare_op0, s390_compare_op1,
operands[0], const0_rtx, const1_rtx)) FAIL; DONE;")
msgfr\t%0,%2
msgf\t%0,%2"
[(set_attr "op_type" "RRE,RXY")
- (set_attr "type" "imul")])
+ (set_attr "type" "imuldi")])
(define_insn "muldi3"
[(set (match_operand:DI 0 "register_operand" "=d,d,d")
mghi\t%0,%h2
msg\t%0,%2"
[(set_attr "op_type" "RRE,RI,RXY")
- (set_attr "type" "imul")])
+ (set_attr "type" "imuldi")])
;
; mulsi3 instruction pattern(s).
""
"mh\t%0,%2"
[(set_attr "op_type" "RX")
- (set_attr "type" "imul")])
+ (set_attr "type" "imulhi")])
(define_insn "mulsi3"
[(set (match_operand:SI 0 "register_operand" "=d,d,d,d")
ms\t%0,%2
msy\t%0,%2"
[(set_attr "op_type" "RRE,RI,RX,RXY")
- (set_attr "type" "imul")])
+ (set_attr "type" "imulsi,imulhi,imulsi,imulsi")])
;
; mulsidi3 instruction pattern(s).
mr\t%0,%2
m\t%0,%2"
[(set_attr "op_type" "RR,RX")
- (set_attr "type" "imul")])
+ (set_attr "type" "imulsi")])
;
; umulsidi3 instruction pattern(s).
mlr\t%0,%2
ml\t%0,%2"
[(set_attr "op_type" "RRE,RXY")
- (set_attr "type" "imul")])
-
-;
-; muldf3 instruction pattern(s).
-;
-
-(define_expand "muldf3"
- [(set (match_operand:DF 0 "register_operand" "=f,f")
- (mult:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0")
- (match_operand:DF 2 "general_operand" "f,R")))]
- "TARGET_HARD_FLOAT"
- "")
-
-(define_insn "*muldf3"
- [(set (match_operand:DF 0 "register_operand" "=f,f")
- (mult:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0")
- (match_operand:DF 2 "general_operand" "f,R")))]
- "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
- "@
- mdbr\t%0,%2
- mdb\t%0,%2"
- [(set_attr "op_type" "RRE,RXE")
- (set_attr "type" "fmuld")])
-
-(define_insn "*muldf3_ibm"
- [(set (match_operand:DF 0 "register_operand" "=f,f")
- (mult:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0")
- (match_operand:DF 2 "general_operand" "f,R")))]
- "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
- "@
- mdr\t%0,%2
- md\t%0,%2"
- [(set_attr "op_type" "RR,RX")
- (set_attr "type" "fmuld")])
-
-(define_insn "*fmadddf"
- [(set (match_operand:DF 0 "register_operand" "=f,f")
- (plus:DF (mult:DF (match_operand:DF 1 "register_operand" "%f,f")
- (match_operand:DF 2 "nonimmediate_operand" "f,R"))
- (match_operand:DF 3 "register_operand" "0,0")))]
- "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT && TARGET_FUSED_MADD"
- "@
- madbr\t%0,%1,%2
- madb\t%0,%1,%2"
- [(set_attr "op_type" "RRE,RXE")
- (set_attr "type" "fmuld")])
-
-(define_insn "*fmsubdf"
- [(set (match_operand:DF 0 "register_operand" "=f,f")
- (minus:DF (mult:DF (match_operand:DF 1 "register_operand" "f,f")
- (match_operand:DF 2 "nonimmediate_operand" "f,R"))
- (match_operand:DF 3 "register_operand" "0,0")))]
- "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT && TARGET_FUSED_MADD"
- "@
- msdbr\t%0,%1,%2
- msdb\t%0,%1,%2"
- [(set_attr "op_type" "RRE,RXE")
- (set_attr "type" "fmuld")])
+ (set_attr "type" "imulsi")])
;
-; mulsf3 instruction pattern(s).
+; mul(df|sf)3 instruction pattern(s).
;
-(define_expand "mulsf3"
- [(set (match_operand:SF 0 "register_operand" "=f,f")
- (mult:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0")
- (match_operand:SF 2 "general_operand" "f,R")))]
+(define_expand "mul<mode>3"
+ [(set (match_operand:FPR 0 "register_operand" "=f,f")
+ (mult:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
+ (match_operand:FPR 2 "general_operand" "f,R")))]
"TARGET_HARD_FLOAT"
"")
-(define_insn "*mulsf3"
- [(set (match_operand:SF 0 "register_operand" "=f,f")
- (mult:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0")
- (match_operand:SF 2 "general_operand" "f,R")))]
+(define_insn "*mul<mode>3"
+ [(set (match_operand:FPR 0 "register_operand" "=f,f")
+ (mult:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
+ (match_operand:FPR 2 "general_operand" "f,R")))]
"TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"@
- meebr\t%0,%2
- meeb\t%0,%2"
+ m<dee>br\t%0,%2
+ m<dee>b\t%0,%2"
[(set_attr "op_type" "RRE,RXE")
- (set_attr "type" "fmuls")])
+ (set_attr "type" "fmul<mode>")])
-(define_insn "*mulsf3_ibm"
- [(set (match_operand:SF 0 "register_operand" "=f,f")
- (mult:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0")
- (match_operand:SF 2 "general_operand" "f,R")))]
+(define_insn "*mul<mode>3_ibm"
+ [(set (match_operand:FPR 0 "register_operand" "=f,f")
+ (mult:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
+ (match_operand:FPR 2 "general_operand" "f,R")))]
"TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
"@
- mer\t%0,%2
- me\t%0,%2"
+ m<de>r\t%0,%2
+ m<de>\t%0,%2"
[(set_attr "op_type" "RR,RX")
- (set_attr "type" "fmuls")])
+ (set_attr "type" "fmul<mode>")])
-(define_insn "*fmaddsf"
- [(set (match_operand:SF 0 "register_operand" "=f,f")
- (plus:SF (mult:SF (match_operand:SF 1 "register_operand" "%f,f")
- (match_operand:SF 2 "nonimmediate_operand" "f,R"))
- (match_operand:SF 3 "register_operand" "0,0")))]
+(define_insn "*fmadd<mode>"
+ [(set (match_operand:FPR 0 "register_operand" "=f,f")
+ (plus:FPR (mult:FPR (match_operand:FPR 1 "register_operand" "%f,f")
+ (match_operand:FPR 2 "nonimmediate_operand" "f,R"))
+ (match_operand:FPR 3 "register_operand" "0,0")))]
"TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT && TARGET_FUSED_MADD"
"@
- maebr\t%0,%1,%2
- maeb\t%0,%1,%2"
+ ma<de>br\t%0,%1,%2
+ ma<de>b\t%0,%1,%2"
[(set_attr "op_type" "RRE,RXE")
- (set_attr "type" "fmuls")])
+ (set_attr "type" "fmul<mode>")])
-(define_insn "*fmsubsf"
- [(set (match_operand:SF 0 "register_operand" "=f,f")
- (minus:SF (mult:SF (match_operand:SF 1 "register_operand" "f,f")
- (match_operand:SF 2 "nonimmediate_operand" "f,R"))
- (match_operand:SF 3 "register_operand" "0,0")))]
+(define_insn "*fmsub<mode>"
+ [(set (match_operand:FPR 0 "register_operand" "=f,f")
+ (minus:FPR (mult:FPR (match_operand:FPR 1 "register_operand" "f,f")
+ (match_operand:FPR 2 "nonimmediate_operand" "f,R"))
+ (match_operand:FPR 3 "register_operand" "0,0")))]
"TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT && TARGET_FUSED_MADD"
"@
- msebr\t%0,%1,%2
- mseb\t%0,%1,%2"
+ ms<de>br\t%0,%1,%2
+ ms<de>b\t%0,%1,%2"
[(set_attr "op_type" "RRE,RXE")
- (set_attr "type" "fmuls")])
+ (set_attr "type" "fmul<mode>")])
;;
;;- Divide and modulo instructions.
})
;
-; divdf3 instruction pattern(s).
-;
-
-(define_expand "divdf3"
- [(set (match_operand:DF 0 "register_operand" "=f,f")
- (div:DF (match_operand:DF 1 "register_operand" "0,0")
- (match_operand:DF 2 "general_operand" "f,R")))]
- "TARGET_HARD_FLOAT"
- "")
-
-(define_insn "*divdf3"
- [(set (match_operand:DF 0 "register_operand" "=f,f")
- (div:DF (match_operand:DF 1 "register_operand" "0,0")
- (match_operand:DF 2 "general_operand" "f,R")))]
- "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
- "@
- ddbr\t%0,%2
- ddb\t%0,%2"
- [(set_attr "op_type" "RRE,RXE")
- (set_attr "type" "fdivd")])
-
-(define_insn "*divdf3_ibm"
- [(set (match_operand:DF 0 "register_operand" "=f,f")
- (div:DF (match_operand:DF 1 "register_operand" "0,0")
- (match_operand:DF 2 "general_operand" "f,R")))]
- "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
- "@
- ddr\t%0,%2
- dd\t%0,%2"
- [(set_attr "op_type" "RR,RX")
- (set_attr "type" "fdivd")])
-
-;
-; divsf3 instruction pattern(s).
+; div(df|sf)3 instruction pattern(s).
;
-(define_expand "divsf3"
- [(set (match_operand:SF 0 "register_operand" "=f,f")
- (div:SF (match_operand:SF 1 "register_operand" "0,0")
- (match_operand:SF 2 "general_operand" "f,R")))]
+(define_expand "div<mode>3"
+ [(set (match_operand:FPR 0 "register_operand" "=f,f")
+ (div:FPR (match_operand:FPR 1 "register_operand" "0,0")
+ (match_operand:FPR 2 "general_operand" "f,R")))]
"TARGET_HARD_FLOAT"
"")
-(define_insn "*divsf3"
- [(set (match_operand:SF 0 "register_operand" "=f,f")
- (div:SF (match_operand:SF 1 "register_operand" "0,0")
- (match_operand:SF 2 "general_operand" "f,R")))]
+(define_insn "*div<mode>3"
+ [(set (match_operand:FPR 0 "register_operand" "=f,f")
+ (div:FPR (match_operand:FPR 1 "register_operand" "0,0")
+ (match_operand:FPR 2 "general_operand" "f,R")))]
"TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"@
- debr\t%0,%2
- deb\t%0,%2"
+ d<de>br\t%0,%2
+ d<de>b\t%0,%2"
[(set_attr "op_type" "RRE,RXE")
- (set_attr "type" "fdivs")])
+ (set_attr "type" "fdiv<mode>")])
-(define_insn "*divsf3"
- [(set (match_operand:SF 0 "register_operand" "=f,f")
- (div:SF (match_operand:SF 1 "register_operand" "0,0")
- (match_operand:SF 2 "general_operand" "f,R")))]
+(define_insn "*div<mode>3_ibm"
+ [(set (match_operand:FPR 0 "register_operand" "=f,f")
+ (div:FPR (match_operand:FPR 1 "register_operand" "0,0")
+ (match_operand:FPR 2 "general_operand" "f,R")))]
"TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
"@
- der\t%0,%2
- de\t%0,%2"
+ d<de>r\t%0,%2
+ d<de>\t%0,%2"
[(set_attr "op_type" "RR,RX")
- (set_attr "type" "fdivs")])
+ (set_attr "type" "fdiv<mode>")])
;;
;;- And instructions.
;;
+(define_expand "and<mode>3"
+ [(set (match_operand:INT 0 "nonimmediate_operand" "")
+ (and:INT (match_operand:INT 1 "nonimmediate_operand" "")
+ (match_operand:INT 2 "general_operand" "")))
+ (clobber (reg:CC CC_REGNUM))]
+ ""
+ "s390_expand_logical_operator (AND, <MODE>mode, operands); DONE;")
+
;
; anddi3 instruction pattern(s).
;
(define_insn "*anddi3_cc"
- [(set (reg 33)
+ [(set (reg CC_REGNUM)
(compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
(match_operand:DI 2 "general_operand" "d,m"))
(const_int 0)))
[(set_attr "op_type" "RRE,RXY")])
(define_insn "*anddi3_cconly"
- [(set (reg 33)
+ [(set (reg CC_REGNUM)
(compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
(match_operand:DI 2 "general_operand" "d,m"))
(const_int 0)))
[(set_attr "op_type" "RRE,RXY")])
(define_insn "*anddi3"
- [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,d,d,d,Q")
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,d,d,d,AQ,Q")
(and:DI (match_operand:DI 1 "nonimmediate_operand"
- "%d,o,0,0,0,0,0,0,0")
+ "%d,o,0,0,0,0,0,0,0,0")
(match_operand:DI 2 "general_operand"
- "M,M,N0HDF,N1HDF,N2HDF,N3HDF,d,m,Q")))
- (clobber (reg:CC 33))]
+ "M,M,N0HDF,N1HDF,N2HDF,N3HDF,d,m,NxQDF,Q")))
+ (clobber (reg:CC CC_REGNUM))]
"TARGET_64BIT && s390_logical_operator_ok_p (operands)"
"@
#
nill\t%0,%j2
ngr\t%0,%2
ng\t%0,%2
- nc\t%O0(8,%R0),%2"
- [(set_attr "op_type" "RRE,RXE,RI,RI,RI,RI,RRE,RXY,SS")])
+ #
+ #"
+ [(set_attr "op_type" "RRE,RXE,RI,RI,RI,RI,RRE,RXY,SI,SS")])
+
+(define_split
+ [(set (match_operand:DI 0 "s_operand" "")
+ (and:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" "")))
+ (clobber (reg:CC CC_REGNUM))]
+ "reload_completed"
+ [(parallel
+ [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
+ (clobber (reg:CC CC_REGNUM))])]
+ "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);")
-(define_expand "anddi3"
- [(set (match_operand:DI 0 "nonimmediate_operand" "")
- (and:DI (match_operand:DI 1 "nonimmediate_operand" "")
- (match_operand:DI 2 "general_operand" "")))
- (clobber (reg:CC 33))]
- "TARGET_64BIT"
- "s390_expand_logical_operator (AND, DImode, operands); DONE;")
;
; andsi3 instruction pattern(s).
;
(define_insn "*andsi3_cc"
- [(set (reg 33)
+ [(set (reg CC_REGNUM)
(compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
(match_operand:SI 2 "general_operand" "d,R,T"))
(const_int 0)))
[(set_attr "op_type" "RR,RX,RXY")])
(define_insn "*andsi3_cconly"
- [(set (reg 33)
+ [(set (reg CC_REGNUM)
(compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
(match_operand:SI 2 "general_operand" "d,R,T"))
(const_int 0)))
[(set_attr "op_type" "RR,RX,RXY")])
(define_insn "*andsi3_zarch"
- [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d,d,d,Q")
- (and:SI (match_operand:SI 1 "nonimmediate_operand" "%d,o,0,0,0,0,0,0")
- (match_operand:SI 2 "general_operand" "M,M,N0HSF,N1HSF,d,R,T,Q")))
- (clobber (reg:CC 33))]
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d,d,d,AQ,Q")
+ (and:SI (match_operand:SI 1 "nonimmediate_operand"
+ "%d,o,0,0,0,0,0,0,0")
+ (match_operand:SI 2 "general_operand"
+ "M,M,N0HSF,N1HSF,d,R,T,NxQSF,Q")))
+ (clobber (reg:CC CC_REGNUM))]
"TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
"@
#
nr\t%0,%2
n\t%0,%2
ny\t%0,%2
- nc\t%O0(4,%R0),%2"
- [(set_attr "op_type" "RRE,RXE,RI,RI,RR,RX,RXY,SS")])
+ #
+ #"
+ [(set_attr "op_type" "RRE,RXE,RI,RI,RR,RX,RXY,SI,SS")])
(define_insn "*andsi3_esa"
- [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,Q")
- (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
- (match_operand:SI 2 "general_operand" "d,R,Q")))
- (clobber (reg:CC 33))]
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,AQ,Q")
+ (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
+ (match_operand:SI 2 "general_operand" "d,R,NxQSF,Q")))
+ (clobber (reg:CC CC_REGNUM))]
"!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
"@
nr\t%0,%2
n\t%0,%2
- nc\t%O0(4,%R0),%2"
- [(set_attr "op_type" "RR,RX,SS")])
-
-(define_expand "andsi3"
- [(set (match_operand:SI 0 "nonimmediate_operand" "")
- (and:SI (match_operand:SI 1 "nonimmediate_operand" "")
- (match_operand:SI 2 "general_operand" "")))
- (clobber (reg:CC 33))]
- ""
- "s390_expand_logical_operator (AND, SImode, operands); DONE;")
+ #
+ #"
+ [(set_attr "op_type" "RR,RX,SI,SS")])
+
+(define_split
+ [(set (match_operand:SI 0 "s_operand" "")
+ (and:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" "")))
+ (clobber (reg:CC CC_REGNUM))]
+ "reload_completed"
+ [(parallel
+ [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
+ (clobber (reg:CC CC_REGNUM))])]
+ "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);")
;
; andhi3 instruction pattern(s).
;
(define_insn "*andhi3_zarch"
- [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,Q")
- (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0")
- (match_operand:HI 2 "general_operand" "d,n,Q")))
- (clobber (reg:CC 33))]
+ [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,AQ,Q")
+ (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0,0")
+ (match_operand:HI 2 "general_operand" "d,n,NxQHF,Q")))
+ (clobber (reg:CC CC_REGNUM))]
"TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
"@
nr\t%0,%2
nill\t%0,%x2
- nc\t%O0(2,%R0),%2"
- [(set_attr "op_type" "RR,RI,SS")])
+ #
+ #"
+ [(set_attr "op_type" "RR,RI,SI,SS")])
(define_insn "*andhi3_esa"
- [(set (match_operand:HI 0 "nonimmediate_operand" "=d,Q")
- (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
- (match_operand:HI 2 "general_operand" "d,Q")))
- (clobber (reg:CC 33))]
+ [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q")
+ (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0")
+ (match_operand:HI 2 "general_operand" "d,NxQHF,Q")))
+ (clobber (reg:CC CC_REGNUM))]
"!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
"@
nr\t%0,%2
- nc\t%O0(2,%R0),%2"
- [(set_attr "op_type" "RR,SS")])
+ #
+ #"
+ [(set_attr "op_type" "RR,SI,SS")])
-(define_expand "andhi3"
- [(set (match_operand:HI 0 "nonimmediate_operand" "")
- (and:HI (match_operand:HI 1 "nonimmediate_operand" "")
- (match_operand:HI 2 "general_operand" "")))
- (clobber (reg:CC 33))]
- ""
- "s390_expand_logical_operator (AND, HImode, operands); DONE;")
+(define_split
+ [(set (match_operand:HI 0 "s_operand" "")
+ (and:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" "")))
+ (clobber (reg:CC CC_REGNUM))]
+ "reload_completed"
+ [(parallel
+ [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
+ (clobber (reg:CC CC_REGNUM))])]
+ "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);")
;
; andqi3 instruction pattern(s).
[(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,Q,S,Q")
(and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0,0,0")
(match_operand:QI 2 "general_operand" "d,n,n,n,Q")))
- (clobber (reg:CC 33))]
+ (clobber (reg:CC CC_REGNUM))]
"TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
"@
nr\t%0,%2
nill\t%0,%b2
- ni\t%0,%b2
- niy\t%0,%b2
- nc\t%O0(1,%R0),%2"
+ ni\t%S0,%b2
+ niy\t%S0,%b2
+ #"
[(set_attr "op_type" "RR,RI,SI,SIY,SS")])
(define_insn "*andqi3_esa"
[(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q")
(and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
(match_operand:QI 2 "general_operand" "d,n,Q")))
- (clobber (reg:CC 33))]
+ (clobber (reg:CC CC_REGNUM))]
"!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
"@
nr\t%0,%2
- ni\t%0,%b2
- nc\t%O0(1,%R0),%2"
+ ni\t%S0,%b2
+ #"
[(set_attr "op_type" "RR,SI,SS")])
-(define_expand "andqi3"
- [(set (match_operand:QI 0 "nonimmediate_operand" "")
- (and:QI (match_operand:QI 1 "nonimmediate_operand" "")
- (match_operand:QI 2 "general_operand" "")))
- (clobber (reg:CC 33))]
- ""
- "s390_expand_logical_operator (AND, QImode, operands); DONE;")
+;
+; Block and (NC) patterns.
+;
+
+(define_insn "*nc"
+ [(set (match_operand:BLK 0 "memory_operand" "=Q")
+ (and:BLK (match_dup 0)
+ (match_operand:BLK 1 "memory_operand" "Q")))
+ (use (match_operand 2 "const_int_operand" "n"))
+ (clobber (reg:CC CC_REGNUM))]
+ "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
+ "nc\t%O0(%2,%R0),%S1"
+ [(set_attr "op_type" "SS")])
+
+(define_split
+ [(set (match_operand 0 "memory_operand" "")
+ (and (match_dup 0)
+ (match_operand 1 "memory_operand" "")))
+ (clobber (reg:CC CC_REGNUM))]
+ "reload_completed
+ && GET_MODE (operands[0]) == GET_MODE (operands[1])
+ && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
+ [(parallel
+ [(set (match_dup 0) (and:BLK (match_dup 0) (match_dup 1)))
+ (use (match_dup 2))
+ (clobber (reg:CC CC_REGNUM))])]
+{
+ operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
+ operands[0] = adjust_address (operands[0], BLKmode, 0);
+ operands[1] = adjust_address (operands[1], BLKmode, 0);
+})
+
+(define_peephole2
+ [(parallel
+ [(set (match_operand:BLK 0 "memory_operand" "")
+ (and:BLK (match_dup 0)
+ (match_operand:BLK 1 "memory_operand" "")))
+ (use (match_operand 2 "const_int_operand" ""))
+ (clobber (reg:CC CC_REGNUM))])
+ (parallel
+ [(set (match_operand:BLK 3 "memory_operand" "")
+ (and:BLK (match_dup 3)
+ (match_operand:BLK 4 "memory_operand" "")))
+ (use (match_operand 5 "const_int_operand" ""))
+ (clobber (reg:CC CC_REGNUM))])]
+ "s390_offset_p (operands[0], operands[3], operands[2])
+ && s390_offset_p (operands[1], operands[4], operands[2])
+ && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
+ [(parallel
+ [(set (match_dup 6) (and:BLK (match_dup 6) (match_dup 7)))
+ (use (match_dup 8))
+ (clobber (reg:CC CC_REGNUM))])]
+ "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
+ operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
+ operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
;;
;;- Bit set (inclusive or) instructions.
;;
+(define_expand "ior<mode>3"
+ [(set (match_operand:INT 0 "nonimmediate_operand" "")
+ (ior:INT (match_operand:INT 1 "nonimmediate_operand" "")
+ (match_operand:INT 2 "general_operand" "")))
+ (clobber (reg:CC CC_REGNUM))]
+ ""
+ "s390_expand_logical_operator (IOR, <MODE>mode, operands); DONE;")
+
;
; iordi3 instruction pattern(s).
;
(define_insn "*iordi3_cc"
- [(set (reg 33)
+ [(set (reg CC_REGNUM)
(compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
(match_operand:DI 2 "general_operand" "d,m"))
(const_int 0)))
[(set_attr "op_type" "RRE,RXY")])
(define_insn "*iordi3_cconly"
- [(set (reg 33)
+ [(set (reg CC_REGNUM)
(compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
(match_operand:DI 2 "general_operand" "d,m"))
(const_int 0)))
[(set_attr "op_type" "RRE,RXY")])
(define_insn "*iordi3"
- [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,d,Q")
- (ior:DI (match_operand:DI 1 "nonimmediate_operand" "0,0,0,0,0,0,0")
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,d,AQ,Q")
+ (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0,0,0,0,0")
(match_operand:DI 2 "general_operand"
- "N0HD0,N1HD0,N2HD0,N3HD0,d,m,Q")))
- (clobber (reg:CC 33))]
+ "N0HD0,N1HD0,N2HD0,N3HD0,d,m,NxQD0,Q")))
+ (clobber (reg:CC CC_REGNUM))]
"TARGET_64BIT && s390_logical_operator_ok_p (operands)"
"@
oihh\t%0,%i2
oill\t%0,%i2
ogr\t%0,%2
og\t%0,%2
- oc\t%O0(8,%R0),%2"
- [(set_attr "op_type" "RI,RI,RI,RI,RRE,RXY,SS")])
+ #
+ #"
+ [(set_attr "op_type" "RI,RI,RI,RI,RRE,RXY,SI,SS")])
-(define_expand "iordi3"
- [(set (match_operand:DI 0 "nonimmediate_operand" "")
- (ior:DI (match_operand:DI 1 "nonimmediate_operand" "")
- (match_operand:DI 2 "general_operand" "")))
- (clobber (reg:CC 33))]
- "TARGET_64BIT"
- "s390_expand_logical_operator (IOR, DImode, operands); DONE;")
+(define_split
+ [(set (match_operand:DI 0 "s_operand" "")
+ (ior:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" "")))
+ (clobber (reg:CC CC_REGNUM))]
+ "reload_completed"
+ [(parallel
+ [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1)))
+ (clobber (reg:CC CC_REGNUM))])]
+ "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);")
;
; iorsi3 instruction pattern(s).
;
(define_insn "*iorsi3_cc"
- [(set (reg 33)
+ [(set (reg CC_REGNUM)
(compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
(match_operand:SI 2 "general_operand" "d,R,T"))
(const_int 0)))
[(set_attr "op_type" "RR,RX,RXY")])
(define_insn "*iorsi3_cconly"
- [(set (reg 33)
+ [(set (reg CC_REGNUM)
(compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
(match_operand:SI 2 "general_operand" "d,R,T"))
(const_int 0)))
[(set_attr "op_type" "RR,RX,RXY")])
(define_insn "*iorsi3_zarch"
- [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d,Q")
- (ior:SI (match_operand:SI 1 "nonimmediate_operand" "0,0,0,0,0,0")
- (match_operand:SI 2 "general_operand" "N0HS0,N1HS0,d,R,T,Q")))
- (clobber (reg:CC 33))]
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d,AQ,Q")
+ (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0,0,0,0")
+ (match_operand:SI 2 "general_operand" "N0HS0,N1HS0,d,R,T,NxQS0,Q")))
+ (clobber (reg:CC CC_REGNUM))]
"TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
"@
oilh\t%0,%i2
or\t%0,%2
o\t%0,%2
oy\t%0,%2
- oc\t%O0(4,%R0),%2"
- [(set_attr "op_type" "RI,RI,RR,RX,RXY,SS")])
+ #
+ #"
+ [(set_attr "op_type" "RI,RI,RR,RX,RXY,SI,SS")])
(define_insn "*iorsi3_esa"
- [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,Q")
- (ior:SI (match_operand:SI 1 "nonimmediate_operand" "0,0,0")
- (match_operand:SI 2 "general_operand" "d,R,Q")))
- (clobber (reg:CC 33))]
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,AQ,Q")
+ (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
+ (match_operand:SI 2 "general_operand" "d,R,NxQS0,Q")))
+ (clobber (reg:CC CC_REGNUM))]
"!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
"@
or\t%0,%2
o\t%0,%2
- oc\t%O0(4,%R0),%2"
- [(set_attr "op_type" "RR,RX,SS")])
-
-(define_expand "iorsi3"
- [(set (match_operand:SI 0 "nonimmediate_operand" "")
- (ior:SI (match_operand:SI 1 "nonimmediate_operand" "")
- (match_operand:SI 2 "general_operand" "")))
- (clobber (reg:CC 33))]
- ""
- "s390_expand_logical_operator (IOR, SImode, operands); DONE;")
+ #
+ #"
+ [(set_attr "op_type" "RR,RX,SI,SS")])
+
+(define_split
+ [(set (match_operand:SI 0 "s_operand" "")
+ (ior:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" "")))
+ (clobber (reg:CC CC_REGNUM))]
+ "reload_completed"
+ [(parallel
+ [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1)))
+ (clobber (reg:CC CC_REGNUM))])]
+ "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);")
;
; iorhi3 instruction pattern(s).
;
(define_insn "*iorhi3_zarch"
- [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,Q")
- (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0")
- (match_operand:HI 2 "general_operand" "d,n,Q")))
- (clobber (reg:CC 33))]
+ [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,AQ,Q")
+ (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0,0")
+ (match_operand:HI 2 "general_operand" "d,n,NxQH0,Q")))
+ (clobber (reg:CC CC_REGNUM))]
"TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
"@
or\t%0,%2
oill\t%0,%x2
- oc\t%O0(2,%R0),%2"
- [(set_attr "op_type" "RR,RI,SS")])
+ #
+ #"
+ [(set_attr "op_type" "RR,RI,SI,SS")])
(define_insn "*iorhi3_esa"
- [(set (match_operand:HI 0 "nonimmediate_operand" "=d,Q")
- (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
- (match_operand:HI 2 "general_operand" "d,Q")))
- (clobber (reg:CC 33))]
+ [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q")
+ (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0")
+ (match_operand:HI 2 "general_operand" "d,NxQH0,Q")))
+ (clobber (reg:CC CC_REGNUM))]
"!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
"@
or\t%0,%2
- oc\t%O0(2,%R0),%2"
- [(set_attr "op_type" "RR,SS")])
+ #
+ #"
+ [(set_attr "op_type" "RR,SI,SS")])
-(define_expand "iorhi3"
- [(set (match_operand:HI 0 "nonimmediate_operand" "")
- (ior:HI (match_operand:HI 1 "nonimmediate_operand" "")
- (match_operand:HI 2 "general_operand" "")))
- (clobber (reg:CC 33))]
- ""
- "s390_expand_logical_operator (IOR, HImode, operands); DONE;")
+(define_split
+ [(set (match_operand:HI 0 "s_operand" "")
+ (ior:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" "")))
+ (clobber (reg:CC CC_REGNUM))]
+ "reload_completed"
+ [(parallel
+ [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1)))
+ (clobber (reg:CC CC_REGNUM))])]
+ "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);")
;
; iorqi3 instruction pattern(s).
[(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,Q,S,Q")
(ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0,0,0")
(match_operand:QI 2 "general_operand" "d,n,n,n,Q")))
- (clobber (reg:CC 33))]
+ (clobber (reg:CC CC_REGNUM))]
"TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
"@
or\t%0,%2
oill\t%0,%b2
- oi\t%0,%b2
- oiy\t%0,%b2
- oc\t%O0(1,%R0),%2"
+ oi\t%S0,%b2
+ oiy\t%S0,%b2
+ #"
[(set_attr "op_type" "RR,RI,SI,SIY,SS")])
(define_insn "*iorqi3_esa"
[(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q")
(ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
(match_operand:QI 2 "general_operand" "d,n,Q")))
- (clobber (reg:CC 33))]
+ (clobber (reg:CC CC_REGNUM))]
"!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
"@
or\t%0,%2
- oi\t%0,%b2
- oc\t%O0(1,%R0),%2"
+ oi\t%S0,%b2
+ #"
[(set_attr "op_type" "RR,SI,SS")])
-(define_expand "iorqi3"
- [(set (match_operand:QI 0 "nonimmediate_operand" "")
- (ior:QI (match_operand:QI 1 "nonimmediate_operand" "")
- (match_operand:QI 2 "general_operand" "")))
- (clobber (reg:CC 33))]
- ""
- "s390_expand_logical_operator (IOR, QImode, operands); DONE;")
+;
+; Block inclusive or (OC) patterns.
+;
+
+(define_insn "*oc"
+ [(set (match_operand:BLK 0 "memory_operand" "=Q")
+ (ior:BLK (match_dup 0)
+ (match_operand:BLK 1 "memory_operand" "Q")))
+ (use (match_operand 2 "const_int_operand" "n"))
+ (clobber (reg:CC CC_REGNUM))]
+ "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
+ "oc\t%O0(%2,%R0),%S1"
+ [(set_attr "op_type" "SS")])
+
+(define_split
+ [(set (match_operand 0 "memory_operand" "")
+ (ior (match_dup 0)
+ (match_operand 1 "memory_operand" "")))
+ (clobber (reg:CC CC_REGNUM))]
+ "reload_completed
+ && GET_MODE (operands[0]) == GET_MODE (operands[1])
+ && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
+ [(parallel
+ [(set (match_dup 0) (ior:BLK (match_dup 0) (match_dup 1)))
+ (use (match_dup 2))
+ (clobber (reg:CC CC_REGNUM))])]
+{
+ operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
+ operands[0] = adjust_address (operands[0], BLKmode, 0);
+ operands[1] = adjust_address (operands[1], BLKmode, 0);
+})
+
+(define_peephole2
+ [(parallel
+ [(set (match_operand:BLK 0 "memory_operand" "")
+ (ior:BLK (match_dup 0)
+ (match_operand:BLK 1 "memory_operand" "")))
+ (use (match_operand 2 "const_int_operand" ""))
+ (clobber (reg:CC CC_REGNUM))])
+ (parallel
+ [(set (match_operand:BLK 3 "memory_operand" "")
+ (ior:BLK (match_dup 3)
+ (match_operand:BLK 4 "memory_operand" "")))
+ (use (match_operand 5 "const_int_operand" ""))
+ (clobber (reg:CC CC_REGNUM))])]
+ "s390_offset_p (operands[0], operands[3], operands[2])
+ && s390_offset_p (operands[1], operands[4], operands[2])
+ && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
+ [(parallel
+ [(set (match_dup 6) (ior:BLK (match_dup 6) (match_dup 7)))
+ (use (match_dup 8))
+ (clobber (reg:CC CC_REGNUM))])]
+ "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
+ operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
+ operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
;;
;;- Xor instructions.
;;
+(define_expand "xor<mode>3"
+ [(set (match_operand:INT 0 "nonimmediate_operand" "")
+ (xor:INT (match_operand:INT 1 "nonimmediate_operand" "")
+ (match_operand:INT 2 "general_operand" "")))
+ (clobber (reg:CC CC_REGNUM))]
+ ""
+ "s390_expand_logical_operator (XOR, <MODE>mode, operands); DONE;")
+
;
; xordi3 instruction pattern(s).
;
(define_insn "*xordi3_cc"
- [(set (reg 33)
+ [(set (reg CC_REGNUM)
(compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
(match_operand:DI 2 "general_operand" "d,m"))
(const_int 0)))
[(set_attr "op_type" "RRE,RXY")])
(define_insn "*xordi3_cconly"
- [(set (reg 33)
+ [(set (reg CC_REGNUM)
(compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
(match_operand:DI 2 "general_operand" "d,m"))
(const_int 0)))
[(set_attr "op_type" "RRE,RXY")])
(define_insn "*xordi3"
- [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,Q")
- (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0")
- (match_operand:DI 2 "general_operand" "d,m,Q")))
- (clobber (reg:CC 33))]
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,AQ,Q")
+ (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0")
+ (match_operand:DI 2 "general_operand" "d,m,NxQD0,Q")))
+ (clobber (reg:CC CC_REGNUM))]
"TARGET_64BIT && s390_logical_operator_ok_p (operands)"
"@
xgr\t%0,%2
xg\t%0,%2
- xc\t%O0(8,%R0),%2"
- [(set_attr "op_type" "RRE,RXY,SS")])
+ #
+ #"
+ [(set_attr "op_type" "RRE,RXY,SI,SS")])
-(define_expand "xordi3"
- [(set (match_operand:DI 0 "nonimmediate_operand" "")
- (xor:DI (match_operand:DI 1 "nonimmediate_operand" "")
- (match_operand:DI 2 "general_operand" "")))
- (clobber (reg:CC 33))]
- "TARGET_64BIT"
- "s390_expand_logical_operator (XOR, DImode, operands); DONE;")
+(define_split
+ [(set (match_operand:DI 0 "s_operand" "")
+ (xor:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" "")))
+ (clobber (reg:CC CC_REGNUM))]
+ "reload_completed"
+ [(parallel
+ [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
+ (clobber (reg:CC CC_REGNUM))])]
+ "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);")
;
; xorsi3 instruction pattern(s).
;
(define_insn "*xorsi3_cc"
- [(set (reg 33)
+ [(set (reg CC_REGNUM)
(compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
(match_operand:SI 2 "general_operand" "d,R,T"))
(const_int 0)))
[(set_attr "op_type" "RR,RX,RXY")])
(define_insn "*xorsi3_cconly"
- [(set (reg 33)
+ [(set (reg CC_REGNUM)
(compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
(match_operand:SI 2 "general_operand" "d,R,T"))
(const_int 0)))
[(set_attr "op_type" "RR,RX,RXY")])
(define_insn "*xorsi3"
- [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,Q")
- (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
- (match_operand:SI 2 "general_operand" "d,R,T,Q")))
- (clobber (reg:CC 33))]
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,AQ,Q")
+ (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0,0")
+ (match_operand:SI 2 "general_operand" "d,R,T,NxQS0,Q")))
+ (clobber (reg:CC CC_REGNUM))]
"s390_logical_operator_ok_p (operands)"
"@
xr\t%0,%2
x\t%0,%2
xy\t%0,%2
- xc\t%O0(4,%R0),%2"
- [(set_attr "op_type" "RR,RX,RXY,SS")])
-
-(define_expand "xorsi3"
- [(set (match_operand:SI 0 "nonimmediate_operand" "")
- (xor:SI (match_operand:SI 1 "nonimmediate_operand" "")
- (match_operand:SI 2 "general_operand" "")))
- (clobber (reg:CC 33))]
- ""
- "s390_expand_logical_operator (XOR, SImode, operands); DONE;")
+ #
+ #"
+ [(set_attr "op_type" "RR,RX,RXY,SI,SS")])
+
+(define_split
+ [(set (match_operand:SI 0 "s_operand" "")
+ (xor:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" "")))
+ (clobber (reg:CC CC_REGNUM))]
+ "reload_completed"
+ [(parallel
+ [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
+ (clobber (reg:CC CC_REGNUM))])]
+ "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);")
;
; xorhi3 instruction pattern(s).
;
(define_insn "*xorhi3"
- [(set (match_operand:HI 0 "nonimmediate_operand" "=d,Q")
- (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
- (match_operand:HI 2 "general_operand" "d,Q")))
- (clobber (reg:CC 33))]
+ [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q")
+ (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0")
+ (match_operand:HI 2 "general_operand" "d,NxQH0,Q")))
+ (clobber (reg:CC CC_REGNUM))]
"s390_logical_operator_ok_p (operands)"
"@
xr\t%0,%2
- xc\t%O0(2,%R0),%2"
- [(set_attr "op_type" "RR,SS")])
+ #
+ #"
+ [(set_attr "op_type" "RR,SI,SS")])
-(define_expand "xorhi3"
- [(set (match_operand:HI 0 "nonimmediate_operand" "")
- (xor:HI (match_operand:HI 1 "nonimmediate_operand" "")
- (match_operand:HI 2 "general_operand" "")))
- (clobber (reg:CC 33))]
- ""
- "s390_expand_logical_operator (XOR, HImode, operands); DONE;")
+(define_split
+ [(set (match_operand:HI 0 "s_operand" "")
+ (xor:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" "")))
+ (clobber (reg:CC CC_REGNUM))]
+ "reload_completed"
+ [(parallel
+ [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
+ (clobber (reg:CC CC_REGNUM))])]
+ "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);")
;
; xorqi3 instruction pattern(s).
[(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,S,Q")
(xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0,0")
(match_operand:QI 2 "general_operand" "d,n,n,Q")))
- (clobber (reg:CC 33))]
+ (clobber (reg:CC CC_REGNUM))]
"s390_logical_operator_ok_p (operands)"
"@
xr\t%0,%2
- xi\t%0,%b2
- xiy\t%0,%b2
- xc\t%O0(1,%R0),%2"
+ xi\t%S0,%b2
+ xiy\t%S0,%b2
+ #"
[(set_attr "op_type" "RR,SI,SIY,SS")])
-(define_expand "xorqi3"
- [(set (match_operand:QI 0 "nonimmediate_operand" "")
- (xor:QI (match_operand:QI 1 "nonimmediate_operand" "")
- (match_operand:QI 2 "general_operand" "")))
- (clobber (reg:CC 33))]
- ""
- "s390_expand_logical_operator (XOR, QImode, operands); DONE;")
-
-
-;;
-;;- Negate instructions.
-;;
-
;
-; negdi2 instruction pattern(s).
+; Block exclusive or (XC) patterns.
;
-(define_expand "negdi2"
- [(parallel
- [(set (match_operand:DI 0 "register_operand" "=d")
- (neg:DI (match_operand:DI 1 "register_operand" "d")))
- (clobber (reg:CC 33))])]
- ""
- "")
-
-(define_insn "*negdi2_64"
- [(set (match_operand:DI 0 "register_operand" "=d")
- (neg:DI (match_operand:DI 1 "register_operand" "d")))
- (clobber (reg:CC 33))]
- "TARGET_64BIT"
- "lcgr\t%0,%1"
- [(set_attr "op_type" "RR")])
+(define_insn "*xc"
+ [(set (match_operand:BLK 0 "memory_operand" "=Q")
+ (xor:BLK (match_dup 0)
+ (match_operand:BLK 1 "memory_operand" "Q")))
+ (use (match_operand 2 "const_int_operand" "n"))
+ (clobber (reg:CC CC_REGNUM))]
+ "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
+ "xc\t%O0(%2,%R0),%S1"
+ [(set_attr "op_type" "SS")])
-(define_insn "*negdi2_31"
- [(set (match_operand:DI 0 "register_operand" "=d")
- (neg:DI (match_operand:DI 1 "register_operand" "d")))
- (clobber (reg:CC 33))]
- "!TARGET_64BIT"
+(define_split
+ [(set (match_operand 0 "memory_operand" "")
+ (xor (match_dup 0)
+ (match_operand 1 "memory_operand" "")))
+ (clobber (reg:CC CC_REGNUM))]
+ "reload_completed
+ && GET_MODE (operands[0]) == GET_MODE (operands[1])
+ && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
+ [(parallel
+ [(set (match_dup 0) (xor:BLK (match_dup 0) (match_dup 1)))
+ (use (match_dup 2))
+ (clobber (reg:CC CC_REGNUM))])]
{
- rtx xop[1];
- xop[0] = gen_label_rtx ();
- output_asm_insn ("lcr\t%0,%1", operands);
- output_asm_insn ("lcr\t%N0,%N1", operands);
- output_asm_insn ("je\t%l0", xop);
- output_asm_insn ("bctr\t%0,0", operands);
- targetm.asm_out.internal_label (asm_out_file, "L",
- CODE_LABEL_NUMBER (xop[0]));
- return "";
-}
- [(set_attr "op_type" "NN")
- (set_attr "type" "other")
- (set_attr "length" "10")])
+ operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
+ operands[0] = adjust_address (operands[0], BLKmode, 0);
+ operands[1] = adjust_address (operands[1], BLKmode, 0);
+})
+
+(define_peephole2
+ [(parallel
+ [(set (match_operand:BLK 0 "memory_operand" "")
+ (xor:BLK (match_dup 0)
+ (match_operand:BLK 1 "memory_operand" "")))
+ (use (match_operand 2 "const_int_operand" ""))
+ (clobber (reg:CC CC_REGNUM))])
+ (parallel
+ [(set (match_operand:BLK 3 "memory_operand" "")
+ (xor:BLK (match_dup 3)
+ (match_operand:BLK 4 "memory_operand" "")))
+ (use (match_operand 5 "const_int_operand" ""))
+ (clobber (reg:CC CC_REGNUM))])]
+ "s390_offset_p (operands[0], operands[3], operands[2])
+ && s390_offset_p (operands[1], operands[4], operands[2])
+ && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
+ [(parallel
+ [(set (match_dup 6) (xor:BLK (match_dup 6) (match_dup 7)))
+ (use (match_dup 8))
+ (clobber (reg:CC CC_REGNUM))])]
+ "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
+ operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
+ operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
;
-; negsi2 instruction pattern(s).
+; Block xor (XC) patterns with src == dest.
;
-(define_insn "negsi2"
- [(set (match_operand:SI 0 "register_operand" "=d")
- (neg:SI (match_operand:SI 1 "register_operand" "d")))
- (clobber (reg:CC 33))]
- ""
- "lcr\t%0,%1"
- [(set_attr "op_type" "RR")])
+(define_insn "*xc_zero"
+ [(set (match_operand:BLK 0 "memory_operand" "=Q")
+ (const_int 0))
+ (use (match_operand 1 "const_int_operand" "n"))
+ (clobber (reg:CC CC_REGNUM))]
+ "INTVAL (operands[1]) >= 1 && INTVAL (operands[1]) <= 256"
+ "xc\t%O0(%1,%R0),%S0"
+ [(set_attr "op_type" "SS")])
+
+(define_peephole2
+ [(parallel
+ [(set (match_operand:BLK 0 "memory_operand" "")
+ (const_int 0))
+ (use (match_operand 1 "const_int_operand" ""))
+ (clobber (reg:CC CC_REGNUM))])
+ (parallel
+ [(set (match_operand:BLK 2 "memory_operand" "")
+ (const_int 0))
+ (use (match_operand 3 "const_int_operand" ""))
+ (clobber (reg:CC CC_REGNUM))])]
+ "s390_offset_p (operands[0], operands[2], operands[1])
+ && INTVAL (operands[1]) + INTVAL (operands[3]) <= 256"
+ [(parallel
+ [(set (match_dup 4) (const_int 0))
+ (use (match_dup 5))
+ (clobber (reg:CC CC_REGNUM))])]
+ "operands[4] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
+ operands[5] = GEN_INT (INTVAL (operands[1]) + INTVAL (operands[3]));")
+
+
+;;
+;;- Negate instructions.
+;;
;
-; negdf2 instruction pattern(s).
+; neg(di|si)2 instruction pattern(s).
;
-(define_expand "negdf2"
+(define_expand "neg<mode>2"
[(parallel
- [(set (match_operand:DF 0 "register_operand" "=f")
- (neg:DF (match_operand:DF 1 "register_operand" "f")))
- (clobber (reg:CC 33))])]
- "TARGET_HARD_FLOAT"
+ [(set (match_operand:DSI 0 "register_operand" "=d")
+ (neg:DSI (match_operand:DSI 1 "register_operand" "d")))
+ (clobber (reg:CC CC_REGNUM))])]
+ ""
"")
-(define_insn "*negdf2"
- [(set (match_operand:DF 0 "register_operand" "=f")
- (neg:DF (match_operand:DF 1 "register_operand" "f")))
- (clobber (reg:CC 33))]
- "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
- "lcdbr\t%0,%1"
- [(set_attr "op_type" "RRE")
- (set_attr "type" "fsimpd")])
+(define_insn "*negdi2_sign_cc"
+ [(set (reg CC_REGNUM)
+ (compare (neg:DI (ashiftrt:DI (ashift:DI (subreg:DI
+ (match_operand:SI 1 "register_operand" "d") 0)
+ (const_int 32)) (const_int 32)))
+ (const_int 0)))
+ (set (match_operand:DI 0 "register_operand" "=d")
+ (neg:DI (sign_extend:DI (match_dup 1))))]
+ "TARGET_64BIT && s390_match_ccmode (insn, CCAmode)"
+ "lcgfr\t%0,%1"
+ [(set_attr "op_type" "RRE")])
+
+(define_insn "*negdi2_sign"
+ [(set (match_operand:DI 0 "register_operand" "=d")
+ (neg:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))))
+ (clobber (reg:CC CC_REGNUM))]
+ "TARGET_64BIT"
+ "lcgfr\t%0,%1"
+ [(set_attr "op_type" "RRE")])
-(define_insn "*negdf2_ibm"
- [(set (match_operand:DF 0 "register_operand" "=f")
- (neg:DF (match_operand:DF 1 "register_operand" "f")))
- (clobber (reg:CC 33))]
- "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
- "lcdr\t%0,%1"
- [(set_attr "op_type" "RR")
- (set_attr "type" "fsimpd")])
+(define_insn "*neg<mode>2_cc"
+ [(set (reg CC_REGNUM)
+ (compare (neg:GPR (match_operand:GPR 1 "register_operand" "d"))
+ (const_int 0)))
+ (set (match_operand:GPR 0 "register_operand" "=d")
+ (neg:GPR (match_dup 1)))]
+ "s390_match_ccmode (insn, CCAmode)"
+ "lc<g>r\t%0,%1"
+ [(set_attr "op_type" "RR<E>")])
+
+(define_insn "*neg<mode>2_cconly"
+ [(set (reg CC_REGNUM)
+ (compare (neg:GPR (match_operand:GPR 1 "register_operand" "d"))
+ (const_int 0)))
+ (clobber (match_scratch:GPR 0 "=d"))]
+ "s390_match_ccmode (insn, CCAmode)"
+ "lc<g>r\t%0,%1"
+ [(set_attr "op_type" "RR<E>")])
+
+(define_insn "*neg<mode>2"
+ [(set (match_operand:GPR 0 "register_operand" "=d")
+ (neg:GPR (match_operand:GPR 1 "register_operand" "d")))
+ (clobber (reg:CC CC_REGNUM))]
+ ""
+ "lc<g>r\t%0,%1"
+ [(set_attr "op_type" "RR<E>")])
+
+(define_insn_and_split "*negdi2_31"
+ [(set (match_operand:DI 0 "register_operand" "=d")
+ (neg:DI (match_operand:DI 1 "register_operand" "d")))
+ (clobber (reg:CC CC_REGNUM))]
+ "!TARGET_64BIT"
+ "#"
+ "&& reload_completed"
+ [(parallel
+ [(set (match_dup 2) (neg:SI (match_dup 3)))
+ (clobber (reg:CC CC_REGNUM))])
+ (parallel
+ [(set (reg:CCAP CC_REGNUM)
+ (compare:CCAP (neg:SI (match_dup 5)) (const_int 0)))
+ (set (match_dup 4) (neg:SI (match_dup 5)))])
+ (set (pc)
+ (if_then_else (ne (reg:CCAP CC_REGNUM) (const_int 0))
+ (pc)
+ (label_ref (match_dup 6))))
+ (parallel
+ [(set (match_dup 2) (plus:SI (match_dup 2) (const_int -1)))
+ (clobber (reg:CC CC_REGNUM))])
+ (match_dup 6)]
+ "operands[2] = operand_subword (operands[0], 0, 0, DImode);
+ operands[3] = operand_subword (operands[1], 0, 0, DImode);
+ operands[4] = operand_subword (operands[0], 1, 0, DImode);
+ operands[5] = operand_subword (operands[1], 1, 0, DImode);
+ operands[6] = gen_label_rtx ();")
;
-; negsf2 instruction pattern(s).
+; neg(df|sf)2 instruction pattern(s).
;
-(define_expand "negsf2"
+(define_expand "neg<mode>2"
[(parallel
- [(set (match_operand:SF 0 "register_operand" "=f")
- (neg:SF (match_operand:SF 1 "register_operand" "f")))
- (clobber (reg:CC 33))])]
+ [(set (match_operand:FPR 0 "register_operand" "=f")
+ (neg:FPR (match_operand:FPR 1 "register_operand" "f")))
+ (clobber (reg:CC CC_REGNUM))])]
"TARGET_HARD_FLOAT"
"")
-(define_insn "*negsf2"
- [(set (match_operand:SF 0 "register_operand" "=f")
- (neg:SF (match_operand:SF 1 "register_operand" "f")))
- (clobber (reg:CC 33))]
+(define_insn "*neg<mode>2_cc"
+ [(set (reg CC_REGNUM)
+ (compare (neg:FPR (match_operand:FPR 1 "register_operand" "f"))
+ (match_operand:FPR 2 "const0_operand" "")))
+ (set (match_operand:FPR 0 "register_operand" "=f")
+ (neg:FPR (match_dup 1)))]
+ "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
+ "lc<de>br\t%0,%1"
+ [(set_attr "op_type" "RRE")
+ (set_attr "type" "fsimp<mode>")])
+
+(define_insn "*neg<mode>2_cconly"
+ [(set (reg CC_REGNUM)
+ (compare (neg:FPR (match_operand:FPR 1 "register_operand" "f"))
+ (match_operand:FPR 2 "const0_operand" "")))
+ (clobber (match_scratch:FPR 0 "=f"))]
+ "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
+ "lc<de>br\t%0,%1"
+ [(set_attr "op_type" "RRE")
+ (set_attr "type" "fsimp<mode>")])
+
+(define_insn "*neg<mode>2"
+ [(set (match_operand:FPR 0 "register_operand" "=f")
+ (neg:FPR (match_operand:FPR 1 "register_operand" "f")))
+ (clobber (reg:CC CC_REGNUM))]
"TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
- "lcebr\t%0,%1"
+ "lc<de>br\t%0,%1"
[(set_attr "op_type" "RRE")
- (set_attr "type" "fsimps")])
+ (set_attr "type" "fsimp<mode>")])
-(define_insn "*negsf2"
- [(set (match_operand:SF 0 "register_operand" "=f")
- (neg:SF (match_operand:SF 1 "register_operand" "f")))
- (clobber (reg:CC 33))]
+(define_insn "*neg<mode>2_ibm"
+ [(set (match_operand:FPR 0 "register_operand" "=f")
+ (neg:FPR (match_operand:FPR 1 "register_operand" "f")))
+ (clobber (reg:CC CC_REGNUM))]
"TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
- "lcer\t%0,%1"
+ "lc<de>r\t%0,%1"
[(set_attr "op_type" "RR")
- (set_attr "type" "fsimps")])
+ (set_attr "type" "fsimp<mode>")])
;;
;;
;
-; absdi2 instruction pattern(s).
+; abs(di|si)2 instruction pattern(s).
;
-(define_insn "absdi2"
+(define_insn "*absdi2_sign_cc"
+ [(set (reg CC_REGNUM)
+ (compare (abs:DI (ashiftrt:DI (ashift:DI (subreg:DI
+ (match_operand:SI 1 "register_operand" "d") 0)
+ (const_int 32)) (const_int 32)))
+ (const_int 0)))
+ (set (match_operand:DI 0 "register_operand" "=d")
+ (abs:DI (sign_extend:DI (match_dup 1))))]
+ "TARGET_64BIT && s390_match_ccmode (insn, CCAmode)"
+ "lpgfr\t%0,%1"
+ [(set_attr "op_type" "RRE")])
+
+(define_insn "*absdi2_sign"
[(set (match_operand:DI 0 "register_operand" "=d")
- (abs:DI (match_operand:DI 1 "register_operand" "d")))
- (clobber (reg:CC 33))]
+ (abs:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))))
+ (clobber (reg:CC CC_REGNUM))]
"TARGET_64BIT"
- "lpgr\t%0,%1"
+ "lpgfr\t%0,%1"
[(set_attr "op_type" "RRE")])
-;
-; abssi2 instruction pattern(s).
-;
-
-(define_insn "abssi2"
- [(set (match_operand:SI 0 "register_operand" "=d")
- (abs:SI (match_operand:SI 1 "register_operand" "d")))
- (clobber (reg:CC 33))]
+(define_insn "*abs<mode>2_cc"
+ [(set (reg CC_REGNUM)
+ (compare (abs:GPR (match_operand:DI 1 "register_operand" "d"))
+ (const_int 0)))
+ (set (match_operand:GPR 0 "register_operand" "=d")
+ (abs:GPR (match_dup 1)))]
+ "s390_match_ccmode (insn, CCAmode)"
+ "lp<g>r\t%0,%1"
+ [(set_attr "op_type" "RR<E>")])
+
+(define_insn "*abs<mode>2_cconly"
+ [(set (reg CC_REGNUM)
+ (compare (abs:GPR (match_operand:GPR 1 "register_operand" "d"))
+ (const_int 0)))
+ (clobber (match_scratch:GPR 0 "=d"))]
+ "s390_match_ccmode (insn, CCAmode)"
+ "lp<g>r\t%0,%1"
+ [(set_attr "op_type" "RR<E>")])
+
+(define_insn "abs<mode>2"
+ [(set (match_operand:GPR 0 "register_operand" "=d")
+ (abs:GPR (match_operand:GPR 1 "register_operand" "d")))
+ (clobber (reg:CC CC_REGNUM))]
""
- "lpr\t%0,%1"
- [(set_attr "op_type" "RR")])
+ "lp<g>r\t%0,%1"
+ [(set_attr "op_type" "RR<E>")])
;
-; absdf2 instruction pattern(s).
+; abs(df|sf)2 instruction pattern(s).
;
-(define_expand "absdf2"
+(define_expand "abs<mode>2"
[(parallel
- [(set (match_operand:DF 0 "register_operand" "=f")
- (abs:DF (match_operand:DF 1 "register_operand" "f")))
- (clobber (reg:CC 33))])]
+ [(set (match_operand:FPR 0 "register_operand" "=f")
+ (abs:FPR (match_operand:FPR 1 "register_operand" "f")))
+ (clobber (reg:CC CC_REGNUM))])]
"TARGET_HARD_FLOAT"
"")
-(define_insn "*absdf2"
- [(set (match_operand:DF 0 "register_operand" "=f")
- (abs:DF (match_operand:DF 1 "register_operand" "f")))
- (clobber (reg:CC 33))]
- "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
- "lpdbr\t%0,%1"
+(define_insn "*abs<mode>2_cc"
+ [(set (reg CC_REGNUM)
+ (compare (abs:FPR (match_operand:FPR 1 "register_operand" "f"))
+ (match_operand:FPR 2 "const0_operand" "")))
+ (set (match_operand:FPR 0 "register_operand" "=f")
+ (abs:FPR (match_dup 1)))]
+ "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
+ "lp<de>br\t%0,%1"
[(set_attr "op_type" "RRE")
- (set_attr "type" "fsimpd")])
-
-(define_insn "*absdf2_ibm"
- [(set (match_operand:DF 0 "register_operand" "=f")
- (abs:DF (match_operand:DF 1 "register_operand" "f")))
- (clobber (reg:CC 33))]
- "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
- "lpdr\t%0,%1"
- [(set_attr "op_type" "RR")
- (set_attr "type" "fsimpd")])
-
-;
-; abssf2 instruction pattern(s).
-;
-
-(define_expand "abssf2"
- [(parallel
- [(set (match_operand:SF 0 "register_operand" "=f")
- (abs:SF (match_operand:SF 1 "register_operand" "f")))
- (clobber (reg:CC 33))])]
- "TARGET_HARD_FLOAT"
- "")
-
-(define_insn "*abssf2"
- [(set (match_operand:SF 0 "register_operand" "=f")
- (abs:SF (match_operand:SF 1 "register_operand" "f")))
- (clobber (reg:CC 33))]
+ (set_attr "type" "fsimp<mode>")])
+
+(define_insn "*abs<mode>2_cconly"
+ [(set (reg CC_REGNUM)
+ (compare (abs:FPR (match_operand:FPR 1 "register_operand" "f"))
+ (match_operand:FPR 2 "const0_operand" "")))
+ (clobber (match_scratch:FPR 0 "=f"))]
+ "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
+ "lp<de>br\t%0,%1"
+ [(set_attr "op_type" "RRE")
+ (set_attr "type" "fsimp<mode>")])
+
+(define_insn "*abs<mode>2"
+ [(set (match_operand:FPR 0 "register_operand" "=f")
+ (abs:FPR (match_operand:FPR 1 "register_operand" "f")))
+ (clobber (reg:CC CC_REGNUM))]
"TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
- "lpebr\t%0,%1"
+ "lp<de>br\t%0,%1"
[(set_attr "op_type" "RRE")
- (set_attr "type" "fsimps")])
+ (set_attr "type" "fsimp<mode>")])
-(define_insn "*abssf2_ibm"
- [(set (match_operand:SF 0 "register_operand" "=f")
- (abs:SF (match_operand:SF 1 "register_operand" "f")))
- (clobber (reg:CC 33))]
+(define_insn "*abs<mode>2_ibm"
+ [(set (match_operand:FPR 0 "register_operand" "=f")
+ (abs:FPR (match_operand:FPR 1 "register_operand" "f")))
+ (clobber (reg:CC CC_REGNUM))]
"TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
- "lper\t%0,%1"
+ "lp<de>r\t%0,%1"
[(set_attr "op_type" "RR")
- (set_attr "type" "fsimps")])
+ (set_attr "type" "fsimp<mode>")])
;;
;;- Negated absolute value instructions
; Integer
;
-(define_insn "*negabssi2"
- [(set (match_operand:SI 0 "register_operand" "=d")
- (neg:SI (abs:SI (match_operand:SI 1 "register_operand" "d"))))
- (clobber (reg:CC 33))]
- ""
- "lnr\t%0,%1"
- [(set_attr "op_type" "RR")])
-
-(define_insn "*negabsdi2"
+(define_insn "*negabsdi2_sign_cc"
+ [(set (reg CC_REGNUM)
+ (compare (neg:DI (abs:DI (ashiftrt:DI (ashift:DI (subreg:DI
+ (match_operand:SI 1 "register_operand" "d") 0)
+ (const_int 32)) (const_int 32))))
+ (const_int 0)))
+ (set (match_operand:DI 0 "register_operand" "=d")
+ (neg:DI (abs:DI (sign_extend:DI (match_dup 1)))))]
+ "TARGET_64BIT && s390_match_ccmode (insn, CCAmode)"
+ "lngfr\t%0,%1"
+ [(set_attr "op_type" "RRE")])
+
+(define_insn "*negabsdi2_sign"
[(set (match_operand:DI 0 "register_operand" "=d")
- (neg:DI (abs:DI (match_operand:DI 1 "register_operand" "d"))))
- (clobber (reg:CC 33))]
+ (neg:DI (abs:DI (sign_extend:DI
+ (match_operand:SI 1 "register_operand" "d")))))
+ (clobber (reg:CC CC_REGNUM))]
"TARGET_64BIT"
- "lngr\t%0,%1"
+ "lngfr\t%0,%1"
[(set_attr "op_type" "RRE")])
+(define_insn "*negabs<mode>2_cc"
+ [(set (reg CC_REGNUM)
+ (compare (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d")))
+ (const_int 0)))
+ (set (match_operand:GPR 0 "register_operand" "=d")
+ (neg:GPR (abs:GPR (match_dup 1))))]
+ "s390_match_ccmode (insn, CCAmode)"
+ "ln<g>r\t%0,%1"
+ [(set_attr "op_type" "RR<E>")])
+
+(define_insn "*negabs<mode>2_cconly"
+ [(set (reg CC_REGNUM)
+ (compare (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d")))
+ (const_int 0)))
+ (clobber (match_scratch:GPR 0 "=d"))]
+ "s390_match_ccmode (insn, CCAmode)"
+ "ln<g>r\t%0,%1"
+ [(set_attr "op_type" "RR<E>")])
+
+(define_insn "*negabs<mode>2"
+ [(set (match_operand:GPR 0 "register_operand" "=d")
+ (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d"))))
+ (clobber (reg:CC CC_REGNUM))]
+ ""
+ "ln<g>r\t%0,%1"
+ [(set_attr "op_type" "RR<E>")])
+
;
; Floating point
;
-(define_insn "*negabssf2"
- [(set (match_operand:SF 0 "register_operand" "=f")
- (neg:SF (abs:SF (match_operand:SF 1 "register_operand" "f"))))
- (clobber (reg:CC 33))]
- "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
- "lnebr\t%0,%1"
+(define_insn "*negabs<mode>2_cc"
+ [(set (reg CC_REGNUM)
+ (compare (neg:FPR (abs:FPR (match_operand:FPR 1 "register_operand" "f")))
+ (match_operand:FPR 2 "const0_operand" "")))
+ (set (match_operand:FPR 0 "register_operand" "=f")
+ (neg:FPR (abs:FPR (match_dup 1))))]
+ "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
+ "ln<de>br\t%0,%1"
[(set_attr "op_type" "RRE")
- (set_attr "type" "fsimps")])
-
-(define_insn "*negabsdf2"
- [(set (match_operand:DF 0 "register_operand" "=f")
- (neg:DF (abs:DF (match_operand:DF 1 "register_operand" "f"))))
- (clobber (reg:CC 33))]
+ (set_attr "type" "fsimp<mode>")])
+
+(define_insn "*negabs<mode>2_cconly"
+ [(set (reg CC_REGNUM)
+ (compare (neg:FPR (abs:FPR (match_operand:FPR 1 "register_operand" "f")))
+ (match_operand:FPR 2 "const0_operand" "")))
+ (clobber (match_scratch:FPR 0 "=f"))]
+ "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
+ "ln<de>br\t%0,%1"
+ [(set_attr "op_type" "RRE")
+ (set_attr "type" "fsimp<mode>")])
+
+(define_insn "*negabs<mode>2"
+ [(set (match_operand:FPR 0 "register_operand" "=f")
+ (neg:FPR (abs:FPR (match_operand:FPR 1 "register_operand" "f"))))
+ (clobber (reg:CC CC_REGNUM))]
"TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
- "lndbr\t%0,%1"
+ "ln<de>br\t%0,%1"
[(set_attr "op_type" "RRE")
- (set_attr "type" "fsimpd")])
+ (set_attr "type" "fsimp<mode>")])
;;
;;- Square root instructions.
;;
;
-; sqrtdf2 instruction pattern(s).
+; sqrt(df|sf)2 instruction pattern(s).
;
-(define_insn "sqrtdf2"
- [(set (match_operand:DF 0 "register_operand" "=f,f")
- (sqrt:DF (match_operand:DF 1 "general_operand" "f,R")))]
+(define_insn "sqrt<mode>2"
+ [(set (match_operand:FPR 0 "register_operand" "=f,f")
+ (sqrt:FPR (match_operand:FPR 1 "general_operand" "f,R")))]
"TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"@
- sqdbr\t%0,%1
- sqdb\t%0,%1"
- [(set_attr "op_type" "RRE,RXE")])
-
-;
-; sqrtsf2 instruction pattern(s).
-;
+ sq<de>br\t%0,%1
+ sq<de>b\t%0,%1"
+ [(set_attr "op_type" "RRE,RXE")
+ (set_attr "type" "fsqrt<mode>")])
-(define_insn "sqrtsf2"
- [(set (match_operand:SF 0 "register_operand" "=f,f")
- (sqrt:SF (match_operand:SF 1 "general_operand" "f,R")))]
- "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
- "@
- sqebr\t%0,%1
- sqeb\t%0,%1"
- [(set_attr "op_type" "RRE,RXE")])
;;
;;- One complement instructions.
;;
;
-; one_cmpldi2 instruction pattern(s).
-;
-
-(define_expand "one_cmpldi2"
- [(parallel
- [(set (match_operand:DI 0 "register_operand" "")
- (xor:DI (match_operand:DI 1 "register_operand" "")
- (const_int -1)))
- (clobber (reg:CC 33))])]
- "TARGET_64BIT"
- "")
-
-;
-; one_cmplsi2 instruction pattern(s).
-;
-
-(define_expand "one_cmplsi2"
- [(parallel
- [(set (match_operand:SI 0 "register_operand" "")
- (xor:SI (match_operand:SI 1 "register_operand" "")
- (const_int -1)))
- (clobber (reg:CC 33))])]
- ""
- "")
-
-;
-; one_cmplhi2 instruction pattern(s).
-;
-
-(define_expand "one_cmplhi2"
- [(parallel
- [(set (match_operand:HI 0 "register_operand" "")
- (xor:HI (match_operand:HI 1 "register_operand" "")
- (const_int -1)))
- (clobber (reg:CC 33))])]
- ""
- "")
-
-;
-; one_cmplqi2 instruction pattern(s).
+; one_cmpl(di|si|hi|qi)2 instruction pattern(s).
;
-(define_expand "one_cmplqi2"
+(define_expand "one_cmpl<mode>2"
[(parallel
- [(set (match_operand:QI 0 "register_operand" "")
- (xor:QI (match_operand:QI 1 "register_operand" "")
- (const_int -1)))
- (clobber (reg:CC 33))])]
+ [(set (match_operand:INT 0 "register_operand" "")
+ (xor:INT (match_operand:INT 1 "register_operand" "")
+ (const_int -1)))
+ (clobber (reg:CC CC_REGNUM))])]
""
"")
;;
;
-; rotldi3 instruction pattern(s).
-;
-
-(define_insn "rotldi3"
- [(set (match_operand:DI 0 "register_operand" "=d")
- (rotate:DI (match_operand:DI 1 "register_operand" "d")
- (match_operand:SI 2 "shift_count_operand" "Y")))]
- "TARGET_64BIT"
- "rllg\t%0,%1,%Y2"
- [(set_attr "op_type" "RSE")
- (set_attr "atype" "reg")])
-
-;
-; rotlsi3 instruction pattern(s).
+; rotl(di|si)3 instruction pattern(s).
;
-(define_insn "rotlsi3"
- [(set (match_operand:SI 0 "register_operand" "=d")
- (rotate:SI (match_operand:SI 1 "register_operand" "d")
- (match_operand:SI 2 "shift_count_operand" "Y")))]
+(define_insn "rotl<mode>3"
+ [(set (match_operand:GPR 0 "register_operand" "=d")
+ (rotate:GPR (match_operand:GPR 1 "register_operand" "d")
+ (match_operand:SI 2 "shift_count_operand" "Y")))]
"TARGET_CPU_ZARCH"
- "rll\t%0,%1,%Y2"
+ "rll<g>\t%0,%1,%Y2"
[(set_attr "op_type" "RSE")
(set_attr "atype" "reg")])
;;
-;;- Arithmetic shift instructions.
+;;- Shift instructions.
;;
;
-; ashldi3 instruction pattern(s).
+; (ashl|lshr)di3 instruction pattern(s).
;
-(define_expand "ashldi3"
+(define_expand "<shift>di3"
[(set (match_operand:DI 0 "register_operand" "")
- (ashift:DI (match_operand:DI 1 "register_operand" "")
- (match_operand:SI 2 "shift_count_operand" "")))]
+ (SHIFT:DI (match_operand:DI 1 "register_operand" "")
+ (match_operand:SI 2 "shift_count_operand" "")))]
""
"")
-(define_insn "*ashldi3_31"
+(define_insn "*<shift>di3_31"
[(set (match_operand:DI 0 "register_operand" "=d")
- (ashift:DI (match_operand:DI 1 "register_operand" "0")
- (match_operand:SI 2 "shift_count_operand" "Y")))]
+ (SHIFT:DI (match_operand:DI 1 "register_operand" "0")
+ (match_operand:SI 2 "shift_count_operand" "Y")))]
"!TARGET_64BIT"
- "sldl\t%0,%Y2"
+ "s<lr>dl\t%0,%Y2"
[(set_attr "op_type" "RS")
(set_attr "atype" "reg")])
-(define_insn "*ashldi3_64"
+(define_insn "*<shift>di3_64"
[(set (match_operand:DI 0 "register_operand" "=d")
- (ashift:DI (match_operand:DI 1 "register_operand" "d")
- (match_operand:SI 2 "shift_count_operand" "Y")))]
+ (SHIFT:DI (match_operand:DI 1 "register_operand" "d")
+ (match_operand:SI 2 "shift_count_operand" "Y")))]
"TARGET_64BIT"
- "sllg\t%0,%1,%Y2"
+ "s<lr>lg\t%0,%1,%Y2"
[(set_attr "op_type" "RSE")
(set_attr "atype" "reg")])
[(set (match_operand:DI 0 "register_operand" "")
(ashiftrt:DI (match_operand:DI 1 "register_operand" "")
(match_operand:SI 2 "shift_count_operand" "")))
- (clobber (reg:CC 33))])]
+ (clobber (reg:CC CC_REGNUM))])]
""
"")
(define_insn "*ashrdi3_cc_31"
- [(set (reg 33)
+ [(set (reg CC_REGNUM)
(compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
(match_operand:SI 2 "shift_count_operand" "Y"))
(const_int 0)))
(set_attr "atype" "reg")])
(define_insn "*ashrdi3_cconly_31"
- [(set (reg 33)
+ [(set (reg CC_REGNUM)
(compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
(match_operand:SI 2 "shift_count_operand" "Y"))
(const_int 0)))
[(set (match_operand:DI 0 "register_operand" "=d")
(ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
(match_operand:SI 2 "shift_count_operand" "Y")))
- (clobber (reg:CC 33))]
+ (clobber (reg:CC CC_REGNUM))]
"!TARGET_64BIT"
"srda\t%0,%Y2"
[(set_attr "op_type" "RS")
(set_attr "atype" "reg")])
(define_insn "*ashrdi3_cc_64"
- [(set (reg 33)
+ [(set (reg CC_REGNUM)
(compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "d")
(match_operand:SI 2 "shift_count_operand" "Y"))
(const_int 0)))
(set_attr "atype" "reg")])
(define_insn "*ashrdi3_cconly_64"
- [(set (reg 33)
+ [(set (reg CC_REGNUM)
(compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "d")
(match_operand:SI 2 "shift_count_operand" "Y"))
(const_int 0)))
[(set (match_operand:DI 0 "register_operand" "=d")
(ashiftrt:DI (match_operand:DI 1 "register_operand" "d")
(match_operand:SI 2 "shift_count_operand" "Y")))
- (clobber (reg:CC 33))]
+ (clobber (reg:CC CC_REGNUM))]
"TARGET_64BIT"
"srag\t%0,%1,%Y2"
[(set_attr "op_type" "RSE")
;
-; ashlsi3 instruction pattern(s).
+; (ashl|lshr)si3 instruction pattern(s).
;
-(define_insn "ashlsi3"
+(define_insn "<shift>si3"
[(set (match_operand:SI 0 "register_operand" "=d")
- (ashift:SI (match_operand:SI 1 "register_operand" "0")
- (match_operand:SI 2 "shift_count_operand" "Y")))]
+ (SHIFT:SI (match_operand:SI 1 "register_operand" "0")
+ (match_operand:SI 2 "shift_count_operand" "Y")))]
""
- "sll\t%0,%Y2"
+ "s<lr>l\t%0,%Y2"
[(set_attr "op_type" "RS")
(set_attr "atype" "reg")])
;
(define_insn "*ashrsi3_cc"
- [(set (reg 33)
+ [(set (reg CC_REGNUM)
(compare (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
(match_operand:SI 2 "shift_count_operand" "Y"))
(const_int 0)))
(define_insn "*ashrsi3_cconly"
- [(set (reg 33)
+ [(set (reg CC_REGNUM)
(compare (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
(match_operand:SI 2 "shift_count_operand" "Y"))
(const_int 0)))
[(set (match_operand:SI 0 "register_operand" "=d")
(ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
(match_operand:SI 2 "shift_count_operand" "Y")))
- (clobber (reg:CC 33))]
+ (clobber (reg:CC CC_REGNUM))]
""
"sra\t%0,%Y2"
[(set_attr "op_type" "RS")
;;
-;;- logical shift instructions.
-;;
-
-;
-; lshrdi3 instruction pattern(s).
-;
-
-(define_expand "lshrdi3"
- [(set (match_operand:DI 0 "register_operand" "")
- (lshiftrt:DI (match_operand:DI 1 "register_operand" "")
- (match_operand:SI 2 "shift_count_operand" "")))]
- ""
- "")
-
-(define_insn "*lshrdi3_31"
- [(set (match_operand:DI 0 "register_operand" "=d")
- (lshiftrt:DI (match_operand:DI 1 "register_operand" "0")
- (match_operand:SI 2 "shift_count_operand" "Y")))]
- "!TARGET_64BIT"
- "srdl\t%0,%Y2"
- [(set_attr "op_type" "RS")
- (set_attr "atype" "reg")])
-
-(define_insn "*lshrdi3_64"
- [(set (match_operand:DI 0 "register_operand" "=d")
- (lshiftrt:DI (match_operand:DI 1 "register_operand" "d")
- (match_operand:SI 2 "shift_count_operand" "Y")))]
- "TARGET_64BIT"
- "srlg\t%0,%1,%Y2"
- [(set_attr "op_type" "RSE")
- (set_attr "atype" "reg")])
-
-;
-; lshrsi3 instruction pattern(s).
-;
-
-(define_insn "lshrsi3"
- [(set (match_operand:SI 0 "register_operand" "=d")
- (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
- (match_operand:SI 2 "shift_count_operand" "Y")))]
- ""
- "srl\t%0,%Y2"
- [(set_attr "op_type" "RS")
- (set_attr "atype" "reg")])
-
-
-;;
;; Branch instruction patterns.
;;
-(define_expand "beq"
- [(match_operand 0 "" "")]
- ""
- "s390_emit_jump (operands[0],
- s390_emit_compare (EQ, s390_compare_op0, s390_compare_op1)); DONE;")
-
-(define_expand "bne"
- [(match_operand 0 "" "")]
- ""
- "s390_emit_jump (operands[0],
- s390_emit_compare (NE, s390_compare_op0, s390_compare_op1)); DONE;")
-
-(define_expand "bgt"
- [(match_operand 0 "" "")]
- ""
- "s390_emit_jump (operands[0],
- s390_emit_compare (GT, s390_compare_op0, s390_compare_op1)); DONE;")
-
-(define_expand "bgtu"
- [(match_operand 0 "" "")]
- ""
- "s390_emit_jump (operands[0],
- s390_emit_compare (GTU, s390_compare_op0, s390_compare_op1)); DONE;")
-
-(define_expand "blt"
- [(match_operand 0 "" "")]
- ""
- "s390_emit_jump (operands[0],
- s390_emit_compare (LT, s390_compare_op0, s390_compare_op1)); DONE;")
-
-(define_expand "bltu"
- [(match_operand 0 "" "")]
- ""
- "s390_emit_jump (operands[0],
- s390_emit_compare (LTU, s390_compare_op0, s390_compare_op1)); DONE;")
-
-(define_expand "bge"
- [(match_operand 0 "" "")]
- ""
- "s390_emit_jump (operands[0],
- s390_emit_compare (GE, s390_compare_op0, s390_compare_op1)); DONE;")
-
-(define_expand "bgeu"
- [(match_operand 0 "" "")]
- ""
- "s390_emit_jump (operands[0],
- s390_emit_compare (GEU, s390_compare_op0, s390_compare_op1)); DONE;")
-
-(define_expand "ble"
- [(match_operand 0 "" "")]
- ""
- "s390_emit_jump (operands[0],
- s390_emit_compare (LE, s390_compare_op0, s390_compare_op1)); DONE;")
-
-(define_expand "bleu"
- [(match_operand 0 "" "")]
- ""
- "s390_emit_jump (operands[0],
- s390_emit_compare (LEU, s390_compare_op0, s390_compare_op1)); DONE;")
-
-(define_expand "bunordered"
- [(match_operand 0 "" "")]
- ""
- "s390_emit_jump (operands[0],
- s390_emit_compare (UNORDERED, s390_compare_op0, s390_compare_op1)); DONE;")
-
-(define_expand "bordered"
- [(match_operand 0 "" "")]
- ""
- "s390_emit_jump (operands[0],
- s390_emit_compare (ORDERED, s390_compare_op0, s390_compare_op1)); DONE;")
-
-(define_expand "buneq"
- [(match_operand 0 "" "")]
- ""
- "s390_emit_jump (operands[0],
- s390_emit_compare (UNEQ, s390_compare_op0, s390_compare_op1)); DONE;")
-
-(define_expand "bunlt"
- [(match_operand 0 "" "")]
- ""
- "s390_emit_jump (operands[0],
- s390_emit_compare (UNLT, s390_compare_op0, s390_compare_op1)); DONE;")
-
-(define_expand "bungt"
- [(match_operand 0 "" "")]
- ""
- "s390_emit_jump (operands[0],
- s390_emit_compare (UNGT, s390_compare_op0, s390_compare_op1)); DONE;")
-
-(define_expand "bunle"
- [(match_operand 0 "" "")]
- ""
- "s390_emit_jump (operands[0],
- s390_emit_compare (UNLE, s390_compare_op0, s390_compare_op1)); DONE;")
-
-(define_expand "bunge"
- [(match_operand 0 "" "")]
- ""
- "s390_emit_jump (operands[0],
- s390_emit_compare (UNGE, s390_compare_op0, s390_compare_op1)); DONE;")
-
-(define_expand "bltgt"
- [(match_operand 0 "" "")]
+(define_expand "b<code>"
+ [(set (pc)
+ (if_then_else (COMPARE (match_operand 0 "" "")
+ (const_int 0))
+ (match_dup 0)
+ (pc)))]
""
"s390_emit_jump (operands[0],
- s390_emit_compare (LTGT, s390_compare_op0, s390_compare_op1)); DONE;")
+ s390_emit_compare (<CODE>, s390_compare_op0, s390_compare_op1)); DONE;")
;;
(define_insn "*cjump_64"
[(set (pc)
(if_then_else
- (match_operator 1 "comparison_operator" [(reg 33) (const_int 0)])
+ (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
(label_ref (match_operand 0 "" ""))
(pc)))]
"TARGET_CPU_ZARCH"
(define_insn "*cjump_31"
[(set (pc)
(if_then_else
- (match_operator 1 "comparison_operator" [(reg 33) (const_int 0)])
+ (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
(label_ref (match_operand 0 "" ""))
(pc)))]
"!TARGET_CPU_ZARCH"
{
- if (get_attr_length (insn) == 4)
- return "j%C1\t%l0";
- else
- abort ();
+ gcc_assert (get_attr_length (insn) == 4);
+ return "j%C1\t%l0";
}
[(set_attr "op_type" "RI")
(set_attr "type" "branch")
(define_insn "*cjump_long"
[(set (pc)
(if_then_else
- (match_operator 1 "comparison_operator" [(reg 33) (const_int 0)])
+ (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
(match_operand 0 "address_operand" "U")
(pc)))]
""
(define_insn "*icjump_64"
[(set (pc)
(if_then_else
- (match_operator 1 "comparison_operator" [(reg 33) (const_int 0)])
+ (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
(pc)
(label_ref (match_operand 0 "" ""))))]
"TARGET_CPU_ZARCH"
(define_insn "*icjump_31"
[(set (pc)
(if_then_else
- (match_operator 1 "comparison_operator" [(reg 33) (const_int 0)])
+ (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
(pc)
(label_ref (match_operand 0 "" ""))))]
"!TARGET_CPU_ZARCH"
{
- if (get_attr_length (insn) == 4)
- return "j%D1\t%l0";
- else
- abort ();
+ gcc_assert (get_attr_length (insn) == 4);
+ return "j%D1\t%l0";
}
[(set_attr "op_type" "RI")
(set_attr "type" "branch")
(define_insn "*icjump_long"
[(set (pc)
(if_then_else
- (match_operator 1 "comparison_operator" [(reg 33) (const_int 0)])
+ (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
(pc)
(match_operand 0 "address_operand" "U")))]
""
})
(define_insn "*trap"
- [(trap_if (match_operator 0 "comparison_operator" [(reg 33) (const_int 0)])
+ [(trap_if (match_operator 0 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
(const_int 0))]
""
"j%C0\t.+2";
(pc)))
(set (match_operand:SI 2 "nonimmediate_operand" "=1,?*m*d")
(plus:SI (match_dup 1) (const_int -1)))
- (clobber (match_scratch:SI 3 "=X,&d"))
- (clobber (reg:CC 33))]
+ (clobber (match_scratch:SI 3 "=X,&1"))
+ (clobber (reg:CC CC_REGNUM))]
"TARGET_CPU_ZARCH"
{
if (which_alternative != 0)
"&& reload_completed
&& (! REG_P (operands[2])
|| ! rtx_equal_p (operands[1], operands[2]))"
- [(set (match_dup 3) (match_dup 1))
- (parallel [(set (reg:CCAN 33)
+ [(parallel [(set (reg:CCAN CC_REGNUM)
(compare:CCAN (plus:SI (match_dup 3) (const_int -1))
(const_int 0)))
(set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))])
(set (match_dup 2) (match_dup 3))
- (set (pc) (if_then_else (ne (reg:CCAN 33) (const_int 0))
+ (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0))
(label_ref (match_dup 0))
(pc)))]
""
(pc)))
(set (match_operand:SI 2 "nonimmediate_operand" "=1,?*m*d")
(plus:SI (match_dup 1) (const_int -1)))
- (clobber (match_scratch:SI 3 "=X,&d"))
- (clobber (reg:CC 33))]
+ (clobber (match_scratch:SI 3 "=X,&1"))
+ (clobber (reg:CC CC_REGNUM))]
"!TARGET_CPU_ZARCH"
{
if (which_alternative != 0)
else if (get_attr_length (insn) == 4)
return "brct\t%1,%l0";
else
- abort ();
+ gcc_unreachable ();
}
"&& reload_completed
&& (! REG_P (operands[2])
|| ! rtx_equal_p (operands[1], operands[2]))"
- [(set (match_dup 3) (match_dup 1))
- (parallel [(set (reg:CCAN 33)
+ [(parallel [(set (reg:CCAN CC_REGNUM)
(compare:CCAN (plus:SI (match_dup 3) (const_int -1))
(const_int 0)))
(set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))])
(set (match_dup 2) (match_dup 3))
- (set (pc) (if_then_else (ne (reg:CCAN 33) (const_int 0))
+ (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0))
(label_ref (match_dup 0))
(pc)))]
""
(pc)))
(set (match_operand:SI 2 "register_operand" "=1,?*m*d")
(plus:SI (match_dup 1) (const_int -1)))
- (clobber (match_scratch:SI 3 "=X,&d"))
- (clobber (reg:CC 33))]
+ (clobber (match_scratch:SI 3 "=X,&1"))
+ (clobber (reg:CC CC_REGNUM))]
"!TARGET_CPU_ZARCH"
{
if (get_attr_op_type (insn) == OP_TYPE_RR)
(const_int 1))
(label_ref (match_operand 0 "" ""))
(pc)))
- (set (match_operand:DI 2 "nonimmediate_operand" "=1,?*m*r")
+ (set (match_operand:DI 2 "nonimmediate_operand" "=1,?*m*d")
(plus:DI (match_dup 1) (const_int -1)))
- (clobber (match_scratch:DI 3 "=X,&d"))
- (clobber (reg:CC 33))]
+ (clobber (match_scratch:DI 3 "=X,&1"))
+ (clobber (reg:CC CC_REGNUM))]
"TARGET_64BIT"
{
if (which_alternative != 0)
"&& reload_completed
&& (! REG_P (operands[2])
|| ! rtx_equal_p (operands[1], operands[2]))"
- [(set (match_dup 3) (match_dup 1))
- (parallel [(set (reg:CCAN 33)
+ [(parallel [(set (reg:CCAN CC_REGNUM)
(compare:CCAN (plus:DI (match_dup 3) (const_int -1))
(const_int 0)))
(set (match_dup 3) (plus:DI (match_dup 3) (const_int -1)))])
(set (match_dup 2) (match_dup 3))
- (set (pc) (if_then_else (ne (reg:CCAN 33) (const_int 0))
+ (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0))
(label_ref (match_dup 0))
(pc)))]
""
[(set (pc) (label_ref (match_operand 0 "" "")))]
"!TARGET_CPU_ZARCH"
{
- if (get_attr_length (insn) == 4)
- return "j\t%l0";
- else
- abort ();
+ gcc_assert (get_attr_length (insn) == 4);
+ return "j\t%l0";
}
[(set_attr "op_type" "RI")
(set_attr "type" "branch")
})
(define_insn "*sibcall_br"
- [(call (mem:QI (reg 1))
+ [(call (mem:QI (reg SIBCALL_REGNUM))
(match_operand 0 "const_int_operand" "n"))]
"SIBLING_CALL_P (insn)
&& GET_MODE (XEXP (XEXP (PATTERN (insn), 0), 0)) == Pmode"
(define_insn "*sibcall_value_br"
[(set (match_operand 0 "" "")
- (call (mem:QI (reg 1))
+ (call (mem:QI (reg SIBCALL_REGNUM))
(match_operand 1 "const_int_operand" "n")))]
"SIBLING_CALL_P (insn)
&& GET_MODE (XEXP (XEXP (XEXP (PATTERN (insn), 1), 0), 0)) == Pmode"
;;- Thread-local storage support.
;;
-(define_insn "get_tp_64"
- [(set (match_operand:DI 0 "nonimmediate_operand" "=??d,Q")
- (unspec:DI [(const_int 0)] UNSPEC_TP))]
+(define_expand "get_tp_64"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "") (reg:DI TP_REGNUM))]
"TARGET_64BIT"
- "@
- ear\t%0,%%a0\;sllg\t%0,%0,32\;ear\t%0,%%a1
- stam\t%%a0,%%a1,%0"
- [(set_attr "op_type" "NN,RS")
- (set_attr "atype" "reg,*")
- (set_attr "type" "o3,*")
- (set_attr "length" "14,*")])
+ "")
-(define_insn "get_tp_31"
- [(set (match_operand:SI 0 "nonimmediate_operand" "=d,Q")
- (unspec:SI [(const_int 0)] UNSPEC_TP))]
+(define_expand "get_tp_31"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "") (reg:SI TP_REGNUM))]
"!TARGET_64BIT"
- "@
- ear\t%0,%%a0
- stam\t%%a0,%%a0,%0"
- [(set_attr "op_type" "RRE,RS")])
+ "")
-(define_insn "set_tp_64"
- [(unspec_volatile [(match_operand:DI 0 "general_operand" "??d,Q")] UNSPECV_SET_TP)
- (clobber (match_scratch:SI 1 "=d,X"))]
+(define_expand "set_tp_64"
+ [(set (reg:DI TP_REGNUM) (match_operand:DI 0 "nonimmediate_operand" ""))
+ (set (reg:DI TP_REGNUM) (unspec_volatile:DI [(reg:DI TP_REGNUM)] UNSPECV_SET_TP))]
"TARGET_64BIT"
- "@
- sar\t%%a1,%0\;srlg\t%1,%0,32\;sar\t%%a0,%1
- lam\t%%a0,%%a1,%0"
- [(set_attr "op_type" "NN,RS")
- (set_attr "atype" "reg,*")
- (set_attr "type" "o3,*")
- (set_attr "length" "14,*")])
+ "")
-(define_insn "set_tp_31"
- [(unspec_volatile [(match_operand:SI 0 "general_operand" "d,Q")] UNSPECV_SET_TP)]
+(define_expand "set_tp_31"
+ [(set (reg:SI TP_REGNUM) (match_operand:SI 0 "nonimmediate_operand" ""))
+ (set (reg:SI TP_REGNUM) (unspec_volatile:SI [(reg:SI TP_REGNUM)] UNSPECV_SET_TP))]
"!TARGET_64BIT"
- "@
- sar\t%%a0,%0
- lam\t%%a0,%%a0,%0"
- [(set_attr "op_type" "RRE,RS")])
+ "")
+
+(define_insn "*set_tp"
+ [(set (reg TP_REGNUM) (unspec_volatile [(reg TP_REGNUM)] UNSPECV_SET_TP))]
+ ""
+ ""
+ [(set_attr "type" "none")
+ (set_attr "length" "0")])
(define_insn "*tls_load_64"
[(set (match_operand:DI 0 "register_operand" "=d")
(define_expand "allocate_stack"
[(match_operand 0 "general_operand" "")
(match_operand 1 "general_operand" "")]
- "TARGET_BACKCHAIN || TARGET_KERNEL_BACKCHAIN"
+ "TARGET_BACKCHAIN"
{
rtx temp = gen_reg_rtx (Pmode);
(define_expand "restore_stack_block"
[(match_operand 0 "register_operand" "")
(match_operand 1 "register_operand" "")]
- "TARGET_BACKCHAIN || TARGET_KERNEL_BACKCHAIN"
+ "TARGET_BACKCHAIN"
{
rtx temp = gen_reg_rtx (Pmode);
/* Copy the backchain to the first word, sp to the second and the
literal pool base to the third. */
- if (TARGET_BACKCHAIN || TARGET_KERNEL_BACKCHAIN)
+ if (TARGET_BACKCHAIN)
{
rtx temp = force_reg (Pmode, s390_back_chain_rtx ());
emit_move_insn (operand_subword (operands[0], 0, 0, mode), temp);
/* Restore the backchain from the first word, sp from the second and the
literal pool base from the third. */
- if (TARGET_BACKCHAIN || TARGET_KERNEL_BACKCHAIN)
+ if (TARGET_BACKCHAIN)
temp = force_reg (Pmode, operand_subword (operands[1], 0, 0, mode));
emit_move_insn (base, operand_subword (operands[1], 2, 0, mode));
s390_output_pool_entry (operands[0], mode, align);
return "";
}
- [(set_attr "op_type" "NN")
- (set (attr "length")
+ [(set (attr "length")
(symbol_ref "GET_MODE_SIZE (GET_MODE (PATTERN (insn)))"))])
-(define_insn "pool_start_31"
- [(unspec_volatile [(const_int 0)] UNSPECV_POOL_START)]
- "!TARGET_CPU_ZARCH"
- ".align\t4"
- [(set_attr "op_type" "NN")
- (set_attr "length" "2")])
-
-(define_insn "pool_end_31"
- [(unspec_volatile [(const_int 0)] UNSPECV_POOL_END)]
- "!TARGET_CPU_ZARCH"
- ".align\t2"
- [(set_attr "op_type" "NN")
- (set_attr "length" "2")])
+(define_insn "pool_align"
+ [(unspec_volatile [(match_operand 0 "const_int_operand" "n")]
+ UNSPECV_POOL_ALIGN)]
+ ""
+ ".align\t%0"
+ [(set (attr "length") (symbol_ref "INTVAL (operands[0])"))])
-(define_insn "pool_start_64"
- [(unspec_volatile [(const_int 0)] UNSPECV_POOL_START)]
- "TARGET_CPU_ZARCH"
- ".section\t.rodata\;.align\t8"
- [(set_attr "op_type" "NN")
- (set_attr "length" "0")])
+(define_insn "pool_section_start"
+ [(unspec_volatile [(const_int 1)] UNSPECV_POOL_SECTION)]
+ ""
+ ".section\t.rodata"
+ [(set_attr "length" "0")])
-(define_insn "pool_end_64"
- [(unspec_volatile [(const_int 0)] UNSPECV_POOL_END)]
- "TARGET_CPU_ZARCH"
+(define_insn "pool_section_end"
+ [(unspec_volatile [(const_int 0)] UNSPECV_POOL_SECTION)]
+ ""
".previous"
- [(set_attr "op_type" "NN")
- (set_attr "length" "0")])
+ [(set_attr "length" "0")])
(define_insn "main_base_31_small"
[(set (match_operand 0 "register_operand" "=a")
[(set (match_operand 0 "register_operand" "=a")
(unspec_volatile [(const_int 0)] UNSPECV_MAIN_POOL))]
"GET_MODE (operands[0]) == Pmode"
- "* abort ();"
- [(set_attr "op_type" "NN")
- (set (attr "type")
+{
+ gcc_unreachable ();
+}
+ [(set (attr "type")
(if_then_else (ne (symbol_ref "TARGET_CPU_ZARCH") (const_int 0))
(const_string "larl") (const_string "la")))])
(unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))]
"!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
"basr\t%0,0\;la\t%0,%1-.(%0)"
- [(set_attr "op_type" "NN")
- (set_attr "type" "la")
- (set_attr "length" "6")])
+ [(set_attr "length" "6")
+ (set_attr "type" "la")])
(define_insn "reload_base_64"
[(set (match_operand 0 "register_operand" "=a")
(define_insn "pool"
[(unspec_volatile [(match_operand 0 "const_int_operand" "n")] UNSPECV_POOL)]
""
- "* abort ();"
- [(set_attr "op_type" "NN")
- (set (attr "length") (symbol_ref "INTVAL (operands[0])"))])
+{
+ gcc_unreachable ();
+}
+ [(set (attr "length") (symbol_ref "INTVAL (operands[0])"))])
;;
;; Insns related to generating the function prologue and epilogue.
[(unspec_volatile [(const_int 0)] UNSPECV_TPF_PROLOGUE)
(clobber (reg:DI 1))]
"TARGET_TPF_PROFILING"
- "bas\t%%r1,4064"
- [(set_attr "type" "jsr")
- (set_attr "op_type" "RX")])
+ "larl\t%%r1,.+14\;tm\t4065,255\;bnz\t4064"
+ [(set_attr "length" "14")])
(define_expand "epilogue"
[(use (const_int 1))]
[(unspec_volatile [(const_int 0)] UNSPECV_TPF_EPILOGUE)
(clobber (reg:DI 1))]
"TARGET_TPF_PROFILING"
- "bas\t%%r1,4070"
- [(set_attr "type" "jsr")
- (set_attr "op_type" "RX")])
-
+ "larl\t%%r1,.+14\;tm\t4071,255\;bnz\t4070"
+ [(set_attr "length" "14")])
(define_expand "sibcall_epilogue"
[(use (const_int 0))]
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