;; a -- Any address register from 1 to 15.
;; c -- Condition code register 33.
;; d -- Any register from 0 to 15.
+;; f -- Floating point registers.
+;; t -- Access registers 36 and 37.
+;; G -- Const double zero operand
;; I -- An 8-bit constant (0..255).
;; J -- A 12-bit constant (0..4095).
;; K -- A 16-bit constant (-32768..32767).
(UNSPECV_SET_TP 500)
])
+;;
+;; Registers
+;;
+
+(define_constants
+ [
+ ; Sibling call register.
+ (SIBCALL_REGNUM 1)
+ ; Literal pool base register.
+ (BASE_REGNUM 13)
+ ; Return address register.
+ (RETURN_REGNUM 14)
+ ; Condition code register.
+ (CC_REGNUM 33)
+ ; Thread local storage pointer register.
+ (TP_REGNUM 36)
+ ])
+
;; Instruction operand type as used in the Principles of Operation.
;; Used to determine defaults for length and other attribute values.
(define_attr "type" "none,integer,load,lr,la,larl,lm,stm,
cs,vs,store,idiv,
imulhi,imulsi,imuldi,
- branch,jsr,fsimpd,fsimps,
- floadd,floads,fstored, fstores,
- fmuld,fmuls,fdivd,fdivs,
- ftoi,itof,fsqrtd,fsqrts,
+ branch,jsr,fsimpdf,fsimpsf,
+ floaddf,floadsf,fstoredf,fstoresf,
+ fmuldf,fmulsf,fdivdf,fdivsf,
+ ftoi,itof,fsqrtdf,fsqrtsf,
other"
(cond [(eq_attr "op_type" "NN") (const_string "other")
(eq_attr "op_type" "SS") (const_string "cs")]
;; Macros
+;; This mode macro allows DF and SF patterns to be generated from the
+;; same template.
+(define_mode_macro FPR [DF SF])
+
;; These mode macros allow 31-bit and 64-bit GPR patterns to be generated
;; from the same template.
(define_mode_macro GPR [(DI "TARGET_64BIT") SI])
(define_code_macro SHIFT [ashift lshiftrt])
+;; In FPR templates, a string like "lt<de>br" will expand to "ltdbr" in DFmode
+;; and "ltebr" in SFmode.
+(define_mode_attr de [(DF "d") (SF "e")])
+
+;; In FPR templates, a string like "m<dee>br" will expand to "mdbr" in DFmode
+;; and "meebr" in SFmode. This is needed for the 'mul<mode>3' pattern.
+(define_mode_attr dee [(DF "d") (SF "ee")])
+
;; In SHIFT templates, a string like "s<lr>dl" will expand to "sldl" in
;; 'ashift' and "srdl" in 'lshiftrt'.
(define_code_attr lr [(ashift "l") (lshiftrt "r")])
;; and "lcr" in SImode.
(define_mode_attr g [(DI "g") (SI "")])
+;; In GPR templates, a string like "c<gf>dbr" will expand to "cgdbr" in DImode
+;; and "cfdbr" in SImode.
+(define_mode_attr gf [(DI "g") (SI "f")])
+
;; ICM mask required to load MODE value into the highest subreg
;; of a SImode register.
(define_mode_attr icm_hi [(HI "12") (QI "8")])
;;
(define_expand "cmp<mode>"
- [(set (reg:CC 33)
+ [(set (reg:CC CC_REGNUM)
(compare:CC (match_operand:GPR 0 "register_operand" "")
(match_operand:GPR 1 "general_operand" "")))]
""
DONE;
})
-(define_expand "cmpdf"
- [(set (reg:CC 33)
- (compare:CC (match_operand:DF 0 "register_operand" "")
- (match_operand:DF 1 "general_operand" "")))]
- "TARGET_HARD_FLOAT"
-{
- s390_compare_op0 = operands[0];
- s390_compare_op1 = operands[1];
- DONE;
-})
-
-(define_expand "cmpsf"
- [(set (reg:CC 33)
- (compare:CC (match_operand:SF 0 "register_operand" "")
- (match_operand:SF 1 "general_operand" "")))]
+(define_expand "cmp<mode>"
+ [(set (reg:CC CC_REGNUM)
+ (compare:CC (match_operand:FPR 0 "register_operand" "")
+ (match_operand:FPR 1 "general_operand" "")))]
"TARGET_HARD_FLOAT"
{
s390_compare_op0 = operands[0];
; Test-under-Mask instructions
(define_insn "*tmqi_mem"
- [(set (reg 33)
+ [(set (reg CC_REGNUM)
(compare (and:QI (match_operand:QI 0 "memory_operand" "Q,S")
(match_operand:QI 1 "immediate_operand" "n,n"))
(match_operand:QI 2 "immediate_operand" "n,n")))]
- "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 0))"
+ "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], false))"
"@
tm\t%S0,%b1
tmy\t%S0,%b1"
[(set_attr "op_type" "SI,SIY")])
(define_insn "*tmdi_reg"
- [(set (reg 33)
+ [(set (reg CC_REGNUM)
(compare (and:DI (match_operand:DI 0 "nonimmediate_operand" "d,d,d,d")
(match_operand:DI 1 "immediate_operand"
"N0HD0,N1HD0,N2HD0,N3HD0"))
(match_operand:DI 2 "immediate_operand" "n,n,n,n")))]
"TARGET_64BIT
- && s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 1))
+ && s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], true))
&& s390_single_part (operands[1], DImode, HImode, 0) >= 0"
"@
tmhh\t%0,%i1
[(set_attr "op_type" "RI")])
(define_insn "*tmsi_reg"
- [(set (reg 33)
+ [(set (reg CC_REGNUM)
(compare (and:SI (match_operand:SI 0 "nonimmediate_operand" "d,d")
(match_operand:SI 1 "immediate_operand" "N0HS0,N1HS0"))
(match_operand:SI 2 "immediate_operand" "n,n")))]
- "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 1))
+ "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], true))
&& s390_single_part (operands[1], SImode, HImode, 0) >= 0"
"@
tmh\t%0,%i1
[(set_attr "op_type" "RI")])
(define_insn "*tm<mode>_full"
- [(set (reg 33)
+ [(set (reg CC_REGNUM)
(compare (match_operand:HQI 0 "register_operand" "d")
(match_operand:HQI 1 "immediate_operand" "n")))]
- "s390_match_ccmode (insn, s390_tm_ccmode (constm1_rtx, operands[1], 1))"
+ "s390_match_ccmode (insn, s390_tm_ccmode (constm1_rtx, operands[1], true))"
"tml\t%0,<max_uint>"
[(set_attr "op_type" "RI")])
; Load-and-Test instructions
(define_insn "*tstdi_sign"
- [(set (reg 33)
+ [(set (reg CC_REGNUM)
(compare (ashiftrt:DI (ashift:DI (subreg:DI (match_operand:SI 0 "register_operand" "d") 0)
(const_int 32)) (const_int 32))
(match_operand:DI 1 "const0_operand" "")))
[(set_attr "op_type" "RRE")])
(define_insn "*tstdi"
- [(set (reg 33)
+ [(set (reg CC_REGNUM)
(compare (match_operand:DI 0 "register_operand" "d")
(match_operand:DI 1 "const0_operand" "")))
(set (match_operand:DI 2 "register_operand" "=d")
[(set_attr "op_type" "RRE")])
(define_insn "*tstdi_cconly"
- [(set (reg 33)
+ [(set (reg CC_REGNUM)
(compare (match_operand:DI 0 "register_operand" "d")
(match_operand:DI 1 "const0_operand" "")))]
"s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
[(set_attr "op_type" "RRE")])
(define_insn "*tstdi_cconly_31"
- [(set (reg 33)
+ [(set (reg CC_REGNUM)
(compare (match_operand:DI 0 "register_operand" "d")
(match_operand:DI 1 "const0_operand" "")))]
"s390_match_ccmode(insn, CCSmode) && !TARGET_64BIT"
(define_insn "*tstsi"
- [(set (reg 33)
+ [(set (reg CC_REGNUM)
(compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S")
(match_operand:SI 1 "const0_operand" "")))
(set (match_operand:SI 2 "register_operand" "=d,d,d")
[(set_attr "op_type" "RR,RS,RSY")])
(define_insn "*tstsi_cconly"
- [(set (reg 33)
+ [(set (reg CC_REGNUM)
(compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S")
(match_operand:SI 1 "const0_operand" "")))
(clobber (match_scratch:SI 2 "=X,d,d"))]
[(set_attr "op_type" "RR,RS,RSY")])
(define_insn "*tstsi_cconly2"
- [(set (reg 33)
+ [(set (reg CC_REGNUM)
(compare (match_operand:SI 0 "register_operand" "d")
(match_operand:SI 1 "const0_operand" "")))]
"s390_match_ccmode(insn, CCSmode)"
[(set_attr "op_type" "RR")])
(define_insn "*tst<mode>CCT"
- [(set (reg 33)
+ [(set (reg CC_REGNUM)
(compare (match_operand:HQI 0 "nonimmediate_operand" "?Q,?S,d")
(match_operand:HQI 1 "const0_operand" "")))
(set (match_operand:HQI 2 "register_operand" "=d,d,0")
[(set_attr "op_type" "RS,RSY,RI")])
(define_insn "*tsthiCCT_cconly"
- [(set (reg 33)
+ [(set (reg CC_REGNUM)
(compare (match_operand:HI 0 "nonimmediate_operand" "Q,S,d")
(match_operand:HI 1 "const0_operand" "")))
(clobber (match_scratch:HI 2 "=d,d,X"))]
[(set_attr "op_type" "RS,RSY,RI")])
(define_insn "*tstqiCCT_cconly"
- [(set (reg 33)
+ [(set (reg CC_REGNUM)
(compare (match_operand:QI 0 "nonimmediate_operand" "?Q,?S,d")
(match_operand:QI 1 "const0_operand" "")))]
"s390_match_ccmode(insn, CCTmode)"
[(set_attr "op_type" "SI,SIY,RI")])
(define_insn "*tst<mode>"
- [(set (reg 33)
+ [(set (reg CC_REGNUM)
(compare (match_operand:HQI 0 "s_operand" "Q,S")
(match_operand:HQI 1 "const0_operand" "")))
(set (match_operand:HQI 2 "register_operand" "=d,d")
[(set_attr "op_type" "RS,RSY")])
(define_insn "*tst<mode>_cconly"
- [(set (reg 33)
+ [(set (reg CC_REGNUM)
(compare (match_operand:HQI 0 "s_operand" "Q,S")
(match_operand:HQI 1 "const0_operand" "")))
(clobber (match_scratch:HQI 2 "=d,d"))]
; Compare (equality) instructions
(define_insn "*cmpdi_cct"
- [(set (reg 33)
+ [(set (reg CC_REGNUM)
(compare (match_operand:DI 0 "nonimmediate_operand" "%d,d,d,Q")
(match_operand:DI 1 "general_operand" "d,K,m,BQ")))]
"s390_match_ccmode (insn, CCTmode) && TARGET_64BIT"
[(set_attr "op_type" "RRE,RI,RXY,SS")])
(define_insn "*cmpsi_cct"
- [(set (reg 33)
+ [(set (reg CC_REGNUM)
(compare (match_operand:SI 0 "nonimmediate_operand" "%d,d,d,d,Q")
(match_operand:SI 1 "general_operand" "d,K,R,T,BQ")))]
"s390_match_ccmode (insn, CCTmode)"
; Compare (signed) instructions
(define_insn "*cmpdi_ccs_sign"
- [(set (reg 33)
+ [(set (reg CC_REGNUM)
(compare (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m"))
(match_operand:DI 0 "register_operand" "d,d")))]
"s390_match_ccmode(insn, CCSRmode) && TARGET_64BIT"
[(set_attr "op_type" "RRE,RXY")])
(define_insn "*cmpdi_ccs"
- [(set (reg 33)
+ [(set (reg CC_REGNUM)
(compare (match_operand:DI 0 "register_operand" "d,d,d")
(match_operand:DI 1 "general_operand" "d,K,m")))]
"s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
[(set_attr "op_type" "RRE,RI,RXY")])
(define_insn "*cmpsi_ccs_sign"
- [(set (reg 33)
+ [(set (reg CC_REGNUM)
(compare (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T"))
(match_operand:SI 0 "register_operand" "d,d")))]
"s390_match_ccmode(insn, CCSRmode)"
[(set_attr "op_type" "RX,RXY")])
(define_insn "*cmpsi_ccs"
- [(set (reg 33)
+ [(set (reg CC_REGNUM)
(compare (match_operand:SI 0 "register_operand" "d,d,d,d")
(match_operand:SI 1 "general_operand" "d,K,R,T")))]
"s390_match_ccmode(insn, CCSmode)"
; Compare (unsigned) instructions
(define_insn "*cmpdi_ccu_zero"
- [(set (reg 33)
+ [(set (reg CC_REGNUM)
(compare (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m"))
(match_operand:DI 0 "register_operand" "d,d")))]
"s390_match_ccmode (insn, CCURmode) && TARGET_64BIT"
[(set_attr "op_type" "RRE,RXY")])
(define_insn "*cmpdi_ccu"
- [(set (reg 33)
+ [(set (reg CC_REGNUM)
(compare (match_operand:DI 0 "nonimmediate_operand" "d,d,Q,BQ")
(match_operand:DI 1 "general_operand" "d,m,BQ,Q")))]
"s390_match_ccmode (insn, CCUmode) && TARGET_64BIT"
[(set_attr "op_type" "RRE,RXY,SS,SS")])
(define_insn "*cmpsi_ccu"
- [(set (reg 33)
+ [(set (reg CC_REGNUM)
(compare (match_operand:SI 0 "nonimmediate_operand" "d,d,d,Q,BQ")
(match_operand:SI 1 "general_operand" "d,R,T,BQ,Q")))]
"s390_match_ccmode (insn, CCUmode)"
[(set_attr "op_type" "RR,RX,RXY,SS,SS")])
(define_insn "*cmphi_ccu"
- [(set (reg 33)
+ [(set (reg CC_REGNUM)
(compare (match_operand:HI 0 "nonimmediate_operand" "d,d,Q,BQ")
(match_operand:HI 1 "general_operand" "Q,S,BQ,Q")))]
"s390_match_ccmode (insn, CCUmode)
[(set_attr "op_type" "RS,RSY,SS,SS")])
(define_insn "*cmpqi_ccu"
- [(set (reg 33)
+ [(set (reg CC_REGNUM)
(compare (match_operand:QI 0 "nonimmediate_operand" "d,d,Q,S,Q,BQ")
(match_operand:QI 1 "general_operand" "Q,S,n,n,BQ,Q")))]
"s390_match_ccmode (insn, CCUmode)
; Block compare (CLC) instruction patterns.
(define_insn "*clc"
- [(set (reg 33)
+ [(set (reg CC_REGNUM)
(compare (match_operand:BLK 0 "memory_operand" "Q")
(match_operand:BLK 1 "memory_operand" "Q")))
(use (match_operand 2 "const_int_operand" "n"))]
[(set_attr "op_type" "SS")])
(define_split
- [(set (reg 33)
+ [(set (reg CC_REGNUM)
(compare (match_operand 0 "memory_operand" "")
(match_operand 1 "memory_operand" "")))]
"reload_completed
})
-; DF instructions
-
-(define_insn "*cmpdf_ccs_0"
- [(set (reg 33)
- (compare (match_operand:DF 0 "register_operand" "f")
- (match_operand:DF 1 "const0_operand" "")))]
- "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
- "ltdbr\t%0,%0"
- [(set_attr "op_type" "RRE")
- (set_attr "type" "fsimpd")])
-
-(define_insn "*cmpdf_ccs_0_ibm"
- [(set (reg 33)
- (compare (match_operand:DF 0 "register_operand" "f")
- (match_operand:DF 1 "const0_operand" "")))]
- "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
- "ltdr\t%0,%0"
- [(set_attr "op_type" "RR")
- (set_attr "type" "fsimpd")])
-
-(define_insn "*cmpdf_ccs"
- [(set (reg 33)
- (compare (match_operand:DF 0 "register_operand" "f,f")
- (match_operand:DF 1 "general_operand" "f,R")))]
- "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
- "@
- cdbr\t%0,%1
- cdb\t%0,%1"
- [(set_attr "op_type" "RRE,RXE")
- (set_attr "type" "fsimpd")])
-
-(define_insn "*cmpdf_ccs_ibm"
- [(set (reg 33)
- (compare (match_operand:DF 0 "register_operand" "f,f")
- (match_operand:DF 1 "general_operand" "f,R")))]
- "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
- "@
- cdr\t%0,%1
- cd\t%0,%1"
- [(set_attr "op_type" "RR,RX")
- (set_attr "type" "fsimpd")])
-
-
-; SF instructions
+; (DF|SF) instructions
-(define_insn "*cmpsf_ccs_0"
- [(set (reg 33)
- (compare (match_operand:SF 0 "register_operand" "f")
- (match_operand:SF 1 "const0_operand" "")))]
+(define_insn "*cmp<mode>_ccs_0"
+ [(set (reg CC_REGNUM)
+ (compare (match_operand:FPR 0 "register_operand" "f")
+ (match_operand:FPR 1 "const0_operand" "")))]
"s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
- "ltebr\t%0,%0"
+ "lt<de>br\t%0,%0"
[(set_attr "op_type" "RRE")
- (set_attr "type" "fsimps")])
+ (set_attr "type" "fsimp<mode>")])
-(define_insn "*cmpsf_ccs_0_ibm"
- [(set (reg 33)
- (compare (match_operand:SF 0 "register_operand" "f")
- (match_operand:SF 1 "const0_operand" "")))]
+(define_insn "*cmp<mode>_ccs_0_ibm"
+ [(set (reg CC_REGNUM)
+ (compare (match_operand:FPR 0 "register_operand" "f")
+ (match_operand:FPR 1 "const0_operand" "")))]
"s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
- "lter\t%0,%0"
+ "lt<de>r\t%0,%0"
[(set_attr "op_type" "RR")
- (set_attr "type" "fsimps")])
+ (set_attr "type" "fsimp<mode>")])
-(define_insn "*cmpsf_ccs"
- [(set (reg 33)
- (compare (match_operand:SF 0 "register_operand" "f,f")
- (match_operand:SF 1 "general_operand" "f,R")))]
+(define_insn "*cmp<mode>_ccs"
+ [(set (reg CC_REGNUM)
+ (compare (match_operand:FPR 0 "register_operand" "f,f")
+ (match_operand:FPR 1 "general_operand" "f,R")))]
"s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"@
- cebr\t%0,%1
- ceb\t%0,%1"
+ c<de>br\t%0,%1
+ c<de>b\t%0,%1"
[(set_attr "op_type" "RRE,RXE")
- (set_attr "type" "fsimps")])
+ (set_attr "type" "fsimp<mode>")])
-(define_insn "*cmpsf_ccs"
- [(set (reg 33)
- (compare (match_operand:SF 0 "register_operand" "f,f")
- (match_operand:SF 1 "general_operand" "f,R")))]
+(define_insn "*cmp<mode>_ccs_ibm"
+ [(set (reg CC_REGNUM)
+ (compare (match_operand:FPR 0 "register_operand" "f,f")
+ (match_operand:FPR 1 "general_operand" "f,R")))]
"s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
"@
- cer\t%0,%1
- ce\t%0,%1"
+ c<de>r\t%0,%1
+ c<de>\t%0,%1"
[(set_attr "op_type" "RR,RX")
- (set_attr "type" "fsimps")])
+ (set_attr "type" "fsimp<mode>")])
;;
[(set_attr "op_type" "RI,RI,RI,RI,RI,RXY,RRE,RXY,RXY,
RR,RX,RXY,RX,RXY,*,*,RS,RS,SS")
(set_attr "type" "*,*,*,*,*,la,lr,load,store,
- floadd,floadd,floadd,fstored,fstored,*,*,*,*,*")])
+ floaddf,floaddf,floaddf,fstoredf,fstoredf,*,*,*,*,*")])
(define_split
[(set (match_operand:DI 0 "register_operand" "")
stdy\t%1,%0
#"
[(set_attr "op_type" "RS,RS,*,*,RR,RX,RXY,RX,RXY,SS")
- (set_attr "type" "lm,stm,*,*,floadd,floadd,floadd,fstored,fstored,*")])
+ (set_attr "type" "lm,stm,*,*,floaddf,floaddf,floaddf,fstoredf,fstoredf,*")])
(define_split
[(set (match_operand:DI 0 "nonimmediate_operand" "")
[(parallel
[(set (match_operand:DI 0 "register_operand" "")
(match_operand:QI 1 "address_operand" ""))
- (clobber (reg:CC 33))])]
+ (clobber (reg:CC CC_REGNUM))])]
"TARGET_64BIT
&& preferred_la_operand_p (operands[1], const0_rtx)"
[(set (match_dup 0) (match_dup 1))]
[(set (match_dup 0)
(plus:DI (match_dup 0)
(match_operand:DI 2 "nonmemory_operand" "")))
- (clobber (reg:CC 33))])]
+ (clobber (reg:CC CC_REGNUM))])]
"TARGET_64BIT
&& !reg_overlap_mentioned_p (operands[0], operands[2])
&& preferred_la_operand_p (operands[1], operands[2])"
[(set_attr "op_type" "RI,RI,RI,RXY,RR,RX,RXY,RX,RXY,
RR,RX,RXY,RX,RXY,RRE,RRE,RS,RS,SS")
(set_attr "type" "*,*,*,la,lr,load,load,store,store,
- floads,floads,floads,fstores,fstores,*,*,*,*,*")])
+ floadsf,floadsf,floadsf,fstoresf,fstoresf,*,*,*,*,*")])
(define_insn "*movsi_esa"
[(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,R,!*f,!*f,!R,d,t,Q,t,?Q")
lam\t%0,%0,%S1
#"
[(set_attr "op_type" "RI,RR,RX,RX,RR,RX,RX,RRE,RRE,RS,RS,SS")
- (set_attr "type" "*,lr,load,store,floads,floads,fstores,*,*,*,*,*")])
+ (set_attr "type" "*,lr,load,store,floadsf,floadsf,fstoresf,*,*,*,*,*")])
(define_peephole2
[(set (match_operand:SI 0 "register_operand" "")
[(parallel
[(set (match_operand:SI 0 "register_operand" "")
(match_operand:QI 1 "address_operand" ""))
- (clobber (reg:CC 33))])]
+ (clobber (reg:CC CC_REGNUM))])]
"!TARGET_64BIT
&& preferred_la_operand_p (operands[1], const0_rtx)"
[(set (match_dup 0) (match_dup 1))]
[(set (match_dup 0)
(plus:SI (match_dup 0)
(match_operand:SI 2 "nonmemory_operand" "")))
- (clobber (reg:CC 33))])]
+ (clobber (reg:CC CC_REGNUM))])]
"!TARGET_64BIT
&& !reg_overlap_mentioned_p (operands[0], operands[2])
&& preferred_la_operand_p (operands[1], operands[2])"
[(set (match_operand:SI 0 "register_operand" "=d")
(and:SI (match_operand:QI 1 "address_operand" "p")
(const_int 2147483647)))
- (clobber (reg:CC 33))]
+ (clobber (reg:CC CC_REGNUM))]
"!TARGET_64BIT"
"#"
"&& reload_completed"
(define_insn "*movstricthi"
[(set (strict_low_part (match_operand:HI 0 "register_operand" "+d,d"))
(match_operand:HI 1 "memory_operand" "Q,S"))
- (clobber (reg:CC 33))]
+ (clobber (reg:CC CC_REGNUM))]
""
"@
icm\t%0,3,%S1
"")
(define_insn "*movdf_64"
- [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,R,T,d,d,m,?Q")
- (match_operand:DF 1 "general_operand" "f,R,T,f,f,d,m,d,?Q"))]
+ [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,f,R,T,d,d,m,?Q")
+ (match_operand:DF 1 "general_operand" "G,f,R,T,f,f,d,m,d,?Q"))]
"TARGET_64BIT"
"@
+ lzdr\t%0
ldr\t%0,%1
ld\t%0,%1
ldy\t%0,%1
lg\t%0,%1
stg\t%1,%0
#"
- [(set_attr "op_type" "RR,RX,RXY,RX,RXY,RRE,RXY,RXY,SS")
- (set_attr "type" "floadd,floadd,floadd,fstored,fstored,lr,load,store,*")])
+ [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RRE,RXY,RXY,SS")
+ (set_attr "type" "fsimpdf,floaddf,floaddf,floaddf,fstoredf,fstoredf,lr,load,store,*")])
(define_insn "*movdf_31"
- [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,R,T,d,Q,d,o,Q")
- (match_operand:DF 1 "general_operand" "f,R,T,f,f,Q,d,dKm,d,Q"))]
+ [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,f,R,T,d,Q,d,o,Q")
+ (match_operand:DF 1 "general_operand" "G,f,R,T,f,f,Q,d,dKm,d,Q"))]
"!TARGET_64BIT"
"@
+ lzdr\t%0
ldr\t%0,%1
ld\t%0,%1
ldy\t%0,%1
#
#
#"
- [(set_attr "op_type" "RR,RX,RXY,RX,RXY,RS,RS,*,*,SS")
- (set_attr "type" "floadd,floadd,floadd,fstored,fstored,lm,stm,*,*,*")])
+ [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RS,RS,*,*,SS")
+ (set_attr "type" "fsimpdf,floaddf,floaddf,floaddf,fstoredf,fstoredf,lm,stm,*,*,*")])
(define_split
[(set (match_operand:DF 0 "nonimmediate_operand" "")
;
(define_insn "movsf"
- [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,f,R,T,d,d,d,R,T,?Q")
- (match_operand:SF 1 "general_operand" "f,R,T,f,f,d,R,T,d,d,?Q"))]
+ [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,f,f,R,T,d,d,d,R,T,?Q")
+ (match_operand:SF 1 "general_operand" "G,f,R,T,f,f,d,R,T,d,d,?Q"))]
""
"@
+ lzer\t%0
ler\t%0,%1
le\t%0,%1
ley\t%0,%1
st\t%1,%0
sty\t%1,%0
#"
- [(set_attr "op_type" "RR,RX,RXY,RX,RXY,RR,RX,RXY,RX,RXY,SS")
- (set_attr "type" "floads,floads,floads,fstores,fstores,
+ [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RR,RX,RXY,RX,RXY,SS")
+ (set_attr "type" "fsimpsf,floadsf,floadsf,floadsf,fstoresf,fstoresf,
lr,load,load,store,store,*")])
;
(reg:QI 0)
(match_operand 3 "immediate_operand" "")] UNSPEC_SRST))
(clobber (scratch:P))
- (clobber (reg:CC 33))])
+ (clobber (reg:CC CC_REGNUM))])
(parallel
[(set (match_operand:P 0 "register_operand" "")
(minus:P (match_dup 4) (match_dup 5)))
- (clobber (reg:CC 33))])]
+ (clobber (reg:CC CC_REGNUM))])]
""
{
operands[4] = gen_reg_rtx (Pmode);
(reg:QI 0)
(match_operand 4 "immediate_operand" "")] UNSPEC_SRST))
(clobber (match_scratch:P 1 "=a"))
- (clobber (reg:CC 33))]
+ (clobber (reg:CC CC_REGNUM))]
""
"srst\t%0,%1\;jo\t.-4"
[(set_attr "length" "8")
(match_operand:BLK 1 "memory_operand" ""))
(use (match_operand 2 "general_operand" ""))
(use (match_dup 3))
- (clobber (reg:CC 33))])]
+ (clobber (reg:CC CC_REGNUM))])]
""
{
enum machine_mode dword_mode = word_mode == DImode ? TImode : DImode;
(mem:BLK (subreg:DI (match_operand:TI 3 "register_operand" "1") 0)))
(use (match_dup 2))
(use (match_dup 3))
- (clobber (reg:CC 33))]
+ (clobber (reg:CC CC_REGNUM))]
"TARGET_64BIT"
"mvcle\t%0,%1,0\;jo\t.-4"
[(set_attr "length" "8")
(mem:BLK (subreg:SI (match_operand:DI 3 "register_operand" "1") 0)))
(use (match_dup 2))
(use (match_dup 3))
- (clobber (reg:CC 33))]
+ (clobber (reg:CC CC_REGNUM))]
"!TARGET_64BIT"
"mvcle\t%0,%1,0\;jo\t.-4"
[(set_attr "length" "8")
(use (match_operand 1 "nonmemory_operand" ""))
(use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
(clobber (match_dup 2))
- (clobber (reg:CC 33))])]
+ (clobber (reg:CC CC_REGNUM))])]
""
"operands[2] = gen_rtx_SCRATCH (Pmode);")
(use (match_operand 1 "nonmemory_operand" "n,a,a"))
(use (match_operand 2 "immediate_operand" "X,R,X"))
(clobber (match_scratch 3 "=X,X,&a"))
- (clobber (reg:CC 33))]
+ (clobber (reg:CC CC_REGNUM))]
"(GET_MODE (operands[1]) == Pmode || GET_MODE (operands[1]) == VOIDmode)
&& GET_MODE (operands[3]) == Pmode"
"#"
(use (match_operand 1 "const_int_operand" ""))
(use (match_operand 2 "immediate_operand" ""))
(clobber (scratch))
- (clobber (reg:CC 33))]
+ (clobber (reg:CC CC_REGNUM))]
"reload_completed"
[(parallel
[(set (match_dup 0) (const_int 0))
(use (match_dup 1))
- (clobber (reg:CC 33))])]
+ (clobber (reg:CC CC_REGNUM))])]
"operands[1] = GEN_INT ((INTVAL (operands[1]) & 0xff) + 1);")
(define_split
(use (match_operand 1 "register_operand" ""))
(use (match_operand 2 "memory_operand" ""))
(clobber (scratch))
- (clobber (reg:CC 33))]
+ (clobber (reg:CC CC_REGNUM))]
"reload_completed"
[(parallel
[(unspec [(match_dup 1) (match_dup 2)
(const_int 0)] UNSPEC_EXECUTE)
(set (match_dup 0) (const_int 0))
(use (const_int 1))
- (clobber (reg:CC 33))])]
+ (clobber (reg:CC CC_REGNUM))])]
"")
(define_split
(use (match_operand 1 "register_operand" ""))
(use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
(clobber (match_operand 2 "register_operand" ""))
- (clobber (reg:CC 33))]
+ (clobber (reg:CC CC_REGNUM))]
"reload_completed && TARGET_CPU_ZARCH"
[(set (match_dup 2) (label_ref (match_dup 3)))
(parallel
(label_ref (match_dup 3))] UNSPEC_EXECUTE)
(set (match_dup 0) (const_int 0))
(use (const_int 1))
- (clobber (reg:CC 33))])]
+ (clobber (reg:CC CC_REGNUM))])]
"operands[3] = gen_label_rtx ();")
; Clear a block of arbitrary length.
(const_int 0))
(use (match_operand 1 "general_operand" ""))
(use (match_dup 2))
- (clobber (reg:CC 33))])]
+ (clobber (reg:CC CC_REGNUM))])]
""
{
enum machine_mode dword_mode = word_mode == DImode ? TImode : DImode;
(const_int 0))
(use (match_dup 2))
(use (match_operand:TI 1 "register_operand" "d"))
- (clobber (reg:CC 33))]
+ (clobber (reg:CC CC_REGNUM))]
"TARGET_64BIT"
"mvcle\t%0,%1,0\;jo\t.-4"
[(set_attr "length" "8")
(const_int 0))
(use (match_dup 2))
(use (match_operand:DI 1 "register_operand" "d"))
- (clobber (reg:CC 33))]
+ (clobber (reg:CC CC_REGNUM))]
"!TARGET_64BIT"
"mvcle\t%0,%1,0\;jo\t.-4"
[(set_attr "length" "8")
(define_expand "cmpmem_short"
[(parallel
- [(set (reg:CCU 33)
+ [(set (reg:CCU CC_REGNUM)
(compare:CCU (match_operand:BLK 0 "memory_operand" "")
(match_operand:BLK 1 "memory_operand" "")))
(use (match_operand 2 "nonmemory_operand" ""))
"operands[3] = gen_rtx_SCRATCH (Pmode);")
(define_insn "*cmpmem_short"
- [(set (reg:CCU 33)
+ [(set (reg:CCU CC_REGNUM)
(compare:CCU (match_operand:BLK 0 "memory_operand" "Q,Q,Q")
(match_operand:BLK 1 "memory_operand" "Q,Q,Q")))
(use (match_operand 2 "nonmemory_operand" "n,a,a"))
[(set_attr "type" "cs")])
(define_split
- [(set (reg:CCU 33)
+ [(set (reg:CCU CC_REGNUM)
(compare:CCU (match_operand:BLK 0 "memory_operand" "")
(match_operand:BLK 1 "memory_operand" "")))
(use (match_operand 2 "const_int_operand" ""))
(clobber (scratch))]
"reload_completed"
[(parallel
- [(set (reg:CCU 33) (compare:CCU (match_dup 0) (match_dup 1)))
+ [(set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
(use (match_dup 2))])]
"operands[2] = GEN_INT ((INTVAL (operands[2]) & 0xff) + 1);")
(define_split
- [(set (reg:CCU 33)
+ [(set (reg:CCU CC_REGNUM)
(compare:CCU (match_operand:BLK 0 "memory_operand" "")
(match_operand:BLK 1 "memory_operand" "")))
(use (match_operand 2 "register_operand" ""))
[(parallel
[(unspec [(match_dup 2) (match_dup 3)
(const_int 0)] UNSPEC_EXECUTE)
- (set (reg:CCU 33) (compare:CCU (match_dup 0) (match_dup 1)))
+ (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
(use (const_int 1))])]
"")
(define_split
- [(set (reg:CCU 33)
+ [(set (reg:CCU CC_REGNUM)
(compare:CCU (match_operand:BLK 0 "memory_operand" "")
(match_operand:BLK 1 "memory_operand" "")))
(use (match_operand 2 "register_operand" ""))
(parallel
[(unspec [(match_dup 2) (mem:BLK (match_dup 3))
(label_ref (match_dup 4))] UNSPEC_EXECUTE)
- (set (reg:CCU 33) (compare:CCU (match_dup 0) (match_dup 1)))
+ (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
(use (const_int 1))])]
"operands[4] = gen_label_rtx ();")
[(parallel
[(clobber (match_dup 2))
(clobber (match_dup 3))
- (set (reg:CCU 33)
+ (set (reg:CCU CC_REGNUM)
(compare:CCU (match_operand:BLK 0 "memory_operand" "")
(match_operand:BLK 1 "memory_operand" "")))
(use (match_operand 2 "general_operand" ""))
(define_insn "*cmpmem_long_64"
[(clobber (match_operand:TI 0 "register_operand" "=d"))
(clobber (match_operand:TI 1 "register_operand" "=d"))
- (set (reg:CCU 33)
+ (set (reg:CCU CC_REGNUM)
(compare:CCU (mem:BLK (subreg:DI (match_operand:TI 2 "register_operand" "0") 0))
(mem:BLK (subreg:DI (match_operand:TI 3 "register_operand" "1") 0))))
(use (match_dup 2))
(define_insn "*cmpmem_long_31"
[(clobber (match_operand:DI 0 "register_operand" "=d"))
(clobber (match_operand:DI 1 "register_operand" "=d"))
- (set (reg:CCU 33)
+ (set (reg:CCU CC_REGNUM)
(compare:CCU (mem:BLK (subreg:SI (match_operand:DI 2 "register_operand" "0") 0))
(mem:BLK (subreg:SI (match_operand:DI 3 "register_operand" "1") 0))))
(use (match_dup 2))
[(set (match_operand:SI 0 "register_operand" "=d")
(unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
UNSPEC_CMPINT))
- (clobber (reg:CC 33))]
+ (clobber (reg:CC CC_REGNUM))]
""
"#"
"reload_completed"
[(set (match_dup 0) (ashift:SI (match_dup 0) (const_int 2)))
(parallel
[(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 30)))
- (clobber (reg:CC 33))])])
+ (clobber (reg:CC CC_REGNUM))])])
(define_insn_and_split "*cmpint_cc"
- [(set (reg 33)
+ [(set (reg CC_REGNUM)
(compare (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
UNSPEC_CMPINT)
(const_int 0)))
[(set (match_operand:DI 0 "register_operand" "=d")
(sign_extend:DI (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
UNSPEC_CMPINT)))
- (clobber (reg:CC 33))]
+ (clobber (reg:CC CC_REGNUM))]
"TARGET_64BIT"
"#"
"&& reload_completed"
[(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34)))
(parallel
[(set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 62)))
- (clobber (reg:CC 33))])])
+ (clobber (reg:CC CC_REGNUM))])])
(define_insn_and_split "*cmpint_sign_cc"
- [(set (reg 33)
+ [(set (reg CC_REGNUM)
(compare (ashiftrt:DI (ashift:DI (subreg:DI
(unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
UNSPEC_CMPINT) 0)
(define_insn "*sethigh<mode>si"
[(set (match_operand:SI 0 "register_operand" "=d,d")
(unspec:SI [(match_operand:HQI 1 "s_operand" "Q,S")] UNSPEC_SETHIGH))
- (clobber (reg:CC 33))]
+ (clobber (reg:CC CC_REGNUM))]
""
"@
icm\t%0,<icm_hi>,%S1
(define_insn "*sethighqidi_64"
[(set (match_operand:DI 0 "register_operand" "=d")
(unspec:DI [(match_operand:QI 1 "s_operand" "QS")] UNSPEC_SETHIGH))
- (clobber (reg:CC 33))]
+ (clobber (reg:CC CC_REGNUM))]
"TARGET_64BIT"
"icmh\t%0,8,%S1"
[(set_attr "op_type" "RSY")])
(define_insn "*sethighqidi_31"
[(set (match_operand:DI 0 "register_operand" "=d,d")
(unspec:DI [(match_operand:QI 1 "s_operand" "Q,S")] UNSPEC_SETHIGH))
- (clobber (reg:CC 33))]
+ (clobber (reg:CC CC_REGNUM))]
"!TARGET_64BIT"
"@
icm\t%0,8,%S1
(zero_extract:SI (match_operand:QI 1 "s_operand" "Q")
(match_operand 2 "const_int_operand" "n")
(const_int 0)))
- (clobber (reg:CC 33))]
+ (clobber (reg:CC CC_REGNUM))]
"!TARGET_64BIT
&& INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 8"
"#"
"&& reload_completed"
[(parallel
[(set (match_dup 0) (unspec:SI [(match_dup 1)] UNSPEC_SETHIGH))
- (clobber (reg:CC 33))])
+ (clobber (reg:CC CC_REGNUM))])
(set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 2)))]
{
operands[2] = GEN_INT (32 - INTVAL (operands[2]));
(zero_extract:SI (match_operand:QI 1 "s_operand" "Q")
(match_operand 2 "const_int_operand" "n")
(const_int 0)))
- (clobber (reg:CC 33))]
+ (clobber (reg:CC CC_REGNUM))]
"!TARGET_64BIT
&& INTVAL (operands[2]) >= 8 && INTVAL (operands[2]) < 16"
"#"
"&& reload_completed"
[(parallel
[(set (match_dup 0) (unspec:SI [(match_dup 1)] UNSPEC_SETHIGH))
- (clobber (reg:CC 33))])
+ (clobber (reg:CC CC_REGNUM))])
(set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 2)))]
{
operands[2] = GEN_INT (32 - INTVAL (operands[2]));
(define_insn_and_split "*extendqidi2_short_displ"
[(set (match_operand:DI 0 "register_operand" "=d")
(sign_extend:DI (match_operand:QI 1 "s_operand" "Q")))
- (clobber (reg:CC 33))]
+ (clobber (reg:CC CC_REGNUM))]
"TARGET_64BIT && !TARGET_LONG_DISPLACEMENT"
"#"
"&& reload_completed"
[(parallel
[(set (match_dup 0) (unspec:DI [(match_dup 1)] UNSPEC_SETHIGH))
- (clobber (reg:CC 33))])
+ (clobber (reg:CC CC_REGNUM))])
(parallel
[(set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 56)))
- (clobber (reg:CC 33))])]
+ (clobber (reg:CC CC_REGNUM))])]
"")
;
(define_insn_and_split "*extendqisi2_short_displ"
[(set (match_operand:SI 0 "register_operand" "=d")
(sign_extend:SI (match_operand:QI 1 "s_operand" "Q")))
- (clobber (reg:CC 33))]
+ (clobber (reg:CC CC_REGNUM))]
"!TARGET_LONG_DISPLACEMENT"
"#"
"&& reload_completed"
[(parallel
[(set (match_dup 0) (unspec:SI [(match_dup 1)] UNSPEC_SETHIGH))
- (clobber (reg:CC 33))])
+ (clobber (reg:CC CC_REGNUM))])
(parallel
[(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 24)))
- (clobber (reg:CC 33))])]
+ (clobber (reg:CC CC_REGNUM))])]
"")
;
[(set (match_operand:DI 0 "register_operand" "=d")
(and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "m") 0)
(const_int 2147483647)))
- (clobber (reg:CC 33))]
+ (clobber (reg:CC CC_REGNUM))]
"TARGET_64BIT"
"#"
"&& reload_completed"
[(set (match_operand:GPR 0 "register_operand" "")
(and:GPR (match_operand:GPR 1 "nonimmediate_operand" "")
(const_int 2147483647)))
- (clobber (reg:CC 33))]
+ (clobber (reg:CC CC_REGNUM))]
"TARGET_64BIT && reload_completed"
[(set (match_dup 0)
(and:GPR (match_dup 1)
(define_insn_and_split "*zero_extendhisi2_31"
[(set (match_operand:SI 0 "register_operand" "=&d")
(zero_extend:SI (match_operand:HI 1 "s_operand" "QS")))
- (clobber (reg:CC 33))]
+ (clobber (reg:CC CC_REGNUM))]
"!TARGET_ZARCH"
"#"
"&& reload_completed"
[(set (match_dup 0) (const_int 0))
(parallel
[(set (strict_low_part (match_dup 2)) (match_dup 1))
- (clobber (reg:CC 33))])]
+ (clobber (reg:CC CC_REGNUM))])]
"operands[2] = gen_lowpart (HImode, operands[0]);")
(define_insn_and_split "*zero_extendqisi2_31"
;
-; fixuns_truncdfdi2 and fix_truncdfsi2 instruction pattern(s).
+; fixuns_trunc(sf|df)(si|di)2 and fix_trunc(sf|df)(si|di)2 instruction pattern(s).
;
-(define_expand "fixuns_truncdfdi2"
- [(set (match_operand:DI 0 "register_operand" "")
- (unsigned_fix:DI (match_operand:DF 1 "register_operand" "")))]
- "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
+(define_expand "fixuns_trunc<FPR:mode><GPR:mode>2"
+ [(set (match_operand:GPR 0 "register_operand" "")
+ (unsigned_fix:GPR (match_operand:FPR 1 "register_operand" "")))]
+ "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
{
rtx label1 = gen_label_rtx ();
rtx label2 = gen_label_rtx ();
- rtx temp = gen_reg_rtx (DFmode);
- operands[1] = force_reg (DFmode, operands[1]);
-
- emit_insn (gen_cmpdf (operands[1],
- CONST_DOUBLE_FROM_REAL_VALUE (
- REAL_VALUE_ATOF ("9223372036854775808.0", DFmode), DFmode)));
+ rtx temp = gen_reg_rtx (<FPR:MODE>mode);
+ REAL_VALUE_TYPE cmp, sub;
+
+ operands[1] = force_reg (<FPR:MODE>mode, operands[1]);
+ real_2expN (&cmp, GET_MODE_BITSIZE(<GPR:MODE>mode) - 1);
+ real_2expN (&sub, GET_MODE_BITSIZE(<GPR:MODE>mode));
+
+ emit_insn (gen_cmp<FPR:mode> (operands[1],
+ CONST_DOUBLE_FROM_REAL_VALUE (cmp, <FPR:MODE>mode)));
emit_jump_insn (gen_blt (label1));
- emit_insn (gen_subdf3 (temp, operands[1],
- CONST_DOUBLE_FROM_REAL_VALUE (
- REAL_VALUE_ATOF ("18446744073709551616.0", DFmode), DFmode)));
- emit_insn (gen_fix_truncdfdi2_ieee (operands[0], temp, GEN_INT(7)));
+ emit_insn (gen_sub<FPR:mode>3 (temp, operands[1],
+ CONST_DOUBLE_FROM_REAL_VALUE (sub, <FPR:MODE>mode)));
+ emit_insn (gen_fix_trunc<FPR:mode><GPR:mode>2_ieee (operands[0], temp,
+ GEN_INT(7)));
emit_jump (label2);
emit_label (label1);
- emit_insn (gen_fix_truncdfdi2_ieee (operands[0], operands[1], GEN_INT(5)));
+ emit_insn (gen_fix_trunc<FPR:mode><GPR:mode>2_ieee (operands[0],
+ operands[1], GEN_INT(5)));
emit_label (label2);
DONE;
})
-(define_expand "fix_truncdfdi2"
+(define_expand "fix_trunc<FPR:mode>di2"
[(set (match_operand:DI 0 "register_operand" "")
- (fix:DI (match_operand:DF 1 "nonimmediate_operand" "")))]
+ (fix:DI (match_operand:FPR 1 "nonimmediate_operand" "")))]
"TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
{
- operands[1] = force_reg (DFmode, operands[1]);
- emit_insn (gen_fix_truncdfdi2_ieee (operands[0], operands[1], GEN_INT(5)));
+ operands[1] = force_reg (<FPR:MODE>mode, operands[1]);
+ emit_insn (gen_fix_trunc<FPR:mode>di2_ieee (operands[0], operands[1],
+ GEN_INT(5)));
DONE;
})
-(define_insn "fix_truncdfdi2_ieee"
- [(set (match_operand:DI 0 "register_operand" "=d")
- (fix:DI (match_operand:DF 1 "register_operand" "f")))
- (unspec:DI [(match_operand:DI 2 "immediate_operand" "K")] UNSPEC_ROUND)
- (clobber (reg:CC 33))]
- "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
- "cgdbr\t%0,%h2,%1"
+(define_insn "fix_trunc<FPR:mode><GPR:mode>2_ieee"
+ [(set (match_operand:GPR 0 "register_operand" "=d")
+ (fix:GPR (match_operand:FPR 1 "register_operand" "f")))
+ (unspec:GPR [(match_operand:GPR 2 "immediate_operand" "K")] UNSPEC_ROUND)
+ (clobber (reg:CC CC_REGNUM))]
+ "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
+ "c<GPR:gf><FPR:de>br\t%0,%h2,%1"
[(set_attr "op_type" "RRE")
(set_attr "type" "ftoi")])
;
-; fixuns_truncdfsi2 and fix_truncdfsi2 instruction pattern(s).
+; fix_truncdfsi2 instruction pattern(s).
;
-(define_expand "fixuns_truncdfsi2"
- [(set (match_operand:SI 0 "register_operand" "")
- (unsigned_fix:SI (match_operand:DF 1 "register_operand" "")))]
- "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
-{
- rtx label1 = gen_label_rtx ();
- rtx label2 = gen_label_rtx ();
- rtx temp = gen_reg_rtx (DFmode);
-
- operands[1] = force_reg (DFmode,operands[1]);
- emit_insn (gen_cmpdf (operands[1],
- CONST_DOUBLE_FROM_REAL_VALUE (
- REAL_VALUE_ATOF ("2147483648.0", DFmode), DFmode)));
- emit_jump_insn (gen_blt (label1));
- emit_insn (gen_subdf3 (temp, operands[1],
- CONST_DOUBLE_FROM_REAL_VALUE (
- REAL_VALUE_ATOF ("4294967296.0", DFmode), DFmode)));
- emit_insn (gen_fix_truncdfsi2_ieee (operands[0], temp, GEN_INT (7)));
- emit_jump (label2);
-
- emit_label (label1);
- emit_insn (gen_fix_truncdfsi2_ieee (operands[0], operands[1], GEN_INT (5)));
- emit_label (label2);
- DONE;
-})
-
(define_expand "fix_truncdfsi2"
[(set (match_operand:SI 0 "register_operand" "")
(fix:SI (match_operand:DF 1 "nonimmediate_operand" "")))]
DONE;
})
-(define_insn "fix_truncdfsi2_ieee"
- [(set (match_operand:SI 0 "register_operand" "=d")
- (fix:SI (match_operand:DF 1 "register_operand" "f")))
- (unspec:SI [(match_operand:SI 2 "immediate_operand" "K")] UNSPEC_ROUND)
- (clobber (reg:CC 33))]
- "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
- "cfdbr\t%0,%h2,%1"
- [(set_attr "op_type" "RRE")
- (set_attr "type" "ftoi")])
-
(define_insn "fix_truncdfsi2_ibm"
[(set (match_operand:SI 0 "register_operand" "=d")
(fix:SI (match_operand:DF 1 "nonimmediate_operand" "+f")))
(use (match_operand:DI 2 "immediate_operand" "m"))
(use (match_operand:DI 3 "immediate_operand" "m"))
(use (match_operand:BLK 4 "memory_operand" "m"))
- (clobber (reg:CC 33))]
+ (clobber (reg:CC CC_REGNUM))]
"TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
{
output_asm_insn ("sd\t%1,%2", operands);
[(set_attr "length" "20")])
;
-; fixuns_truncsfdi2 and fix_truncsfdi2 instruction pattern(s).
-;
-
-(define_expand "fixuns_truncsfdi2"
- [(set (match_operand:DI 0 "register_operand" "")
- (unsigned_fix:DI (match_operand:SF 1 "register_operand" "")))]
- "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
-{
- rtx label1 = gen_label_rtx ();
- rtx label2 = gen_label_rtx ();
- rtx temp = gen_reg_rtx (SFmode);
-
- operands[1] = force_reg (SFmode, operands[1]);
- emit_insn (gen_cmpsf (operands[1],
- CONST_DOUBLE_FROM_REAL_VALUE (
- REAL_VALUE_ATOF ("9223372036854775808.0", SFmode), SFmode)));
- emit_jump_insn (gen_blt (label1));
-
- emit_insn (gen_subsf3 (temp, operands[1],
- CONST_DOUBLE_FROM_REAL_VALUE (
- REAL_VALUE_ATOF ("18446744073709551616.0", SFmode), SFmode)));
- emit_insn (gen_fix_truncsfdi2_ieee (operands[0], temp, GEN_INT(7)));
- emit_jump (label2);
-
- emit_label (label1);
- emit_insn (gen_fix_truncsfdi2_ieee (operands[0], operands[1], GEN_INT(5)));
- emit_label (label2);
- DONE;
-})
-
-(define_expand "fix_truncsfdi2"
- [(set (match_operand:DI 0 "register_operand" "")
- (fix:DI (match_operand:SF 1 "nonimmediate_operand" "")))]
- "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
-{
- operands[1] = force_reg (SFmode, operands[1]);
- emit_insn (gen_fix_truncsfdi2_ieee (operands[0], operands[1], GEN_INT(5)));
- DONE;
-})
-
-(define_insn "fix_truncsfdi2_ieee"
- [(set (match_operand:DI 0 "register_operand" "=d")
- (fix:DI (match_operand:SF 1 "register_operand" "f")))
- (unspec:DI [(match_operand:DI 2 "immediate_operand" "K")] UNSPEC_ROUND)
- (clobber (reg:CC 33))]
- "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
- "cgebr\t%0,%h2,%1"
- [(set_attr "op_type" "RRE")
- (set_attr "type" "ftoi")])
-
-;
-; fixuns_truncsfsi2 and fix_truncsfsi2 instruction pattern(s).
+; fix_truncsfsi2 instruction pattern(s).
;
-(define_expand "fixuns_truncsfsi2"
- [(set (match_operand:SI 0 "register_operand" "")
- (unsigned_fix:SI (match_operand:SF 1 "register_operand" "")))]
- "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
-{
- rtx label1 = gen_label_rtx ();
- rtx label2 = gen_label_rtx ();
- rtx temp = gen_reg_rtx (SFmode);
-
- operands[1] = force_reg (SFmode, operands[1]);
- emit_insn (gen_cmpsf (operands[1],
- CONST_DOUBLE_FROM_REAL_VALUE (
- REAL_VALUE_ATOF ("2147483648.0", SFmode), SFmode)));
- emit_jump_insn (gen_blt (label1));
- emit_insn (gen_subsf3 (temp, operands[1],
- CONST_DOUBLE_FROM_REAL_VALUE (
- REAL_VALUE_ATOF ("4294967296.0", SFmode), SFmode)));
- emit_insn (gen_fix_truncsfsi2_ieee (operands[0], temp, GEN_INT (7)));
- emit_jump (label2);
-
- emit_label (label1);
- emit_insn (gen_fix_truncsfsi2_ieee (operands[0], operands[1], GEN_INT (5)));
- emit_label (label2);
- DONE;
-})
-
(define_expand "fix_truncsfsi2"
[(set (match_operand:SI 0 "register_operand" "")
(fix:SI (match_operand:SF 1 "nonimmediate_operand" "")))]
DONE;
})
-(define_insn "fix_truncsfsi2_ieee"
- [(set (match_operand:SI 0 "register_operand" "=d")
- (fix:SI (match_operand:SF 1 "register_operand" "f")))
- (unspec:SI [(match_operand:SI 2 "immediate_operand" "K")] UNSPEC_ROUND)
- (clobber (reg:CC 33))]
- "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
- "cfebr\t%0,%h2,%1"
- [(set_attr "op_type" "RRE")
- (set_attr "type" "ftoi")])
-
-;
-; floatdidf2 instruction pattern(s).
-;
-
-(define_insn "floatdidf2"
- [(set (match_operand:DF 0 "register_operand" "=f")
- (float:DF (match_operand:DI 1 "register_operand" "d")))]
- "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
- "cdgbr\t%0,%1"
- [(set_attr "op_type" "RRE")
- (set_attr "type" "itof" )])
-
;
-; floatdisf2 instruction pattern(s).
+; floatdi(df|sf)2 instruction pattern(s).
;
-(define_insn "floatdisf2"
- [(set (match_operand:SF 0 "register_operand" "=f")
- (float:SF (match_operand:DI 1 "register_operand" "d")))]
+(define_insn "floatdi<mode>2"
+ [(set (match_operand:FPR 0 "register_operand" "=f")
+ (float:FPR (match_operand:DI 1 "register_operand" "d")))]
"TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
- "cegbr\t%0,%1"
+ "c<de>gbr\t%0,%1"
[(set_attr "op_type" "RRE")
(set_attr "type" "itof" )])
(float:DF (match_operand:SI 1 "register_operand" "d")))
(use (match_operand:DI 2 "immediate_operand" "m"))
(use (match_operand:BLK 3 "memory_operand" "m"))
- (clobber (reg:CC 33))]
+ (clobber (reg:CC CC_REGNUM))]
"TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
{
output_asm_insn ("st\t%1,%N3", operands);
ler\t%0,%1
le\t%0,%1"
[(set_attr "op_type" "RR,RX")
- (set_attr "type" "floads,floads")])
+ (set_attr "type" "floadsf")])
;
; extendsfdf2 instruction pattern(s).
ldebr\t%0,%1
ldeb\t%0,%1"
[(set_attr "op_type" "RRE,RXE")
- (set_attr "type" "floads,floads")])
+ (set_attr "type" "floadsf")])
(define_insn "extendsfdf2_ibm"
[(set (match_operand:DF 0 "register_operand" "=f,f")
(float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,R")))
- (clobber (reg:CC 33))]
+ (clobber (reg:CC CC_REGNUM))]
"TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
"@
sdr\t%0,%0\;ler\t%0,%1
sdr\t%0,%0\;le\t%0,%1"
[(set_attr "length" "4,6")
- (set_attr "type" "floads,floads")])
+ (set_attr "type" "floadsf")])
;;
[(set (match_operand:TI 0 "register_operand" "=&d")
(plus:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
(match_operand:TI 2 "general_operand" "do") ) )
- (clobber (reg:CC 33))]
+ (clobber (reg:CC CC_REGNUM))]
"TARGET_64BIT"
"#"
"&& reload_completed"
[(parallel
- [(set (reg:CCL1 33)
+ [(set (reg:CCL1 CC_REGNUM)
(compare:CCL1 (plus:DI (match_dup 7) (match_dup 8))
(match_dup 7)))
(set (match_dup 6) (plus:DI (match_dup 7) (match_dup 8)))])
(parallel
[(set (match_dup 3) (plus:DI (plus:DI (match_dup 4) (match_dup 5))
- (ltu:DI (reg:CCL1 33) (const_int 0))))
- (clobber (reg:CC 33))])]
+ (ltu:DI (reg:CCL1 CC_REGNUM) (const_int 0))))
+ (clobber (reg:CC CC_REGNUM))])]
"operands[3] = operand_subword (operands[0], 0, 0, TImode);
operands[4] = operand_subword (operands[1], 0, 0, TImode);
operands[5] = operand_subword (operands[2], 0, 0, TImode);
[(set (match_operand:DI 0 "register_operand" "=d,d")
(plus:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,m"))
(match_operand:DI 1 "register_operand" "0,0")))
- (clobber (reg:CC 33))]
+ (clobber (reg:CC CC_REGNUM))]
"TARGET_64BIT"
"@
agfr\t%0,%2
[(set_attr "op_type" "RRE,RXY")])
(define_insn "*adddi3_zero_cc"
- [(set (reg 33)
+ [(set (reg CC_REGNUM)
(compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))
(match_operand:DI 1 "register_operand" "0,0"))
(const_int 0)))
[(set_attr "op_type" "RRE,RXY")])
(define_insn "*adddi3_zero_cconly"
- [(set (reg 33)
+ [(set (reg CC_REGNUM)
(compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))
(match_operand:DI 1 "register_operand" "0,0"))
(const_int 0)))
[(set (match_operand:DI 0 "register_operand" "=d,d")
(plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))
(match_operand:DI 1 "register_operand" "0,0")))
- (clobber (reg:CC 33))]
+ (clobber (reg:CC CC_REGNUM))]
"TARGET_64BIT"
"@
algfr\t%0,%2
[(set_attr "op_type" "RRE,RXY")])
(define_insn "*adddi3_imm_cc"
- [(set (reg 33)
+ [(set (reg CC_REGNUM)
(compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "0")
(match_operand:DI 2 "const_int_operand" "K"))
(const_int 0)))
[(set_attr "op_type" "RI")])
(define_insn "*adddi3_carry1_cc"
- [(set (reg 33)
+ [(set (reg CC_REGNUM)
(compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
(match_operand:DI 2 "general_operand" "d,m"))
(match_dup 1)))
[(set_attr "op_type" "RRE,RXY")])
(define_insn "*adddi3_carry1_cconly"
- [(set (reg 33)
+ [(set (reg CC_REGNUM)
(compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
(match_operand:DI 2 "general_operand" "d,m"))
(match_dup 1)))
[(set_attr "op_type" "RRE,RXY")])
(define_insn "*adddi3_carry2_cc"
- [(set (reg 33)
+ [(set (reg CC_REGNUM)
(compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
(match_operand:DI 2 "general_operand" "d,m"))
(match_dup 2)))
[(set_attr "op_type" "RRE,RXY")])
(define_insn "*adddi3_carry2_cconly"
- [(set (reg 33)
+ [(set (reg CC_REGNUM)
(compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
(match_operand:DI 2 "general_operand" "d,m"))
(match_dup 2)))
[(set_attr "op_type" "RRE,RXY")])
(define_insn "*adddi3_cc"
- [(set (reg 33)
+ [(set (reg CC_REGNUM)
(compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
(match_operand:DI 2 "general_operand" "d,m"))
(const_int 0)))
[(set_attr "op_type" "RRE,RXY")])
(define_insn "*adddi3_cconly"
- [(set (reg 33)
+ [(set (reg CC_REGNUM)
(compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
(match_operand:DI 2 "general_operand" "d,m"))
(const_int 0)))
[(set_attr "op_type" "RRE,RXY")])
(define_insn "*adddi3_cconly2"
- [(set (reg 33)
+ [(set (reg CC_REGNUM)
(compare (match_operand:DI 1 "nonimmediate_operand" "%0,0")
(neg:SI (match_operand:DI 2 "general_operand" "d,m"))))
(clobber (match_scratch:DI 0 "=d,d"))]
[(set (match_operand:DI 0 "register_operand" "=d,d,d")
(plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0")
(match_operand:DI 2 "general_operand" "d,K,m") ) )
- (clobber (reg:CC 33))]
+ (clobber (reg:CC CC_REGNUM))]
"TARGET_64BIT"
"@
agr\t%0,%2
[(set (match_operand:DI 0 "register_operand" "=&d")
(plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
(match_operand:DI 2 "general_operand" "do") ) )
- (clobber (reg:CC 33))]
+ (clobber (reg:CC CC_REGNUM))]
"!TARGET_64BIT && TARGET_CPU_ZARCH"
"#"
"&& reload_completed"
[(parallel
- [(set (reg:CCL1 33)
+ [(set (reg:CCL1 CC_REGNUM)
(compare:CCL1 (plus:SI (match_dup 7) (match_dup 8))
(match_dup 7)))
(set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))])
(parallel
[(set (match_dup 3) (plus:SI (plus:SI (match_dup 4) (match_dup 5))
- (ltu:SI (reg:CCL1 33) (const_int 0))))
- (clobber (reg:CC 33))])]
+ (ltu:SI (reg:CCL1 CC_REGNUM) (const_int 0))))
+ (clobber (reg:CC CC_REGNUM))])]
"operands[3] = operand_subword (operands[0], 0, 0, DImode);
operands[4] = operand_subword (operands[1], 0, 0, DImode);
operands[5] = operand_subword (operands[2], 0, 0, DImode);
[(set (match_operand:DI 0 "register_operand" "=&d")
(plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
(match_operand:DI 2 "general_operand" "do") ) )
- (clobber (reg:CC 33))]
+ (clobber (reg:CC CC_REGNUM))]
"!TARGET_CPU_ZARCH"
"#"
"&& reload_completed"
[(parallel
[(set (match_dup 3) (plus:SI (match_dup 4) (match_dup 5)))
- (clobber (reg:CC 33))])
+ (clobber (reg:CC CC_REGNUM))])
(parallel
- [(set (reg:CCL1 33)
+ [(set (reg:CCL1 CC_REGNUM)
(compare:CCL1 (plus:SI (match_dup 7) (match_dup 8))
(match_dup 7)))
(set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))])
(set (pc)
- (if_then_else (ltu (reg:CCL1 33) (const_int 0))
+ (if_then_else (ltu (reg:CCL1 CC_REGNUM) (const_int 0))
(pc)
(label_ref (match_dup 9))))
(parallel
[(set (match_dup 3) (plus:SI (match_dup 3) (const_int 1)))
- (clobber (reg:CC 33))])
+ (clobber (reg:CC CC_REGNUM))])
(match_dup 9)]
"operands[3] = operand_subword (operands[0], 0, 0, DImode);
operands[4] = operand_subword (operands[1], 0, 0, DImode);
[(set (match_operand:DI 0 "register_operand" "")
(plus:DI (match_operand:DI 1 "nonimmediate_operand" "")
(match_operand:DI 2 "general_operand" "")))
- (clobber (reg:CC 33))])]
+ (clobber (reg:CC CC_REGNUM))])]
""
"")
;
(define_insn "*addsi3_imm_cc"
- [(set (reg 33)
+ [(set (reg CC_REGNUM)
(compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "0")
(match_operand:SI 2 "const_int_operand" "K"))
(const_int 0)))
[(set_attr "op_type" "RI")])
(define_insn "*addsi3_carry1_cc"
- [(set (reg 33)
+ [(set (reg CC_REGNUM)
(compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
(match_operand:SI 2 "general_operand" "d,R,T"))
(match_dup 1)))
[(set_attr "op_type" "RR,RX,RXY")])
(define_insn "*addsi3_carry1_cconly"
- [(set (reg 33)
+ [(set (reg CC_REGNUM)
(compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
(match_operand:SI 2 "general_operand" "d,R,T"))
(match_dup 1)))
[(set_attr "op_type" "RR,RX,RXY")])
(define_insn "*addsi3_carry2_cc"
- [(set (reg 33)
+ [(set (reg CC_REGNUM)
(compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
(match_operand:SI 2 "general_operand" "d,R,T"))
(match_dup 2)))
[(set_attr "op_type" "RR,RX,RXY")])
(define_insn "*addsi3_carry2_cconly"
- [(set (reg 33)
+ [(set (reg CC_REGNUM)
(compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
(match_operand:SI 2 "general_operand" "d,R,T"))
(match_dup 2)))
[(set_attr "op_type" "RR,RX,RXY")])
(define_insn "*addsi3_cc"
- [(set (reg 33)
+ [(set (reg CC_REGNUM)
(compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
(match_operand:SI 2 "general_operand" "d,R,T"))
(const_int 0)))
[(set_attr "op_type" "RR,RX,RXY")])
(define_insn "*addsi3_cconly"
- [(set (reg 33)
+ [(set (reg CC_REGNUM)
(compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
(match_operand:SI 2 "general_operand" "d,R,T"))
(const_int 0)))
[(set_attr "op_type" "RR,RX,RXY")])
(define_insn "*addsi3_cconly2"
- [(set (reg 33)
+ [(set (reg CC_REGNUM)
(compare (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
(neg:SI (match_operand:SI 2 "general_operand" "d,R,T"))))
(clobber (match_scratch:SI 0 "=d,d,d"))]
[(set (match_operand:SI 0 "register_operand" "=d,d")
(plus:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T"))
(match_operand:SI 1 "register_operand" "0,0")))
- (clobber (reg:CC 33))]
+ (clobber (reg:CC CC_REGNUM))]
""
"@
ah\t%0,%2
[(set (match_operand:SI 0 "register_operand" "=d,d,d,d")
(plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
(match_operand:SI 2 "general_operand" "d,K,R,T")))
- (clobber (reg:CC 33))]
+ (clobber (reg:CC CC_REGNUM))]
""
"@
ar\t%0,%2
[(set_attr "op_type" "RR,RI,RX,RXY")])
;
-; adddf3 instruction pattern(s).
+; add(df|sf)3 instruction pattern(s).
;
-(define_expand "adddf3"
+(define_expand "add<mode>3"
[(parallel
- [(set (match_operand:DF 0 "register_operand" "=f,f")
- (plus:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0")
- (match_operand:DF 2 "general_operand" "f,R")))
- (clobber (reg:CC 33))])]
+ [(set (match_operand:FPR 0 "register_operand" "=f,f")
+ (plus:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
+ (match_operand:FPR 2 "general_operand" "f,R")))
+ (clobber (reg:CC CC_REGNUM))])]
"TARGET_HARD_FLOAT"
"")
-(define_insn "*adddf3"
- [(set (match_operand:DF 0 "register_operand" "=f,f")
- (plus:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0")
- (match_operand:DF 2 "general_operand" "f,R")))
- (clobber (reg:CC 33))]
+(define_insn "*add<mode>3"
+ [(set (match_operand:FPR 0 "register_operand" "=f,f")
+ (plus:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
+ (match_operand:FPR 2 "general_operand" "f,R")))
+ (clobber (reg:CC CC_REGNUM))]
"TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"@
- adbr\t%0,%2
- adb\t%0,%2"
+ a<de>br\t%0,%2
+ a<de>b\t%0,%2"
[(set_attr "op_type" "RRE,RXE")
- (set_attr "type" "fsimpd,fsimpd")])
-
-(define_insn "*adddf3_cc"
- [(set (reg 33)
- (compare (plus:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0")
- (match_operand:DF 2 "general_operand" "f,R"))
- (match_operand:DF 3 "const0_operand" "")))
- (set (match_operand:DF 0 "register_operand" "=f,f")
- (plus:DF (match_dup 1) (match_dup 2)))]
+ (set_attr "type" "fsimp<mode>")])
+
+(define_insn "*add<mode>3_cc"
+ [(set (reg CC_REGNUM)
+ (compare (plus:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
+ (match_operand:FPR 2 "general_operand" "f,R"))
+ (match_operand:FPR 3 "const0_operand" "")))
+ (set (match_operand:FPR 0 "register_operand" "=f,f")
+ (plus:FPR (match_dup 1) (match_dup 2)))]
"s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"@
- adbr\t%0,%2
- adb\t%0,%2"
+ a<de>br\t%0,%2
+ a<de>b\t%0,%2"
[(set_attr "op_type" "RRE,RXE")
- (set_attr "type" "fsimpd,fsimpd")])
-
-(define_insn "*adddf3_cconly"
- [(set (reg 33)
- (compare (plus:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0")
- (match_operand:DF 2 "general_operand" "f,R"))
- (match_operand:DF 3 "const0_operand" "")))
- (clobber (match_scratch:DF 0 "=f,f"))]
+ (set_attr "type" "fsimp<mode>")])
+
+(define_insn "*add<mode>3_cconly"
+ [(set (reg CC_REGNUM)
+ (compare (plus:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
+ (match_operand:FPR 2 "general_operand" "f,R"))
+ (match_operand:FPR 3 "const0_operand" "")))
+ (clobber (match_scratch:FPR 0 "=f,f"))]
"s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"@
- adbr\t%0,%2
- adb\t%0,%2"
+ a<de>br\t%0,%2
+ a<de>b\t%0,%2"
[(set_attr "op_type" "RRE,RXE")
- (set_attr "type" "fsimpd,fsimpd")])
+ (set_attr "type" "fsimp<mode>")])
-(define_insn "*adddf3_ibm"
- [(set (match_operand:DF 0 "register_operand" "=f,f")
- (plus:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0")
- (match_operand:DF 2 "general_operand" "f,R")))
- (clobber (reg:CC 33))]
+(define_insn "*add<mode>3_ibm"
+ [(set (match_operand:FPR 0 "register_operand" "=f,f")
+ (plus:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
+ (match_operand:FPR 2 "general_operand" "f,R")))
+ (clobber (reg:CC CC_REGNUM))]
"TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
"@
- adr\t%0,%2
- ad\t%0,%2"
+ a<de>r\t%0,%2
+ a<de>\t%0,%2"
[(set_attr "op_type" "RR,RX")
- (set_attr "type" "fsimpd,fsimpd")])
-
-;
-; addsf3 instruction pattern(s).
-;
-
-(define_expand "addsf3"
- [(parallel
- [(set (match_operand:SF 0 "register_operand" "=f,f")
- (plus:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0")
- (match_operand:SF 2 "general_operand" "f,R")))
- (clobber (reg:CC 33))])]
- "TARGET_HARD_FLOAT"
- "")
-
-(define_insn "*addsf3"
- [(set (match_operand:SF 0 "register_operand" "=f,f")
- (plus:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0")
- (match_operand:SF 2 "general_operand" "f,R")))
- (clobber (reg:CC 33))]
- "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
- "@
- aebr\t%0,%2
- aeb\t%0,%2"
- [(set_attr "op_type" "RRE,RXE")
- (set_attr "type" "fsimps,fsimps")])
-
-(define_insn "*addsf3_cc"
- [(set (reg 33)
- (compare (plus:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0")
- (match_operand:SF 2 "general_operand" "f,R"))
- (match_operand:SF 3 "const0_operand" "")))
- (set (match_operand:SF 0 "register_operand" "=f,f")
- (plus:SF (match_dup 1) (match_dup 2)))]
- "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
- "@
- aebr\t%0,%2
- aeb\t%0,%2"
- [(set_attr "op_type" "RRE,RXE")
- (set_attr "type" "fsimps,fsimps")])
-
-(define_insn "*addsf3_cconly"
- [(set (reg 33)
- (compare (plus:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0")
- (match_operand:SF 2 "general_operand" "f,R"))
- (match_operand:SF 3 "const0_operand" "")))
- (clobber (match_scratch:SF 0 "=f,f"))]
- "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
- "@
- aebr\t%0,%2
- aeb\t%0,%2"
- [(set_attr "op_type" "RRE,RXE")
- (set_attr "type" "fsimps,fsimps")])
-
-(define_insn "*addsf3"
- [(set (match_operand:SF 0 "register_operand" "=f,f")
- (plus:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0")
- (match_operand:SF 2 "general_operand" "f,R")))
- (clobber (reg:CC 33))]
- "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
- "@
- aer\t%0,%2
- ae\t%0,%2"
- [(set_attr "op_type" "RR,RX")
- (set_attr "type" "fsimps,fsimps")])
+ (set_attr "type" "fsimp<mode>")])
;;
[(set (match_operand:TI 0 "register_operand" "=&d")
(minus:TI (match_operand:TI 1 "register_operand" "0")
(match_operand:TI 2 "general_operand" "do") ) )
- (clobber (reg:CC 33))]
+ (clobber (reg:CC CC_REGNUM))]
"TARGET_64BIT"
"#"
"&& reload_completed"
[(parallel
- [(set (reg:CCL2 33)
+ [(set (reg:CCL2 CC_REGNUM)
(compare:CCL2 (minus:DI (match_dup 7) (match_dup 8))
(match_dup 7)))
(set (match_dup 6) (minus:DI (match_dup 7) (match_dup 8)))])
(parallel
[(set (match_dup 3) (minus:DI (minus:DI (match_dup 4) (match_dup 5))
- (gtu:DI (reg:CCL2 33) (const_int 0))))
- (clobber (reg:CC 33))])]
+ (gtu:DI (reg:CCL2 CC_REGNUM) (const_int 0))))
+ (clobber (reg:CC CC_REGNUM))])]
"operands[3] = operand_subword (operands[0], 0, 0, TImode);
operands[4] = operand_subword (operands[1], 0, 0, TImode);
operands[5] = operand_subword (operands[2], 0, 0, TImode);
[(set (match_operand:DI 0 "register_operand" "=d,d")
(minus:DI (match_operand:DI 1 "register_operand" "0,0")
(sign_extend:DI (match_operand:SI 2 "general_operand" "d,m"))))
- (clobber (reg:CC 33))]
+ (clobber (reg:CC CC_REGNUM))]
"TARGET_64BIT"
"@
sgfr\t%0,%2
[(set_attr "op_type" "RRE,RXY")])
(define_insn "*subdi3_zero_cc"
- [(set (reg 33)
+ [(set (reg CC_REGNUM)
(compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
(zero_extend:DI (match_operand:SI 2 "general_operand" "d,m")))
(const_int 0)))
[(set_attr "op_type" "RRE,RXY")])
(define_insn "*subdi3_zero_cconly"
- [(set (reg 33)
+ [(set (reg CC_REGNUM)
(compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
(zero_extend:DI (match_operand:SI 2 "general_operand" "d,m")))
(const_int 0)))
[(set (match_operand:DI 0 "register_operand" "=d,d")
(minus:DI (match_operand:DI 1 "register_operand" "0,0")
(zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))))
- (clobber (reg:CC 33))]
+ (clobber (reg:CC CC_REGNUM))]
"TARGET_64BIT"
"@
slgfr\t%0,%2
[(set_attr "op_type" "RRE,RXY")])
(define_insn "*subdi3_borrow_cc"
- [(set (reg 33)
+ [(set (reg CC_REGNUM)
(compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
(match_operand:DI 2 "general_operand" "d,m"))
(match_dup 1)))
[(set_attr "op_type" "RRE,RXY")])
(define_insn "*subdi3_borrow_cconly"
- [(set (reg 33)
+ [(set (reg CC_REGNUM)
(compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
(match_operand:DI 2 "general_operand" "d,m"))
(match_dup 1)))
[(set_attr "op_type" "RRE,RXY")])
(define_insn "*subdi3_cc"
- [(set (reg 33)
+ [(set (reg CC_REGNUM)
(compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
(match_operand:DI 2 "general_operand" "d,m"))
(const_int 0)))
[(set_attr "op_type" "RRE,RXY")])
(define_insn "*subdi3_cc2"
- [(set (reg 33)
+ [(set (reg CC_REGNUM)
(compare (match_operand:DI 1 "register_operand" "0,0")
(match_operand:DI 2 "general_operand" "d,m")))
(set (match_operand:DI 0 "register_operand" "=d,d")
[(set_attr "op_type" "RRE,RXY")])
(define_insn "*subdi3_cconly"
- [(set (reg 33)
+ [(set (reg CC_REGNUM)
(compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
(match_operand:DI 2 "general_operand" "d,m"))
(const_int 0)))
[(set_attr "op_type" "RRE,RXY")])
(define_insn "*subdi3_cconly2"
- [(set (reg 33)
+ [(set (reg CC_REGNUM)
(compare (match_operand:DI 1 "register_operand" "0,0")
(match_operand:DI 2 "general_operand" "d,m")))
(clobber (match_scratch:DI 0 "=d,d"))]
[(set (match_operand:DI 0 "register_operand" "=d,d")
(minus:DI (match_operand:DI 1 "register_operand" "0,0")
(match_operand:DI 2 "general_operand" "d,m") ) )
- (clobber (reg:CC 33))]
+ (clobber (reg:CC CC_REGNUM))]
"TARGET_64BIT"
"@
sgr\t%0,%2
[(set (match_operand:DI 0 "register_operand" "=&d")
(minus:DI (match_operand:DI 1 "register_operand" "0")
(match_operand:DI 2 "general_operand" "do") ) )
- (clobber (reg:CC 33))]
+ (clobber (reg:CC CC_REGNUM))]
"!TARGET_64BIT && TARGET_CPU_ZARCH"
"#"
"&& reload_completed"
[(parallel
- [(set (reg:CCL2 33)
+ [(set (reg:CCL2 CC_REGNUM)
(compare:CCL2 (minus:SI (match_dup 7) (match_dup 8))
(match_dup 7)))
(set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))])
(parallel
[(set (match_dup 3) (minus:SI (minus:SI (match_dup 4) (match_dup 5))
- (gtu:SI (reg:CCL2 33) (const_int 0))))
- (clobber (reg:CC 33))])]
+ (gtu:SI (reg:CCL2 CC_REGNUM) (const_int 0))))
+ (clobber (reg:CC CC_REGNUM))])]
"operands[3] = operand_subword (operands[0], 0, 0, DImode);
operands[4] = operand_subword (operands[1], 0, 0, DImode);
operands[5] = operand_subword (operands[2], 0, 0, DImode);
[(set (match_operand:DI 0 "register_operand" "=&d")
(minus:DI (match_operand:DI 1 "register_operand" "0")
(match_operand:DI 2 "general_operand" "do") ) )
- (clobber (reg:CC 33))]
+ (clobber (reg:CC CC_REGNUM))]
"!TARGET_CPU_ZARCH"
"#"
"&& reload_completed"
[(parallel
[(set (match_dup 3) (minus:SI (match_dup 4) (match_dup 5)))
- (clobber (reg:CC 33))])
+ (clobber (reg:CC CC_REGNUM))])
(parallel
- [(set (reg:CCL2 33)
+ [(set (reg:CCL2 CC_REGNUM)
(compare:CCL2 (minus:SI (match_dup 7) (match_dup 8))
(match_dup 7)))
(set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))])
(set (pc)
- (if_then_else (gtu (reg:CCL2 33) (const_int 0))
+ (if_then_else (gtu (reg:CCL2 CC_REGNUM) (const_int 0))
(pc)
(label_ref (match_dup 9))))
(parallel
[(set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))
- (clobber (reg:CC 33))])
+ (clobber (reg:CC CC_REGNUM))])
(match_dup 9)]
"operands[3] = operand_subword (operands[0], 0, 0, DImode);
operands[4] = operand_subword (operands[1], 0, 0, DImode);
[(set (match_operand:DI 0 "register_operand" "")
(minus:DI (match_operand:DI 1 "register_operand" "")
(match_operand:DI 2 "general_operand" "")))
- (clobber (reg:CC 33))])]
+ (clobber (reg:CC CC_REGNUM))])]
""
"")
;
(define_insn "*subsi3_borrow_cc"
- [(set (reg 33)
+ [(set (reg CC_REGNUM)
(compare (minus:SI (match_operand:SI 1 "register_operand" "0,0,0")
(match_operand:SI 2 "general_operand" "d,R,T"))
(match_dup 1)))
[(set_attr "op_type" "RR,RX,RXY")])
(define_insn "*subsi3_borrow_cconly"
- [(set (reg 33)
+ [(set (reg CC_REGNUM)
(compare (minus:SI (match_operand:SI 1 "register_operand" "0,0,0")
(match_operand:SI 2 "general_operand" "d,R,T"))
(match_dup 1)))
[(set_attr "op_type" "RR,RX,RXY")])
(define_insn "*subsi3_cc"
- [(set (reg 33)
+ [(set (reg CC_REGNUM)
(compare (minus:SI (match_operand:SI 1 "register_operand" "0,0,0")
(match_operand:SI 2 "general_operand" "d,R,T"))
(const_int 0)))
[(set_attr "op_type" "RR,RX,RXY")])
(define_insn "*subsi3_cc2"
- [(set (reg 33)
+ [(set (reg CC_REGNUM)
(compare (match_operand:SI 1 "register_operand" "0,0,0")
(match_operand:SI 2 "general_operand" "d,R,T")))
(set (match_operand:SI 0 "register_operand" "=d,d,d")
[(set_attr "op_type" "RR,RX,RXY")])
(define_insn "*subsi3_cconly"
- [(set (reg 33)
+ [(set (reg CC_REGNUM)
(compare (minus:SI (match_operand:SI 1 "register_operand" "0,0,0")
(match_operand:SI 2 "general_operand" "d,R,T"))
(const_int 0)))
[(set_attr "op_type" "RR,RX,RXY")])
(define_insn "*subsi3_cconly2"
- [(set (reg 33)
+ [(set (reg CC_REGNUM)
(compare (match_operand:SI 1 "register_operand" "0,0,0")
(match_operand:SI 2 "general_operand" "d,R,T")))
(clobber (match_scratch:SI 0 "=d,d,d"))]
[(set (match_operand:SI 0 "register_operand" "=d,d")
(minus:SI (match_operand:SI 1 "register_operand" "0,0")
(sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T"))))
- (clobber (reg:CC 33))]
+ (clobber (reg:CC CC_REGNUM))]
""
"@
sh\t%0,%2
[(set (match_operand:SI 0 "register_operand" "=d,d,d")
(minus:SI (match_operand:SI 1 "register_operand" "0,0,0")
(match_operand:SI 2 "general_operand" "d,R,T")))
- (clobber (reg:CC 33))]
+ (clobber (reg:CC CC_REGNUM))]
""
"@
sr\t%0,%2
;
-; subdf3 instruction pattern(s).
+; sub(df|sf)3 instruction pattern(s).
;
-(define_expand "subdf3"
+(define_expand "sub<mode>3"
[(parallel
- [(set (match_operand:DF 0 "register_operand" "=f,f")
- (minus:DF (match_operand:DF 1 "register_operand" "0,0")
- (match_operand:DF 2 "general_operand" "f,R")))
- (clobber (reg:CC 33))])]
+ [(set (match_operand:FPR 0 "register_operand" "=f,f")
+ (minus:FPR (match_operand:FPR 1 "register_operand" "0,0")
+ (match_operand:FPR 2 "general_operand" "f,R")))
+ (clobber (reg:CC CC_REGNUM))])]
"TARGET_HARD_FLOAT"
"")
-(define_insn "*subdf3"
- [(set (match_operand:DF 0 "register_operand" "=f,f")
- (minus:DF (match_operand:DF 1 "register_operand" "0,0")
- (match_operand:DF 2 "general_operand" "f,R")))
- (clobber (reg:CC 33))]
+(define_insn "*sub<mode>3"
+ [(set (match_operand:FPR 0 "register_operand" "=f,f")
+ (minus:FPR (match_operand:FPR 1 "register_operand" "0,0")
+ (match_operand:FPR 2 "general_operand" "f,R")))
+ (clobber (reg:CC CC_REGNUM))]
"TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"@
- sdbr\t%0,%2
- sdb\t%0,%2"
+ s<de>br\t%0,%2
+ s<de>b\t%0,%2"
[(set_attr "op_type" "RRE,RXE")
- (set_attr "type" "fsimpd,fsimpd")])
-
-(define_insn "*subdf3_cc"
- [(set (reg 33)
- (compare (minus:DF (match_operand:DF 1 "nonimmediate_operand" "0,0")
- (match_operand:DF 2 "general_operand" "f,R"))
- (match_operand:DF 3 "const0_operand" "")))
- (set (match_operand:DF 0 "register_operand" "=f,f")
- (minus:DF (match_dup 1) (match_dup 2)))]
+ (set_attr "type" "fsimp<mode>")])
+
+(define_insn "*sub<mode>3_cc"
+ [(set (reg CC_REGNUM)
+ (compare (minus:FPR (match_operand:FPR 1 "nonimmediate_operand" "0,0")
+ (match_operand:FPR 2 "general_operand" "f,R"))
+ (match_operand:FPR 3 "const0_operand" "")))
+ (set (match_operand:FPR 0 "register_operand" "=f,f")
+ (minus:FPR (match_dup 1) (match_dup 2)))]
"s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"@
- sdbr\t%0,%2
- sdb\t%0,%2"
+ s<de>br\t%0,%2
+ s<de>b\t%0,%2"
[(set_attr "op_type" "RRE,RXE")
- (set_attr "type" "fsimpd,fsimpd")])
-
-(define_insn "*subdf3_cconly"
- [(set (reg 33)
- (compare (minus:DF (match_operand:DF 1 "nonimmediate_operand" "0,0")
- (match_operand:DF 2 "general_operand" "f,R"))
- (match_operand:DF 3 "const0_operand" "")))
- (clobber (match_scratch:DF 0 "=f,f"))]
+ (set_attr "type" "fsimp<mode>")])
+
+(define_insn "*sub<mode>3_cconly"
+ [(set (reg CC_REGNUM)
+ (compare (minus:FPR (match_operand:FPR 1 "nonimmediate_operand" "0,0")
+ (match_operand:FPR 2 "general_operand" "f,R"))
+ (match_operand:FPR 3 "const0_operand" "")))
+ (clobber (match_scratch:FPR 0 "=f,f"))]
"s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"@
- sdbr\t%0,%2
- sdb\t%0,%2"
+ s<de>br\t%0,%2
+ s<de>b\t%0,%2"
[(set_attr "op_type" "RRE,RXE")
- (set_attr "type" "fsimpd,fsimpd")])
+ (set_attr "type" "fsimp<mode>")])
-(define_insn "*subdf3_ibm"
- [(set (match_operand:DF 0 "register_operand" "=f,f")
- (minus:DF (match_operand:DF 1 "register_operand" "0,0")
- (match_operand:DF 2 "general_operand" "f,R")))
- (clobber (reg:CC 33))]
+(define_insn "*sub<mode>3_ibm"
+ [(set (match_operand:FPR 0 "register_operand" "=f,f")
+ (minus:FPR (match_operand:FPR 1 "register_operand" "0,0")
+ (match_operand:FPR 2 "general_operand" "f,R")))
+ (clobber (reg:CC CC_REGNUM))]
"TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
"@
- sdr\t%0,%2
- sd\t%0,%2"
+ s<de>r\t%0,%2
+ s<de>\t%0,%2"
[(set_attr "op_type" "RR,RX")
- (set_attr "type" "fsimpd,fsimpd")])
-
-;
-; subsf3 instruction pattern(s).
-;
-
-(define_expand "subsf3"
- [(parallel
- [(set (match_operand:SF 0 "register_operand" "=f,f")
- (minus:SF (match_operand:SF 1 "register_operand" "0,0")
- (match_operand:SF 2 "general_operand" "f,R")))
- (clobber (reg:CC 33))])]
- "TARGET_HARD_FLOAT"
- "")
-
-(define_insn "*subsf3"
- [(set (match_operand:SF 0 "register_operand" "=f,f")
- (minus:SF (match_operand:SF 1 "register_operand" "0,0")
- (match_operand:SF 2 "general_operand" "f,R")))
- (clobber (reg:CC 33))]
- "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
- "@
- sebr\t%0,%2
- seb\t%0,%2"
- [(set_attr "op_type" "RRE,RXE")
- (set_attr "type" "fsimps,fsimps")])
-
-(define_insn "*subsf3_cc"
- [(set (reg 33)
- (compare (minus:SF (match_operand:SF 1 "nonimmediate_operand" "0,0")
- (match_operand:SF 2 "general_operand" "f,R"))
- (match_operand:SF 3 "const0_operand" "")))
- (set (match_operand:SF 0 "register_operand" "=f,f")
- (minus:SF (match_dup 1) (match_dup 2)))]
- "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
- "@
- sebr\t%0,%2
- seb\t%0,%2"
- [(set_attr "op_type" "RRE,RXE")
- (set_attr "type" "fsimps,fsimps")])
-
-(define_insn "*subsf3_cconly"
- [(set (reg 33)
- (compare (minus:SF (match_operand:SF 1 "nonimmediate_operand" "0,0")
- (match_operand:SF 2 "general_operand" "f,R"))
- (match_operand:SF 3 "const0_operand" "")))
- (clobber (match_scratch:SF 0 "=f,f"))]
- "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
- "@
- sebr\t%0,%2
- seb\t%0,%2"
- [(set_attr "op_type" "RRE,RXE")
- (set_attr "type" "fsimps,fsimps")])
-
-(define_insn "*subsf3_ibm"
- [(set (match_operand:SF 0 "register_operand" "=f,f")
- (minus:SF (match_operand:SF 1 "register_operand" "0,0")
- (match_operand:SF 2 "general_operand" "f,R")))
- (clobber (reg:CC 33))]
- "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
- "@
- ser\t%0,%2
- se\t%0,%2"
- [(set_attr "op_type" "RR,RX")
- (set_attr "type" "fsimps,fsimps")])
+ (set_attr "type" "fsimp<mode>")])
;;
;
(define_insn "*add<mode>3_alc_cc"
- [(set (reg 33)
+ [(set (reg CC_REGNUM)
(compare
(plus:GPR (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0")
(match_operand:GPR 2 "general_operand" "d,m"))
(plus:GPR (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0")
(match_operand:GPR 2 "general_operand" "d,m"))
(match_operand:GPR 3 "s390_alc_comparison" "")))
- (clobber (reg:CC 33))]
+ (clobber (reg:CC CC_REGNUM))]
"TARGET_CPU_ZARCH"
"@
alc<g>r\t%0,%2
[(set_attr "op_type" "RRE,RXY")])
(define_insn "*sub<mode>3_slb_cc"
- [(set (reg 33)
+ [(set (reg CC_REGNUM)
(compare
(minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0")
(match_operand:GPR 2 "general_operand" "d,m"))
(minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0")
(match_operand:GPR 2 "general_operand" "d,m"))
(match_operand:GPR 3 "s390_slb_comparison" "")))
- (clobber (reg:CC 33))]
+ (clobber (reg:CC CC_REGNUM))]
"TARGET_CPU_ZARCH"
"@
slb<g>r\t%0,%2
(define_insn_and_split "*scond<mode>"
[(set (match_operand:GPR 0 "register_operand" "=&d")
(match_operand:GPR 1 "s390_alc_comparison" ""))
- (clobber (reg:CC 33))]
+ (clobber (reg:CC CC_REGNUM))]
"TARGET_CPU_ZARCH"
"#"
"&& reload_completed"
(parallel
[(set (match_dup 0) (plus:GPR (plus:GPR (match_dup 0) (match_dup 0))
(match_dup 1)))
- (clobber (reg:CC 33))])]
+ (clobber (reg:CC CC_REGNUM))])]
"")
(define_insn_and_split "*scond<mode>_neg"
[(set (match_operand:GPR 0 "register_operand" "=&d")
(match_operand:GPR 1 "s390_slb_comparison" ""))
- (clobber (reg:CC 33))]
+ (clobber (reg:CC CC_REGNUM))]
"TARGET_CPU_ZARCH"
"#"
"&& reload_completed"
(parallel
[(set (match_dup 0) (minus:GPR (minus:GPR (match_dup 0) (match_dup 0))
(match_dup 1)))
- (clobber (reg:CC 33))])
+ (clobber (reg:CC CC_REGNUM))])
(parallel
[(set (match_dup 0) (neg:GPR (match_dup 0)))
- (clobber (reg:CC 33))])]
+ (clobber (reg:CC CC_REGNUM))])]
"")
(set_attr "type" "imulsi")])
;
-; muldf3 instruction pattern(s).
+; mul(df|sf)3 instruction pattern(s).
;
-(define_expand "muldf3"
- [(set (match_operand:DF 0 "register_operand" "=f,f")
- (mult:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0")
- (match_operand:DF 2 "general_operand" "f,R")))]
+(define_expand "mul<mode>3"
+ [(set (match_operand:FPR 0 "register_operand" "=f,f")
+ (mult:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
+ (match_operand:FPR 2 "general_operand" "f,R")))]
"TARGET_HARD_FLOAT"
"")
-(define_insn "*muldf3"
- [(set (match_operand:DF 0 "register_operand" "=f,f")
- (mult:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0")
- (match_operand:DF 2 "general_operand" "f,R")))]
+(define_insn "*mul<mode>3"
+ [(set (match_operand:FPR 0 "register_operand" "=f,f")
+ (mult:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
+ (match_operand:FPR 2 "general_operand" "f,R")))]
"TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"@
- mdbr\t%0,%2
- mdb\t%0,%2"
+ m<dee>br\t%0,%2
+ m<dee>b\t%0,%2"
[(set_attr "op_type" "RRE,RXE")
- (set_attr "type" "fmuld")])
+ (set_attr "type" "fmul<mode>")])
-(define_insn "*muldf3_ibm"
- [(set (match_operand:DF 0 "register_operand" "=f,f")
- (mult:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0")
- (match_operand:DF 2 "general_operand" "f,R")))]
+(define_insn "*mul<mode>3_ibm"
+ [(set (match_operand:FPR 0 "register_operand" "=f,f")
+ (mult:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
+ (match_operand:FPR 2 "general_operand" "f,R")))]
"TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
"@
- mdr\t%0,%2
- md\t%0,%2"
+ m<de>r\t%0,%2
+ m<de>\t%0,%2"
[(set_attr "op_type" "RR,RX")
- (set_attr "type" "fmuld")])
+ (set_attr "type" "fmul<mode>")])
-(define_insn "*fmadddf"
- [(set (match_operand:DF 0 "register_operand" "=f,f")
- (plus:DF (mult:DF (match_operand:DF 1 "register_operand" "%f,f")
- (match_operand:DF 2 "nonimmediate_operand" "f,R"))
- (match_operand:DF 3 "register_operand" "0,0")))]
- "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT && TARGET_FUSED_MADD"
- "@
- madbr\t%0,%1,%2
- madb\t%0,%1,%2"
- [(set_attr "op_type" "RRE,RXE")
- (set_attr "type" "fmuld")])
-
-(define_insn "*fmsubdf"
- [(set (match_operand:DF 0 "register_operand" "=f,f")
- (minus:DF (mult:DF (match_operand:DF 1 "register_operand" "f,f")
- (match_operand:DF 2 "nonimmediate_operand" "f,R"))
- (match_operand:DF 3 "register_operand" "0,0")))]
- "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT && TARGET_FUSED_MADD"
- "@
- msdbr\t%0,%1,%2
- msdb\t%0,%1,%2"
- [(set_attr "op_type" "RRE,RXE")
- (set_attr "type" "fmuld")])
-
-;
-; mulsf3 instruction pattern(s).
-;
-
-(define_expand "mulsf3"
- [(set (match_operand:SF 0 "register_operand" "=f,f")
- (mult:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0")
- (match_operand:SF 2 "general_operand" "f,R")))]
- "TARGET_HARD_FLOAT"
- "")
-
-(define_insn "*mulsf3"
- [(set (match_operand:SF 0 "register_operand" "=f,f")
- (mult:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0")
- (match_operand:SF 2 "general_operand" "f,R")))]
- "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
- "@
- meebr\t%0,%2
- meeb\t%0,%2"
- [(set_attr "op_type" "RRE,RXE")
- (set_attr "type" "fmuls")])
-
-(define_insn "*mulsf3_ibm"
- [(set (match_operand:SF 0 "register_operand" "=f,f")
- (mult:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0")
- (match_operand:SF 2 "general_operand" "f,R")))]
- "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
- "@
- mer\t%0,%2
- me\t%0,%2"
- [(set_attr "op_type" "RR,RX")
- (set_attr "type" "fmuls")])
-
-(define_insn "*fmaddsf"
- [(set (match_operand:SF 0 "register_operand" "=f,f")
- (plus:SF (mult:SF (match_operand:SF 1 "register_operand" "%f,f")
- (match_operand:SF 2 "nonimmediate_operand" "f,R"))
- (match_operand:SF 3 "register_operand" "0,0")))]
+(define_insn "*fmadd<mode>"
+ [(set (match_operand:FPR 0 "register_operand" "=f,f")
+ (plus:FPR (mult:FPR (match_operand:FPR 1 "register_operand" "%f,f")
+ (match_operand:FPR 2 "nonimmediate_operand" "f,R"))
+ (match_operand:FPR 3 "register_operand" "0,0")))]
"TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT && TARGET_FUSED_MADD"
"@
- maebr\t%0,%1,%2
- maeb\t%0,%1,%2"
+ ma<de>br\t%0,%1,%2
+ ma<de>b\t%0,%1,%2"
[(set_attr "op_type" "RRE,RXE")
- (set_attr "type" "fmuls")])
+ (set_attr "type" "fmul<mode>")])
-(define_insn "*fmsubsf"
- [(set (match_operand:SF 0 "register_operand" "=f,f")
- (minus:SF (mult:SF (match_operand:SF 1 "register_operand" "f,f")
- (match_operand:SF 2 "nonimmediate_operand" "f,R"))
- (match_operand:SF 3 "register_operand" "0,0")))]
+(define_insn "*fmsub<mode>"
+ [(set (match_operand:FPR 0 "register_operand" "=f,f")
+ (minus:FPR (mult:FPR (match_operand:FPR 1 "register_operand" "f,f")
+ (match_operand:FPR 2 "nonimmediate_operand" "f,R"))
+ (match_operand:FPR 3 "register_operand" "0,0")))]
"TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT && TARGET_FUSED_MADD"
"@
- msebr\t%0,%1,%2
- mseb\t%0,%1,%2"
+ ms<de>br\t%0,%1,%2
+ ms<de>b\t%0,%1,%2"
[(set_attr "op_type" "RRE,RXE")
- (set_attr "type" "fmuls")])
+ (set_attr "type" "fmul<mode>")])
;;
;;- Divide and modulo instructions.
})
;
-; divdf3 instruction pattern(s).
+; div(df|sf)3 instruction pattern(s).
;
-(define_expand "divdf3"
- [(set (match_operand:DF 0 "register_operand" "=f,f")
- (div:DF (match_operand:DF 1 "register_operand" "0,0")
- (match_operand:DF 2 "general_operand" "f,R")))]
+(define_expand "div<mode>3"
+ [(set (match_operand:FPR 0 "register_operand" "=f,f")
+ (div:FPR (match_operand:FPR 1 "register_operand" "0,0")
+ (match_operand:FPR 2 "general_operand" "f,R")))]
"TARGET_HARD_FLOAT"
"")
-(define_insn "*divdf3"
- [(set (match_operand:DF 0 "register_operand" "=f,f")
- (div:DF (match_operand:DF 1 "register_operand" "0,0")
- (match_operand:DF 2 "general_operand" "f,R")))]
+(define_insn "*div<mode>3"
+ [(set (match_operand:FPR 0 "register_operand" "=f,f")
+ (div:FPR (match_operand:FPR 1 "register_operand" "0,0")
+ (match_operand:FPR 2 "general_operand" "f,R")))]
"TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"@
- ddbr\t%0,%2
- ddb\t%0,%2"
+ d<de>br\t%0,%2
+ d<de>b\t%0,%2"
[(set_attr "op_type" "RRE,RXE")
- (set_attr "type" "fdivd")])
+ (set_attr "type" "fdiv<mode>")])
-(define_insn "*divdf3_ibm"
- [(set (match_operand:DF 0 "register_operand" "=f,f")
- (div:DF (match_operand:DF 1 "register_operand" "0,0")
- (match_operand:DF 2 "general_operand" "f,R")))]
+(define_insn "*div<mode>3_ibm"
+ [(set (match_operand:FPR 0 "register_operand" "=f,f")
+ (div:FPR (match_operand:FPR 1 "register_operand" "0,0")
+ (match_operand:FPR 2 "general_operand" "f,R")))]
"TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
"@
- ddr\t%0,%2
- dd\t%0,%2"
+ d<de>r\t%0,%2
+ d<de>\t%0,%2"
[(set_attr "op_type" "RR,RX")
- (set_attr "type" "fdivd")])
-
-;
-; divsf3 instruction pattern(s).
-;
-
-(define_expand "divsf3"
- [(set (match_operand:SF 0 "register_operand" "=f,f")
- (div:SF (match_operand:SF 1 "register_operand" "0,0")
- (match_operand:SF 2 "general_operand" "f,R")))]
- "TARGET_HARD_FLOAT"
- "")
-
-(define_insn "*divsf3"
- [(set (match_operand:SF 0 "register_operand" "=f,f")
- (div:SF (match_operand:SF 1 "register_operand" "0,0")
- (match_operand:SF 2 "general_operand" "f,R")))]
- "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
- "@
- debr\t%0,%2
- deb\t%0,%2"
- [(set_attr "op_type" "RRE,RXE")
- (set_attr "type" "fdivs")])
-
-(define_insn "*divsf3"
- [(set (match_operand:SF 0 "register_operand" "=f,f")
- (div:SF (match_operand:SF 1 "register_operand" "0,0")
- (match_operand:SF 2 "general_operand" "f,R")))]
- "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
- "@
- der\t%0,%2
- de\t%0,%2"
- [(set_attr "op_type" "RR,RX")
- (set_attr "type" "fdivs")])
+ (set_attr "type" "fdiv<mode>")])
;;
;;- And instructions.
;;
+(define_expand "and<mode>3"
+ [(set (match_operand:INT 0 "nonimmediate_operand" "")
+ (and:INT (match_operand:INT 1 "nonimmediate_operand" "")
+ (match_operand:INT 2 "general_operand" "")))
+ (clobber (reg:CC CC_REGNUM))]
+ ""
+ "s390_expand_logical_operator (AND, <MODE>mode, operands); DONE;")
+
;
; anddi3 instruction pattern(s).
;
(define_insn "*anddi3_cc"
- [(set (reg 33)
+ [(set (reg CC_REGNUM)
(compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
(match_operand:DI 2 "general_operand" "d,m"))
(const_int 0)))
[(set_attr "op_type" "RRE,RXY")])
(define_insn "*anddi3_cconly"
- [(set (reg 33)
+ [(set (reg CC_REGNUM)
(compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
(match_operand:DI 2 "general_operand" "d,m"))
(const_int 0)))
"%d,o,0,0,0,0,0,0,0,0")
(match_operand:DI 2 "general_operand"
"M,M,N0HDF,N1HDF,N2HDF,N3HDF,d,m,NxQDF,Q")))
- (clobber (reg:CC 33))]
+ (clobber (reg:CC CC_REGNUM))]
"TARGET_64BIT && s390_logical_operator_ok_p (operands)"
"@
#
(define_split
[(set (match_operand:DI 0 "s_operand" "")
(and:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" "")))
- (clobber (reg:CC 33))]
+ (clobber (reg:CC CC_REGNUM))]
"reload_completed"
[(parallel
[(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
- (clobber (reg:CC 33))])]
+ (clobber (reg:CC CC_REGNUM))])]
"s390_narrow_logical_operator (AND, &operands[0], &operands[1]);")
-(define_expand "anddi3"
- [(set (match_operand:DI 0 "nonimmediate_operand" "")
- (and:DI (match_operand:DI 1 "nonimmediate_operand" "")
- (match_operand:DI 2 "general_operand" "")))
- (clobber (reg:CC 33))]
- "TARGET_64BIT"
- "s390_expand_logical_operator (AND, DImode, operands); DONE;")
;
; andsi3 instruction pattern(s).
;
(define_insn "*andsi3_cc"
- [(set (reg 33)
+ [(set (reg CC_REGNUM)
(compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
(match_operand:SI 2 "general_operand" "d,R,T"))
(const_int 0)))
[(set_attr "op_type" "RR,RX,RXY")])
(define_insn "*andsi3_cconly"
- [(set (reg 33)
+ [(set (reg CC_REGNUM)
(compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
(match_operand:SI 2 "general_operand" "d,R,T"))
(const_int 0)))
"%d,o,0,0,0,0,0,0,0")
(match_operand:SI 2 "general_operand"
"M,M,N0HSF,N1HSF,d,R,T,NxQSF,Q")))
- (clobber (reg:CC 33))]
+ (clobber (reg:CC CC_REGNUM))]
"TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
"@
#
[(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,AQ,Q")
(and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
(match_operand:SI 2 "general_operand" "d,R,NxQSF,Q")))
- (clobber (reg:CC 33))]
+ (clobber (reg:CC CC_REGNUM))]
"!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
"@
nr\t%0,%2
(define_split
[(set (match_operand:SI 0 "s_operand" "")
(and:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" "")))
- (clobber (reg:CC 33))]
+ (clobber (reg:CC CC_REGNUM))]
"reload_completed"
[(parallel
[(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
- (clobber (reg:CC 33))])]
+ (clobber (reg:CC CC_REGNUM))])]
"s390_narrow_logical_operator (AND, &operands[0], &operands[1]);")
-(define_expand "andsi3"
- [(set (match_operand:SI 0 "nonimmediate_operand" "")
- (and:SI (match_operand:SI 1 "nonimmediate_operand" "")
- (match_operand:SI 2 "general_operand" "")))
- (clobber (reg:CC 33))]
- ""
- "s390_expand_logical_operator (AND, SImode, operands); DONE;")
-
;
; andhi3 instruction pattern(s).
;
[(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,AQ,Q")
(and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0,0")
(match_operand:HI 2 "general_operand" "d,n,NxQHF,Q")))
- (clobber (reg:CC 33))]
+ (clobber (reg:CC CC_REGNUM))]
"TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
"@
nr\t%0,%2
[(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q")
(and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0")
(match_operand:HI 2 "general_operand" "d,NxQHF,Q")))
- (clobber (reg:CC 33))]
+ (clobber (reg:CC CC_REGNUM))]
"!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
"@
nr\t%0,%2
(define_split
[(set (match_operand:HI 0 "s_operand" "")
(and:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" "")))
- (clobber (reg:CC 33))]
+ (clobber (reg:CC CC_REGNUM))]
"reload_completed"
[(parallel
[(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
- (clobber (reg:CC 33))])]
+ (clobber (reg:CC CC_REGNUM))])]
"s390_narrow_logical_operator (AND, &operands[0], &operands[1]);")
-(define_expand "andhi3"
- [(set (match_operand:HI 0 "nonimmediate_operand" "")
- (and:HI (match_operand:HI 1 "nonimmediate_operand" "")
- (match_operand:HI 2 "general_operand" "")))
- (clobber (reg:CC 33))]
- ""
- "s390_expand_logical_operator (AND, HImode, operands); DONE;")
-
;
; andqi3 instruction pattern(s).
;
[(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,Q,S,Q")
(and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0,0,0")
(match_operand:QI 2 "general_operand" "d,n,n,n,Q")))
- (clobber (reg:CC 33))]
+ (clobber (reg:CC CC_REGNUM))]
"TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
"@
nr\t%0,%2
[(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q")
(and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
(match_operand:QI 2 "general_operand" "d,n,Q")))
- (clobber (reg:CC 33))]
+ (clobber (reg:CC CC_REGNUM))]
"!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
"@
nr\t%0,%2
#"
[(set_attr "op_type" "RR,SI,SS")])
-(define_expand "andqi3"
- [(set (match_operand:QI 0 "nonimmediate_operand" "")
- (and:QI (match_operand:QI 1 "nonimmediate_operand" "")
- (match_operand:QI 2 "general_operand" "")))
- (clobber (reg:CC 33))]
- ""
- "s390_expand_logical_operator (AND, QImode, operands); DONE;")
-
;
; Block and (NC) patterns.
;
(and:BLK (match_dup 0)
(match_operand:BLK 1 "memory_operand" "Q")))
(use (match_operand 2 "const_int_operand" "n"))
- (clobber (reg:CC 33))]
+ (clobber (reg:CC CC_REGNUM))]
"INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
"nc\t%O0(%2,%R0),%S1"
[(set_attr "op_type" "SS")])
[(set (match_operand 0 "memory_operand" "")
(and (match_dup 0)
(match_operand 1 "memory_operand" "")))
- (clobber (reg:CC 33))]
+ (clobber (reg:CC CC_REGNUM))]
"reload_completed
&& GET_MODE (operands[0]) == GET_MODE (operands[1])
&& GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
[(parallel
[(set (match_dup 0) (and:BLK (match_dup 0) (match_dup 1)))
(use (match_dup 2))
- (clobber (reg:CC 33))])]
+ (clobber (reg:CC CC_REGNUM))])]
{
operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
operands[0] = adjust_address (operands[0], BLKmode, 0);
(and:BLK (match_dup 0)
(match_operand:BLK 1 "memory_operand" "")))
(use (match_operand 2 "const_int_operand" ""))
- (clobber (reg:CC 33))])
+ (clobber (reg:CC CC_REGNUM))])
(parallel
[(set (match_operand:BLK 3 "memory_operand" "")
(and:BLK (match_dup 3)
(match_operand:BLK 4 "memory_operand" "")))
(use (match_operand 5 "const_int_operand" ""))
- (clobber (reg:CC 33))])]
+ (clobber (reg:CC CC_REGNUM))])]
"s390_offset_p (operands[0], operands[3], operands[2])
&& s390_offset_p (operands[1], operands[4], operands[2])
&& INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
[(parallel
[(set (match_dup 6) (and:BLK (match_dup 6) (match_dup 7)))
(use (match_dup 8))
- (clobber (reg:CC 33))])]
+ (clobber (reg:CC CC_REGNUM))])]
"operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
;;- Bit set (inclusive or) instructions.
;;
+(define_expand "ior<mode>3"
+ [(set (match_operand:INT 0 "nonimmediate_operand" "")
+ (ior:INT (match_operand:INT 1 "nonimmediate_operand" "")
+ (match_operand:INT 2 "general_operand" "")))
+ (clobber (reg:CC CC_REGNUM))]
+ ""
+ "s390_expand_logical_operator (IOR, <MODE>mode, operands); DONE;")
+
;
; iordi3 instruction pattern(s).
;
(define_insn "*iordi3_cc"
- [(set (reg 33)
+ [(set (reg CC_REGNUM)
(compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
(match_operand:DI 2 "general_operand" "d,m"))
(const_int 0)))
[(set_attr "op_type" "RRE,RXY")])
(define_insn "*iordi3_cconly"
- [(set (reg 33)
+ [(set (reg CC_REGNUM)
(compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
(match_operand:DI 2 "general_operand" "d,m"))
(const_int 0)))
(ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0,0,0,0,0")
(match_operand:DI 2 "general_operand"
"N0HD0,N1HD0,N2HD0,N3HD0,d,m,NxQD0,Q")))
- (clobber (reg:CC 33))]
+ (clobber (reg:CC CC_REGNUM))]
"TARGET_64BIT && s390_logical_operator_ok_p (operands)"
"@
oihh\t%0,%i2
(define_split
[(set (match_operand:DI 0 "s_operand" "")
(ior:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" "")))
- (clobber (reg:CC 33))]
+ (clobber (reg:CC CC_REGNUM))]
"reload_completed"
[(parallel
[(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1)))
- (clobber (reg:CC 33))])]
+ (clobber (reg:CC CC_REGNUM))])]
"s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);")
-(define_expand "iordi3"
- [(set (match_operand:DI 0 "nonimmediate_operand" "")
- (ior:DI (match_operand:DI 1 "nonimmediate_operand" "")
- (match_operand:DI 2 "general_operand" "")))
- (clobber (reg:CC 33))]
- "TARGET_64BIT"
- "s390_expand_logical_operator (IOR, DImode, operands); DONE;")
-
;
; iorsi3 instruction pattern(s).
;
(define_insn "*iorsi3_cc"
- [(set (reg 33)
+ [(set (reg CC_REGNUM)
(compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
(match_operand:SI 2 "general_operand" "d,R,T"))
(const_int 0)))
[(set_attr "op_type" "RR,RX,RXY")])
(define_insn "*iorsi3_cconly"
- [(set (reg 33)
+ [(set (reg CC_REGNUM)
(compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
(match_operand:SI 2 "general_operand" "d,R,T"))
(const_int 0)))
[(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d,AQ,Q")
(ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0,0,0,0")
(match_operand:SI 2 "general_operand" "N0HS0,N1HS0,d,R,T,NxQS0,Q")))
- (clobber (reg:CC 33))]
+ (clobber (reg:CC CC_REGNUM))]
"TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
"@
oilh\t%0,%i2
[(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,AQ,Q")
(ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
(match_operand:SI 2 "general_operand" "d,R,NxQS0,Q")))
- (clobber (reg:CC 33))]
+ (clobber (reg:CC CC_REGNUM))]
"!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
"@
or\t%0,%2
(define_split
[(set (match_operand:SI 0 "s_operand" "")
(ior:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" "")))
- (clobber (reg:CC 33))]
+ (clobber (reg:CC CC_REGNUM))]
"reload_completed"
[(parallel
[(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1)))
- (clobber (reg:CC 33))])]
+ (clobber (reg:CC CC_REGNUM))])]
"s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);")
-(define_expand "iorsi3"
- [(set (match_operand:SI 0 "nonimmediate_operand" "")
- (ior:SI (match_operand:SI 1 "nonimmediate_operand" "")
- (match_operand:SI 2 "general_operand" "")))
- (clobber (reg:CC 33))]
- ""
- "s390_expand_logical_operator (IOR, SImode, operands); DONE;")
-
;
; iorhi3 instruction pattern(s).
;
[(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,AQ,Q")
(ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0,0")
(match_operand:HI 2 "general_operand" "d,n,NxQH0,Q")))
- (clobber (reg:CC 33))]
+ (clobber (reg:CC CC_REGNUM))]
"TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
"@
or\t%0,%2
[(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q")
(ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0")
(match_operand:HI 2 "general_operand" "d,NxQH0,Q")))
- (clobber (reg:CC 33))]
+ (clobber (reg:CC CC_REGNUM))]
"!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
"@
or\t%0,%2
(define_split
[(set (match_operand:HI 0 "s_operand" "")
(ior:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" "")))
- (clobber (reg:CC 33))]
+ (clobber (reg:CC CC_REGNUM))]
"reload_completed"
[(parallel
[(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1)))
- (clobber (reg:CC 33))])]
+ (clobber (reg:CC CC_REGNUM))])]
"s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);")
-(define_expand "iorhi3"
- [(set (match_operand:HI 0 "nonimmediate_operand" "")
- (ior:HI (match_operand:HI 1 "nonimmediate_operand" "")
- (match_operand:HI 2 "general_operand" "")))
- (clobber (reg:CC 33))]
- ""
- "s390_expand_logical_operator (IOR, HImode, operands); DONE;")
-
;
; iorqi3 instruction pattern(s).
;
[(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,Q,S,Q")
(ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0,0,0")
(match_operand:QI 2 "general_operand" "d,n,n,n,Q")))
- (clobber (reg:CC 33))]
+ (clobber (reg:CC CC_REGNUM))]
"TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
"@
or\t%0,%2
[(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q")
(ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
(match_operand:QI 2 "general_operand" "d,n,Q")))
- (clobber (reg:CC 33))]
+ (clobber (reg:CC CC_REGNUM))]
"!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
"@
or\t%0,%2
#"
[(set_attr "op_type" "RR,SI,SS")])
-(define_expand "iorqi3"
- [(set (match_operand:QI 0 "nonimmediate_operand" "")
- (ior:QI (match_operand:QI 1 "nonimmediate_operand" "")
- (match_operand:QI 2 "general_operand" "")))
- (clobber (reg:CC 33))]
- ""
- "s390_expand_logical_operator (IOR, QImode, operands); DONE;")
-
;
; Block inclusive or (OC) patterns.
;
(ior:BLK (match_dup 0)
(match_operand:BLK 1 "memory_operand" "Q")))
(use (match_operand 2 "const_int_operand" "n"))
- (clobber (reg:CC 33))]
+ (clobber (reg:CC CC_REGNUM))]
"INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
"oc\t%O0(%2,%R0),%S1"
[(set_attr "op_type" "SS")])
[(set (match_operand 0 "memory_operand" "")
(ior (match_dup 0)
(match_operand 1 "memory_operand" "")))
- (clobber (reg:CC 33))]
+ (clobber (reg:CC CC_REGNUM))]
"reload_completed
&& GET_MODE (operands[0]) == GET_MODE (operands[1])
&& GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
[(parallel
[(set (match_dup 0) (ior:BLK (match_dup 0) (match_dup 1)))
(use (match_dup 2))
- (clobber (reg:CC 33))])]
+ (clobber (reg:CC CC_REGNUM))])]
{
operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
operands[0] = adjust_address (operands[0], BLKmode, 0);
(ior:BLK (match_dup 0)
(match_operand:BLK 1 "memory_operand" "")))
(use (match_operand 2 "const_int_operand" ""))
- (clobber (reg:CC 33))])
+ (clobber (reg:CC CC_REGNUM))])
(parallel
[(set (match_operand:BLK 3 "memory_operand" "")
(ior:BLK (match_dup 3)
(match_operand:BLK 4 "memory_operand" "")))
(use (match_operand 5 "const_int_operand" ""))
- (clobber (reg:CC 33))])]
+ (clobber (reg:CC CC_REGNUM))])]
"s390_offset_p (operands[0], operands[3], operands[2])
&& s390_offset_p (operands[1], operands[4], operands[2])
&& INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
[(parallel
[(set (match_dup 6) (ior:BLK (match_dup 6) (match_dup 7)))
(use (match_dup 8))
- (clobber (reg:CC 33))])]
+ (clobber (reg:CC CC_REGNUM))])]
"operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
;;- Xor instructions.
;;
+(define_expand "xor<mode>3"
+ [(set (match_operand:INT 0 "nonimmediate_operand" "")
+ (xor:INT (match_operand:INT 1 "nonimmediate_operand" "")
+ (match_operand:INT 2 "general_operand" "")))
+ (clobber (reg:CC CC_REGNUM))]
+ ""
+ "s390_expand_logical_operator (XOR, <MODE>mode, operands); DONE;")
+
;
; xordi3 instruction pattern(s).
;
(define_insn "*xordi3_cc"
- [(set (reg 33)
+ [(set (reg CC_REGNUM)
(compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
(match_operand:DI 2 "general_operand" "d,m"))
(const_int 0)))
[(set_attr "op_type" "RRE,RXY")])
(define_insn "*xordi3_cconly"
- [(set (reg 33)
+ [(set (reg CC_REGNUM)
(compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
(match_operand:DI 2 "general_operand" "d,m"))
(const_int 0)))
[(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,AQ,Q")
(xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0")
(match_operand:DI 2 "general_operand" "d,m,NxQD0,Q")))
- (clobber (reg:CC 33))]
+ (clobber (reg:CC CC_REGNUM))]
"TARGET_64BIT && s390_logical_operator_ok_p (operands)"
"@
xgr\t%0,%2
(define_split
[(set (match_operand:DI 0 "s_operand" "")
(xor:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" "")))
- (clobber (reg:CC 33))]
+ (clobber (reg:CC CC_REGNUM))]
"reload_completed"
[(parallel
[(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
- (clobber (reg:CC 33))])]
+ (clobber (reg:CC CC_REGNUM))])]
"s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);")
-(define_expand "xordi3"
- [(set (match_operand:DI 0 "nonimmediate_operand" "")
- (xor:DI (match_operand:DI 1 "nonimmediate_operand" "")
- (match_operand:DI 2 "general_operand" "")))
- (clobber (reg:CC 33))]
- "TARGET_64BIT"
- "s390_expand_logical_operator (XOR, DImode, operands); DONE;")
-
;
; xorsi3 instruction pattern(s).
;
(define_insn "*xorsi3_cc"
- [(set (reg 33)
+ [(set (reg CC_REGNUM)
(compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
(match_operand:SI 2 "general_operand" "d,R,T"))
(const_int 0)))
[(set_attr "op_type" "RR,RX,RXY")])
(define_insn "*xorsi3_cconly"
- [(set (reg 33)
+ [(set (reg CC_REGNUM)
(compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
(match_operand:SI 2 "general_operand" "d,R,T"))
(const_int 0)))
[(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,AQ,Q")
(xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0,0")
(match_operand:SI 2 "general_operand" "d,R,T,NxQS0,Q")))
- (clobber (reg:CC 33))]
+ (clobber (reg:CC CC_REGNUM))]
"s390_logical_operator_ok_p (operands)"
"@
xr\t%0,%2
(define_split
[(set (match_operand:SI 0 "s_operand" "")
(xor:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" "")))
- (clobber (reg:CC 33))]
+ (clobber (reg:CC CC_REGNUM))]
"reload_completed"
[(parallel
[(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
- (clobber (reg:CC 33))])]
+ (clobber (reg:CC CC_REGNUM))])]
"s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);")
-(define_expand "xorsi3"
- [(set (match_operand:SI 0 "nonimmediate_operand" "")
- (xor:SI (match_operand:SI 1 "nonimmediate_operand" "")
- (match_operand:SI 2 "general_operand" "")))
- (clobber (reg:CC 33))]
- ""
- "s390_expand_logical_operator (XOR, SImode, operands); DONE;")
-
;
; xorhi3 instruction pattern(s).
;
[(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q")
(xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0")
(match_operand:HI 2 "general_operand" "d,NxQH0,Q")))
- (clobber (reg:CC 33))]
+ (clobber (reg:CC CC_REGNUM))]
"s390_logical_operator_ok_p (operands)"
"@
xr\t%0,%2
(define_split
[(set (match_operand:HI 0 "s_operand" "")
(xor:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" "")))
- (clobber (reg:CC 33))]
+ (clobber (reg:CC CC_REGNUM))]
"reload_completed"
[(parallel
[(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
- (clobber (reg:CC 33))])]
+ (clobber (reg:CC CC_REGNUM))])]
"s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);")
-(define_expand "xorhi3"
- [(set (match_operand:HI 0 "nonimmediate_operand" "")
- (xor:HI (match_operand:HI 1 "nonimmediate_operand" "")
- (match_operand:HI 2 "general_operand" "")))
- (clobber (reg:CC 33))]
- ""
- "s390_expand_logical_operator (XOR, HImode, operands); DONE;")
-
;
; xorqi3 instruction pattern(s).
;
[(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,S,Q")
(xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0,0")
(match_operand:QI 2 "general_operand" "d,n,n,Q")))
- (clobber (reg:CC 33))]
+ (clobber (reg:CC CC_REGNUM))]
"s390_logical_operator_ok_p (operands)"
"@
xr\t%0,%2
#"
[(set_attr "op_type" "RR,SI,SIY,SS")])
-(define_expand "xorqi3"
- [(set (match_operand:QI 0 "nonimmediate_operand" "")
- (xor:QI (match_operand:QI 1 "nonimmediate_operand" "")
- (match_operand:QI 2 "general_operand" "")))
- (clobber (reg:CC 33))]
- ""
- "s390_expand_logical_operator (XOR, QImode, operands); DONE;")
-
;
; Block exclusive or (XC) patterns.
;
(xor:BLK (match_dup 0)
(match_operand:BLK 1 "memory_operand" "Q")))
(use (match_operand 2 "const_int_operand" "n"))
- (clobber (reg:CC 33))]
+ (clobber (reg:CC CC_REGNUM))]
"INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
"xc\t%O0(%2,%R0),%S1"
[(set_attr "op_type" "SS")])
[(set (match_operand 0 "memory_operand" "")
(xor (match_dup 0)
(match_operand 1 "memory_operand" "")))
- (clobber (reg:CC 33))]
+ (clobber (reg:CC CC_REGNUM))]
"reload_completed
&& GET_MODE (operands[0]) == GET_MODE (operands[1])
&& GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
[(parallel
[(set (match_dup 0) (xor:BLK (match_dup 0) (match_dup 1)))
(use (match_dup 2))
- (clobber (reg:CC 33))])]
+ (clobber (reg:CC CC_REGNUM))])]
{
operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
operands[0] = adjust_address (operands[0], BLKmode, 0);
(xor:BLK (match_dup 0)
(match_operand:BLK 1 "memory_operand" "")))
(use (match_operand 2 "const_int_operand" ""))
- (clobber (reg:CC 33))])
+ (clobber (reg:CC CC_REGNUM))])
(parallel
[(set (match_operand:BLK 3 "memory_operand" "")
(xor:BLK (match_dup 3)
(match_operand:BLK 4 "memory_operand" "")))
(use (match_operand 5 "const_int_operand" ""))
- (clobber (reg:CC 33))])]
+ (clobber (reg:CC CC_REGNUM))])]
"s390_offset_p (operands[0], operands[3], operands[2])
&& s390_offset_p (operands[1], operands[4], operands[2])
&& INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
[(parallel
[(set (match_dup 6) (xor:BLK (match_dup 6) (match_dup 7)))
(use (match_dup 8))
- (clobber (reg:CC 33))])]
+ (clobber (reg:CC CC_REGNUM))])]
"operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
[(set (match_operand:BLK 0 "memory_operand" "=Q")
(const_int 0))
(use (match_operand 1 "const_int_operand" "n"))
- (clobber (reg:CC 33))]
+ (clobber (reg:CC CC_REGNUM))]
"INTVAL (operands[1]) >= 1 && INTVAL (operands[1]) <= 256"
"xc\t%O0(%1,%R0),%S0"
[(set_attr "op_type" "SS")])
[(set (match_operand:BLK 0 "memory_operand" "")
(const_int 0))
(use (match_operand 1 "const_int_operand" ""))
- (clobber (reg:CC 33))])
+ (clobber (reg:CC CC_REGNUM))])
(parallel
[(set (match_operand:BLK 2 "memory_operand" "")
(const_int 0))
(use (match_operand 3 "const_int_operand" ""))
- (clobber (reg:CC 33))])]
+ (clobber (reg:CC CC_REGNUM))])]
"s390_offset_p (operands[0], operands[2], operands[1])
&& INTVAL (operands[1]) + INTVAL (operands[3]) <= 256"
[(parallel
[(set (match_dup 4) (const_int 0))
(use (match_dup 5))
- (clobber (reg:CC 33))])]
+ (clobber (reg:CC CC_REGNUM))])]
"operands[4] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
operands[5] = GEN_INT (INTVAL (operands[1]) + INTVAL (operands[3]));")
[(parallel
[(set (match_operand:DSI 0 "register_operand" "=d")
(neg:DSI (match_operand:DSI 1 "register_operand" "d")))
- (clobber (reg:CC 33))])]
+ (clobber (reg:CC CC_REGNUM))])]
""
"")
(define_insn "*negdi2_sign_cc"
- [(set (reg 33)
+ [(set (reg CC_REGNUM)
(compare (neg:DI (ashiftrt:DI (ashift:DI (subreg:DI
(match_operand:SI 1 "register_operand" "d") 0)
(const_int 32)) (const_int 32)))
(define_insn "*negdi2_sign"
[(set (match_operand:DI 0 "register_operand" "=d")
(neg:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))))
- (clobber (reg:CC 33))]
+ (clobber (reg:CC CC_REGNUM))]
"TARGET_64BIT"
"lcgfr\t%0,%1"
[(set_attr "op_type" "RRE")])
(define_insn "*neg<mode>2_cc"
- [(set (reg 33)
+ [(set (reg CC_REGNUM)
(compare (neg:GPR (match_operand:GPR 1 "register_operand" "d"))
(const_int 0)))
(set (match_operand:GPR 0 "register_operand" "=d")
[(set_attr "op_type" "RR<E>")])
(define_insn "*neg<mode>2_cconly"
- [(set (reg 33)
+ [(set (reg CC_REGNUM)
(compare (neg:GPR (match_operand:GPR 1 "register_operand" "d"))
(const_int 0)))
(clobber (match_scratch:GPR 0 "=d"))]
(define_insn "*neg<mode>2"
[(set (match_operand:GPR 0 "register_operand" "=d")
(neg:GPR (match_operand:GPR 1 "register_operand" "d")))
- (clobber (reg:CC 33))]
+ (clobber (reg:CC CC_REGNUM))]
""
"lc<g>r\t%0,%1"
[(set_attr "op_type" "RR<E>")])
(define_insn_and_split "*negdi2_31"
[(set (match_operand:DI 0 "register_operand" "=d")
(neg:DI (match_operand:DI 1 "register_operand" "d")))
- (clobber (reg:CC 33))]
+ (clobber (reg:CC CC_REGNUM))]
"!TARGET_64BIT"
"#"
"&& reload_completed"
[(parallel
[(set (match_dup 2) (neg:SI (match_dup 3)))
- (clobber (reg:CC 33))])
+ (clobber (reg:CC CC_REGNUM))])
(parallel
- [(set (reg:CCAP 33)
+ [(set (reg:CCAP CC_REGNUM)
(compare:CCAP (neg:SI (match_dup 5)) (const_int 0)))
(set (match_dup 4) (neg:SI (match_dup 5)))])
(set (pc)
- (if_then_else (ne (reg:CCAP 33) (const_int 0))
+ (if_then_else (ne (reg:CCAP CC_REGNUM) (const_int 0))
(pc)
(label_ref (match_dup 6))))
(parallel
[(set (match_dup 2) (plus:SI (match_dup 2) (const_int -1)))
- (clobber (reg:CC 33))])
+ (clobber (reg:CC CC_REGNUM))])
(match_dup 6)]
"operands[2] = operand_subword (operands[0], 0, 0, DImode);
operands[3] = operand_subword (operands[1], 0, 0, DImode);
operands[6] = gen_label_rtx ();")
;
-; negdf2 instruction pattern(s).
+; neg(df|sf)2 instruction pattern(s).
;
-(define_expand "negdf2"
- [(parallel
- [(set (match_operand:DF 0 "register_operand" "=f")
- (neg:DF (match_operand:DF 1 "register_operand" "f")))
- (clobber (reg:CC 33))])]
- "TARGET_HARD_FLOAT"
- "")
-
-(define_insn "*negdf2_cc"
- [(set (reg 33)
- (compare (neg:DF (match_operand:DF 1 "register_operand" "f"))
- (match_operand:DF 2 "const0_operand" "")))
- (set (match_operand:DF 0 "register_operand" "=f")
- (neg:DF (match_dup 1)))]
- "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
- "lcdbr\t%0,%1"
- [(set_attr "op_type" "RRE")
- (set_attr "type" "fsimpd")])
-
-(define_insn "*negdf2_cconly"
- [(set (reg 33)
- (compare (neg:DF (match_operand:DF 1 "register_operand" "f"))
- (match_operand:DF 2 "const0_operand" "")))
- (clobber (match_scratch:DF 0 "=f"))]
- "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
- "lcdbr\t%0,%1"
- [(set_attr "op_type" "RRE")
- (set_attr "type" "fsimpd")])
-
-(define_insn "*negdf2"
- [(set (match_operand:DF 0 "register_operand" "=f")
- (neg:DF (match_operand:DF 1 "register_operand" "f")))
- (clobber (reg:CC 33))]
- "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
- "lcdbr\t%0,%1"
- [(set_attr "op_type" "RRE")
- (set_attr "type" "fsimpd")])
-
-(define_insn "*negdf2_ibm"
- [(set (match_operand:DF 0 "register_operand" "=f")
- (neg:DF (match_operand:DF 1 "register_operand" "f")))
- (clobber (reg:CC 33))]
- "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
- "lcdr\t%0,%1"
- [(set_attr "op_type" "RR")
- (set_attr "type" "fsimpd")])
-
-;
-; negsf2 instruction pattern(s).
-;
-
-(define_expand "negsf2"
+(define_expand "neg<mode>2"
[(parallel
- [(set (match_operand:SF 0 "register_operand" "=f")
- (neg:SF (match_operand:SF 1 "register_operand" "f")))
- (clobber (reg:CC 33))])]
+ [(set (match_operand:FPR 0 "register_operand" "=f")
+ (neg:FPR (match_operand:FPR 1 "register_operand" "f")))
+ (clobber (reg:CC CC_REGNUM))])]
"TARGET_HARD_FLOAT"
"")
-(define_insn "*negsf2_cc"
- [(set (reg 33)
- (compare (neg:SF (match_operand:SF 1 "register_operand" "f"))
- (match_operand:SF 2 "const0_operand" "")))
- (set (match_operand:SF 0 "register_operand" "=f")
- (neg:SF (match_dup 1)))]
+(define_insn "*neg<mode>2_cc"
+ [(set (reg CC_REGNUM)
+ (compare (neg:FPR (match_operand:FPR 1 "register_operand" "f"))
+ (match_operand:FPR 2 "const0_operand" "")))
+ (set (match_operand:FPR 0 "register_operand" "=f")
+ (neg:FPR (match_dup 1)))]
"s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
- "lcebr\t%0,%1"
+ "lc<de>br\t%0,%1"
[(set_attr "op_type" "RRE")
- (set_attr "type" "fsimps")])
+ (set_attr "type" "fsimp<mode>")])
-(define_insn "*negsf2_cconly"
- [(set (reg 33)
- (compare (neg:SF (match_operand:SF 1 "register_operand" "f"))
- (match_operand:SF 2 "const0_operand" "")))
- (clobber (match_scratch:SF 0 "=f"))]
+(define_insn "*neg<mode>2_cconly"
+ [(set (reg CC_REGNUM)
+ (compare (neg:FPR (match_operand:FPR 1 "register_operand" "f"))
+ (match_operand:FPR 2 "const0_operand" "")))
+ (clobber (match_scratch:FPR 0 "=f"))]
"s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
- "lcebr\t%0,%1"
+ "lc<de>br\t%0,%1"
[(set_attr "op_type" "RRE")
- (set_attr "type" "fsimps")])
+ (set_attr "type" "fsimp<mode>")])
-(define_insn "*negsf2"
- [(set (match_operand:SF 0 "register_operand" "=f")
- (neg:SF (match_operand:SF 1 "register_operand" "f")))
- (clobber (reg:CC 33))]
+(define_insn "*neg<mode>2"
+ [(set (match_operand:FPR 0 "register_operand" "=f")
+ (neg:FPR (match_operand:FPR 1 "register_operand" "f")))
+ (clobber (reg:CC CC_REGNUM))]
"TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
- "lcebr\t%0,%1"
+ "lc<de>br\t%0,%1"
[(set_attr "op_type" "RRE")
- (set_attr "type" "fsimps")])
+ (set_attr "type" "fsimp<mode>")])
-(define_insn "*negsf2"
- [(set (match_operand:SF 0 "register_operand" "=f")
- (neg:SF (match_operand:SF 1 "register_operand" "f")))
- (clobber (reg:CC 33))]
+(define_insn "*neg<mode>2_ibm"
+ [(set (match_operand:FPR 0 "register_operand" "=f")
+ (neg:FPR (match_operand:FPR 1 "register_operand" "f")))
+ (clobber (reg:CC CC_REGNUM))]
"TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
- "lcer\t%0,%1"
+ "lc<de>r\t%0,%1"
[(set_attr "op_type" "RR")
- (set_attr "type" "fsimps")])
+ (set_attr "type" "fsimp<mode>")])
;;
;
(define_insn "*absdi2_sign_cc"
- [(set (reg 33)
+ [(set (reg CC_REGNUM)
(compare (abs:DI (ashiftrt:DI (ashift:DI (subreg:DI
(match_operand:SI 1 "register_operand" "d") 0)
(const_int 32)) (const_int 32)))
(define_insn "*absdi2_sign"
[(set (match_operand:DI 0 "register_operand" "=d")
(abs:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))))
- (clobber (reg:CC 33))]
+ (clobber (reg:CC CC_REGNUM))]
"TARGET_64BIT"
"lpgfr\t%0,%1"
[(set_attr "op_type" "RRE")])
(define_insn "*abs<mode>2_cc"
- [(set (reg 33)
+ [(set (reg CC_REGNUM)
(compare (abs:GPR (match_operand:DI 1 "register_operand" "d"))
(const_int 0)))
(set (match_operand:GPR 0 "register_operand" "=d")
[(set_attr "op_type" "RR<E>")])
(define_insn "*abs<mode>2_cconly"
- [(set (reg 33)
+ [(set (reg CC_REGNUM)
(compare (abs:GPR (match_operand:GPR 1 "register_operand" "d"))
(const_int 0)))
(clobber (match_scratch:GPR 0 "=d"))]
(define_insn "abs<mode>2"
[(set (match_operand:GPR 0 "register_operand" "=d")
(abs:GPR (match_operand:GPR 1 "register_operand" "d")))
- (clobber (reg:CC 33))]
+ (clobber (reg:CC CC_REGNUM))]
""
"lp<g>r\t%0,%1"
[(set_attr "op_type" "RR<E>")])
;
-; absdf2 instruction pattern(s).
-;
-
-(define_expand "absdf2"
- [(parallel
- [(set (match_operand:DF 0 "register_operand" "=f")
- (abs:DF (match_operand:DF 1 "register_operand" "f")))
- (clobber (reg:CC 33))])]
- "TARGET_HARD_FLOAT"
- "")
-
-(define_insn "*absdf2_cc"
- [(set (reg 33)
- (compare (abs:DF (match_operand:DF 1 "register_operand" "f"))
- (match_operand:DF 2 "const0_operand" "")))
- (set (match_operand:DF 0 "register_operand" "=f")
- (abs:DF (match_dup 1)))]
- "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
- "lpdbr\t%0,%1"
- [(set_attr "op_type" "RRE")
- (set_attr "type" "fsimpd")])
-
-(define_insn "*absdf2_cconly"
- [(set (reg 33)
- (compare (abs:DF (match_operand:DF 1 "register_operand" "f"))
- (match_operand:DF 2 "const0_operand" "")))
- (clobber (match_scratch:DF 0 "=f"))]
- "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
- "lpdbr\t%0,%1"
- [(set_attr "op_type" "RRE")
- (set_attr "type" "fsimpd")])
-
-(define_insn "*absdf2"
- [(set (match_operand:DF 0 "register_operand" "=f")
- (abs:DF (match_operand:DF 1 "register_operand" "f")))
- (clobber (reg:CC 33))]
- "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
- "lpdbr\t%0,%1"
- [(set_attr "op_type" "RRE")
- (set_attr "type" "fsimpd")])
-
-(define_insn "*absdf2_ibm"
- [(set (match_operand:DF 0 "register_operand" "=f")
- (abs:DF (match_operand:DF 1 "register_operand" "f")))
- (clobber (reg:CC 33))]
- "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
- "lpdr\t%0,%1"
- [(set_attr "op_type" "RR")
- (set_attr "type" "fsimpd")])
-
-;
-; abssf2 instruction pattern(s).
+; abs(df|sf)2 instruction pattern(s).
;
-(define_expand "abssf2"
+(define_expand "abs<mode>2"
[(parallel
- [(set (match_operand:SF 0 "register_operand" "=f")
- (abs:SF (match_operand:SF 1 "register_operand" "f")))
- (clobber (reg:CC 33))])]
+ [(set (match_operand:FPR 0 "register_operand" "=f")
+ (abs:FPR (match_operand:FPR 1 "register_operand" "f")))
+ (clobber (reg:CC CC_REGNUM))])]
"TARGET_HARD_FLOAT"
"")
-(define_insn "*abssf2_cc"
- [(set (reg 33)
- (compare (abs:SF (match_operand:SF 1 "register_operand" "f"))
- (match_operand:SF 2 "const0_operand" "")))
- (set (match_operand:SF 0 "register_operand" "=f")
- (abs:SF (match_dup 1)))]
+(define_insn "*abs<mode>2_cc"
+ [(set (reg CC_REGNUM)
+ (compare (abs:FPR (match_operand:FPR 1 "register_operand" "f"))
+ (match_operand:FPR 2 "const0_operand" "")))
+ (set (match_operand:FPR 0 "register_operand" "=f")
+ (abs:FPR (match_dup 1)))]
"s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
- "lpebr\t%0,%1"
+ "lp<de>br\t%0,%1"
[(set_attr "op_type" "RRE")
- (set_attr "type" "fsimps")])
+ (set_attr "type" "fsimp<mode>")])
-(define_insn "*abssf2_cconly"
- [(set (reg 33)
- (compare (abs:SF (match_operand:SF 1 "register_operand" "f"))
- (match_operand:SF 2 "const0_operand" "")))
- (clobber (match_scratch:SF 0 "=f"))]
+(define_insn "*abs<mode>2_cconly"
+ [(set (reg CC_REGNUM)
+ (compare (abs:FPR (match_operand:FPR 1 "register_operand" "f"))
+ (match_operand:FPR 2 "const0_operand" "")))
+ (clobber (match_scratch:FPR 0 "=f"))]
"s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
- "lpebr\t%0,%1"
+ "lp<de>br\t%0,%1"
[(set_attr "op_type" "RRE")
- (set_attr "type" "fsimps")])
+ (set_attr "type" "fsimp<mode>")])
-(define_insn "*abssf2"
- [(set (match_operand:SF 0 "register_operand" "=f")
- (abs:SF (match_operand:SF 1 "register_operand" "f")))
- (clobber (reg:CC 33))]
+(define_insn "*abs<mode>2"
+ [(set (match_operand:FPR 0 "register_operand" "=f")
+ (abs:FPR (match_operand:FPR 1 "register_operand" "f")))
+ (clobber (reg:CC CC_REGNUM))]
"TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
- "lpebr\t%0,%1"
+ "lp<de>br\t%0,%1"
[(set_attr "op_type" "RRE")
- (set_attr "type" "fsimps")])
+ (set_attr "type" "fsimp<mode>")])
-(define_insn "*abssf2_ibm"
- [(set (match_operand:SF 0 "register_operand" "=f")
- (abs:SF (match_operand:SF 1 "register_operand" "f")))
- (clobber (reg:CC 33))]
+(define_insn "*abs<mode>2_ibm"
+ [(set (match_operand:FPR 0 "register_operand" "=f")
+ (abs:FPR (match_operand:FPR 1 "register_operand" "f")))
+ (clobber (reg:CC CC_REGNUM))]
"TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
- "lper\t%0,%1"
+ "lp<de>r\t%0,%1"
[(set_attr "op_type" "RR")
- (set_attr "type" "fsimps")])
+ (set_attr "type" "fsimp<mode>")])
;;
;;- Negated absolute value instructions
;
(define_insn "*negabsdi2_sign_cc"
- [(set (reg 33)
+ [(set (reg CC_REGNUM)
(compare (neg:DI (abs:DI (ashiftrt:DI (ashift:DI (subreg:DI
(match_operand:SI 1 "register_operand" "d") 0)
(const_int 32)) (const_int 32))))
[(set (match_operand:DI 0 "register_operand" "=d")
(neg:DI (abs:DI (sign_extend:DI
(match_operand:SI 1 "register_operand" "d")))))
- (clobber (reg:CC 33))]
+ (clobber (reg:CC CC_REGNUM))]
"TARGET_64BIT"
"lngfr\t%0,%1"
[(set_attr "op_type" "RRE")])
(define_insn "*negabs<mode>2_cc"
- [(set (reg 33)
+ [(set (reg CC_REGNUM)
(compare (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d")))
(const_int 0)))
(set (match_operand:GPR 0 "register_operand" "=d")
[(set_attr "op_type" "RR<E>")])
(define_insn "*negabs<mode>2_cconly"
- [(set (reg 33)
+ [(set (reg CC_REGNUM)
(compare (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d")))
(const_int 0)))
(clobber (match_scratch:GPR 0 "=d"))]
(define_insn "*negabs<mode>2"
[(set (match_operand:GPR 0 "register_operand" "=d")
(neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d"))))
- (clobber (reg:CC 33))]
+ (clobber (reg:CC CC_REGNUM))]
""
"ln<g>r\t%0,%1"
[(set_attr "op_type" "RR<E>")])
; Floating point
;
-(define_insn "*negabsdf2_cc"
- [(set (reg 33)
- (compare (neg:DF (abs:DF (match_operand:DF 1 "register_operand" "f")))
- (match_operand:DF 2 "const0_operand" "")))
- (set (match_operand:DF 0 "register_operand" "=f")
- (neg:DF (abs:DF (match_dup 1))))]
- "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
- "lndbr\t%0,%1"
- [(set_attr "op_type" "RRE")
- (set_attr "type" "fsimpd")])
-
-(define_insn "*negabsdf2_cconly"
- [(set (reg 33)
- (compare (neg:DF (abs:DF (match_operand:DF 1 "register_operand" "f")))
- (match_operand:DF 2 "const0_operand" "")))
- (clobber (match_scratch:DF 0 "=f"))]
- "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
- "lndbr\t%0,%1"
- [(set_attr "op_type" "RRE")
- (set_attr "type" "fsimpd")])
-
-(define_insn "*negabsdf2"
- [(set (match_operand:DF 0 "register_operand" "=f")
- (neg:DF (abs:DF (match_operand:DF 1 "register_operand" "f"))))
- (clobber (reg:CC 33))]
- "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
- "lndbr\t%0,%1"
- [(set_attr "op_type" "RRE")
- (set_attr "type" "fsimpd")])
-
-(define_insn "*negabssf2_cc"
- [(set (reg 33)
- (compare (neg:SF (abs:SF (match_operand:SF 1 "register_operand" "f")))
- (match_operand:SF 2 "const0_operand" "")))
- (set (match_operand:SF 0 "register_operand" "=f")
- (neg:SF (abs:SF (match_dup 1))))]
+(define_insn "*negabs<mode>2_cc"
+ [(set (reg CC_REGNUM)
+ (compare (neg:FPR (abs:FPR (match_operand:FPR 1 "register_operand" "f")))
+ (match_operand:FPR 2 "const0_operand" "")))
+ (set (match_operand:FPR 0 "register_operand" "=f")
+ (neg:FPR (abs:FPR (match_dup 1))))]
"s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
- "lnebr\t%0,%1"
+ "ln<de>br\t%0,%1"
[(set_attr "op_type" "RRE")
- (set_attr "type" "fsimps")])
+ (set_attr "type" "fsimp<mode>")])
-(define_insn "*negabssf2_cconly"
- [(set (reg 33)
- (compare (neg:SF (abs:SF (match_operand:SF 1 "register_operand" "f")))
- (match_operand:SF 2 "const0_operand" "")))
- (clobber (match_scratch:SF 0 "=f"))]
+(define_insn "*negabs<mode>2_cconly"
+ [(set (reg CC_REGNUM)
+ (compare (neg:FPR (abs:FPR (match_operand:FPR 1 "register_operand" "f")))
+ (match_operand:FPR 2 "const0_operand" "")))
+ (clobber (match_scratch:FPR 0 "=f"))]
"s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
- "lnebr\t%0,%1"
+ "ln<de>br\t%0,%1"
[(set_attr "op_type" "RRE")
- (set_attr "type" "fsimps")])
+ (set_attr "type" "fsimp<mode>")])
-(define_insn "*negabssf2"
- [(set (match_operand:SF 0 "register_operand" "=f")
- (neg:SF (abs:SF (match_operand:SF 1 "register_operand" "f"))))
- (clobber (reg:CC 33))]
+(define_insn "*negabs<mode>2"
+ [(set (match_operand:FPR 0 "register_operand" "=f")
+ (neg:FPR (abs:FPR (match_operand:FPR 1 "register_operand" "f"))))
+ (clobber (reg:CC CC_REGNUM))]
"TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
- "lnebr\t%0,%1"
+ "ln<de>br\t%0,%1"
[(set_attr "op_type" "RRE")
- (set_attr "type" "fsimps")])
+ (set_attr "type" "fsimp<mode>")])
;;
;;- Square root instructions.
;;
;
-; sqrtdf2 instruction pattern(s).
+; sqrt(df|sf)2 instruction pattern(s).
;
-(define_insn "sqrtdf2"
- [(set (match_operand:DF 0 "register_operand" "=f,f")
- (sqrt:DF (match_operand:DF 1 "general_operand" "f,R")))]
+(define_insn "sqrt<mode>2"
+ [(set (match_operand:FPR 0 "register_operand" "=f,f")
+ (sqrt:FPR (match_operand:FPR 1 "general_operand" "f,R")))]
"TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"@
- sqdbr\t%0,%1
- sqdb\t%0,%1"
+ sq<de>br\t%0,%1
+ sq<de>b\t%0,%1"
[(set_attr "op_type" "RRE,RXE")
- (set_attr "type" "fsqrtd")])
+ (set_attr "type" "fsqrt<mode>")])
-;
-; sqrtsf2 instruction pattern(s).
-;
-
-(define_insn "sqrtsf2"
- [(set (match_operand:SF 0 "register_operand" "=f,f")
- (sqrt:SF (match_operand:SF 1 "general_operand" "f,R")))]
- "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
- "@
- sqebr\t%0,%1
- sqeb\t%0,%1"
- [(set_attr "op_type" "RRE,RXE")
- (set_attr "type" "fsqrts")])
;;
;;- One complement instructions.
[(set (match_operand:INT 0 "register_operand" "")
(xor:INT (match_operand:INT 1 "register_operand" "")
(const_int -1)))
- (clobber (reg:CC 33))])]
+ (clobber (reg:CC CC_REGNUM))])]
""
"")
[(set (match_operand:DI 0 "register_operand" "")
(ashiftrt:DI (match_operand:DI 1 "register_operand" "")
(match_operand:SI 2 "shift_count_operand" "")))
- (clobber (reg:CC 33))])]
+ (clobber (reg:CC CC_REGNUM))])]
""
"")
(define_insn "*ashrdi3_cc_31"
- [(set (reg 33)
+ [(set (reg CC_REGNUM)
(compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
(match_operand:SI 2 "shift_count_operand" "Y"))
(const_int 0)))
(set_attr "atype" "reg")])
(define_insn "*ashrdi3_cconly_31"
- [(set (reg 33)
+ [(set (reg CC_REGNUM)
(compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
(match_operand:SI 2 "shift_count_operand" "Y"))
(const_int 0)))
[(set (match_operand:DI 0 "register_operand" "=d")
(ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
(match_operand:SI 2 "shift_count_operand" "Y")))
- (clobber (reg:CC 33))]
+ (clobber (reg:CC CC_REGNUM))]
"!TARGET_64BIT"
"srda\t%0,%Y2"
[(set_attr "op_type" "RS")
(set_attr "atype" "reg")])
(define_insn "*ashrdi3_cc_64"
- [(set (reg 33)
+ [(set (reg CC_REGNUM)
(compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "d")
(match_operand:SI 2 "shift_count_operand" "Y"))
(const_int 0)))
(set_attr "atype" "reg")])
(define_insn "*ashrdi3_cconly_64"
- [(set (reg 33)
+ [(set (reg CC_REGNUM)
(compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "d")
(match_operand:SI 2 "shift_count_operand" "Y"))
(const_int 0)))
[(set (match_operand:DI 0 "register_operand" "=d")
(ashiftrt:DI (match_operand:DI 1 "register_operand" "d")
(match_operand:SI 2 "shift_count_operand" "Y")))
- (clobber (reg:CC 33))]
+ (clobber (reg:CC CC_REGNUM))]
"TARGET_64BIT"
"srag\t%0,%1,%Y2"
[(set_attr "op_type" "RSE")
;
(define_insn "*ashrsi3_cc"
- [(set (reg 33)
+ [(set (reg CC_REGNUM)
(compare (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
(match_operand:SI 2 "shift_count_operand" "Y"))
(const_int 0)))
(define_insn "*ashrsi3_cconly"
- [(set (reg 33)
+ [(set (reg CC_REGNUM)
(compare (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
(match_operand:SI 2 "shift_count_operand" "Y"))
(const_int 0)))
[(set (match_operand:SI 0 "register_operand" "=d")
(ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
(match_operand:SI 2 "shift_count_operand" "Y")))
- (clobber (reg:CC 33))]
+ (clobber (reg:CC CC_REGNUM))]
""
"sra\t%0,%Y2"
[(set_attr "op_type" "RS")
(define_insn "*cjump_64"
[(set (pc)
(if_then_else
- (match_operator 1 "s390_comparison" [(reg 33) (const_int 0)])
+ (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
(label_ref (match_operand 0 "" ""))
(pc)))]
"TARGET_CPU_ZARCH"
(define_insn "*cjump_31"
[(set (pc)
(if_then_else
- (match_operator 1 "s390_comparison" [(reg 33) (const_int 0)])
+ (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
(label_ref (match_operand 0 "" ""))
(pc)))]
"!TARGET_CPU_ZARCH"
{
- if (get_attr_length (insn) == 4)
- return "j%C1\t%l0";
- else
- abort ();
+ gcc_assert (get_attr_length (insn) == 4);
+ return "j%C1\t%l0";
}
[(set_attr "op_type" "RI")
(set_attr "type" "branch")
(define_insn "*cjump_long"
[(set (pc)
(if_then_else
- (match_operator 1 "s390_comparison" [(reg 33) (const_int 0)])
+ (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
(match_operand 0 "address_operand" "U")
(pc)))]
""
(define_insn "*icjump_64"
[(set (pc)
(if_then_else
- (match_operator 1 "s390_comparison" [(reg 33) (const_int 0)])
+ (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
(pc)
(label_ref (match_operand 0 "" ""))))]
"TARGET_CPU_ZARCH"
(define_insn "*icjump_31"
[(set (pc)
(if_then_else
- (match_operator 1 "s390_comparison" [(reg 33) (const_int 0)])
+ (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
(pc)
(label_ref (match_operand 0 "" ""))))]
"!TARGET_CPU_ZARCH"
{
- if (get_attr_length (insn) == 4)
- return "j%D1\t%l0";
- else
- abort ();
+ gcc_assert (get_attr_length (insn) == 4);
+ return "j%D1\t%l0";
}
[(set_attr "op_type" "RI")
(set_attr "type" "branch")
(define_insn "*icjump_long"
[(set (pc)
(if_then_else
- (match_operator 1 "s390_comparison" [(reg 33) (const_int 0)])
+ (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
(pc)
(match_operand 0 "address_operand" "U")))]
""
})
(define_insn "*trap"
- [(trap_if (match_operator 0 "s390_comparison" [(reg 33) (const_int 0)])
+ [(trap_if (match_operator 0 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
(const_int 0))]
""
"j%C0\t.+2";
(set (match_operand:SI 2 "nonimmediate_operand" "=1,?*m*d")
(plus:SI (match_dup 1) (const_int -1)))
(clobber (match_scratch:SI 3 "=X,&1"))
- (clobber (reg:CC 33))]
+ (clobber (reg:CC CC_REGNUM))]
"TARGET_CPU_ZARCH"
{
if (which_alternative != 0)
"&& reload_completed
&& (! REG_P (operands[2])
|| ! rtx_equal_p (operands[1], operands[2]))"
- [(parallel [(set (reg:CCAN 33)
+ [(parallel [(set (reg:CCAN CC_REGNUM)
(compare:CCAN (plus:SI (match_dup 3) (const_int -1))
(const_int 0)))
(set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))])
(set (match_dup 2) (match_dup 3))
- (set (pc) (if_then_else (ne (reg:CCAN 33) (const_int 0))
+ (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0))
(label_ref (match_dup 0))
(pc)))]
""
(set (match_operand:SI 2 "nonimmediate_operand" "=1,?*m*d")
(plus:SI (match_dup 1) (const_int -1)))
(clobber (match_scratch:SI 3 "=X,&1"))
- (clobber (reg:CC 33))]
+ (clobber (reg:CC CC_REGNUM))]
"!TARGET_CPU_ZARCH"
{
if (which_alternative != 0)
else if (get_attr_length (insn) == 4)
return "brct\t%1,%l0";
else
- abort ();
+ gcc_unreachable ();
}
"&& reload_completed
&& (! REG_P (operands[2])
|| ! rtx_equal_p (operands[1], operands[2]))"
- [(parallel [(set (reg:CCAN 33)
+ [(parallel [(set (reg:CCAN CC_REGNUM)
(compare:CCAN (plus:SI (match_dup 3) (const_int -1))
(const_int 0)))
(set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))])
(set (match_dup 2) (match_dup 3))
- (set (pc) (if_then_else (ne (reg:CCAN 33) (const_int 0))
+ (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0))
(label_ref (match_dup 0))
(pc)))]
""
(set (match_operand:SI 2 "register_operand" "=1,?*m*d")
(plus:SI (match_dup 1) (const_int -1)))
(clobber (match_scratch:SI 3 "=X,&1"))
- (clobber (reg:CC 33))]
+ (clobber (reg:CC CC_REGNUM))]
"!TARGET_CPU_ZARCH"
{
if (get_attr_op_type (insn) == OP_TYPE_RR)
(set (match_operand:DI 2 "nonimmediate_operand" "=1,?*m*d")
(plus:DI (match_dup 1) (const_int -1)))
(clobber (match_scratch:DI 3 "=X,&1"))
- (clobber (reg:CC 33))]
+ (clobber (reg:CC CC_REGNUM))]
"TARGET_64BIT"
{
if (which_alternative != 0)
"&& reload_completed
&& (! REG_P (operands[2])
|| ! rtx_equal_p (operands[1], operands[2]))"
- [(parallel [(set (reg:CCAN 33)
+ [(parallel [(set (reg:CCAN CC_REGNUM)
(compare:CCAN (plus:DI (match_dup 3) (const_int -1))
(const_int 0)))
(set (match_dup 3) (plus:DI (match_dup 3) (const_int -1)))])
(set (match_dup 2) (match_dup 3))
- (set (pc) (if_then_else (ne (reg:CCAN 33) (const_int 0))
+ (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0))
(label_ref (match_dup 0))
(pc)))]
""
[(set (pc) (label_ref (match_operand 0 "" "")))]
"!TARGET_CPU_ZARCH"
{
- if (get_attr_length (insn) == 4)
- return "j\t%l0";
- else
- abort ();
+ gcc_assert (get_attr_length (insn) == 4);
+ return "j\t%l0";
}
[(set_attr "op_type" "RI")
(set_attr "type" "branch")
})
(define_insn "*sibcall_br"
- [(call (mem:QI (reg 1))
+ [(call (mem:QI (reg SIBCALL_REGNUM))
(match_operand 0 "const_int_operand" "n"))]
"SIBLING_CALL_P (insn)
&& GET_MODE (XEXP (XEXP (PATTERN (insn), 0), 0)) == Pmode"
(define_insn "*sibcall_value_br"
[(set (match_operand 0 "" "")
- (call (mem:QI (reg 1))
+ (call (mem:QI (reg SIBCALL_REGNUM))
(match_operand 1 "const_int_operand" "n")))]
"SIBLING_CALL_P (insn)
&& GET_MODE (XEXP (XEXP (XEXP (PATTERN (insn), 1), 0), 0)) == Pmode"
;;
(define_expand "get_tp_64"
- [(set (match_operand:DI 0 "nonimmediate_operand" "") (reg:DI 36))]
+ [(set (match_operand:DI 0 "nonimmediate_operand" "") (reg:DI TP_REGNUM))]
"TARGET_64BIT"
"")
(define_expand "get_tp_31"
- [(set (match_operand:SI 0 "nonimmediate_operand" "") (reg:SI 36))]
+ [(set (match_operand:SI 0 "nonimmediate_operand" "") (reg:SI TP_REGNUM))]
"!TARGET_64BIT"
"")
(define_expand "set_tp_64"
- [(set (reg:DI 36) (match_operand:DI 0 "nonimmediate_operand" ""))
- (set (reg:DI 36) (unspec_volatile:DI [(reg:DI 36)] UNSPECV_SET_TP))]
+ [(set (reg:DI TP_REGNUM) (match_operand:DI 0 "nonimmediate_operand" ""))
+ (set (reg:DI TP_REGNUM) (unspec_volatile:DI [(reg:DI TP_REGNUM)] UNSPECV_SET_TP))]
"TARGET_64BIT"
"")
(define_expand "set_tp_31"
- [(set (reg:SI 36) (match_operand:SI 0 "nonimmediate_operand" ""))
- (set (reg:SI 36) (unspec_volatile:SI [(reg:SI 36)] UNSPECV_SET_TP))]
+ [(set (reg:SI TP_REGNUM) (match_operand:SI 0 "nonimmediate_operand" ""))
+ (set (reg:SI TP_REGNUM) (unspec_volatile:SI [(reg:SI TP_REGNUM)] UNSPECV_SET_TP))]
"!TARGET_64BIT"
"")
(define_insn "*set_tp"
- [(set (reg 36) (unspec_volatile [(reg 36)] UNSPECV_SET_TP))]
+ [(set (reg TP_REGNUM) (unspec_volatile [(reg TP_REGNUM)] UNSPECV_SET_TP))]
""
""
[(set_attr "type" "none")
[(set (match_operand 0 "register_operand" "=a")
(unspec_volatile [(const_int 0)] UNSPECV_MAIN_POOL))]
"GET_MODE (operands[0]) == Pmode"
- "* abort ();"
+{
+ gcc_unreachable ();
+}
[(set (attr "type")
(if_then_else (ne (symbol_ref "TARGET_CPU_ZARCH") (const_int 0))
(const_string "larl") (const_string "la")))])
(define_insn "pool"
[(unspec_volatile [(match_operand 0 "const_int_operand" "n")] UNSPECV_POOL)]
""
- "* abort ();"
+{
+ gcc_unreachable ();
+}
[(set (attr "length") (symbol_ref "INTVAL (operands[0])"))])
;;
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