;; I -- An 8-bit constant (0..255).
;; J -- A 12-bit constant (0..4095).
;; K -- A 16-bit constant (-32768..32767).
-;; L -- Value appropriate as displacement.
+;; L -- Value appropriate as displacement.
;; (0..4095) for short displacement
;; (-524288..524287) for long displacement
;; M -- Constant integer with a value of 0x7fffffff.
;; H,Q: mode of the part
;; D,S,H: mode of the containing operand
;; 0,F: value of the other parts (F - all bits set)
-;;
+;;
;; The constraint matches if the specified part of a constant
;; has a value different from its other parts.
;; Q -- Memory reference without index register and with short displacement.
; Literal pool
(UNSPEC_RELOAD_BASE 210)
(UNSPEC_MAIN_BASE 211)
+ (UNSPEC_LTREF 212)
; TLS relocation specifiers
(UNSPEC_TLSGD 500)
[; Blockage
(UNSPECV_BLOCKAGE 0)
+ ; TPF Support
+ (UNSPECV_TPF_PROLOGUE 20)
+ (UNSPECV_TPF_EPILOGUE 21)
+
; Literal pool
(UNSPECV_POOL 200)
(UNSPECV_POOL_START 201)
;; Processor type. This attribute must exactly match the processor_type
-;; enumeration in s390.h.
+;; enumeration in s390.h. The current machine description does not
+;; distinguish between g5 and g6, but there are differences between the two
+;; CPUs could in theory be modeled.
(define_attr "cpu" "g5,g6,z900,z990"
(const (symbol_ref "s390_tune")))
(eq_attr "op_type" "SIY") (const_string "agen")]
(const_string "reg")))
-;; Generic pipeline function unit.
-
-(define_function_unit "integer" 1 0
- (eq_attr "type" "none") 0 0)
-
-(define_function_unit "integer" 1 0
- (eq_attr "type" "integer") 1 1)
-
-(define_function_unit "integer" 1 0
- (eq_attr "type" "fsimpd") 1 1)
-
-(define_function_unit "integer" 1 0
- (eq_attr "type" "fsimps") 1 1)
-
-(define_function_unit "integer" 1 0
- (eq_attr "type" "load") 1 1)
-
-(define_function_unit "integer" 1 0
- (eq_attr "type" "floadd") 1 1)
-
-(define_function_unit "integer" 1 0
- (eq_attr "type" "floads") 1 1)
-
-(define_function_unit "integer" 1 0
- (eq_attr "type" "la") 1 1)
-
-(define_function_unit "integer" 1 0
- (eq_attr "type" "larl") 1 1)
-
-(define_function_unit "integer" 1 0
- (eq_attr "type" "lr") 1 1)
-
-(define_function_unit "integer" 1 0
- (eq_attr "type" "branch") 1 1)
-
-(define_function_unit "integer" 1 0
- (eq_attr "type" "store") 1 1)
-
-(define_function_unit "integer" 1 0
- (eq_attr "type" "fstored") 1 1)
-
-(define_function_unit "integer" 1 0
- (eq_attr "type" "fstores") 1 1)
-
-(define_function_unit "integer" 1 0
- (eq_attr "type" "lm") 2 2)
-
-(define_function_unit "integer" 1 0
- (eq_attr "type" "stm") 2 2)
-
-(define_function_unit "integer" 1 0
- (eq_attr "type" "cs") 5 5)
-
-(define_function_unit "integer" 1 0
- (eq_attr "type" "vs") 30 30)
-
-(define_function_unit "integer" 1 0
- (eq_attr "type" "jsr") 5 5)
-
-(define_function_unit "integer" 1 0
- (eq_attr "type" "imul") 7 7)
-
-(define_function_unit "integer" 1 0
- (eq_attr "type" "fmuld") 6 6)
-
-(define_function_unit "integer" 1 0
- (eq_attr "type" "fmuls") 6 6)
-
-(define_function_unit "integer" 1 0
- (eq_attr "type" "idiv") 33 33)
-
-(define_function_unit "integer" 1 0
- (eq_attr "type" "fdivd") 33 33)
-
-(define_function_unit "integer" 1 0
- (eq_attr "type" "fdivs") 33 33)
-
-(define_function_unit "integer" 1 0
- (eq_attr "type" "fsqrtd") 30 30)
-
-(define_function_unit "integer" 1 0
- (eq_attr "type" "fsqrts") 30 30)
-
-(define_function_unit "integer" 1 0
- (eq_attr "type" "ftoi") 2 2)
-
-(define_function_unit "integer" 1 0
- (eq_attr "type" "itof") 2 2)
-
-(define_function_unit "integer" 1 0
- (eq_attr "type" "o2") 2 2)
-
-(define_function_unit "integer" 1 0
- (eq_attr "type" "o3") 3 3)
-
-(define_function_unit "integer" 1 0
- (eq_attr "type" "other") 5 5)
-
-;; Pipeline description for z900
-
+;; Pipeline description for z900. For lack of anything better,
+;; this description is also used for the g5 and g6.
(include "2064.md")
+
+;; Pipeline description for z990.
(include "2084.md")
;; Length in bytes.
})
-; Test-under-Mask (zero_extract) instructions
-
-(define_insn "*tmdi_ext"
- [(set (reg 33)
- (compare (zero_extract:DI (match_operand:DI 0 "register_operand" "d")
- (match_operand:DI 1 "const_int_operand" "n")
- (match_operand:DI 2 "const_int_operand" "n"))
- (const_int 0)))]
- "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT
- && INTVAL (operands[1]) >= 1 && INTVAL (operands[2]) >= 0
- && INTVAL (operands[1]) + INTVAL (operands[2]) <= 64
- && (INTVAL (operands[1]) + INTVAL (operands[2]) - 1) >> 4
- == INTVAL (operands[2]) >> 4"
-{
- int part = INTVAL (operands[2]) >> 4;
- int block = (1 << INTVAL (operands[1])) - 1;
- int shift = 16 - INTVAL (operands[1]) - (INTVAL (operands[2]) & 15);
-
- operands[2] = GEN_INT (block << shift);
-
- switch (part)
- {
- case 0: return "tmhh\t%0,%x2";
- case 1: return "tmhl\t%0,%x2";
- case 2: return "tmlh\t%0,%x2";
- case 3: return "tmll\t%0,%x2";
- default: abort ();
- }
-}
- [(set_attr "op_type" "RI")])
-
-(define_insn "*tmsi_ext"
- [(set (reg 33)
- (compare (zero_extract:SI (match_operand:SI 0 "register_operand" "d")
- (match_operand:SI 1 "const_int_operand" "n")
- (match_operand:SI 2 "const_int_operand" "n"))
- (const_int 0)))]
- "s390_match_ccmode(insn, CCTmode)
- && INTVAL (operands[1]) >= 1 && INTVAL (operands[2]) >= 0
- && INTVAL (operands[1]) + INTVAL (operands[2]) <= 32
- && (INTVAL (operands[1]) + INTVAL (operands[2]) - 1) >> 4
- == INTVAL (operands[2]) >> 4"
-{
- int part = INTVAL (operands[2]) >> 4;
- int block = (1 << INTVAL (operands[1])) - 1;
- int shift = 16 - INTVAL (operands[1]) - (INTVAL (operands[2]) & 15);
-
- operands[2] = GEN_INT (block << shift);
-
- switch (part)
- {
- case 0: return "tmh\t%0,%x2";
- case 1: return "tml\t%0,%x2";
- default: abort ();
- }
-}
- [(set_attr "op_type" "RI")])
-
-(define_insn "*tmqisi_ext"
- [(set (reg 33)
- (compare (zero_extract:SI (match_operand:QI 0 "memory_operand" "Q,S")
- (match_operand:SI 1 "const_int_operand" "n,n")
- (match_operand:SI 2 "const_int_operand" "n,n"))
- (const_int 0)))]
- "!TARGET_64BIT && s390_match_ccmode(insn, CCTmode)
- && INTVAL (operands[1]) >= 1 && INTVAL (operands[2]) >= 0
- && INTVAL (operands[1]) + INTVAL (operands[2]) <= 8"
-{
- int block = (1 << INTVAL (operands[1])) - 1;
- int shift = 8 - INTVAL (operands[1]) - INTVAL (operands[2]);
-
- operands[2] = GEN_INT (block << shift);
- return which_alternative == 0 ? "tm\t%0,%b2" : "tmy\t%0,%b2";
-}
- [(set_attr "op_type" "SI,SIY")])
-
-(define_insn "*tmqidi_ext"
- [(set (reg 33)
- (compare (zero_extract:DI (match_operand:QI 0 "memory_operand" "Q,S")
- (match_operand:SI 1 "const_int_operand" "n,n")
- (match_operand:SI 2 "const_int_operand" "n,n"))
- (const_int 0)))]
- "TARGET_64BIT && s390_match_ccmode(insn, CCTmode)
- && INTVAL (operands[1]) >= 1 && INTVAL (operands[2]) >= 0
- && INTVAL (operands[1]) + INTVAL (operands[2]) <= 8"
-{
- int block = (1 << INTVAL (operands[1])) - 1;
- int shift = 8 - INTVAL (operands[1]) - INTVAL (operands[2]);
-
- operands[2] = GEN_INT (block << shift);
- return which_alternative == 0 ? "tm\t%0,%b2" : "tmy\t%0,%b2";
-}
- [(set_attr "op_type" "SI,SIY")])
-
-
; Test-under-Mask instructions
-(define_insn "*tmdi_mem"
- [(set (reg 33)
- (compare (and:DI (match_operand:DI 0 "memory_operand" "Q,S")
- (match_operand:DI 1 "immediate_operand" "n,n"))
- (match_operand:DI 2 "immediate_operand" "n,n")))]
- "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 0))
- && s390_single_part (operands[1], DImode, QImode, 0) >= 0"
-{
- int part = s390_single_part (operands[1], DImode, QImode, 0);
- operands[1] = GEN_INT (s390_extract_part (operands[1], QImode, 0));
-
- operands[0] = gen_rtx_MEM (QImode,
- plus_constant (XEXP (operands[0], 0), part));
- return which_alternative == 0 ? "tm\t%0,%b1" : "tmy\t%0,%b1";
-}
- [(set_attr "op_type" "SI,SIY")])
-
-(define_insn "*tmsi_mem"
- [(set (reg 33)
- (compare (and:SI (match_operand:SI 0 "memory_operand" "Q,S")
- (match_operand:SI 1 "immediate_operand" "n,n"))
- (match_operand:SI 2 "immediate_operand" "n,n")))]
- "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 0))
- && s390_single_part (operands[1], SImode, QImode, 0) >= 0"
-{
- int part = s390_single_part (operands[1], SImode, QImode, 0);
- operands[1] = GEN_INT (s390_extract_part (operands[1], QImode, 0));
-
- operands[0] = gen_rtx_MEM (QImode,
- plus_constant (XEXP (operands[0], 0), part));
- return which_alternative == 0 ? "tm\t%0,%b1" : "tmy\t%0,%b1";
-}
- [(set_attr "op_type" "SI")])
-
-(define_insn "*tmhi_mem"
- [(set (reg 33)
- (compare (and:SI (subreg:SI (match_operand:HI 0 "memory_operand" "Q,S") 0)
- (match_operand:SI 1 "immediate_operand" "n,n"))
- (match_operand:SI 2 "immediate_operand" "n,n")))]
- "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 0))
- && s390_single_part (operands[1], HImode, QImode, 0) >= 0"
-{
- int part = s390_single_part (operands[1], HImode, QImode, 0);
- operands[1] = GEN_INT (s390_extract_part (operands[1], QImode, 0));
-
- operands[0] = gen_rtx_MEM (QImode,
- plus_constant (XEXP (operands[0], 0), part));
- return which_alternative == 0 ? "tm\t%0,%b1" : "tmy\t%0,%b1";
-}
- [(set_attr "op_type" "SI")])
-
(define_insn "*tmqi_mem"
[(set (reg 33)
- (compare (and:SI (subreg:SI (match_operand:QI 0 "memory_operand" "Q,S") 0)
- (match_operand:SI 1 "immediate_operand" "n,n"))
- (match_operand:SI 2 "immediate_operand" "n,n")))]
+ (compare (and:QI (match_operand:QI 0 "memory_operand" "Q,S")
+ (match_operand:QI 1 "immediate_operand" "n,n"))
+ (match_operand:QI 2 "immediate_operand" "n,n")))]
"s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 0))"
"@
tm\t%0,%b1
(define_insn "*tmdi_reg"
[(set (reg 33)
(compare (and:DI (match_operand:DI 0 "nonimmediate_operand" "d,d,d,d")
- (match_operand:DI 1 "immediate_operand"
+ (match_operand:DI 1 "immediate_operand"
"N0HD0,N1HD0,N2HD0,N3HD0"))
(match_operand:DI 2 "immediate_operand" "n,n,n,n")))]
"TARGET_64BIT
(set_attr "type" "larl")])
(define_insn "*movdi_64"
- [(set (match_operand:DI 0 "nonimmediate_operand"
+ [(set (match_operand:DI 0 "nonimmediate_operand"
"=d,d,d,d,d,d,d,d,m,!*f,!*f,!*f,!R,!T,?Q")
- (match_operand:DI 1 "general_operand"
+ (match_operand:DI 1 "general_operand"
"K,N0HD0,N1HD0,N2HD0,N3HD0,L,d,m,d,*f,R,T,*f,*f,?Q"))]
"TARGET_64BIT"
"@
(match_operand:QI 1 "address_operand" ""))
(clobber (reg:CC 33))])]
"TARGET_64BIT
- && strict_memory_address_p (VOIDmode, operands[1])
- && preferred_la_operand_p (operands[1])"
+ && preferred_la_operand_p (operands[1], const0_rtx)"
[(set (match_dup 0) (match_dup 1))]
"")
(clobber (reg:CC 33))])]
"TARGET_64BIT
&& !reg_overlap_mentioned_p (operands[0], operands[2])
- && strict_memory_address_p (VOIDmode, gen_rtx_PLUS (DImode, operands[1], operands[2]))
- && preferred_la_operand_p (gen_rtx_PLUS (DImode, operands[1], operands[2]))"
+ && preferred_la_operand_p (operands[1], operands[2])"
[(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))]
"")
(set_attr "type" "larl")])
(define_insn "*movsi_zarch"
- [(set (match_operand:SI 0 "nonimmediate_operand"
+ [(set (match_operand:SI 0 "nonimmediate_operand"
"=d,d,d,d,d,d,d,R,T,!*f,!*f,!*f,!R,!T,?Q")
- (match_operand:SI 1 "general_operand"
+ (match_operand:SI 1 "general_operand"
"K,N0HS0,N1HS0,L,d,R,T,d,d,*f,R,T,*f,*f,?Q"))]
"TARGET_ZARCH"
"@
(match_operand:QI 1 "address_operand" ""))
(clobber (reg:CC 33))])]
"!TARGET_64BIT
- && strict_memory_address_p (VOIDmode, operands[1])
- && preferred_la_operand_p (operands[1])"
+ && preferred_la_operand_p (operands[1], const0_rtx)"
[(set (match_dup 0) (match_dup 1))]
"")
(clobber (reg:CC 33))])]
"!TARGET_64BIT
&& !reg_overlap_mentioned_p (operands[0], operands[2])
- && strict_memory_address_p (VOIDmode, gen_rtx_PLUS (SImode, operands[1], operands[2]))
- && preferred_la_operand_p (gen_rtx_PLUS (SImode, operands[1], operands[2]))"
+ && preferred_la_operand_p (operands[1], operands[2])"
[(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))]
"")
(match_operand:HI 1 "general_operand" ""))]
""
{
- /* Make it explicit that loading a register from memory
+ /* Make it explicit that loading a register from memory
always sign-extends (at least) to SImode. */
if (optimize && !no_new_pseudos
&& register_operand (operands[0], VOIDmode)
- && GET_CODE (operands[1]) == MEM
- && GET_CODE (XEXP (operands[1], 0)) != ADDRESSOF)
+ && GET_CODE (operands[1]) == MEM)
{
rtx tmp = gen_reg_rtx (SImode);
rtx ext = gen_rtx_SIGN_EXTEND (SImode, operands[1]);
is just as fast as a QImode load. */
if (TARGET_ZARCH && optimize && !no_new_pseudos
&& register_operand (operands[0], VOIDmode)
- && GET_CODE (operands[1]) == MEM
- && GET_CODE (XEXP (operands[1], 0)) != ADDRESSOF)
+ && GET_CODE (operands[1]) == MEM)
{
rtx tmp = gen_reg_rtx (word_mode);
rtx ext = gen_rtx_ZERO_EXTEND (word_mode, operands[1]);
;
; load_multiple pattern(s).
;
+; ??? Due to reload problems with replacing registers inside match_parallel
+; we currently support load_multiple/store_multiple only after reload.
+;
(define_expand "load_multiple"
[(match_par_dup 3 [(set (match_operand 0 "" "")
(match_operand 1 "" ""))
(use (match_operand 2 "" ""))])]
- ""
+ "reload_completed"
{
enum machine_mode mode;
int regno;
}
else
FAIL;
-
- if (from == frame_pointer_rtx || from == arg_pointer_rtx)
- FAIL;
}
else
{
[(match_parallel 0 "load_multiple_operation"
[(set (match_operand:DI 1 "register_operand" "=r")
(match_operand:DI 2 "s_operand" "QS"))])]
- "word_mode == DImode"
+ "reload_completed && word_mode == DImode"
{
int words = XVECLEN (operands[0], 0);
operands[0] = gen_rtx_REG (DImode, REGNO (operands[1]) + words - 1);
[(match_parallel 0 "load_multiple_operation"
[(set (match_operand:SI 1 "register_operand" "=r,r")
(match_operand:SI 2 "s_operand" "Q,S"))])]
- ""
+ "reload_completed"
{
int words = XVECLEN (operands[0], 0);
operands[0] = gen_rtx_REG (SImode, REGNO (operands[1]) + words - 1);
[(match_par_dup 3 [(set (match_operand 0 "" "")
(match_operand 1 "" ""))
(use (match_operand 2 "" ""))])]
- ""
+ "reload_completed"
{
enum machine_mode mode;
int regno;
}
else
FAIL;
-
- if (to == frame_pointer_rtx || to == arg_pointer_rtx)
- FAIL;
}
else
{
[(match_parallel 0 "store_multiple_operation"
[(set (match_operand:DI 1 "s_operand" "=QS")
(match_operand:DI 2 "register_operand" "r"))])]
- "word_mode == DImode"
+ "reload_completed && word_mode == DImode"
{
int words = XVECLEN (operands[0], 0);
operands[0] = gen_rtx_REG (DImode, REGNO (operands[2]) + words - 1);
[(match_parallel 0 "store_multiple_operation"
[(set (match_operand:SI 1 "s_operand" "=Q,S")
(match_operand:SI 2 "register_operand" "r,r"))])]
- ""
+ "reload_completed"
{
int words = XVECLEN (operands[0], 0);
operands[0] = gen_rtx_REG (SImode, REGNO (operands[2]) + words - 1);
(define_expand "strlendi"
[(set (reg:QI 0) (match_operand:QI 2 "immediate_operand" ""))
- (parallel
+ (parallel
[(set (match_dup 4)
(unspec:DI [(const_int 0)
(match_operand:BLK 1 "memory_operand" "")
(define_expand "strlensi"
[(set (reg:QI 0) (match_operand:QI 2 "immediate_operand" ""))
- (parallel
+ (parallel
[(set (match_dup 4)
(unspec:SI [(const_int 0)
(match_operand:BLK 1 "memory_operand" "")
(reg:QI 0)
(match_operand 4 "immediate_operand" "")] UNSPEC_SRST))
(clobber (match_scratch:SI 1 "=a"))
- (clobber (reg:CC 33))]
+ (clobber (reg:CC 33))]
"!TARGET_64BIT"
"srst\t%0,%1\;jo\t.-4"
[(set_attr "op_type" "NN")
(set_attr "length" "8")])
;
-; movstrM instruction pattern(s).
+; movmemM instruction pattern(s).
;
-(define_expand "movstrdi"
+(define_expand "movmemdi"
[(set (match_operand:BLK 0 "memory_operand" "")
(match_operand:BLK 1 "memory_operand" ""))
(use (match_operand:DI 2 "general_operand" ""))
(match_operand 3 "" "")]
"TARGET_64BIT"
- "s390_expand_movstr (operands[0], operands[1], operands[2]); DONE;")
+ "s390_expand_movmem (operands[0], operands[1], operands[2]); DONE;")
-(define_expand "movstrsi"
+(define_expand "movmemsi"
[(set (match_operand:BLK 0 "memory_operand" "")
(match_operand:BLK 1 "memory_operand" ""))
(use (match_operand:SI 2 "general_operand" ""))
(match_operand 3 "" "")]
""
- "s390_expand_movstr (operands[0], operands[1], operands[2]); DONE;")
+ "s390_expand_movmem (operands[0], operands[1], operands[2]); DONE;")
; Move a block that is up to 256 bytes in length.
; The block length is taken as (operands[2] % 256) + 1.
-(define_expand "movstr_short"
+(define_expand "movmem_short"
[(parallel
[(set (match_operand:BLK 0 "memory_operand" "")
(match_operand:BLK 1 "memory_operand" ""))
""
"operands[3] = gen_rtx_SCRATCH (Pmode);")
-(define_insn "*movstr_short"
+(define_insn "*movmem_short"
[(set (match_operand:BLK 0 "memory_operand" "=Q,Q")
(match_operand:BLK 1 "memory_operand" "Q,Q"))
(use (match_operand 2 "nonmemory_operand" "n,a"))
; Move a block of arbitrary length.
-(define_expand "movstr_long"
+(define_expand "movmem_long"
[(parallel
[(clobber (match_dup 2))
(clobber (match_dup 3))
operands[3] = reg1;
})
-(define_insn "*movstr_long_64"
+(define_insn "*movmem_long_64"
[(clobber (match_operand:TI 0 "register_operand" "=d"))
(clobber (match_operand:TI 1 "register_operand" "=d"))
(set (mem:BLK (subreg:DI (match_operand:TI 2 "register_operand" "0") 0))
(set_attr "type" "vs")
(set_attr "length" "8")])
-(define_insn "*movstr_long_31"
+(define_insn "*movmem_long_31"
[(clobber (match_operand:DI 0 "register_operand" "=d"))
(clobber (match_operand:DI 1 "register_operand" "=d"))
(set (mem:BLK (subreg:SI (match_operand:DI 2 "register_operand" "0") 0))
(set_attr "length" "8")])
;
-; clrstrM instruction pattern(s).
+; clrmemM instruction pattern(s).
;
-(define_expand "clrstrdi"
+(define_expand "clrmemdi"
[(set (match_operand:BLK 0 "memory_operand" "")
(const_int 0))
(use (match_operand:DI 1 "general_operand" ""))
(match_operand 2 "" "")]
"TARGET_64BIT"
- "s390_expand_clrstr (operands[0], operands[1]); DONE;")
+ "s390_expand_clrmem (operands[0], operands[1]); DONE;")
-(define_expand "clrstrsi"
+(define_expand "clrmemsi"
[(set (match_operand:BLK 0 "memory_operand" "")
(const_int 0))
(use (match_operand:SI 1 "general_operand" ""))
(match_operand 2 "" "")]
""
- "s390_expand_clrstr (operands[0], operands[1]); DONE;")
+ "s390_expand_clrmem (operands[0], operands[1]); DONE;")
; Clear a block that is up to 256 bytes in length.
; The block length is taken as (operands[1] % 256) + 1.
-(define_expand "clrstr_short"
+(define_expand "clrmem_short"
[(parallel
[(set (match_operand:BLK 0 "memory_operand" "")
(const_int 0))
""
"operands[2] = gen_rtx_SCRATCH (Pmode);")
-(define_insn "*clrstr_short"
+(define_insn "*clrmem_short"
[(set (match_operand:BLK 0 "memory_operand" "=Q,Q")
(const_int 0))
(use (match_operand 1 "nonmemory_operand" "n,a"))
; Clear a block of arbitrary length.
-(define_expand "clrstr_long"
+(define_expand "clrmem_long"
[(parallel
[(clobber (match_dup 1))
(set (match_operand:BLK 0 "memory_operand" "")
operands[2] = reg1;
})
-(define_insn "*clrstr_long_64"
+(define_insn "*clrmem_long_64"
[(clobber (match_operand:TI 0 "register_operand" "=d"))
(set (mem:BLK (subreg:DI (match_operand:TI 2 "register_operand" "0") 0))
(const_int 0))
(set_attr "type" "vs")
(set_attr "length" "8")])
-(define_insn "*clrstr_long_31"
+(define_insn "*clrmem_long_31"
[(clobber (match_operand:DI 0 "register_operand" "=d"))
(set (mem:BLK (subreg:SI (match_operand:DI 2 "register_operand" "0") 0))
(const_int 0))
(define_insn_and_split "*extendqidi2_short_displ"
[(set (match_operand:DI 0 "register_operand" "=d")
- (sign_extend:DI (match_operand:QI 1 "s_operand" "Q")))]
+ (sign_extend:DI (match_operand:QI 1 "s_operand" "Q")))
+ (clobber (reg:CC 33))]
"TARGET_64BIT && !TARGET_LONG_DISPLACEMENT"
"#"
"&& reload_completed"
(define_insn_and_split "*extendqisi2_short_displ"
[(set (match_operand:SI 0 "register_operand" "=d")
- (sign_extend:SI (match_operand:QI 1 "s_operand" "Q")))]
+ (sign_extend:SI (match_operand:QI 1 "s_operand" "Q")))
+ (clobber (reg:CC 33))]
"!TARGET_LONG_DISPLACEMENT"
"#"
"&& reload_completed"
(define_insn_and_split "*llgt_sidi_split"
[(set (match_operand:DI 0 "register_operand" "=d")
- (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "m") 0)
+ (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "m") 0)
(const_int 2147483647)))
(clobber (reg:CC 33))]
"TARGET_64BIT"
"#"
"&& reload_completed"
[(set (match_dup 0)
- (and:DI (subreg:DI (match_dup 1) 0)
+ (and:DI (subreg:DI (match_dup 1) 0)
(const_int 2147483647)))]
"")
;;
;
+; addti3 instruction pattern(s).
+;
+
+(define_insn_and_split "addti3"
+ [(set (match_operand:TI 0 "register_operand" "=&d")
+ (plus:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
+ (match_operand:TI 2 "general_operand" "do") ) )
+ (clobber (reg:CC 33))]
+ "TARGET_64BIT"
+ "#"
+ "&& reload_completed"
+ [(parallel
+ [(set (reg:CCL1 33)
+ (compare:CCL1 (plus:DI (match_dup 7) (match_dup 8))
+ (match_dup 7)))
+ (set (match_dup 6) (plus:DI (match_dup 7) (match_dup 8)))])
+ (parallel
+ [(set (match_dup 3) (plus:DI (plus:DI (match_dup 4) (match_dup 5))
+ (ltu:DI (reg:CCL1 33) (const_int 0))))
+ (clobber (reg:CC 33))])]
+ "operands[3] = operand_subword (operands[0], 0, 0, TImode);
+ operands[4] = operand_subword (operands[1], 0, 0, TImode);
+ operands[5] = operand_subword (operands[2], 0, 0, TImode);
+ operands[6] = operand_subword (operands[0], 1, 0, TImode);
+ operands[7] = operand_subword (operands[1], 1, 0, TImode);
+ operands[8] = operand_subword (operands[2], 1, 0, TImode);"
+ [(set_attr "op_type" "NN")])
+
+;
; adddi3 instruction pattern(s).
;
;;
;
+; subti3 instruction pattern(s).
+;
+
+(define_insn_and_split "subti3"
+ [(set (match_operand:TI 0 "register_operand" "=&d")
+ (minus:TI (match_operand:TI 1 "register_operand" "0")
+ (match_operand:TI 2 "general_operand" "do") ) )
+ (clobber (reg:CC 33))]
+ "TARGET_64BIT"
+ "#"
+ "&& reload_completed"
+ [(parallel
+ [(set (reg:CCL2 33)
+ (compare:CCL2 (minus:DI (match_dup 7) (match_dup 8))
+ (match_dup 7)))
+ (set (match_dup 6) (minus:DI (match_dup 7) (match_dup 8)))])
+ (parallel
+ [(set (match_dup 3) (minus:DI (minus:DI (match_dup 4) (match_dup 5))
+ (gtu:DI (reg:CCL2 33) (const_int 0))))
+ (clobber (reg:CC 33))])]
+ "operands[3] = operand_subword (operands[0], 0, 0, TImode);
+ operands[4] = operand_subword (operands[1], 0, 0, TImode);
+ operands[5] = operand_subword (operands[2], 0, 0, TImode);
+ operands[6] = operand_subword (operands[0], 1, 0, TImode);
+ operands[7] = operand_subword (operands[1], 1, 0, TImode);
+ operands[8] = operand_subword (operands[2], 1, 0, TImode);"
+ [(set_attr "op_type" "NN")])
+
+;
; subdi3 instruction pattern(s).
;
slg\t%0,%2"
[(set_attr "op_type" "RRE,RXY")])
+(define_insn "*subdi3_cc2"
+ [(set (reg 33)
+ (compare (match_operand:DI 1 "register_operand" "0,0")
+ (match_operand:DI 2 "general_operand" "d,m")))
+ (set (match_operand:DI 0 "register_operand" "=d,d")
+ (minus:DI (match_dup 1) (match_dup 2)))]
+ "s390_match_ccmode (insn, CCL3mode) && TARGET_64BIT"
+ "@
+ slgr\t%0,%2
+ slg\t%0,%2"
+ [(set_attr "op_type" "RRE,RXY")])
+
(define_insn "*subdi3_cconly"
[(set (reg 33)
(compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
slg\t%0,%2"
[(set_attr "op_type" "RRE,RXY")])
+(define_insn "*subdi3_cconly2"
+ [(set (reg 33)
+ (compare (match_operand:DI 1 "register_operand" "0,0")
+ (match_operand:DI 2 "general_operand" "d,m")))
+ (clobber (match_scratch:DI 0 "=d,d"))]
+ "s390_match_ccmode (insn, CCL3mode) && TARGET_64BIT"
+ "@
+ slgr\t%0,%2
+ slg\t%0,%2"
+ [(set_attr "op_type" "RRE,RXY")])
+
(define_insn "*subdi3_64"
[(set (match_operand:DI 0 "register_operand" "=d,d")
(minus:DI (match_operand:DI 1 "register_operand" "0,0")
sly\t%0,%2"
[(set_attr "op_type" "RR,RX,RXY")])
+(define_insn "*subsi3_cc2"
+ [(set (reg 33)
+ (compare (match_operand:SI 1 "register_operand" "0,0,0")
+ (match_operand:SI 2 "general_operand" "d,R,T")))
+ (set (match_operand:SI 0 "register_operand" "=d,d,d")
+ (minus:SI (match_dup 1) (match_dup 2)))]
+ "s390_match_ccmode (insn, CCL3mode)"
+ "@
+ slr\t%0,%2
+ sl\t%0,%2
+ sly\t%0,%2"
+ [(set_attr "op_type" "RR,RX,RXY")])
+
(define_insn "*subsi3_cconly"
[(set (reg 33)
(compare (minus:SI (match_operand:SI 1 "register_operand" "0,0,0")
sly\t%0,%2"
[(set_attr "op_type" "RR,RX,RXY")])
+(define_insn "*subsi3_cconly2"
+ [(set (reg 33)
+ (compare (match_operand:SI 1 "register_operand" "0,0,0")
+ (match_operand:SI 2 "general_operand" "d,R,T")))
+ (clobber (match_scratch:SI 0 "=d,d,d"))]
+ "s390_match_ccmode (insn, CCL3mode)"
+ "@
+ slr\t%0,%2
+ sl\t%0,%2
+ sly\t%0,%2"
+ [(set_attr "op_type" "RR,RX,RXY")])
+
(define_insn "*subsi3_sign"
[(set (match_operand:SI 0 "register_operand" "=d,d")
(minus:SI (match_operand:SI 1 "register_operand" "0,0")
(define_insn "*subdf3_cc"
[(set (reg 33)
- (compare (minus:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0")
+ (compare (minus:DF (match_operand:DF 1 "nonimmediate_operand" "0,0")
(match_operand:DF 2 "general_operand" "f,R"))
(match_operand:DF 3 "const0_operand" "")))
(set (match_operand:DF 0 "register_operand" "=f,f")
(define_insn "*subdf3_cconly"
[(set (reg 33)
- (compare (minus:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0")
+ (compare (minus:DF (match_operand:DF 1 "nonimmediate_operand" "0,0")
(match_operand:DF 2 "general_operand" "f,R"))
(match_operand:DF 3 "const0_operand" "")))
(clobber (match_scratch:DF 0 "=f,f"))]
(define_insn "*subsf3_cc"
[(set (reg 33)
- (compare (minus:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0")
+ (compare (minus:SF (match_operand:SF 1 "nonimmediate_operand" "0,0")
(match_operand:SF 2 "general_operand" "f,R"))
(match_operand:SF 3 "const0_operand" "")))
(set (match_operand:SF 0 "register_operand" "=f,f")
(define_insn "*subsf3_cconly"
[(set (reg 33)
- (compare (minus:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0")
+ (compare (minus:SF (match_operand:SF 1 "nonimmediate_operand" "0,0")
(match_operand:SF 2 "general_operand" "f,R"))
(match_operand:SF 3 "const0_operand" "")))
(clobber (match_scratch:SF 0 "=f,f"))]
;
(define_insn "*adddi3_alc_cc"
- [(set (reg 33)
+ [(set (reg 33)
(compare
(plus:DI (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
(match_operand:DI 2 "general_operand" "d,m"))
(const_int 0)))
(set (match_operand:DI 0 "register_operand" "=d,d")
(plus:DI (plus:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
- "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
+ "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
"@
alcgr\\t%0,%2
alcg\\t%0,%2"
(plus:DI (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
(match_operand:DI 2 "general_operand" "d,m"))
(match_operand:DI 3 "s390_alc_comparison" "")))
- (clobber (reg:CC 33))]
- "TARGET_64BIT"
+ (clobber (reg:CC 33))]
+ "TARGET_64BIT"
"@
alcgr\\t%0,%2
alcg\\t%0,%2"
[(set_attr "op_type" "RRE,RXY")])
(define_insn "*subdi3_slb_cc"
- [(set (reg 33)
+ [(set (reg 33)
(compare
(minus:DI (minus:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
(match_operand:DI 2 "general_operand" "d,m"))
(const_int 0)))
(set (match_operand:DI 0 "register_operand" "=d,d")
(minus:DI (minus:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
- "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
+ "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
"@
slbgr\\t%0,%2
slbg\\t%0,%2"
(minus:DI (minus:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
(match_operand:DI 2 "general_operand" "d,m"))
(match_operand:DI 3 "s390_slb_comparison" "")))
- (clobber (reg:CC 33))]
- "TARGET_64BIT"
+ (clobber (reg:CC 33))]
+ "TARGET_64BIT"
"@
slbgr\\t%0,%2
slbg\\t%0,%2"
[(set_attr "op_type" "RRE,RXY")])
+(define_expand "adddicc"
+ [(match_operand:DI 0 "register_operand" "")
+ (match_operand 1 "comparison_operator" "")
+ (match_operand:DI 2 "register_operand" "")
+ (match_operand:DI 3 "const_int_operand" "")]
+ "TARGET_64BIT"
+ "if (!s390_expand_addcc (GET_CODE (operands[1]),
+ s390_compare_op0, s390_compare_op1,
+ operands[0], operands[2],
+ operands[3])) FAIL; DONE;")
+
;
; addsicc instruction pattern(s).
;
(define_insn "*addsi3_alc_cc"
- [(set (reg 33)
+ [(set (reg 33)
(compare
(plus:SI (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
(match_operand:SI 2 "general_operand" "d,m"))
(const_int 0)))
(set (match_operand:SI 0 "register_operand" "=d,d")
(plus:SI (plus:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
- "s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH"
+ "s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH"
"@
alcr\\t%0,%2
alc\\t%0,%2"
(match_operand:SI 2 "general_operand" "d,m"))
(match_operand:SI 3 "s390_alc_comparison" "")))
(clobber (reg:CC 33))]
- "TARGET_CPU_ZARCH"
+ "TARGET_CPU_ZARCH"
"@
alcr\\t%0,%2
alc\\t%0,%2"
[(set_attr "op_type" "RRE,RXY")])
(define_insn "*subsi3_slb_cc"
- [(set (reg 33)
+ [(set (reg 33)
(compare
(minus:SI (minus:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
(match_operand:SI 2 "general_operand" "d,m"))
(const_int 0)))
(set (match_operand:SI 0 "register_operand" "=d,d")
(minus:SI (minus:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
- "s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH"
+ "s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH"
"@
slbr\\t%0,%2
slb\\t%0,%2"
(minus:SI (minus:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
(match_operand:SI 2 "general_operand" "d,m"))
(match_operand:SI 3 "s390_slb_comparison" "")))
- (clobber (reg:CC 33))]
- "TARGET_CPU_ZARCH"
+ (clobber (reg:CC 33))]
+ "TARGET_CPU_ZARCH"
"@
slbr\\t%0,%2
slb\\t%0,%2"
[(set_attr "op_type" "RRE,RXY")])
+(define_expand "addsicc"
+ [(match_operand:SI 0 "register_operand" "")
+ (match_operand 1 "comparison_operator" "")
+ (match_operand:SI 2 "register_operand" "")
+ (match_operand:SI 3 "const_int_operand" "")]
+ "TARGET_CPU_ZARCH"
+ "if (!s390_expand_addcc (GET_CODE (operands[1]),
+ s390_compare_op0, s390_compare_op1,
+ operands[0], operands[2],
+ operands[3])) FAIL; DONE;")
+
+;
+; scond instruction pattern(s).
+;
+
+(define_insn_and_split "*sconddi"
+ [(set (match_operand:DI 0 "register_operand" "=&d")
+ (match_operand:DI 1 "s390_alc_comparison" ""))
+ (clobber (reg:CC 33))]
+ "TARGET_64BIT"
+ "#"
+ "&& reload_completed"
+ [(set (match_dup 0) (const_int 0))
+ (parallel
+ [(set (match_dup 0) (plus:DI (plus:DI (match_dup 0) (match_dup 0))
+ (match_dup 1)))
+ (clobber (reg:CC 33))])]
+ ""
+ [(set_attr "op_type" "NN")])
+
+(define_insn_and_split "*scondsi"
+ [(set (match_operand:SI 0 "register_operand" "=&d")
+ (match_operand:SI 1 "s390_alc_comparison" ""))
+ (clobber (reg:CC 33))]
+ "TARGET_CPU_ZARCH"
+ "#"
+ "&& reload_completed"
+ [(set (match_dup 0) (const_int 0))
+ (parallel
+ [(set (match_dup 0) (plus:SI (plus:SI (match_dup 0) (match_dup 0))
+ (match_dup 1)))
+ (clobber (reg:CC 33))])]
+ ""
+ [(set_attr "op_type" "NN")])
+
+(define_insn_and_split "*sconddi_neg"
+ [(set (match_operand:DI 0 "register_operand" "=&d")
+ (match_operand:DI 1 "s390_slb_comparison" ""))
+ (clobber (reg:CC 33))]
+ "TARGET_64BIT"
+ "#"
+ "&& reload_completed"
+ [(set (match_dup 0) (const_int 0))
+ (parallel
+ [(set (match_dup 0) (minus:DI (minus:DI (match_dup 0) (match_dup 0))
+ (match_dup 1)))
+ (clobber (reg:CC 33))])
+ (parallel
+ [(set (match_dup 0) (neg:DI (match_dup 0)))
+ (clobber (reg:CC 33))])]
+ ""
+ [(set_attr "op_type" "NN")])
+
+(define_insn_and_split "*scondsi_neg"
+ [(set (match_operand:SI 0 "register_operand" "=&d")
+ (match_operand:SI 1 "s390_slb_comparison" ""))
+ (clobber (reg:CC 33))]
+ "TARGET_CPU_ZARCH"
+ "#"
+ "&& reload_completed"
+ [(set (match_dup 0) (const_int 0))
+ (parallel
+ [(set (match_dup 0) (minus:SI (minus:SI (match_dup 0) (match_dup 0))
+ (match_dup 1)))
+ (clobber (reg:CC 33))])
+ (parallel
+ [(set (match_dup 0) (neg:SI (match_dup 0)))
+ (clobber (reg:CC 33))])]
+ ""
+ [(set_attr "op_type" "NN")])
+
+(define_expand "sltu"
+ [(match_operand:SI 0 "register_operand" "")]
+ "TARGET_CPU_ZARCH"
+ "if (!s390_expand_addcc (LTU, s390_compare_op0, s390_compare_op1,
+ operands[0], const0_rtx, const1_rtx)) FAIL; DONE;")
+
+(define_expand "sgtu"
+ [(match_operand:SI 0 "register_operand" "")]
+ "TARGET_CPU_ZARCH"
+ "if (!s390_expand_addcc (GTU, s390_compare_op0, s390_compare_op1,
+ operands[0], const0_rtx, const1_rtx)) FAIL; DONE;")
+
+(define_expand "sleu"
+ [(match_operand:SI 0 "register_operand" "")]
+ "TARGET_CPU_ZARCH"
+ "if (!s390_expand_addcc (LEU, s390_compare_op0, s390_compare_op1,
+ operands[0], const0_rtx, const1_rtx)) FAIL; DONE;")
+
+(define_expand "sgeu"
+ [(match_operand:SI 0 "register_operand" "")]
+ "TARGET_CPU_ZARCH"
+ "if (!s390_expand_addcc (GEU, s390_compare_op0, s390_compare_op1,
+ operands[0], const0_rtx, const1_rtx)) FAIL; DONE;")
+
;;
;;- Multiply instructions.
(define_insn "divmodtidi3"
[(set (match_operand:TI 0 "register_operand" "=d,d")
(ior:TI
- (zero_extend:TI
- (div:DI (match_operand:DI 1 "register_operand" "0,0")
- (match_operand:DI 2 "general_operand" "d,m")))
(ashift:TI
(zero_extend:TI
- (mod:DI (match_dup 1)
- (match_dup 2)))
- (const_int 64))))]
+ (mod:DI (match_operand:DI 1 "register_operand" "0,0")
+ (match_operand:DI 2 "general_operand" "d,m")))
+ (const_int 64))
+ (zero_extend:TI (div:DI (match_dup 1) (match_dup 2)))))]
"TARGET_64BIT"
"@
dsgr\t%0,%2
(define_insn "divmodtisi3"
[(set (match_operand:TI 0 "register_operand" "=d,d")
(ior:TI
- (zero_extend:TI
- (div:DI (match_operand:DI 1 "register_operand" "0,0")
- (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "d,m"))))
(ashift:TI
(zero_extend:TI
- (mod:DI (match_dup 1)
- (sign_extend:DI (match_dup 2))))
- (const_int 64))))]
+ (mod:DI (match_operand:DI 1 "register_operand" "0,0")
+ (sign_extend:DI
+ (match_operand:SI 2 "nonimmediate_operand" "d,m"))))
+ (const_int 64))
+ (zero_extend:TI
+ (div:DI (match_dup 1) (sign_extend:DI (match_dup 2))))))]
"TARGET_64BIT"
"@
dsgfr\t%0,%2
div_equal = gen_rtx_UDIV (DImode, operands[1], operands[2]);
mod_equal = gen_rtx_UMOD (DImode, operands[1], operands[2]);
equal = gen_rtx_IOR (TImode,
- gen_rtx_ZERO_EXTEND (TImode, div_equal),
gen_rtx_ASHIFT (TImode,
gen_rtx_ZERO_EXTEND (TImode, mod_equal),
- GEN_INT (64)));
+ GEN_INT (64)),
+ gen_rtx_ZERO_EXTEND (TImode, div_equal));
operands[4] = gen_reg_rtx(TImode);
emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[4]));
(define_insn "udivmodtidi3"
[(set (match_operand:TI 0 "register_operand" "=d,d")
- (ior:TI (zero_extend:TI
- (truncate:DI
- (udiv:TI (match_operand:TI 1 "register_operand" "0,0")
- (zero_extend:TI
- (match_operand:DI 2 "nonimmediate_operand" "d,m")))))
- (ashift:TI
- (zero_extend:TI
- (truncate:DI
- (umod:TI (match_dup 1) (zero_extend:TI (match_dup 2)))))
- (const_int 64))))]
+ (ior:TI
+ (ashift:TI
+ (zero_extend:TI
+ (truncate:DI
+ (umod:TI (match_operand:TI 1 "register_operand" "0,0")
+ (zero_extend:TI
+ (match_operand:DI 2 "nonimmediate_operand" "d,m")))))
+ (const_int 64))
+ (zero_extend:TI
+ (truncate:DI
+ (udiv:TI (match_dup 1) (zero_extend:TI (match_dup 2)))))))]
"TARGET_64BIT"
"@
dlgr\t%0,%2
div_equal = gen_rtx_DIV (SImode, operands[1], operands[2]);
mod_equal = gen_rtx_MOD (SImode, operands[1], operands[2]);
equal = gen_rtx_IOR (DImode,
- gen_rtx_ZERO_EXTEND (DImode, div_equal),
gen_rtx_ASHIFT (DImode,
gen_rtx_ZERO_EXTEND (DImode, mod_equal),
- GEN_INT (32)));
+ GEN_INT (32)),
+ gen_rtx_ZERO_EXTEND (DImode, div_equal));
operands[4] = gen_reg_rtx(DImode);
emit_insn (gen_extendsidi2 (operands[4], operands[1]));
(define_insn "divmoddisi3"
[(set (match_operand:DI 0 "register_operand" "=d,d")
- (ior:DI (zero_extend:DI
- (truncate:SI
- (div:DI (match_operand:DI 1 "register_operand" "0,0")
- (sign_extend:DI
- (match_operand:SI 2 "nonimmediate_operand" "d,R")))))
- (ashift:DI
- (zero_extend:DI
- (truncate:SI
- (mod:DI (match_dup 1) (sign_extend:SI (match_dup 2)))))
- (const_int 32))))]
+ (ior:DI
+ (ashift:DI
+ (zero_extend:DI
+ (truncate:SI
+ (mod:DI (match_operand:DI 1 "register_operand" "0,0")
+ (sign_extend:DI
+ (match_operand:SI 2 "nonimmediate_operand" "d,R")))))
+ (const_int 32))
+ (zero_extend:DI
+ (truncate:SI
+ (div:DI (match_dup 1) (sign_extend:DI (match_dup 2)))))))]
"!TARGET_64BIT"
"@
dr\t%0,%2
div_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
mod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
equal = gen_rtx_IOR (DImode,
- gen_rtx_ZERO_EXTEND (DImode, div_equal),
gen_rtx_ASHIFT (DImode,
gen_rtx_ZERO_EXTEND (DImode, mod_equal),
- GEN_INT (32)));
+ GEN_INT (32)),
+ gen_rtx_ZERO_EXTEND (DImode, div_equal));
operands[4] = gen_reg_rtx(DImode);
emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[4]));
(define_insn "udivmoddisi3"
[(set (match_operand:DI 0 "register_operand" "=d,d")
- (ior:DI (zero_extend:DI
- (truncate:SI
- (udiv:DI (match_operand:DI 1 "register_operand" "0,0")
- (zero_extend:DI
- (match_operand:SI 2 "nonimmediate_operand" "d,m")))))
- (ashift:DI
- (zero_extend:DI
- (truncate:SI
- (umod:DI (match_dup 1) (zero_extend:DI (match_dup 2)))))
- (const_int 32))))]
+ (ior:DI
+ (ashift:DI
+ (zero_extend:DI
+ (truncate:SI
+ (umod:DI (match_operand:DI 1 "register_operand" "0,0")
+ (zero_extend:DI
+ (match_operand:SI 2 "nonimmediate_operand" "d,m")))))
+ (const_int 32))
+ (zero_extend:DI
+ (truncate:SI
+ (udiv:DI (match_dup 1) (zero_extend:DI (match_dup 2)))))))]
"!TARGET_64BIT && TARGET_CPU_ZARCH"
"@
dlr\t%0,%2
udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
equal = gen_rtx_IOR (DImode,
- gen_rtx_ZERO_EXTEND (DImode, udiv_equal),
gen_rtx_ASHIFT (DImode,
gen_rtx_ZERO_EXTEND (DImode, umod_equal),
- GEN_INT (32)));
+ GEN_INT (32)),
+ gen_rtx_ZERO_EXTEND (DImode, udiv_equal));
operands[3] = gen_reg_rtx (DImode);
emit_move_insn (operands[0], const0_rtx);
emit_insn (gen_cmpsi (operands[2], operands[1]));
emit_jump_insn (gen_bgtu (label3));
- emit_insn (gen_cmpsi (operands[2], const1_rtx));
+ emit_insn (gen_cmpsi (operands[2], const0_rtx));
emit_jump_insn (gen_blt (label2));
emit_insn (gen_cmpsi (operands[2], const1_rtx));
emit_jump_insn (gen_beq (label1));
udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
equal = gen_rtx_IOR (DImode,
- gen_rtx_ZERO_EXTEND (DImode, udiv_equal),
gen_rtx_ASHIFT (DImode,
gen_rtx_ZERO_EXTEND (DImode, umod_equal),
- GEN_INT (32)));
+ GEN_INT (32)),
+ gen_rtx_ZERO_EXTEND (DImode, udiv_equal));
operands[3] = gen_reg_rtx (DImode);
emit_move_insn(operands[0], operands[1]);
emit_insn (gen_cmpsi (operands[2], operands[1]));
emit_jump_insn (gen_bgtu (label3));
- emit_insn (gen_cmpsi (operands[2], const1_rtx));
+ emit_insn (gen_cmpsi (operands[2], const0_rtx));
emit_jump_insn (gen_blt (label2));
emit_insn (gen_cmpsi (operands[2], const1_rtx));
emit_jump_insn (gen_beq (label1));
(match_operand:DI 2 "general_operand" "d,m"))
(const_int 0)))
(clobber (match_scratch:DI 0 "=d,d"))]
- "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
+ "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT
+ /* Do not steal TM patterns. */
+ && s390_single_part (operands[2], DImode, HImode, 0) < 0"
"@
ngr\t%0,%2
ng\t%0,%2"
(define_insn "anddi3"
[(set (match_operand:DI 0 "register_operand" "=d,d,d,d,d,d,d,d")
(and:DI (match_operand:DI 1 "nonimmediate_operand" "d,o,0,0,0,0,0,0")
- (match_operand:DI 2 "general_operand"
+ (match_operand:DI 2 "general_operand"
"M,M,N0HDF,N1HDF,N2HDF,N3HDF,d,m")))
(clobber (reg:CC 33))]
"TARGET_64BIT"
(match_operand:SI 2 "general_operand" "d,R,T"))
(const_int 0)))
(clobber (match_scratch:SI 0 "=d,d,d"))]
- "s390_match_ccmode(insn, CCTmode)"
+ "s390_match_ccmode(insn, CCTmode)
+ /* Do not steal TM patterns. */
+ && s390_single_part (operands[2], SImode, HImode, 0) < 0"
"@
nr\t%0,%2
n\t%0,%2
[(set_attr "op_type" "RR,RX,RXY")])
(define_expand "andsi3"
- [(parallel
+ [(parallel
[(set (match_operand:SI 0 "register_operand" "")
(and:SI (match_operand:SI 1 "nonimmediate_operand" "")
(match_operand:SI 2 "general_operand" "")))
#
#
nilh\t%0,%j2
- nill\t%0,%j2
+ nill\t%0,%j2
nr\t%0,%2
n\t%0,%2
ny\t%0,%2"
[(set_attr "op_type" "RR,RX,RXY")])
(define_expand "iorsi3"
- [(parallel
+ [(parallel
[(set (match_operand:SI 0 "register_operand" "")
(ior:SI (match_operand:SI 1 "nonimmediate_operand" "")
(match_operand:SI 2 "general_operand" "")))
;;
(define_expand "beq"
- [(set (reg:CCZ 33) (compare:CCZ (match_dup 1) (match_dup 2)))
- (set (pc)
- (if_then_else (eq (reg:CCZ 33) (const_int 0))
- (label_ref (match_operand 0 "" ""))
- (pc)))]
+ [(match_operand 0 "" "")]
""
- "operands[1] = s390_compare_op0; operands[2] = s390_compare_op1;")
+ "s390_emit_jump (operands[0],
+ s390_emit_compare (EQ, s390_compare_op0, s390_compare_op1)); DONE;")
(define_expand "bne"
- [(set (reg:CCZ 33) (compare:CCZ (match_dup 1) (match_dup 2)))
- (set (pc)
- (if_then_else (ne (reg:CCZ 33) (const_int 0))
- (label_ref (match_operand 0 "" ""))
- (pc)))]
+ [(match_operand 0 "" "")]
""
- "operands[1] = s390_compare_op0; operands[2] = s390_compare_op1;")
+ "s390_emit_jump (operands[0],
+ s390_emit_compare (NE, s390_compare_op0, s390_compare_op1)); DONE;")
(define_expand "bgt"
- [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
- (set (pc)
- (if_then_else (gt (reg:CCS 33) (const_int 0))
- (label_ref (match_operand 0 "" ""))
- (pc)))]
+ [(match_operand 0 "" "")]
""
- "operands[1] = s390_compare_op0; operands[2] = s390_compare_op1;")
+ "s390_emit_jump (operands[0],
+ s390_emit_compare (GT, s390_compare_op0, s390_compare_op1)); DONE;")
(define_expand "bgtu"
- [(set (reg:CCU 33) (compare:CCU (match_dup 1) (match_dup 2)))
- (set (pc)
- (if_then_else (gtu (reg:CCU 33) (const_int 0))
- (label_ref (match_operand 0 "" ""))
- (pc)))]
+ [(match_operand 0 "" "")]
""
- "operands[1] = s390_compare_op0; operands[2] = s390_compare_op1;")
+ "s390_emit_jump (operands[0],
+ s390_emit_compare (GTU, s390_compare_op0, s390_compare_op1)); DONE;")
(define_expand "blt"
- [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
- (set (pc)
- (if_then_else (lt (reg:CCS 33) (const_int 0))
- (label_ref (match_operand 0 "" ""))
- (pc)))]
+ [(match_operand 0 "" "")]
""
- "operands[1] = s390_compare_op0; operands[2] = s390_compare_op1;")
+ "s390_emit_jump (operands[0],
+ s390_emit_compare (LT, s390_compare_op0, s390_compare_op1)); DONE;")
(define_expand "bltu"
- [(set (reg:CCU 33) (compare:CCU (match_dup 1) (match_dup 2)))
- (set (pc)
- (if_then_else (ltu (reg:CCU 33) (const_int 0))
- (label_ref (match_operand 0 "" ""))
- (pc)))]
+ [(match_operand 0 "" "")]
""
- "operands[1] = s390_compare_op0; operands[2] = s390_compare_op1;")
+ "s390_emit_jump (operands[0],
+ s390_emit_compare (LTU, s390_compare_op0, s390_compare_op1)); DONE;")
(define_expand "bge"
- [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
- (set (pc)
- (if_then_else (ge (reg:CCS 33) (const_int 0))
- (label_ref (match_operand 0 "" ""))
- (pc)))]
+ [(match_operand 0 "" "")]
""
- "operands[1] = s390_compare_op0; operands[2] = s390_compare_op1;")
+ "s390_emit_jump (operands[0],
+ s390_emit_compare (GE, s390_compare_op0, s390_compare_op1)); DONE;")
(define_expand "bgeu"
- [(set (reg:CCU 33) (compare:CCU (match_dup 1) (match_dup 2)))
- (set (pc)
- (if_then_else (geu (reg:CCU 33) (const_int 0))
- (label_ref (match_operand 0 "" ""))
- (pc)))]
+ [(match_operand 0 "" "")]
""
- "operands[1] = s390_compare_op0; operands[2] = s390_compare_op1;")
+ "s390_emit_jump (operands[0],
+ s390_emit_compare (GEU, s390_compare_op0, s390_compare_op1)); DONE;")
(define_expand "ble"
- [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
- (set (pc)
- (if_then_else (le (reg:CCS 33) (const_int 0))
- (label_ref (match_operand 0 "" ""))
- (pc)))]
+ [(match_operand 0 "" "")]
""
- "operands[1] = s390_compare_op0; operands[2] = s390_compare_op1;")
+ "s390_emit_jump (operands[0],
+ s390_emit_compare (LE, s390_compare_op0, s390_compare_op1)); DONE;")
(define_expand "bleu"
- [(set (reg:CCU 33) (compare:CCU (match_dup 1) (match_dup 2)))
- (set (pc)
- (if_then_else (leu (reg:CCU 33) (const_int 0))
- (label_ref (match_operand 0 "" ""))
- (pc)))]
+ [(match_operand 0 "" "")]
""
- "operands[1] = s390_compare_op0; operands[2] = s390_compare_op1;")
+ "s390_emit_jump (operands[0],
+ s390_emit_compare (LEU, s390_compare_op0, s390_compare_op1)); DONE;")
(define_expand "bunordered"
- [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
- (set (pc)
- (if_then_else (unordered (reg:CCS 33) (const_int 0))
- (label_ref (match_operand 0 "" ""))
- (pc)))]
+ [(match_operand 0 "" "")]
""
- "operands[1] = s390_compare_op0; operands[2] = s390_compare_op1;")
+ "s390_emit_jump (operands[0],
+ s390_emit_compare (UNORDERED, s390_compare_op0, s390_compare_op1)); DONE;")
(define_expand "bordered"
- [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
- (set (pc)
- (if_then_else (ordered (reg:CCS 33) (const_int 0))
- (label_ref (match_operand 0 "" ""))
- (pc)))]
+ [(match_operand 0 "" "")]
""
- "operands[1] = s390_compare_op0; operands[2] = s390_compare_op1;")
+ "s390_emit_jump (operands[0],
+ s390_emit_compare (ORDERED, s390_compare_op0, s390_compare_op1)); DONE;")
(define_expand "buneq"
- [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
- (set (pc)
- (if_then_else (uneq (reg:CCS 33) (const_int 0))
- (label_ref (match_operand 0 "" ""))
- (pc)))]
- ""
- "operands[1] = s390_compare_op0; operands[2] = s390_compare_op1;")
-
-(define_expand "bungt"
- [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
- (set (pc)
- (if_then_else (ungt (reg:CCS 33) (const_int 0))
- (label_ref (match_operand 0 "" ""))
- (pc)))]
+ [(match_operand 0 "" "")]
""
- "operands[1] = s390_compare_op0; operands[2] = s390_compare_op1;")
+ "s390_emit_jump (operands[0],
+ s390_emit_compare (UNEQ, s390_compare_op0, s390_compare_op1)); DONE;")
(define_expand "bunlt"
- [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
- (set (pc)
- (if_then_else (unlt (reg:CCS 33) (const_int 0))
- (label_ref (match_operand 0 "" ""))
- (pc)))]
+ [(match_operand 0 "" "")]
""
- "operands[1] = s390_compare_op0; operands[2] = s390_compare_op1;")
+ "s390_emit_jump (operands[0],
+ s390_emit_compare (UNLT, s390_compare_op0, s390_compare_op1)); DONE;")
-(define_expand "bunge"
- [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
- (set (pc)
- (if_then_else (unge (reg:CCS 33) (const_int 0))
- (label_ref (match_operand 0 "" ""))
- (pc)))]
+(define_expand "bungt"
+ [(match_operand 0 "" "")]
""
- "operands[1] = s390_compare_op0; operands[2] = s390_compare_op1;")
+ "s390_emit_jump (operands[0],
+ s390_emit_compare (UNGT, s390_compare_op0, s390_compare_op1)); DONE;")
(define_expand "bunle"
- [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
- (set (pc)
- (if_then_else (unle (reg:CCS 33) (const_int 0))
- (label_ref (match_operand 0 "" ""))
- (pc)))]
+ [(match_operand 0 "" "")]
+ ""
+ "s390_emit_jump (operands[0],
+ s390_emit_compare (UNLE, s390_compare_op0, s390_compare_op1)); DONE;")
+
+(define_expand "bunge"
+ [(match_operand 0 "" "")]
""
- "operands[1] = s390_compare_op0; operands[2] = s390_compare_op1;")
+ "s390_emit_jump (operands[0],
+ s390_emit_compare (UNGE, s390_compare_op0, s390_compare_op1)); DONE;")
(define_expand "bltgt"
- [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
- (set (pc)
- (if_then_else (ltgt (reg:CCS 33) (const_int 0))
- (label_ref (match_operand 0 "" ""))
- (pc)))]
+ [(match_operand 0 "" "")]
""
- "operands[1] = s390_compare_op0; operands[2] = s390_compare_op1;")
+ "s390_emit_jump (operands[0],
+ s390_emit_compare (LTGT, s390_compare_op0, s390_compare_op1)); DONE;")
;;
;;- Conditional jump instructions.
;;
-(define_insn "cjump"
- [(set (pc)
- (if_then_else
- (match_operator 1 "comparison_operator" [(reg 33) (const_int 0)])
- (label_ref (match_operand 0 "" ""))
- (pc)))]
- ""
+(define_insn "*cjump_64"
+ [(set (pc)
+ (if_then_else
+ (match_operator 1 "comparison_operator" [(reg 33) (const_int 0)])
+ (label_ref (match_operand 0 "" ""))
+ (pc)))]
+ "TARGET_CPU_ZARCH"
{
if (get_attr_length (insn) == 4)
return "j%C1\t%l0";
- else if (TARGET_CPU_ZARCH)
+ else
return "jg%C1\t%l0";
+}
+ [(set_attr "op_type" "RI")
+ (set_attr "type" "branch")
+ (set (attr "length")
+ (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
+ (const_int 4) (const_int 6)))])
+
+(define_insn "*cjump_31"
+ [(set (pc)
+ (if_then_else
+ (match_operator 1 "comparison_operator" [(reg 33) (const_int 0)])
+ (label_ref (match_operand 0 "" ""))
+ (pc)))]
+ "!TARGET_CPU_ZARCH"
+{
+ if (get_attr_length (insn) == 4)
+ return "j%C1\t%l0";
else
abort ();
}
[(set_attr "op_type" "RI")
(set_attr "type" "branch")
(set (attr "length")
- (cond [(lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
- (const_int 4)
- (ne (symbol_ref "TARGET_CPU_ZARCH") (const_int 0))
- (const_int 6)
- (eq (symbol_ref "flag_pic") (const_int 0))
- (const_int 6)] (const_int 8)))])
+ (if_then_else (eq (symbol_ref "flag_pic") (const_int 0))
+ (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
+ (const_int 4) (const_int 6))
+ (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
+ (const_int 4) (const_int 8))))])
(define_insn "*cjump_long"
- [(set (pc)
- (if_then_else
- (match_operator 1 "comparison_operator" [(reg 33) (const_int 0)])
- (match_operand 0 "address_operand" "U")
- (pc)))]
+ [(set (pc)
+ (if_then_else
+ (match_operator 1 "comparison_operator" [(reg 33) (const_int 0)])
+ (match_operand 0 "address_operand" "U")
+ (pc)))]
""
{
if (get_attr_op_type (insn) == OP_TYPE_RR)
[(set (attr "op_type")
(if_then_else (match_operand 0 "register_operand" "")
(const_string "RR") (const_string "RX")))
- (set_attr "type" "branch")
+ (set_attr "type" "branch")
(set_attr "atype" "agen")])
;;- Negated conditional jump instructions.
;;
-(define_insn "icjump"
- [(set (pc)
- (if_then_else
- (match_operator 1 "comparison_operator" [(reg 33) (const_int 0)])
- (pc)
- (label_ref (match_operand 0 "" ""))))]
- ""
+(define_insn "*icjump_64"
+ [(set (pc)
+ (if_then_else
+ (match_operator 1 "comparison_operator" [(reg 33) (const_int 0)])
+ (pc)
+ (label_ref (match_operand 0 "" ""))))]
+ "TARGET_CPU_ZARCH"
{
if (get_attr_length (insn) == 4)
return "j%D1\t%l0";
- else if (TARGET_CPU_ZARCH)
+ else
return "jg%D1\t%l0";
+}
+ [(set_attr "op_type" "RI")
+ (set_attr "type" "branch")
+ (set (attr "length")
+ (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
+ (const_int 4) (const_int 6)))])
+
+(define_insn "*icjump_31"
+ [(set (pc)
+ (if_then_else
+ (match_operator 1 "comparison_operator" [(reg 33) (const_int 0)])
+ (pc)
+ (label_ref (match_operand 0 "" ""))))]
+ "!TARGET_CPU_ZARCH"
+{
+ if (get_attr_length (insn) == 4)
+ return "j%D1\t%l0";
else
abort ();
}
[(set_attr "op_type" "RI")
(set_attr "type" "branch")
(set (attr "length")
- (cond [(lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
- (const_int 4)
- (ne (symbol_ref "TARGET_CPU_ZARCH") (const_int 0))
- (const_int 6)
- (eq (symbol_ref "flag_pic") (const_int 0))
- (const_int 6)] (const_int 8)))])
+ (if_then_else (eq (symbol_ref "flag_pic") (const_int 0))
+ (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
+ (const_int 4) (const_int 6))
+ (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
+ (const_int 4) (const_int 8))))])
(define_insn "*icjump_long"
- [(set (pc)
- (if_then_else
- (match_operator 1 "comparison_operator" [(reg 33) (const_int 0)])
- (pc)
- (match_operand 0 "address_operand" "U")))]
+ [(set (pc)
+ (if_then_else
+ (match_operator 1 "comparison_operator" [(reg 33) (const_int 0)])
+ (pc)
+ (match_operand 0 "address_operand" "U")))]
""
{
if (get_attr_op_type (insn) == OP_TYPE_RR)
[(trap_if (const_int 1) (const_int 0))]
""
"j\t.+2"
- [(set_attr "op_type" "RX")
+ [(set_attr "op_type" "RI")
(set_attr "type" "branch")])
(define_expand "conditional_trap"
- [(set (match_dup 2) (match_dup 3))
- (trap_if (match_operator 0 "comparison_operator"
- [(match_dup 2) (const_int 0)])
- (match_operand:SI 1 "general_operand" ""))]
+ [(trap_if (match_operand 0 "comparison_operator" "")
+ (match_operand 1 "general_operand" ""))]
""
{
- enum machine_mode ccmode;
-
- if (operands[1] != const0_rtx) FAIL;
-
- ccmode = s390_select_ccmode (GET_CODE (operands[0]),
- s390_compare_op0, s390_compare_op1);
- operands[2] = gen_rtx_REG (ccmode, 33);
- operands[3] = gen_rtx_COMPARE (ccmode, s390_compare_op0, s390_compare_op1);
+ if (operands[1] != const0_rtx) FAIL;
+ operands[0] = s390_emit_compare (GET_CODE (operands[0]),
+ s390_compare_op0, s390_compare_op1);
})
(define_insn "*trap"
(use (match_operand 4 "" ""))] ; label
""
{
- if (GET_MODE (operands[0]) == SImode)
- emit_jump_insn (gen_doloop_si (operands[4], operands[0], operands[0]));
+ if (GET_MODE (operands[0]) == SImode && !TARGET_CPU_ZARCH)
+ emit_jump_insn (gen_doloop_si31 (operands[4], operands[0], operands[0]));
+ else if (GET_MODE (operands[0]) == SImode && TARGET_CPU_ZARCH)
+ emit_jump_insn (gen_doloop_si64 (operands[4], operands[0], operands[0]));
else if (GET_MODE (operands[0]) == DImode && TARGET_64BIT)
emit_jump_insn (gen_doloop_di (operands[4], operands[0], operands[0]));
else
DONE;
})
-(define_insn "doloop_si"
+(define_insn_and_split "doloop_si64"
[(set (pc)
(if_then_else
(ne (match_operand:SI 1 "register_operand" "d,d")
(const_int 1))
(label_ref (match_operand 0 "" ""))
(pc)))
- (set (match_operand:SI 2 "register_operand" "=1,?*m*d")
+ (set (match_operand:SI 2 "nonimmediate_operand" "=1,?*m*d")
(plus:SI (match_dup 1) (const_int -1)))
(clobber (match_scratch:SI 3 "=X,&d"))
(clobber (reg:CC 33))]
- ""
+ "TARGET_CPU_ZARCH"
{
if (which_alternative != 0)
return "#";
else if (get_attr_length (insn) == 4)
return "brct\t%1,%l0";
- else if (TARGET_CPU_ZARCH)
+ else
return "ahi\t%1,-1\;jgne\t%l0";
+}
+ "&& reload_completed
+ && (! REG_P (operands[2])
+ || ! rtx_equal_p (operands[1], operands[2]))"
+ [(set (match_dup 3) (match_dup 1))
+ (parallel [(set (reg:CCAN 33)
+ (compare:CCAN (plus:SI (match_dup 3) (const_int -1))
+ (const_int 0)))
+ (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))])
+ (set (match_dup 2) (match_dup 3))
+ (set (pc) (if_then_else (ne (reg:CCAN 33) (const_int 0))
+ (label_ref (match_dup 0))
+ (pc)))]
+ ""
+ [(set_attr "op_type" "RI")
+ (set_attr "type" "branch")
+ (set (attr "length")
+ (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
+ (const_int 4) (const_int 10)))])
+
+(define_insn_and_split "doloop_si31"
+ [(set (pc)
+ (if_then_else
+ (ne (match_operand:SI 1 "register_operand" "d,d")
+ (const_int 1))
+ (label_ref (match_operand 0 "" ""))
+ (pc)))
+ (set (match_operand:SI 2 "nonimmediate_operand" "=1,?*m*d")
+ (plus:SI (match_dup 1) (const_int -1)))
+ (clobber (match_scratch:SI 3 "=X,&d"))
+ (clobber (reg:CC 33))]
+ "!TARGET_CPU_ZARCH"
+{
+ if (which_alternative != 0)
+ return "#";
+ else if (get_attr_length (insn) == 4)
+ return "brct\t%1,%l0";
else
abort ();
}
+ "&& reload_completed
+ && (! REG_P (operands[2])
+ || ! rtx_equal_p (operands[1], operands[2]))"
+ [(set (match_dup 3) (match_dup 1))
+ (parallel [(set (reg:CCAN 33)
+ (compare:CCAN (plus:SI (match_dup 3) (const_int -1))
+ (const_int 0)))
+ (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))])
+ (set (match_dup 2) (match_dup 3))
+ (set (pc) (if_then_else (ne (reg:CCAN 33) (const_int 0))
+ (label_ref (match_dup 0))
+ (pc)))]
+ ""
[(set_attr "op_type" "RI")
(set_attr "type" "branch")
(set (attr "length")
- (cond [(lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
- (const_int 4)
- (ne (symbol_ref "TARGET_CPU_ZARCH") (const_int 0))
- (const_int 10)
- (eq (symbol_ref "flag_pic") (const_int 0))
- (const_int 6)] (const_int 8)))])
+ (if_then_else (eq (symbol_ref "flag_pic") (const_int 0))
+ (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
+ (const_int 4) (const_int 6))
+ (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
+ (const_int 4) (const_int 8))))])
(define_insn "*doloop_si_long"
[(set (pc)
(plus:SI (match_dup 1) (const_int -1)))
(clobber (match_scratch:SI 3 "=X,&d"))
(clobber (reg:CC 33))]
- ""
+ "!TARGET_CPU_ZARCH"
{
if (get_attr_op_type (insn) == OP_TYPE_RR)
return "bctr\t%1,%0";
(set_attr "type" "branch")
(set_attr "atype" "agen")])
-(define_split
- [(set (pc)
- (if_then_else (ne (match_operand:SI 1 "register_operand" "")
- (const_int 1))
- (match_operand 0 "" "")
- (pc)))
- (set (match_operand:SI 2 "nonimmediate_operand" "")
- (plus:SI (match_dup 1) (const_int -1)))
- (clobber (match_scratch:SI 3 ""))
- (clobber (reg:CC 33))]
- "reload_completed
- && (! REG_P (operands[2])
- || ! rtx_equal_p (operands[1], operands[2]))"
- [(set (match_dup 3) (match_dup 1))
- (parallel [(set (reg:CCAN 33)
- (compare:CCAN (plus:SI (match_dup 3) (const_int -1))
- (const_int 0)))
- (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))])
- (set (match_dup 2) (match_dup 3))
- (set (pc) (if_then_else (ne (reg:CCAN 33) (const_int 0))
- (match_dup 0)
- (pc)))]
- "")
-
-(define_insn "doloop_di"
+(define_insn_and_split "doloop_di"
[(set (pc)
(if_then_else
(ne (match_operand:DI 1 "register_operand" "d,d")
(const_int 1))
(label_ref (match_operand 0 "" ""))
(pc)))
- (set (match_operand:DI 2 "register_operand" "=1,?*m*r")
+ (set (match_operand:DI 2 "nonimmediate_operand" "=1,?*m*r")
(plus:DI (match_dup 1) (const_int -1)))
(clobber (match_scratch:DI 3 "=X,&d"))
(clobber (reg:CC 33))]
else
return "aghi\t%1,-1\;jgne\t%l0";
}
- [(set_attr "op_type" "RI")
- (set_attr "type" "branch")
- (set (attr "length")
- (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
- (const_int 4) (const_int 10)))])
-
-(define_split
- [(set (pc)
- (if_then_else (ne (match_operand:DI 1 "register_operand" "")
- (const_int 1))
- (match_operand 0 "" "")
- (pc)))
- (set (match_operand:DI 2 "nonimmediate_operand" "")
- (plus:DI (match_dup 1) (const_int -1)))
- (clobber (match_scratch:DI 3 ""))
- (clobber (reg:CC 33))]
- "reload_completed
+ "&& reload_completed
&& (! REG_P (operands[2])
|| ! rtx_equal_p (operands[1], operands[2]))"
[(set (match_dup 3) (match_dup 1))
(set (match_dup 3) (plus:DI (match_dup 3) (const_int -1)))])
(set (match_dup 2) (match_dup 3))
(set (pc) (if_then_else (ne (reg:CCAN 33) (const_int 0))
- (match_dup 0)
+ (label_ref (match_dup 0))
(pc)))]
- "")
+ ""
+ [(set_attr "op_type" "RI")
+ (set_attr "type" "branch")
+ (set (attr "length")
+ (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
+ (const_int 4) (const_int 10)))])
;;
;;- Unconditional jump instructions.
; jump instruction pattern(s).
;
-(define_insn "jump"
- [(set (pc) (label_ref (match_operand 0 "" "")))]
+(define_expand "jump"
+ [(match_operand 0 "" "")]
""
+ "s390_emit_jump (operands[0], NULL_RTX); DONE;")
+
+(define_insn "*jump64"
+ [(set (pc) (label_ref (match_operand 0 "" "")))]
+ "TARGET_CPU_ZARCH"
{
if (get_attr_length (insn) == 4)
return "j\t%l0";
- else if (TARGET_CPU_ZARCH)
+ else
return "jg\t%l0";
+}
+ [(set_attr "op_type" "RI")
+ (set_attr "type" "branch")
+ (set (attr "length")
+ (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
+ (const_int 4) (const_int 6)))])
+
+(define_insn "*jump31"
+ [(set (pc) (label_ref (match_operand 0 "" "")))]
+ "!TARGET_CPU_ZARCH"
+{
+ if (get_attr_length (insn) == 4)
+ return "j\t%l0";
else
abort ();
}
[(set_attr "op_type" "RI")
(set_attr "type" "branch")
(set (attr "length")
- (cond [(lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
- (const_int 4)
- (ne (symbol_ref "TARGET_CPU_ZARCH") (const_int 0))
- (const_int 6)
- (eq (symbol_ref "flag_pic") (const_int 0))
- (const_int 6)] (const_int 8)))])
+ (if_then_else (eq (symbol_ref "flag_pic") (const_int 0))
+ (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
+ (const_int 4) (const_int 6))
+ (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
+ (const_int 4) (const_int 8))))])
;
; indirect-jump instruction pattern(s).
emit_move_insn (base, gen_rtx_LABEL_REF (Pmode, operands[3]));
- index = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, base, index));
+ index = gen_const_mem (Pmode, gen_rtx_PLUS (Pmode, base, index));
emit_move_insn (target, index);
if (flag_pic)
[(set_attr "type" "none")
(set_attr "length" "0")])
-
-
;
-; call instruction pattern(s).
+; sibcall patterns
;
-(define_expand "call"
+(define_expand "sibcall"
[(call (match_operand 0 "" "")
- (match_operand 1 "" ""))
- (use (match_operand 2 "" ""))]
+ (match_operand 1 "" ""))]
""
{
- bool plt_call = false;
- rtx insn;
-
- /* Direct function calls need special treatment. */
- if (GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF)
- {
- rtx sym = XEXP (operands[0], 0);
+ s390_emit_call (XEXP (operands[0], 0), NULL_RTX, NULL_RTX, NULL_RTX);
+ DONE;
+})
- /* When calling a global routine in PIC mode, we must
- replace the symbol itself with the PLT stub. */
- if (flag_pic && !SYMBOL_REF_LOCAL_P (sym))
- {
- sym = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, sym), UNSPEC_PLT);
- sym = gen_rtx_CONST (Pmode, sym);
- plt_call = true;
- }
+(define_insn "*sibcall_br"
+ [(call (mem:QI (reg 1))
+ (match_operand 0 "const_int_operand" "n"))]
+ "SIBLING_CALL_P (insn)
+ && GET_MODE (XEXP (XEXP (PATTERN (insn), 0), 0)) == Pmode"
+ "br\t%%r1"
+ [(set_attr "op_type" "RR")
+ (set_attr "type" "branch")
+ (set_attr "atype" "agen")])
- /* Unless we can use the bras(l) insn, force the
- routine address into a register. */
- if (!TARGET_SMALL_EXEC && !TARGET_CPU_ZARCH)
- {
- if (flag_pic)
- sym = legitimize_pic_address (sym, 0);
- else
- sym = force_reg (Pmode, sym);
- }
+(define_insn "*sibcall_brc"
+ [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
+ (match_operand 1 "const_int_operand" "n"))]
+ "SIBLING_CALL_P (insn) && TARGET_SMALL_EXEC"
+ "j\t%0"
+ [(set_attr "op_type" "RI")
+ (set_attr "type" "branch")])
- operands[0] = gen_rtx_MEM (QImode, sym);
- }
+(define_insn "*sibcall_brcl"
+ [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
+ (match_operand 1 "const_int_operand" "n"))]
+ "SIBLING_CALL_P (insn) && TARGET_CPU_ZARCH"
+ "jg\t%0"
+ [(set_attr "op_type" "RIL")
+ (set_attr "type" "branch")])
- /* Emit insn. */
- insn = emit_call_insn (gen_call_exp (operands[0], operands[1],
- gen_rtx_REG (Pmode, RETURN_REGNUM)));
+;
+; sibcall_value patterns
+;
- /* 31-bit PLT stubs use the GOT register implicitly. */
- if (!TARGET_64BIT && plt_call)
- use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx);
-
+(define_expand "sibcall_value"
+ [(set (match_operand 0 "" "")
+ (call (match_operand 1 "" "")
+ (match_operand 2 "" "")))]
+ ""
+{
+ s390_emit_call (XEXP (operands[1], 0), NULL_RTX, operands[0], NULL_RTX);
DONE;
})
-(define_expand "call_exp"
- [(parallel [(call (match_operand 0 "" "")
- (match_operand 1 "" ""))
- (clobber (match_operand 2 "" ""))])]
+(define_insn "*sibcall_value_br"
+ [(set (match_operand 0 "" "")
+ (call (mem:QI (reg 1))
+ (match_operand 1 "const_int_operand" "n")))]
+ "SIBLING_CALL_P (insn)
+ && GET_MODE (XEXP (XEXP (XEXP (PATTERN (insn), 1), 0), 0)) == Pmode"
+ "br\t%%r1"
+ [(set_attr "op_type" "RR")
+ (set_attr "type" "branch")
+ (set_attr "atype" "agen")])
+
+(define_insn "*sibcall_value_brc"
+ [(set (match_operand 0 "" "")
+ (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
+ (match_operand 2 "const_int_operand" "n")))]
+ "SIBLING_CALL_P (insn) && TARGET_SMALL_EXEC"
+ "j\t%1"
+ [(set_attr "op_type" "RI")
+ (set_attr "type" "branch")])
+
+(define_insn "*sibcall_value_brcl"
+ [(set (match_operand 0 "" "")
+ (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
+ (match_operand 2 "const_int_operand" "n")))]
+ "SIBLING_CALL_P (insn) && TARGET_CPU_ZARCH"
+ "jg\t%1"
+ [(set_attr "op_type" "RIL")
+ (set_attr "type" "branch")])
+
+
+;
+; call instruction pattern(s).
+;
+
+(define_expand "call"
+ [(call (match_operand 0 "" "")
+ (match_operand 1 "" ""))
+ (use (match_operand 2 "" ""))]
""
- "")
+{
+ s390_emit_call (XEXP (operands[0], 0), NULL_RTX, NULL_RTX,
+ gen_rtx_REG (Pmode, RETURN_REGNUM));
+ DONE;
+})
(define_insn "*bras"
[(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
(match_operand 1 "const_int_operand" "n"))
(clobber (match_operand 2 "register_operand" "=r"))]
- "TARGET_SMALL_EXEC && GET_MODE (operands[2]) == Pmode"
+ "!SIBLING_CALL_P (insn)
+ && TARGET_SMALL_EXEC
+ && GET_MODE (operands[2]) == Pmode"
"bras\t%2,%0"
[(set_attr "op_type" "RI")
(set_attr "type" "jsr")])
[(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
(match_operand 1 "const_int_operand" "n"))
(clobber (match_operand 2 "register_operand" "=r"))]
- "TARGET_CPU_ZARCH && GET_MODE (operands[2]) == Pmode"
+ "!SIBLING_CALL_P (insn)
+ && TARGET_CPU_ZARCH
+ && GET_MODE (operands[2]) == Pmode"
"brasl\t%2,%0"
[(set_attr "op_type" "RIL")
(set_attr "type" "jsr")])
[(call (mem:QI (match_operand 0 "address_operand" "U"))
(match_operand 1 "const_int_operand" "n"))
(clobber (match_operand 2 "register_operand" "=r"))]
- "GET_MODE (operands[2]) == Pmode"
+ "!SIBLING_CALL_P (insn) && GET_MODE (operands[2]) == Pmode"
{
if (get_attr_op_type (insn) == OP_TYPE_RR)
return "basr\t%2,%0";
(use (match_operand 3 "" ""))]
""
{
- bool plt_call = false;
- rtx insn;
-
- /* Direct function calls need special treatment. */
- if (GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF)
- {
- rtx sym = XEXP (operands[1], 0);
-
- /* When calling a global routine in PIC mode, we must
- replace the symbol itself with the PLT stub. */
- if (flag_pic && !SYMBOL_REF_LOCAL_P (sym))
- {
- sym = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, sym), UNSPEC_PLT);
- sym = gen_rtx_CONST (Pmode, sym);
- plt_call = true;
- }
-
- /* Unless we can use the bras(l) insn, force the
- routine address into a register. */
- if (!TARGET_SMALL_EXEC && !TARGET_CPU_ZARCH)
- {
- if (flag_pic)
- sym = legitimize_pic_address (sym, 0);
- else
- sym = force_reg (Pmode, sym);
- }
-
- operands[1] = gen_rtx_MEM (QImode, sym);
- }
-
- /* Emit insn. */
- insn = emit_call_insn (
- gen_call_value_exp (operands[0], operands[1], operands[2],
- gen_rtx_REG (Pmode, RETURN_REGNUM)));
-
- /* 31-bit PLT stubs use the GOT register implicitly. */
- if (!TARGET_64BIT && plt_call)
- use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx);
-
+ s390_emit_call (XEXP (operands[1], 0), NULL_RTX, operands[0],
+ gen_rtx_REG (Pmode, RETURN_REGNUM));
DONE;
})
-(define_expand "call_value_exp"
- [(parallel [(set (match_operand 0 "" "")
- (call (match_operand 1 "" "")
- (match_operand 2 "" "")))
- (clobber (match_operand 3 "" ""))])]
- ""
- "")
-
(define_insn "*bras_r"
[(set (match_operand 0 "" "")
(call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
(match_operand:SI 2 "const_int_operand" "n")))
(clobber (match_operand 3 "register_operand" "=r"))]
- "TARGET_SMALL_EXEC && GET_MODE (operands[3]) == Pmode"
+ "!SIBLING_CALL_P (insn)
+ && TARGET_SMALL_EXEC
+ && GET_MODE (operands[3]) == Pmode"
"bras\t%3,%1"
[(set_attr "op_type" "RI")
(set_attr "type" "jsr")])
(call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
(match_operand 2 "const_int_operand" "n")))
(clobber (match_operand 3 "register_operand" "=r"))]
- "TARGET_CPU_ZARCH && GET_MODE (operands[3]) == Pmode"
+ "!SIBLING_CALL_P (insn)
+ && TARGET_CPU_ZARCH
+ && GET_MODE (operands[3]) == Pmode"
"brasl\t%3,%1"
[(set_attr "op_type" "RIL")
(set_attr "type" "jsr")])
(call (mem:QI (match_operand 1 "address_operand" "U"))
(match_operand 2 "const_int_operand" "n")))
(clobber (match_operand 3 "register_operand" "=r"))]
- "GET_MODE (operands[3]) == Pmode"
+ "!SIBLING_CALL_P (insn) && GET_MODE (operands[3]) == Pmode"
{
if (get_attr_op_type (insn) == OP_TYPE_RR)
return "basr\t%3,%1";
ly\t%0,%1%J2"
[(set_attr "op_type" "RX,RXY")])
-(define_expand "call_value_tls"
- [(set (match_operand 0 "" "")
- (call (const_int 0) (const_int 0)))
- (use (match_operand 1 "" ""))]
- ""
-{
- rtx insn, sym;
-
- if (!flag_pic)
- abort ();
-
- sym = s390_tls_get_offset ();
- sym = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, sym), UNSPEC_PLT);
- sym = gen_rtx_CONST (Pmode, sym);
-
- /* Unless we can use the bras(l) insn, force the
- routine address into a register. */
- if (!TARGET_SMALL_EXEC && !TARGET_CPU_ZARCH)
- {
- if (flag_pic)
- sym = legitimize_pic_address (sym, 0);
- else
- sym = force_reg (Pmode, sym);
- }
-
- sym = gen_rtx_MEM (QImode, sym);
-
- /* Emit insn. */
- insn = emit_call_insn (
- gen_call_value_tls_exp (operands[0], sym, const0_rtx,
- gen_rtx_REG (Pmode, RETURN_REGNUM),
- operands[1]));
-
- /* The calling convention of __tls_get_offset uses the
- GOT register implicitly. */
- use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx);
- use_reg (&CALL_INSN_FUNCTION_USAGE (insn), operands[0]);
- CONST_OR_PURE_CALL_P (insn) = 1;
-
- DONE;
-})
-
-(define_expand "call_value_tls_exp"
- [(parallel [(set (match_operand 0 "" "")
- (call (match_operand 1 "" "")
- (match_operand 2 "" "")))
- (clobber (match_operand 3 "" ""))
- (use (match_operand 4 "" ""))])]
- ""
- "")
-
(define_insn "*bras_tls"
[(set (match_operand 0 "" "")
(call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
(match_operand 2 "const_int_operand" "n")))
(clobber (match_operand 3 "register_operand" "=r"))
(use (match_operand 4 "" ""))]
- "TARGET_SMALL_EXEC && GET_MODE (operands[3]) == Pmode"
+ "!SIBLING_CALL_P (insn)
+ && TARGET_SMALL_EXEC
+ && GET_MODE (operands[3]) == Pmode"
"bras\t%3,%1%J4"
[(set_attr "op_type" "RI")
(set_attr "type" "jsr")])
(match_operand 2 "const_int_operand" "n")))
(clobber (match_operand 3 "register_operand" "=r"))
(use (match_operand 4 "" ""))]
- "TARGET_CPU_ZARCH && GET_MODE (operands[3]) == Pmode"
+ "!SIBLING_CALL_P (insn)
+ && TARGET_CPU_ZARCH
+ && GET_MODE (operands[3]) == Pmode"
"brasl\t%3,%1%J4"
[(set_attr "op_type" "RIL")
(set_attr "type" "jsr")])
(match_operand 2 "const_int_operand" "n")))
(clobber (match_operand 3 "register_operand" "=r"))
(use (match_operand 4 "" ""))]
- "GET_MODE (operands[3]) == Pmode"
+ "!SIBLING_CALL_P (insn) && GET_MODE (operands[3]) == Pmode"
{
if (get_attr_op_type (insn) == OP_TYPE_RR)
return "basr\t%3,%1%J4";
;
(define_expand "allocate_stack"
- [(set (reg 15)
- (plus (reg 15) (match_operand 1 "general_operand" "")))
- (set (match_operand 0 "general_operand" "")
- (reg 15))]
- "TARGET_BACKCHAIN"
+ [(match_operand 0 "general_operand" "")
+ (match_operand 1 "general_operand" "")]
+ "TARGET_BACKCHAIN || TARGET_KERNEL_BACKCHAIN"
{
- rtx stack = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
- rtx chain = gen_rtx_MEM (Pmode, stack);
- rtx temp = gen_reg_rtx (Pmode);
-
- emit_move_insn (temp, chain);
-
- if (TARGET_64BIT)
- emit_insn (gen_adddi3 (stack, stack, negate_rtx (Pmode, operands[1])));
- else
- emit_insn (gen_addsi3 (stack, stack, negate_rtx (Pmode, operands[1])));
+ rtx temp = gen_reg_rtx (Pmode);
- emit_move_insn (chain, temp);
+ emit_move_insn (temp, s390_back_chain_rtx ());
+ anti_adjust_stack (operands[1]);
+ emit_move_insn (s390_back_chain_rtx (), temp);
- emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
- DONE;
+ emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
+ DONE;
})
[(match_operand 0 "" "")]
"flag_pic"
{
- s390_load_got (false);
+ emit_insn (s390_load_got ());
emit_insn (gen_rtx_USE (VOIDmode, pic_offset_table_rtx));
DONE;
})
"DONE;")
(define_expand "restore_stack_block"
- [(use (match_operand 0 "register_operand" ""))
- (set (match_dup 2) (match_dup 3))
- (set (match_dup 0) (match_operand 1 "register_operand" ""))
- (set (match_dup 3) (match_dup 2))]
- ""
+ [(match_operand 0 "register_operand" "")
+ (match_operand 1 "register_operand" "")]
+ "TARGET_BACKCHAIN || TARGET_KERNEL_BACKCHAIN"
{
- operands[2] = gen_reg_rtx (Pmode);
- operands[3] = gen_rtx_MEM (Pmode, operands[0]);
+ rtx temp = gen_reg_rtx (Pmode);
+
+ emit_move_insn (temp, s390_back_chain_rtx ());
+ emit_move_insn (operands[0], operands[1]);
+ emit_move_insn (s390_back_chain_rtx (), temp);
+
+ DONE;
})
(define_expand "save_stack_nonlocal"
(match_operand 1 "register_operand" "")]
""
{
- rtx temp = gen_reg_rtx (Pmode);
+ enum machine_mode mode = TARGET_64BIT ? OImode : TImode;
+ rtx base = gen_rtx_REG (Pmode, BASE_REGNUM);
+
+ /* Copy the backchain to the first word, sp to the second and the
+ literal pool base to the third. */
+
+ if (TARGET_BACKCHAIN || TARGET_KERNEL_BACKCHAIN)
+ {
+ rtx temp = force_reg (Pmode, s390_back_chain_rtx ());
+ emit_move_insn (operand_subword (operands[0], 0, 0, mode), temp);
+ }
+
+ emit_move_insn (operand_subword (operands[0], 1, 0, mode), operands[1]);
+ emit_move_insn (operand_subword (operands[0], 2, 0, mode), base);
- /* Copy the backchain to the first word, sp to the second and the literal pool
- base to the third. */
- emit_move_insn (operand_subword (operands[0], 2, 0,
- TARGET_64BIT ? OImode : TImode),
- gen_rtx_REG (Pmode, BASE_REGISTER));
- emit_move_insn (temp, gen_rtx_MEM (Pmode, operands[1]));
- emit_move_insn (operand_subword (operands[0], 0, 0,
- TARGET_64BIT ? OImode : TImode),
- temp);
- emit_move_insn (operand_subword (operands[0], 1, 0,
- TARGET_64BIT ? OImode : TImode),
- operands[1]);
DONE;
})
(match_operand 1 "memory_operand" "")]
""
{
- rtx temp = gen_reg_rtx (Pmode);
- rtx base = gen_rtx_REG (Pmode, BASE_REGISTER);
+ enum machine_mode mode = TARGET_64BIT ? OImode : TImode;
+ rtx base = gen_rtx_REG (Pmode, BASE_REGNUM);
+ rtx temp = NULL_RTX;
/* Restore the backchain from the first word, sp from the second and the
literal pool base from the third. */
- emit_move_insn (temp,
- operand_subword (operands[1], 0, 0,
- TARGET_64BIT ? OImode : TImode));
- emit_move_insn (operands[0],
- operand_subword (operands[1], 1, 0,
- TARGET_64BIT ? OImode : TImode));
- emit_move_insn (gen_rtx_MEM (Pmode, operands[0]), temp);
- emit_move_insn (base,
- operand_subword (operands[1], 2, 0,
- TARGET_64BIT ? OImode : TImode));
- emit_insn (gen_rtx_USE (VOIDmode, base));
+ if (TARGET_BACKCHAIN || TARGET_KERNEL_BACKCHAIN)
+ temp = force_reg (Pmode, operand_subword (operands[1], 0, 0, mode));
+
+ emit_move_insn (base, operand_subword (operands[1], 2, 0, mode));
+ emit_move_insn (operands[0], operand_subword (operands[1], 1, 0, mode));
+
+ if (temp)
+ emit_move_insn (s390_back_chain_rtx (), temp);
+
+ emit_insn (gen_rtx_USE (VOIDmode, base));
DONE;
})
{
enum machine_mode mode = GET_MODE (PATTERN (insn));
unsigned int align = GET_MODE_BITSIZE (mode);
- s390_output_pool_entry (asm_out_file, operands[0], mode, align);
+ s390_output_pool_entry (operands[0], mode, align);
return "";
}
[(set_attr "op_type" "NN")
- (set (attr "length")
+ (set (attr "length")
(symbol_ref "GET_MODE_SIZE (GET_MODE (PATTERN (insn)))"))])
(define_insn "pool_start_31"
(set_attr "type" "larl")])
(define_insn "main_pool"
- [(unspec_volatile [(const_int 0)] UNSPECV_MAIN_POOL)]
- ""
+ [(set (match_operand 0 "register_operand" "=a")
+ (unspec_volatile [(const_int 0)] UNSPECV_MAIN_POOL))]
+ "GET_MODE (operands[0]) == Pmode"
"* abort ();"
- [(set_attr "op_type" "NN")])
+ [(set_attr "op_type" "NN")
+ (set (attr "type")
+ (if_then_else (ne (symbol_ref "TARGET_CPU_ZARCH") (const_int 0))
+ (const_string "larl") (const_string "la")))])
(define_insn "reload_base_31"
[(set (match_operand 0 "register_operand" "=a")
""
"s390_emit_prologue (); DONE;")
+(define_insn "prologue_tpf"
+ [(unspec_volatile [(const_int 0)] UNSPECV_TPF_PROLOGUE)
+ (clobber (reg:DI 1))]
+ "TARGET_TPF_PROFILING"
+ "bas\t%%r1,4064"
+ [(set_attr "type" "jsr")
+ (set_attr "op_type" "RX")])
+
(define_expand "epilogue"
[(use (const_int 1))]
""
- "s390_emit_epilogue (); DONE;")
+ "s390_emit_epilogue (false); DONE;")
+
+(define_insn "epilogue_tpf"
+ [(unspec_volatile [(const_int 0)] UNSPECV_TPF_EPILOGUE)
+ (clobber (reg:DI 1))]
+ "TARGET_TPF_PROFILING"
+ "bas\t%%r1,4070"
+ [(set_attr "type" "jsr")
+ (set_attr "op_type" "RX")])
+
+
+(define_expand "sibcall_epilogue"
+ [(use (const_int 0))]
+ ""
+ "s390_emit_epilogue (true); DONE;")
(define_insn "*return"
[(return)
GEN_INT (0x7fffffff)));
DONE;
})
+
+;; Instruction definition to expand eh_return macro to support
+;; swapping in special linkage return addresses.
+
+(define_expand "eh_return"
+ [(use (match_operand 0 "register_operand" ""))]
+ "TARGET_TPF"
+{
+ s390_emit_tpf_eh_return (operands[0]);
+ DONE;
+})
+
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