;;- Machine description for GNU compiler -- S/390 / zSeries version.
-;; Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005
-;; Free Software Foundation, Inc.
+;; Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008,
+;; 2009 Free Software Foundation, Inc.
;; Contributed by Hartmut Penner (hpenner@de.ibm.com) and
-;; Ulrich Weigand (uweigand@de.ibm.com).
+;; Ulrich Weigand (uweigand@de.ibm.com) and
+;; Andreas Krebbel (Andreas.Krebbel@de.ibm.com)
;; This file is part of GCC.
;; GCC is free software; you can redistribute it and/or modify it under
;; the terms of the GNU General Public License as published by the Free
-;; Software Foundation; either version 2, or (at your option) any later
+;; Software Foundation; either version 3, or (at your option) any later
;; version.
;; GCC is distributed in the hope that it will be useful, but WITHOUT ANY
;; for more details.
;; You should have received a copy of the GNU General Public License
-;; along with GCC; see the file COPYING. If not, write to the Free
-;; Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
-;; 02110-1301, USA.
+;; along with GCC; see the file COPYING3. If not see
+;; <http://www.gnu.org/licenses/>.
;;
-;; Special constraints for s/390 machine description:
-;;
-;; a -- Any address register from 1 to 15.
-;; c -- Condition code register 33.
-;; d -- Any register from 0 to 15.
-;; f -- Floating point registers.
-;; t -- Access registers 36 and 37.
-;; G -- Const double zero operand
-;; I -- An 8-bit constant (0..255).
-;; J -- A 12-bit constant (0..4095).
-;; K -- A 16-bit constant (-32768..32767).
-;; L -- Value appropriate as displacement.
-;; (0..4095) for short displacement
-;; (-524288..524287) for long displacement
-;; M -- Constant integer with a value of 0x7fffffff.
-;; N -- Multiple letter constraint followed by 4 parameter letters.
-;; 0..9,x: number of the part counting from most to least significant
-;; H,Q: mode of the part
-;; D,S,H: mode of the containing operand
-;; 0,F: value of the other parts (F - all bits set)
-;;
-;; The constraint matches if the specified part of a constant
-;; has a value different from its other parts. If the letter x
-;; is specified instead of a part number, the constraint matches
-;; if there is any single part with non-default value.
-;; O -- Multiple letter constraint followed by 1 parameter.
-;; s: Signed extended immediate value (-2G .. 2G-1).
-;; p: Positive extended immediate value (0 .. 4G-1).
-;; n: Negative extended immediate value (-4G .. -1).
-;; These constraints do not accept any operand if the machine does
-;; not provide the extended-immediate facility.
-;; P -- Any integer constant that can be loaded without literal pool.
-;; Q -- Memory reference without index register and with short displacement.
-;; R -- Memory reference with index register and short displacement.
-;; S -- Memory reference without index register but with long displacement.
-;; T -- Memory reference with index register and long displacement.
-;; A -- Multiple letter constraint followed by Q, R, S, or T:
-;; Offsettable memory reference of type specified by second letter.
-;; B -- Multiple letter constraint followed by Q, R, S, or T:
-;; Memory reference of the type specified by second letter that
-;; does *not* refer to a literal pool entry.
-;; U -- Pointer with short displacement.
-;; W -- Pointer with long displacement.
-;; Y -- Shift count operand.
+;; See constraints.md for a description of constraints specific to s390.
;;
+
;; Special formats used for outputting 390 instructions.
;;
;; %C: print opcode suffix for branch condition.
;; %Y: print shift count operand.
;;
;; %b: print integer X as if it's an unsigned byte.
+;; %c: print integer X as if it's an signed byte.
;; %x: print integer X as if it's an unsigned halfword.
;; %h: print integer X as if it's a signed halfword.
;; %i: print the first nonzero HImode part of X.
(define_constants
[; Miscellaneous
(UNSPEC_ROUND 1)
- (UNSPEC_CMPINT 2)
+ (UNSPEC_CCU_TO_INT 2)
+ (UNSPEC_CCZ_TO_INT 3)
(UNSPEC_ICM 10)
+ (UNSPEC_TIE 11)
; GOT/PLT and lt-relative accesses
(UNSPEC_LTREL_OFFSET 100)
(UNSPEC_LTREL_BASE 101)
+ (UNSPEC_POOL_OFFSET 102)
(UNSPEC_GOTENT 110)
(UNSPEC_GOT 111)
(UNSPEC_GOTOFF 112)
(UNSPEC_INSN 213)
(UNSPEC_EXECUTE 214)
+ ; Atomic Support
+ (UNSPEC_MB 400)
+
; TLS relocation specifiers
(UNSPEC_TLSGD 500)
(UNSPEC_TLSLDM 501)
; String Functions
(UNSPEC_SRST 600)
(UNSPEC_MVST 601)
-
+
; Stack Smashing Protector
(UNSPEC_SP_SET 700)
(UNSPEC_SP_TEST 701)
+
+ ; Copy sign instructions
+ (UNSPEC_COPYSIGN 800)
+
+ ; Test Data Class (TDC)
+ (UNSPEC_TDC_INSN 900)
])
;;
(UNSPECV_SET_TP 500)
; Atomic Support
- (UNSPECV_MB 700)
- (UNSPECV_CAS 701)
+ (UNSPECV_CAS 700)
])
;;
;; Registers
;;
+; Registers with special meaning
+
(define_constants
[
; Sibling call register.
(TP_REGNUM 36)
])
+; Hardware register names
+
+(define_constants
+ [
+ ; General purpose registers
+ (GPR0_REGNUM 0)
+ ; Floating point registers.
+ (FPR0_REGNUM 16)
+ (FPR2_REGNUM 18)
+ ])
+
+;;
+;; PFPO GPR0 argument format
+;;
+
+(define_constants
+ [
+ ; PFPO operation type
+ (PFPO_CONVERT 0x1000000)
+ ; PFPO operand types
+ (PFPO_OP_TYPE_SF 0x5)
+ (PFPO_OP_TYPE_DF 0x6)
+ (PFPO_OP_TYPE_TF 0x7)
+ (PFPO_OP_TYPE_SD 0x8)
+ (PFPO_OP_TYPE_DD 0x9)
+ (PFPO_OP_TYPE_TD 0xa)
+ ; Bitposition of operand types
+ (PFPO_OP0_TYPE_SHIFT 16)
+ (PFPO_OP1_TYPE_SHIFT 8)
+ ])
+
;; Instruction operand type as used in the Principles of Operation.
;; Used to determine defaults for length and other attribute values.
(define_attr "op_type"
- "NN,E,RR,RRE,RX,RS,RSI,RI,SI,S,SS,SSE,RXE,RSE,RIL,RIE,RXY,RSY,SIY"
+ "NN,E,RR,RRE,RX,RS,RSI,RI,SI,S,SS,SSE,RXE,RSE,RIL,RIE,RXY,RSY,SIY,RRF,RRR,SIL,RRS,RIS"
(const_string "NN"))
;; Instruction type attribute used for scheduling.
(define_attr "type" "none,integer,load,lr,la,larl,lm,stm,
cs,vs,store,sem,idiv,
imulhi,imulsi,imuldi,
- branch,jsr,fsimpdf,fsimpsf,
- floaddf,floadsf,fstoredf,fstoresf,
- fmuldf,fmulsf,fdivdf,fdivsf,
- ftoi,itof,fsqrtdf,fsqrtsf,
- other"
+ branch,jsr,fsimptf,fsimpdf,fsimpsf,
+ floadtf,floaddf,floadsf,fstoredf,fstoresf,
+ fmultf,fmuldf,fmulsf,fdivtf,fdivdf,fdivsf,
+ ftoi,fsqrttf,fsqrtdf,fsqrtsf,
+ ftrunctf,ftruncdf, ftruncsd, ftruncdd,
+ itoftf, itofdf, itofsf, itofdd, itoftd,
+ fdivdd, fdivtd, floaddd, floadsd, fmuldd, fmultd,
+ fsimpdd, fsimpsd, fsimptd, fstoredd, fstoresd,
+ ftoidfp, other"
(cond [(eq_attr "op_type" "NN") (const_string "other")
(eq_attr "op_type" "SS") (const_string "cs")]
(const_string "integer")))
(const_string "reg")
(const_string "agen")))
+;; Properties concerning Z10 execution grouping and value forwarding.
+;; z10_super: instruction is superscalar.
+;; z10_super_c: instruction is superscalar and meets the condition of z10_c.
+;; z10_fwd: The instruction reads the value of an operand and stores it into a
+;; target register. It can forward this value to a second instruction that reads
+;; the same register if that second instruction is issued in the same group.
+;; z10_rec: The instruction is in the T pipeline and reads a register. If the
+;; instruction in the S pipe writes to the register, then the T instruction
+;; can immediately read the new value.
+;; z10_fr: union of Z10_fwd and z10_rec.
+;; z10_c: second operand of instruction is a register and read with complemented bits.
+;;
+;; An additional suffix A1, A3, or E1 indicates the respective AGI bypass.
+
+
+(define_attr "z10prop" "none,
+ z10_super, z10_super_E1, z10_super_A1, z10_super_c, z10_super_c_E1,
+ z10_fwd, z10_fwd_A1, z10_fwd_A3, z10_fwd_E1,
+ z10_rec,
+ z10_fr, z10_fr_A3, z10_fr_E1,
+ z10_c"
+ (const_string "none"))
+
+
;; Length in bytes.
(define_attr "length" ""
- (cond [(eq_attr "op_type" "E,RR") (const_int 2)
- (eq_attr "op_type" "RX,RI,RRE,RS,RSI,S,SI") (const_int 4)]
+ (cond [(eq_attr "op_type" "E,RR") (const_int 2)
+ (eq_attr "op_type" "RX,RI,RRE,RS,RSI,S,SI,RRF,RRR") (const_int 4)]
(const_int 6)))
;; distinguish between g5 and g6, but there are differences between the two
;; CPUs could in theory be modeled.
-(define_attr "cpu" "g5,g6,z900,z990,z9_109"
+(define_attr "cpu" "g5,g6,z900,z990,z9_109,z10"
(const (symbol_ref "s390_tune")))
+(define_attr "cpu_facility" "standard,ieee,zarch,longdisp,extimm,dfp,z10"
+ (const_string "standard"))
+
+(define_attr "enabled" ""
+ (cond [(eq_attr "cpu_facility" "standard")
+ (const_int 1)
+
+ (and (eq_attr "cpu_facility" "ieee")
+ (ne (symbol_ref "TARGET_CPU_IEEE_FLOAT") (const_int 0)))
+ (const_int 1)
+
+ (and (eq_attr "cpu_facility" "zarch")
+ (ne (symbol_ref "TARGET_ZARCH") (const_int 0)))
+ (const_int 1)
+
+ (and (eq_attr "cpu_facility" "longdisp")
+ (ne (symbol_ref "TARGET_LONG_DISPLACEMENT") (const_int 0)))
+ (const_int 1)
+
+ (and (eq_attr "cpu_facility" "extimm")
+ (ne (symbol_ref "TARGET_EXTIMM") (const_int 0)))
+ (const_int 1)
+
+ (and (eq_attr "cpu_facility" "dfp")
+ (ne (symbol_ref "TARGET_DFP") (const_int 0)))
+ (const_int 1)
+
+ (and (eq_attr "cpu_facility" "z10")
+ (ne (symbol_ref "TARGET_Z10") (const_int 0)))
+ (const_int 1)]
+ (const_int 0)))
+
;; Pipeline description for z900. For lack of anything better,
;; this description is also used for the g5 and g6.
(include "2064.md")
-;; Pipeline description for z990.
+;; Pipeline description for z990, z9-109 and z9-ec.
(include "2084.md")
+;; Pipeline description for z10
+(include "2097.md")
+
;; Predicates
(include "predicates.md")
+;; Constraint definitions
+(include "constraints.md")
+
;; Other includes
(include "tpf.md")
-;; Macros
+;; Iterators
-;; This mode macro allows DF and SF patterns to be generated from the
+;; These mode iterators allow floating point patterns to be generated from the
;; same template.
-(define_mode_macro FPR [DF SF])
-
-;; These mode macros allow 31-bit and 64-bit TDSI patterns to be generated
+(define_mode_iterator FP_ALL [TF DF SF (TD "TARGET_HARD_DFP") (DD "TARGET_HARD_DFP")
+ (SD "TARGET_HARD_DFP")])
+(define_mode_iterator FP [TF DF SF (TD "TARGET_HARD_DFP") (DD "TARGET_HARD_DFP")])
+(define_mode_iterator FPALL [TF DF SF TD DD SD])
+(define_mode_iterator BFP [TF DF SF])
+(define_mode_iterator DFP [TD DD])
+(define_mode_iterator DFP_ALL [TD DD SD])
+(define_mode_iterator DSF [DF SF])
+(define_mode_iterator SD_SF [SF SD])
+(define_mode_iterator DD_DF [DF DD])
+(define_mode_iterator TD_TF [TF TD])
+
+;; This mode iterator allows 31-bit and 64-bit TDSI patterns to be generated
;; from the same template.
-(define_mode_macro TDSI [(TI "TARGET_64BIT") DI SI])
+(define_mode_iterator TDSI [(TI "TARGET_64BIT") DI SI])
-;; These mode macros allow 31-bit and 64-bit GPR patterns to be generated
+;; These mode iterators allow 31-bit and 64-bit GPR patterns to be generated
;; from the same template.
-(define_mode_macro GPR [(DI "TARGET_64BIT") SI])
-(define_mode_macro DSI [DI SI])
+(define_mode_iterator GPR [(DI "TARGET_64BIT") SI])
+(define_mode_iterator DSI [DI SI])
-;; This mode macro allows :P to be used for patterns that operate on
+;; These mode iterators allow :P to be used for patterns that operate on
;; pointer-sized quantities. Exactly one of the two alternatives will match.
-(define_mode_macro DP [(TI "TARGET_64BIT") (DI "!TARGET_64BIT")])
-(define_mode_macro P [(DI "TARGET_64BIT") (SI "!TARGET_64BIT")])
+(define_mode_iterator DP [(TI "TARGET_64BIT") (DI "!TARGET_64BIT")])
+(define_mode_iterator P [(DI "TARGET_64BIT") (SI "!TARGET_64BIT")])
-;; This mode macro allows the QI and HI patterns to be defined from
+;; This mode iterator allows the QI and HI patterns to be defined from
;; the same template.
-(define_mode_macro HQI [HI QI])
+(define_mode_iterator HQI [HI QI])
-;; This mode macro allows the integer patterns to be defined from the
+;; This mode iterator allows the integer patterns to be defined from the
;; same template.
-(define_mode_macro INT [(DI "TARGET_64BIT") SI HI QI])
+(define_mode_iterator INT [(DI "TARGET_64BIT") SI HI QI])
+(define_mode_iterator INTALL [TI DI SI HI QI])
-;; This macro allows to unify all 'bCOND' expander patterns.
-(define_code_macro COMPARE [eq ne gt gtu lt ltu ge geu le leu unordered
+;; This iterator allows to unify all 'bCOND' expander patterns.
+(define_code_iterator COMPARE [eq ne gt gtu lt ltu ge geu le leu unordered
ordered uneq unlt ungt unle unge ltgt])
-;; This macro allows to unify all 'sCOND' patterns.
-(define_code_macro SCOND [ltu gtu leu geu])
+;; This iterator allows to unify all 'sCOND' patterns.
+(define_code_iterator SCOND [ltu gtu leu geu])
-;; This macro allows some 'ashift' and 'lshiftrt' pattern to be defined from
+;; This iterator allows some 'ashift' and 'lshiftrt' pattern to be defined from
;; the same template.
-(define_code_macro SHIFT [ashift lshiftrt])
+(define_code_iterator SHIFT [ashift lshiftrt])
-;; These macros allow to combine most atomic operations.
-(define_code_macro ATOMIC [and ior xor plus minus mult])
+;; This iterator and attribute allow to combine most atomic operations.
+(define_code_iterator ATOMIC [and ior xor plus minus mult])
(define_code_attr atomic [(and "and") (ior "ior") (xor "xor")
(plus "add") (minus "sub") (mult "nand")])
+;; In FP templates, a string like "lt<de>br" will expand to "ltxbr" in
+;; TF/TDmode, "ltdbr" in DF/DDmode, and "ltebr" in SF/SDmode.
+(define_mode_attr xde [(TF "x") (DF "d") (SF "e") (TD "x") (DD "d") (SD "e")])
+
+;; In FP templates, a <dee> in "m<dee><bt>r" will expand to "mx<bt>r" in
+;; TF/TDmode, "md<bt>r" in DF/DDmode, "mee<bt>r" in SFmode and "me<bt>r in
+;; SDmode.
+(define_mode_attr xdee [(TF "x") (DF "d") (SF "ee") (TD "x") (DD "d") (SD "e")])
+
+;; In FP templates, "<RRe>" will expand to "RRE" in TFmode and "RR" otherwise.
+;; Likewise for "<RXe>".
+(define_mode_attr RRe [(TF "RRE") (DF "RR") (SF "RR")])
+(define_mode_attr RXe [(TF "RXE") (DF "RX") (SF "RX")])
+
+;; The decimal floating point variants of add, sub, div and mul support 3
+;; fp register operands. The following attributes allow to merge the bfp and
+;; dfp variants in a single insn definition.
-;; In FPR templates, a string like "lt<de>br" will expand to "ltdbr" in DFmode
-;; and "ltebr" in SFmode.
-(define_mode_attr de [(DF "d") (SF "e")])
+;; This attribute is used to set op_type accordingly.
+(define_mode_attr RRer [(TF "RRE") (DF "RRE") (SF "RRE") (TD "RRR")
+ (DD "RRR") (SD "RRR")])
-;; In FPR templates, a string like "m<dee>br" will expand to "mdbr" in DFmode
-;; and "meebr" in SFmode. This is needed for the 'mul<mode>3' pattern.
-(define_mode_attr dee [(DF "d") (SF "ee")])
+;; This attribute is used in the operand constraint list in order to have the
+;; first and the second operand match for bfp modes.
+(define_mode_attr f0 [(TF "0") (DF "0") (SF "0") (TD "f") (DD "f") (DD "f")])
+
+;; This attribute is used in the operand list of the instruction to have an
+;; additional operand for the dfp instructions.
+(define_mode_attr op1 [(TF "") (DF "") (SF "")
+ (TD "%1,") (DD "%1,") (SD "%1,")])
+
+
+;; This attribute is used in the operand constraint list
+;; for instructions dealing with the sign bit of 32 or 64bit fp values.
+;; TFmode values are represented by a fp register pair. Since the
+;; sign bit instructions only handle single source and target fp registers
+;; these instructions can only be used for TFmode values if the source and
+;; target operand uses the same fp register.
+(define_mode_attr fT0 [(TF "0") (DF "f") (SF "f")])
+
+;; In FP templates, "<Rf>" will expand to "f" in TFmode and "R" otherwise.
+;; This is used to disable the memory alternative in TFmode patterns.
+(define_mode_attr Rf [(TF "f") (DF "R") (SF "R") (TD "f") (DD "f") (SD "f")])
+
+;; This attribute adds b for bfp instructions and t for dfp instructions and is used
+;; within instruction mnemonics.
+(define_mode_attr bt [(TF "b") (DF "b") (SF "b") (TD "t") (DD "t") (SD "t")])
+
+;; This attribute is used within instruction mnemonics. It evaluates to d for dfp
+;; modes and to an empty string for bfp modes.
+(define_mode_attr _d [(TF "") (DF "") (SF "") (TD "d") (DD "d") (SD "d")])
;; In GPR and P templates, a constraint like "<d0>" will expand to "d" in DImode
;; and "0" in SImode. This allows to combine instructions of which the 31bit
;; version only operates on one register. The DImode version needs an additional
;; register for the assembler output.
(define_mode_attr 1 [(DI "%1,") (SI "")])
-
-;; In SHIFT templates, a string like "s<lr>dl" will expand to "sldl" in
+
+;; In SHIFT templates, a string like "s<lr>dl" will expand to "sldl" in
;; 'ashift' and "srdl" in 'lshiftrt'.
(define_code_attr lr [(ashift "l") (lshiftrt "r")])
;; In SHIFT templates, this attribute holds the correct standard name for the
-;; pattern itself and the corresponding function calls.
+;; pattern itself and the corresponding function calls.
(define_code_attr shift [(ashift "ashl") (lshiftrt "lshr")])
;; This attribute handles differences in the instruction 'type' and will result
;; in "RRE" for DImode and "RR" for SImode.
(define_mode_attr E [(DI "E") (SI "")])
+;; This attribute handles differences in the instruction 'type' and makes RX<Y>
+;; to result in "RXY" for DImode and "RX" for SImode.
+(define_mode_attr Y [(DI "Y") (SI "")])
+
;; This attribute handles differences in the instruction 'type' and will result
;; in "RSE" for TImode and "RS" for DImode.
(define_mode_attr TE [(TI "E") (DI "")])
;; and "lcr" in SImode.
(define_mode_attr g [(DI "g") (SI "")])
+;; In GPR templates, a string like "sl<y>" will expand to "slg" in DImode
+;; and "sly" in SImode. This is useful because on 64bit the ..g instructions
+;; were enhanced with long displacements whereas 31bit instructions got a ..y
+;; variant for long displacements.
+(define_mode_attr y [(DI "g") (SI "y")])
+
;; In DP templates, a string like "cds<g>" will expand to "cdsg" in TImode
;; and "cds" in DImode.
(define_mode_attr tg [(TI "g") (DI "")])
;; in SImode.
(define_mode_attr DBL [(DI "TI") (SI "DI")])
+;; This attribute expands to DF for TFmode and to DD for TDmode . It is
+;; used for Txmode splitters splitting a Txmode copy into 2 Dxmode copies.
+(define_mode_attr HALF_TMODE [(TF "DF") (TD "DD")])
+
;; Maximum unsigned integer that fits in MODE.
(define_mode_attr max_uint [(HI "65535") (QI "255")])
-
;;
;;- Compare instructions.
;;
(define_expand "cmp<mode>"
[(set (reg:CC CC_REGNUM)
- (compare:CC (match_operand:FPR 0 "register_operand" "")
- (match_operand:FPR 1 "general_operand" "")))]
+ (compare:CC (match_operand:FP 0 "register_operand" "")
+ (match_operand:FP 1 "general_operand" "")))]
"TARGET_HARD_FLOAT"
{
s390_compare_op0 = operands[0];
"@
tm\t%S0,%b1
tmy\t%S0,%b1"
- [(set_attr "op_type" "SI,SIY")])
+ [(set_attr "op_type" "SI,SIY")
+ (set_attr "z10prop" "z10_super,z10_super")])
(define_insn "*tmdi_reg"
[(set (reg CC_REGNUM)
tmhl\t%0,%i1
tmlh\t%0,%i1
tmll\t%0,%i1"
- [(set_attr "op_type" "RI")])
+ [(set_attr "op_type" "RI")
+ (set_attr "z10prop" "z10_super,z10_super,z10_super,z10_super")])
(define_insn "*tmsi_reg"
[(set (reg CC_REGNUM)
"@
tmh\t%0,%i1
tml\t%0,%i1"
- [(set_attr "op_type" "RI")])
+ [(set_attr "op_type" "RI")
+ (set_attr "z10prop" "z10_super,z10_super")])
(define_insn "*tm<mode>_full"
[(set (reg CC_REGNUM)
(match_operand:HQI 1 "immediate_operand" "n")))]
"s390_match_ccmode (insn, s390_tm_ccmode (constm1_rtx, operands[1], true))"
"tml\t%0,<max_uint>"
- [(set_attr "op_type" "RI")])
+ [(set_attr "op_type" "RI")
+ (set_attr "z10prop" "z10_super")])
+;
; Load-and-Test instructions
+;
+
+; tst(di|si) instruction pattern(s).
(define_insn "*tstdi_sign"
[(set (reg CC_REGNUM)
- (compare (ashiftrt:DI (ashift:DI (subreg:DI (match_operand:SI 0 "register_operand" "d") 0)
- (const_int 32)) (const_int 32))
- (match_operand:DI 1 "const0_operand" "")))
- (set (match_operand:DI 2 "register_operand" "=d")
+ (compare
+ (ashiftrt:DI
+ (ashift:DI
+ (subreg:DI (match_operand:SI 0 "nonimmediate_operand" "d,RT") 0)
+ (const_int 32)) (const_int 32))
+ (match_operand:DI 1 "const0_operand" "")))
+ (set (match_operand:DI 2 "register_operand" "=d,d")
(sign_extend:DI (match_dup 0)))]
"s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
- "ltgfr\t%2,%0"
- [(set_attr "op_type" "RRE")])
-
-(define_insn "*tstdi_extimm"
+ "ltgfr\t%2,%0
+ ltgf\t%2,%0"
+ [(set_attr "op_type" "RRE,RXY")
+ (set_attr "cpu_facility" "*,z10")
+ (set_attr "z10prop" "z10_super_E1,z10_super_E1") ])
+
+; ltr, lt, ltgr, ltg
+(define_insn "*tst<mode>_extimm"
[(set (reg CC_REGNUM)
- (compare (match_operand:DI 0 "nonimmediate_operand" "d,m")
- (match_operand:DI 1 "const0_operand" "")))
- (set (match_operand:DI 2 "register_operand" "=d,d")
+ (compare (match_operand:GPR 0 "nonimmediate_operand" "d,RT")
+ (match_operand:GPR 1 "const0_operand" "")))
+ (set (match_operand:GPR 2 "register_operand" "=d,d")
(match_dup 0))]
- "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT && TARGET_EXTIMM"
+ "s390_match_ccmode(insn, CCSmode) && TARGET_EXTIMM"
"@
- ltgr\t%2,%0
- ltg\t%2,%0"
- [(set_attr "op_type" "RRE,RXY")])
+ lt<g>r\t%2,%0
+ lt<g>\t%2,%0"
+ [(set_attr "op_type" "RR<E>,RXY")
+ (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3") ])
-(define_insn "*tstdi_cconly_extimm"
+; ltr, lt, ltgr, ltg
+(define_insn "*tst<mode>_cconly_extimm"
[(set (reg CC_REGNUM)
- (compare (match_operand:DI 0 "nonimmediate_operand" "d,m")
- (match_operand:DI 1 "const0_operand" "")))
- (clobber (match_scratch:DI 2 "=X,d"))]
- "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT && TARGET_EXTIMM"
+ (compare (match_operand:GPR 0 "nonimmediate_operand" "d,RT")
+ (match_operand:GPR 1 "const0_operand" "")))
+ (clobber (match_scratch:GPR 2 "=X,d"))]
+ "s390_match_ccmode(insn, CCSmode) && TARGET_EXTIMM"
"@
- ltgr\t%0,%0
- ltg\t%2,%0"
- [(set_attr "op_type" "RRE,RXY")])
+ lt<g>r\t%0,%0
+ lt<g>\t%2,%0"
+ [(set_attr "op_type" "RR<E>,RXY")
+ (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3")])
(define_insn "*tstdi"
[(set (reg CC_REGNUM)
(match_dup 0))]
"s390_match_ccmode(insn, CCSmode) && TARGET_64BIT && !TARGET_EXTIMM"
"ltgr\t%2,%0"
- [(set_attr "op_type" "RRE")])
-
-(define_insn "*tstdi_cconly"
- [(set (reg CC_REGNUM)
- (compare (match_operand:DI 0 "register_operand" "d")
- (match_operand:DI 1 "const0_operand" "")))]
- "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
- "ltgr\t%0,%0"
- [(set_attr "op_type" "RRE")])
-
-(define_insn "*tstdi_cconly_31"
- [(set (reg CC_REGNUM)
- (compare (match_operand:DI 0 "register_operand" "d")
- (match_operand:DI 1 "const0_operand" "")))]
- "s390_match_ccmode(insn, CCSmode) && !TARGET_64BIT"
- "srda\t%0,0"
- [(set_attr "op_type" "RS")
- (set_attr "atype" "reg")])
-
-(define_insn "*tstsi_extimm"
- [(set (reg CC_REGNUM)
- (compare (match_operand:SI 0 "nonimmediate_operand" "d,m")
- (match_operand:SI 1 "const0_operand" "")))
- (set (match_operand:SI 2 "register_operand" "=d,d")
- (match_dup 0))]
- "s390_match_ccmode(insn, CCSmode) && TARGET_EXTIMM"
- "@
- ltr\t%2,%0
- lt\t%2,%0"
- [(set_attr "op_type" "RR,RXY")])
-
-(define_insn "*tstsi_cconly_extimm"
- [(set (reg CC_REGNUM)
- (compare (match_operand:SI 0 "nonimmediate_operand" "d,m")
- (match_operand:SI 1 "const0_operand" "")))
- (clobber (match_scratch:SI 2 "=X,d"))]
- "s390_match_ccmode(insn, CCSmode) && TARGET_EXTIMM"
- "@
- ltr\t%0,%0
- lt\t%2,%0"
- [(set_attr "op_type" "RR,RXY")])
+ [(set_attr "op_type" "RRE")
+ (set_attr "z10prop" "z10_fr_E1")])
(define_insn "*tstsi"
[(set (reg CC_REGNUM)
ltr\t%2,%0
icm\t%2,15,%S0
icmy\t%2,15,%S0"
- [(set_attr "op_type" "RR,RS,RSY")])
+ [(set_attr "op_type" "RR,RS,RSY")
+ (set_attr "z10prop" "z10_fr_E1,z10_super_E1,z10_super_E1")])
(define_insn "*tstsi_cconly"
[(set (reg CC_REGNUM)
ltr\t%0,%0
icm\t%2,15,%S0
icmy\t%2,15,%S0"
- [(set_attr "op_type" "RR,RS,RSY")])
+ [(set_attr "op_type" "RR,RS,RSY")
+ (set_attr "z10prop" "z10_fr_E1,z10_super_E1,z10_super_E1")])
+
+(define_insn "*tstdi_cconly_31"
+ [(set (reg CC_REGNUM)
+ (compare (match_operand:DI 0 "register_operand" "d")
+ (match_operand:DI 1 "const0_operand" "")))]
+ "s390_match_ccmode(insn, CCSmode) && !TARGET_64BIT"
+ "srda\t%0,0"
+ [(set_attr "op_type" "RS")
+ (set_attr "atype" "reg")])
-(define_insn "*tstsi_cconly2"
+; ltr, ltgr
+(define_insn "*tst<mode>_cconly2"
[(set (reg CC_REGNUM)
- (compare (match_operand:SI 0 "register_operand" "d")
- (match_operand:SI 1 "const0_operand" "")))]
+ (compare (match_operand:GPR 0 "register_operand" "d")
+ (match_operand:GPR 1 "const0_operand" "")))]
"s390_match_ccmode(insn, CCSmode)"
- "ltr\t%0,%0"
- [(set_attr "op_type" "RR")])
+ "lt<g>r\t%0,%0"
+ [(set_attr "op_type" "RR<E>")
+ (set_attr "z10prop" "z10_fr_E1")])
+
+; tst(hi|qi) instruction pattern(s).
(define_insn "*tst<mode>CCT"
[(set (reg CC_REGNUM)
icm\t%2,<icm_lo>,%S0
icmy\t%2,<icm_lo>,%S0
tml\t%0,<max_uint>"
- [(set_attr "op_type" "RS,RSY,RI")])
+ [(set_attr "op_type" "RS,RSY,RI")
+ (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super")])
(define_insn "*tsthiCCT_cconly"
[(set (reg CC_REGNUM)
icm\t%2,3,%S0
icmy\t%2,3,%S0
tml\t%0,65535"
- [(set_attr "op_type" "RS,RSY,RI")])
+ [(set_attr "op_type" "RS,RSY,RI")
+ (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super")])
(define_insn "*tstqiCCT_cconly"
[(set (reg CC_REGNUM)
cli\t%S0,0
cliy\t%S0,0
tml\t%0,255"
- [(set_attr "op_type" "SI,SIY,RI")])
+ [(set_attr "op_type" "SI,SIY,RI")
+ (set_attr "z10prop" "z10_super,z10_super,z10_super")])
(define_insn "*tst<mode>"
[(set (reg CC_REGNUM)
"@
icm\t%2,<icm_lo>,%S0
icmy\t%2,<icm_lo>,%S0"
- [(set_attr "op_type" "RS,RSY")])
+ [(set_attr "op_type" "RS,RSY")
+ (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
(define_insn "*tst<mode>_cconly"
[(set (reg CC_REGNUM)
"@
icm\t%2,<icm_lo>,%S0
icmy\t%2,<icm_lo>,%S0"
- [(set_attr "op_type" "RS,RSY")])
+ [(set_attr "op_type" "RS,RSY")
+ (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
; Compare (equality) instructions
(define_insn "*cmpdi_cct"
[(set (reg CC_REGNUM)
(compare (match_operand:DI 0 "nonimmediate_operand" "%d,d,d,d,Q")
- (match_operand:DI 1 "general_operand" "d,K,Os,m,BQ")))]
+ (match_operand:DI 1 "general_operand" "d,K,Os,RT,BQ")))]
"s390_match_ccmode (insn, CCTmode) && TARGET_64BIT"
"@
cgr\t%0,%1
cgfi\t%0,%1
cg\t%0,%1
#"
- [(set_attr "op_type" "RRE,RI,RIL,RXY,SS")])
+ [(set_attr "op_type" "RRE,RI,RIL,RXY,SS")
+ (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,*")])
(define_insn "*cmpsi_cct"
[(set (reg CC_REGNUM)
c\t%0,%1
cy\t%0,%1
#"
- [(set_attr "op_type" "RR,RI,RIL,RX,RXY,SS")])
-
+ [(set_attr "op_type" "RR,RI,RIL,RX,RXY,SS")
+ (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,*")])
; Compare (signed) instructions
(define_insn "*cmpdi_ccs_sign"
[(set (reg CC_REGNUM)
- (compare (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m"))
- (match_operand:DI 0 "register_operand" "d,d")))]
+ (compare (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand"
+ "d,RT,b"))
+ (match_operand:DI 0 "register_operand" "d, d,d")))]
"s390_match_ccmode(insn, CCSRmode) && TARGET_64BIT"
"@
cgfr\t%0,%1
- cgf\t%0,%1"
- [(set_attr "op_type" "RRE,RXY")])
+ cgf\t%0,%1
+ cgfrl\t%0,%1"
+ [(set_attr "op_type" "RRE,RXY,RIL")
+ (set_attr "z10prop" "z10_c,*,*")
+ (set_attr "type" "*,*,larl")])
+
-(define_insn "*cmpdi_ccs"
- [(set (reg CC_REGNUM)
- (compare (match_operand:DI 0 "register_operand" "d,d,d,d")
- (match_operand:DI 1 "general_operand" "d,K,Os,m")))]
- "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
- "@
- cgr\t%0,%1
- cghi\t%0,%h1
- cgfi\t%0,%1
- cg\t%0,%1"
- [(set_attr "op_type" "RRE,RI,RIL,RXY")])
(define_insn "*cmpsi_ccs_sign"
[(set (reg CC_REGNUM)
- (compare (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T"))
- (match_operand:SI 0 "register_operand" "d,d")))]
+ (compare (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T,b"))
+ (match_operand:SI 0 "register_operand" "d,d,d")))]
"s390_match_ccmode(insn, CCSRmode)"
"@
ch\t%0,%1
- chy\t%0,%1"
- [(set_attr "op_type" "RX,RXY")])
+ chy\t%0,%1
+ chrl\t%0,%1"
+ [(set_attr "op_type" "RX,RXY,RIL")
+ (set_attr "cpu_facility" "*,*,z10")
+ (set_attr "type" "*,*,larl")])
+
+(define_insn "*cmphi_ccs_z10"
+ [(set (reg CC_REGNUM)
+ (compare (match_operand:HI 0 "s_operand" "Q")
+ (match_operand:HI 1 "immediate_operand" "K")))]
+ "s390_match_ccmode(insn, CCSmode) && TARGET_Z10"
+ "chhsi\t%0,%1"
+ [(set_attr "op_type" "SIL")])
+
+(define_insn "*cmpdi_ccs_signhi_rl"
+ [(set (reg CC_REGNUM)
+ (compare (sign_extend:DI (match_operand:HI 1 "memory_operand" "RT,b"))
+ (match_operand:GPR 0 "register_operand" "d,d")))]
+ "s390_match_ccmode(insn, CCSRmode) && TARGET_Z10"
+ "@
+ cgh\t%0,%1
+ cghrl\t%0,%1"
+ [(set_attr "op_type" "RXY,RIL")
+ (set_attr "type" "*,larl")])
-(define_insn "*cmpsi_ccs"
+; cr, chi, cfi, c, cy, cgr, cghi, cgfi, cg, chsi, cghsi, crl, cgrl
+(define_insn "*cmp<mode>_ccs"
[(set (reg CC_REGNUM)
- (compare (match_operand:SI 0 "register_operand" "d,d,d,d,d")
- (match_operand:SI 1 "general_operand" "d,K,Os,R,T")))]
+ (compare (match_operand:GPR 0 "nonimmediate_operand"
+ "d,d,Q, d,d,d,d")
+ (match_operand:GPR 1 "general_operand"
+ "d,K,K,Os,R,T,b")))]
"s390_match_ccmode(insn, CCSmode)"
"@
- cr\t%0,%1
- chi\t%0,%h1
- cfi\t%0,%1
- c\t%0,%1
- cy\t%0,%1"
- [(set_attr "op_type" "RR,RI,RIL,RX,RXY")])
+ c<g>r\t%0,%1
+ c<g>hi\t%0,%h1
+ c<g>hsi\t%0,%h1
+ c<g>fi\t%0,%1
+ c<g>\t%0,%1
+ c<y>\t%0,%1
+ c<g>rl\t%0,%1"
+ [(set_attr "op_type" "RR<E>,RI,SIL,RIL,RX<Y>,RXY,RIL")
+ (set_attr "cpu_facility" "*,*,z10,extimm,*,*,z10")
+ (set_attr "type" "*,*,*,*,*,*,larl")
+ (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,z10_super,z10_super")])
; Compare (unsigned) instructions
+(define_insn "*cmpsi_ccu_zerohi_rlsi"
+ [(set (reg CC_REGNUM)
+ (compare (zero_extend:SI (mem:HI (match_operand:SI 1
+ "larl_operand" "X")))
+ (match_operand:SI 0 "register_operand" "d")))]
+ "s390_match_ccmode(insn, CCURmode) && TARGET_Z10"
+ "clhrl\t%0,%1"
+ [(set_attr "op_type" "RIL")
+ (set_attr "type" "larl")
+ (set_attr "z10prop" "z10_super")])
+
+; clhrl, clghrl
+(define_insn "*cmp<GPR:mode>_ccu_zerohi_rldi"
+ [(set (reg CC_REGNUM)
+ (compare (zero_extend:GPR (mem:HI (match_operand:DI 1
+ "larl_operand" "X")))
+ (match_operand:GPR 0 "register_operand" "d")))]
+ "s390_match_ccmode(insn, CCURmode) && TARGET_Z10"
+ "cl<g>hrl\t%0,%1"
+ [(set_attr "op_type" "RIL")
+ (set_attr "type" "larl")
+ (set_attr "z10prop" "z10_super")])
+
(define_insn "*cmpdi_ccu_zero"
[(set (reg CC_REGNUM)
- (compare (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m"))
- (match_operand:DI 0 "register_operand" "d,d")))]
+ (compare (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand"
+ "d,RT,b"))
+ (match_operand:DI 0 "register_operand" "d, d,d")))]
"s390_match_ccmode (insn, CCURmode) && TARGET_64BIT"
"@
clgfr\t%0,%1
- clgf\t%0,%1"
- [(set_attr "op_type" "RRE,RXY")])
+ clgf\t%0,%1
+ clgfrl\t%0,%1"
+ [(set_attr "op_type" "RRE,RXY,RIL")
+ (set_attr "cpu_facility" "*,*,z10")
+ (set_attr "type" "*,*,larl")
+ (set_attr "z10prop" "z10_super_c,z10_super_E1,z10_super")])
(define_insn "*cmpdi_ccu"
[(set (reg CC_REGNUM)
- (compare (match_operand:DI 0 "nonimmediate_operand" "d,d,d,Q,BQ")
- (match_operand:DI 1 "general_operand" "d,Op,m,BQ,Q")))]
+ (compare (match_operand:DI 0 "nonimmediate_operand"
+ "d, d,d,Q, d, Q,BQ")
+ (match_operand:DI 1 "general_operand"
+ "d,Op,b,D,RT,BQ,Q")))]
"s390_match_ccmode (insn, CCUmode) && TARGET_64BIT"
"@
clgr\t%0,%1
clgfi\t%0,%1
+ clgrl\t%0,%1
+ clghsi\t%0,%x1
clg\t%0,%1
#
#"
- [(set_attr "op_type" "RRE,RIL,RXY,SS,SS")])
+ [(set_attr "op_type" "RRE,RIL,RIL,SIL,RXY,SS,SS")
+ (set_attr "cpu_facility" "*,extimm,z10,z10,*,*,*")
+ (set_attr "type" "*,*,larl,*,*,*,*")
+ (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,*,*")])
(define_insn "*cmpsi_ccu"
[(set (reg CC_REGNUM)
- (compare (match_operand:SI 0 "nonimmediate_operand" "d,d,d,d,Q,BQ")
- (match_operand:SI 1 "general_operand" "d,Os,R,T,BQ,Q")))]
+ (compare (match_operand:SI 0 "nonimmediate_operand" "d, d,d,Q,d,d, Q,BQ")
+ (match_operand:SI 1 "general_operand" "d,Os,b,D,R,T,BQ, Q")))]
"s390_match_ccmode (insn, CCUmode)"
"@
clr\t%0,%1
clfi\t%0,%o1
+ clrl\t%0,%1
+ clfhsi\t%0,%x1
cl\t%0,%1
cly\t%0,%1
#
#"
- [(set_attr "op_type" "RR,RIL,RX,RXY,SS,SS")])
+ [(set_attr "op_type" "RR,RIL,RIL,SIL,RX,RXY,SS,SS")
+ (set_attr "cpu_facility" "*,extimm,z10,z10,*,*,*,*")
+ (set_attr "type" "*,*,larl,*,*,*,*,*")
+ (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,z10_super,*,*")])
(define_insn "*cmphi_ccu"
[(set (reg CC_REGNUM)
- (compare (match_operand:HI 0 "nonimmediate_operand" "d,d,Q,BQ")
- (match_operand:HI 1 "general_operand" "Q,S,BQ,Q")))]
+ (compare (match_operand:HI 0 "nonimmediate_operand" "d,d,Q,Q,BQ")
+ (match_operand:HI 1 "general_operand" "Q,S,D,BQ,Q")))]
"s390_match_ccmode (insn, CCUmode)
&& !register_operand (operands[1], HImode)"
"@
clm\t%0,3,%S1
clmy\t%0,3,%S1
+ clhhsi\t%0,%1
#
#"
- [(set_attr "op_type" "RS,RSY,SS,SS")])
+ [(set_attr "op_type" "RS,RSY,SIL,SS,SS")
+ (set_attr "cpu_facility" "*,*,z10,*,*")
+ (set_attr "z10prop" "*,*,z10_super,*,*")])
(define_insn "*cmpqi_ccu"
[(set (reg CC_REGNUM)
cliy\t%S0,%b1
#
#"
- [(set_attr "op_type" "RS,RSY,SI,SIY,SS,SS")])
+ [(set_attr "op_type" "RS,RSY,SI,SIY,SS,SS")
+ (set_attr "z10prop" "*,*,z10_super,z10_super,*,*")])
; Block compare (CLC) instruction patterns.
})
-; (DF|SF) instructions
+; (TF|DF|SF|TD|DD|SD) instructions
+; ltxbr, ltdbr, ltebr, ltxtr, ltdtr
(define_insn "*cmp<mode>_ccs_0"
[(set (reg CC_REGNUM)
- (compare (match_operand:FPR 0 "register_operand" "f")
- (match_operand:FPR 1 "const0_operand" "")))]
- "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
- "lt<de>br\t%0,%0"
+ (compare (match_operand:FP 0 "register_operand" "f")
+ (match_operand:FP 1 "const0_operand" "")))]
+ "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT"
+ "lt<xde><bt>r\t%0,%0"
[(set_attr "op_type" "RRE")
(set_attr "type" "fsimp<mode>")])
-(define_insn "*cmp<mode>_ccs_0_ibm"
- [(set (reg CC_REGNUM)
- (compare (match_operand:FPR 0 "register_operand" "f")
- (match_operand:FPR 1 "const0_operand" "")))]
- "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
- "lt<de>r\t%0,%0"
- [(set_attr "op_type" "RR")
- (set_attr "type" "fsimp<mode>")])
-
+; cxtr, cxbr, cdbr, cebr, cdb, ceb, cxbtr, cdbtr
(define_insn "*cmp<mode>_ccs"
[(set (reg CC_REGNUM)
- (compare (match_operand:FPR 0 "register_operand" "f,f")
- (match_operand:FPR 1 "general_operand" "f,R")))]
- "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
+ (compare (match_operand:FP 0 "register_operand" "f,f")
+ (match_operand:FP 1 "general_operand" "f,<Rf>")))]
+ "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT"
"@
- c<de>br\t%0,%1
- c<de>b\t%0,%1"
+ c<xde><bt>r\t%0,%1
+ c<xde>b\t%0,%1"
[(set_attr "op_type" "RRE,RXE")
(set_attr "type" "fsimp<mode>")])
-(define_insn "*cmp<mode>_ccs_ibm"
- [(set (reg CC_REGNUM)
- (compare (match_operand:FPR 0 "register_operand" "f,f")
- (match_operand:FPR 1 "general_operand" "f,R")))]
- "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
- "@
- c<de>r\t%0,%1
- c<de>\t%0,%1"
- [(set_attr "op_type" "RR,RX")
- (set_attr "type" "fsimp<mode>")])
+; Compare and Branch instructions
+
+; cij, cgij, crj, cgrj, cfi, cgfi, cr, cgr
+; The following instructions do a complementary access of their second
+; operand (z01 only): crj_c, cgrjc, cr, cgr
+(define_insn "*cmp_and_br_signed_<mode>"
+ [(set (pc)
+ (if_then_else (match_operator 0 "s390_signed_integer_comparison"
+ [(match_operand:GPR 1 "register_operand" "d,d")
+ (match_operand:GPR 2 "nonmemory_operand" "d,C")])
+ (label_ref (match_operand 3 "" ""))
+ (pc)))
+ (clobber (reg:CC CC_REGNUM))]
+ "TARGET_Z10"
+{
+ if (get_attr_length (insn) == 6)
+ return which_alternative ?
+ "c<g>ij%C0\t%1,%c2,%l3" : "c<g>rj%C0\t%1,%2,%l3";
+ else
+ return which_alternative ?
+ "c<g>fi\t%1,%c2\;jg%C0\t%l3" : "c<g>r\t%1,%2\;jg%C0\t%l3";
+}
+ [(set_attr "op_type" "RIE")
+ (set_attr "type" "branch")
+ (set_attr "z10prop" "z10_super_c,z10_super")
+ (set (attr "length")
+ (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000))
+ (const_int 6) (const_int 12)))]) ; 8 byte for cr/jg
+ ; 10 byte for cgr/jg
+
+; clij, clgij, clrj, clgrj, clfi, clgfi, clr, clgr
+; The following instructions do a complementary access of their second
+; operand (z10 only): clrj, clgrj, clr, clgr
+(define_insn "*cmp_and_br_unsigned_<mode>"
+ [(set (pc)
+ (if_then_else (match_operator 0 "s390_unsigned_integer_comparison"
+ [(match_operand:GPR 1 "register_operand" "d,d")
+ (match_operand:GPR 2 "nonmemory_operand" "d,I")])
+ (label_ref (match_operand 3 "" ""))
+ (pc)))
+ (clobber (reg:CC CC_REGNUM))]
+ "TARGET_Z10"
+{
+ if (get_attr_length (insn) == 6)
+ return which_alternative ?
+ "cl<g>ij%C0\t%1,%b2,%l3" : "cl<g>rj%C0\t%1,%2,%l3";
+ else
+ return which_alternative ?
+ "cl<g>fi\t%1,%b2\;jg%C0\t%l3" : "cl<g>r\t%1,%2\;jg%C0\t%l3";
+}
+ [(set_attr "op_type" "RIE")
+ (set_attr "type" "branch")
+ (set_attr "z10prop" "z10_super_c,z10_super")
+ (set (attr "length")
+ (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000))
+ (const_int 6) (const_int 12)))]) ; 8 byte for clr/jg
+ ; 10 byte for clgr/jg
;;
;;- Move instructions.
;
(define_insn "movti"
- [(set (match_operand:TI 0 "nonimmediate_operand" "=d,QS,d,o,Q")
- (match_operand:TI 1 "general_operand" "QS,d,dPm,d,Q"))]
+ [(set (match_operand:TI 0 "nonimmediate_operand" "=d,QS,d,o")
+ (match_operand:TI 1 "general_operand" "QS,d,dPRT,d"))]
"TARGET_64BIT"
"@
lmg\t%0,%N0,%S1
stmg\t%1,%N1,%S0
#
- #
#"
- [(set_attr "op_type" "RSY,RSY,*,*,SS")
- (set_attr "type" "lm,stm,*,*,*")])
+ [(set_attr "op_type" "RSY,RSY,*,*")
+ (set_attr "type" "lm,stm,*,*")])
(define_split
[(set (match_operand:TI 0 "nonimmediate_operand" "")
operands[1] = replace_equiv_address (operands[1], addr);
})
-(define_expand "reload_outti"
- [(parallel [(match_operand:TI 0 "" "")
- (match_operand:TI 1 "register_operand" "d")
- (match_operand:DI 2 "register_operand" "=&a")])]
- "TARGET_64BIT"
+
+;
+; Patterns used for secondary reloads
+;
+
+; z10 provides move instructions accepting larl memory operands.
+; Unfortunately there is no such variant for QI, TI and FP mode moves.
+; These patterns are also used for unaligned SI and DI accesses.
+
+(define_expand "reload<INTALL:mode><P:mode>_tomem_z10"
+ [(parallel [(match_operand:INTALL 0 "memory_operand" "")
+ (match_operand:INTALL 1 "register_operand" "=d")
+ (match_operand:P 2 "register_operand" "=&a")])]
+ "TARGET_Z10"
+{
+ s390_reload_symref_address (operands[1], operands[0], operands[2], 1);
+ DONE;
+})
+
+(define_expand "reload<INTALL:mode><P:mode>_toreg_z10"
+ [(parallel [(match_operand:INTALL 0 "register_operand" "=d")
+ (match_operand:INTALL 1 "memory_operand" "")
+ (match_operand:P 2 "register_operand" "=a")])]
+ "TARGET_Z10"
+{
+ s390_reload_symref_address (operands[0], operands[1], operands[2], 0);
+ DONE;
+})
+
+(define_expand "reload<FPALL:mode><P:mode>_tomem_z10"
+ [(parallel [(match_operand:FPALL 0 "memory_operand" "")
+ (match_operand:FPALL 1 "register_operand" "=d")
+ (match_operand:P 2 "register_operand" "=&a")])]
+ "TARGET_Z10"
+{
+ s390_reload_symref_address (operands[1], operands[0], operands[2], 1);
+ DONE;
+})
+
+(define_expand "reload<FPALL:mode><P:mode>_toreg_z10"
+ [(parallel [(match_operand:FPALL 0 "register_operand" "=d")
+ (match_operand:FPALL 1 "memory_operand" "")
+ (match_operand:P 2 "register_operand" "=a")])]
+ "TARGET_Z10"
+{
+ s390_reload_symref_address (operands[0], operands[1], operands[2], 0);
+ DONE;
+})
+
+(define_expand "reload<P:mode>_larl_odd_addend_z10"
+ [(parallel [(match_operand:P 0 "register_operand" "=d")
+ (match_operand:P 1 "larl_operand" "")
+ (match_operand:P 2 "register_operand" "=a")])]
+ "TARGET_Z10"
+{
+ s390_reload_larl_operand (operands[0], operands[1], operands[2]);
+ DONE;
+})
+
+; Handles loading a PLUS (load address) expression
+
+(define_expand "reload<mode>_plus"
+ [(parallel [(match_operand:P 0 "register_operand" "=a")
+ (match_operand:P 1 "s390_plus_operand" "")
+ (match_operand:P 2 "register_operand" "=&a")])]
+ ""
+{
+ s390_expand_plus_operand (operands[0], operands[1], operands[2]);
+ DONE;
+})
+
+; Handles assessing a non-offsetable memory address
+
+(define_expand "reload<mode>_nonoffmem_in"
+ [(parallel [(match_operand 0 "register_operand" "")
+ (match_operand 1 "" "")
+ (match_operand:P 2 "register_operand" "=&a")])]
+ ""
+{
+ gcc_assert (MEM_P (operands[1]));
+ s390_load_address (operands[2], find_replacement (&XEXP (operands[1], 0)));
+ operands[1] = replace_equiv_address (operands[1], operands[2]);
+ emit_move_insn (operands[0], operands[1]);
+ DONE;
+})
+
+(define_expand "reload<mode>_nonoffmem_out"
+ [(parallel [(match_operand 0 "" "")
+ (match_operand 1 "register_operand" "")
+ (match_operand:P 2 "register_operand" "=&a")])]
+ ""
{
gcc_assert (MEM_P (operands[0]));
s390_load_address (operands[2], find_replacement (&XEXP (operands[0], 0)));
DONE;
})
+(define_expand "reload<mode>_PIC_addr"
+ [(parallel [(match_operand 0 "register_operand" "=d")
+ (match_operand 1 "larl_operand" "")
+ (match_operand:P 2 "register_operand" "=a")])]
+ ""
+{
+ rtx new_rtx = legitimize_pic_address (operands[1], operands[2]);
+ emit_move_insn (operands[0], new_rtx);
+})
+
;
; movdi instruction pattern(s).
;
""
{
/* Handle symbolic constants. */
- if (TARGET_64BIT && SYMBOLIC_CONST (operands[1]))
+ if (TARGET_64BIT
+ && (SYMBOLIC_CONST (operands[1])
+ || (GET_CODE (operands[1]) == PLUS
+ && XEXP (operands[1], 0) == pic_offset_table_rtx
+ && SYMBOLIC_CONST (XEXP (operands[1], 1)))))
emit_symbolic_move (operands);
})
&& !FP_REG_P (operands[0])"
"larl\t%0,%1"
[(set_attr "op_type" "RIL")
- (set_attr "type" "larl")])
+ (set_attr "type" "larl")
+ (set_attr "z10prop" "z10_super_A1")])
-(define_insn "*movdi_64extimm"
+(define_insn "*movdi_64"
[(set (match_operand:DI 0 "nonimmediate_operand"
- "=d,d,d,d,d,d,d,d,d,d,d,m,!*f,!*f,!*f,!R,!T,d,t,Q,t,?Q")
+ "=d,d,d,d,d,d,d,d,f,d,d,d,d,d,
+ RT,!*f,!*f,!*f,!R,!T,b,Q,d,t,Q,t")
(match_operand:DI 1 "general_operand"
- "K,N0HD0,N1HD0,N2HD0,N3HD0,Os,N0SD0,N1SD0,L,d,m,d,*f,R,T,*f,*f,t,d,t,Q,?Q"))]
- "TARGET_64BIT && TARGET_EXTIMM"
+ "K,N0HD0,N1HD0,N2HD0,N3HD0,Os,N0SD0,N1SD0,d,f,L,b,d,RT,
+ d,*f,R,T,*f,*f,d,K,t,d,t,Q"))]
+ "TARGET_64BIT"
"@
lghi\t%0,%h1
llihh\t%0,%i1
lgfi\t%0,%1
llihf\t%0,%k1
llilf\t%0,%k1
+ ldgr\t%0,%1
+ lgdr\t%0,%1
lay\t%0,%a1
+ lgrl\t%0,%1
lgr\t%0,%1
lg\t%0,%1
stg\t%1,%0
ldy\t%0,%1
std\t%1,%0
stdy\t%1,%0
+ stgrl\t%1,%0
+ mvghi\t%0,%1
#
#
stam\t%1,%N1,%S0
- lam\t%0,%N0,%S1
- #"
- [(set_attr "op_type" "RI,RI,RI,RI,RI,RIL,RIL,RIL,RXY,RRE,RXY,RXY,
- RR,RX,RXY,RX,RXY,*,*,RS,RS,SS")
- (set_attr "type" "*,*,*,*,*,*,*,*,la,lr,load,store,
- floaddf,floaddf,floaddf,fstoredf,fstoredf,*,*,*,*,*")])
-
-(define_insn "*movdi_64"
- [(set (match_operand:DI 0 "nonimmediate_operand"
- "=d,d,d,d,d,d,d,d,m,!*f,!*f,!*f,!R,!T,d,t,Q,t,?Q")
- (match_operand:DI 1 "general_operand"
- "K,N0HD0,N1HD0,N2HD0,N3HD0,L,d,m,d,*f,R,T,*f,*f,t,d,t,Q,?Q"))]
- "TARGET_64BIT && !TARGET_EXTIMM"
- "@
- lghi\t%0,%h1
- llihh\t%0,%i1
- llihl\t%0,%i1
- llilh\t%0,%i1
- llill\t%0,%i1
- lay\t%0,%a1
- lgr\t%0,%1
- lg\t%0,%1
- stg\t%1,%0
- ldr\t%0,%1
- ld\t%0,%1
- ldy\t%0,%1
- std\t%1,%0
- stdy\t%1,%0
- #
- #
- stam\t%1,%N1,%S0
- lam\t%0,%N0,%S1
- #"
- [(set_attr "op_type" "RI,RI,RI,RI,RI,RXY,RRE,RXY,RXY,
- RR,RX,RXY,RX,RXY,*,*,RS,RS,SS")
- (set_attr "type" "*,*,*,*,*,la,lr,load,store,
- floaddf,floaddf,floaddf,fstoredf,fstoredf,*,*,*,*,*")])
+ lam\t%0,%N0,%S1"
+ [(set_attr "op_type" "RI,RI,RI,RI,RI,RIL,RIL,RIL,RRE,RRE,RXY,RIL,RRE,RXY,
+ RXY,RR,RX,RXY,RX,RXY,RIL,SIL,*,*,RS,RS")
+ (set_attr "type" "*,*,*,*,*,*,*,*,floaddf,floaddf,la,larl,lr,load,store,
+ floaddf,floaddf,floaddf,fstoredf,fstoredf,larl,*,*,*,
+ *,*")
+ (set_attr "cpu_facility" "*,*,*,*,*,extimm,extimm,extimm,dfp,dfp,longdisp,
+ z10,*,*,*,*,*,longdisp,*,longdisp,
+ z10,z10,*,*,*,*")
+ (set_attr "z10prop" "z10_fwd_A1,
+ z10_fwd_E1,
+ z10_fwd_E1,
+ z10_fwd_E1,
+ z10_fwd_E1,
+ z10_fwd_A1,
+ z10_fwd_E1,
+ z10_fwd_E1,
+ *,
+ *,
+ z10_fwd_A1,
+ z10_fwd_A3,
+ z10_fr_E1,
+ z10_fwd_A3,
+ z10_rec,
+ *,
+ *,
+ *,
+ *,
+ *,
+ z10_rec,
+ z10_super,
+ *,
+ *,
+ *,
+ *")
+])
(define_split
[(set (match_operand:DI 0 "register_operand" "")
s390_split_access_reg (operands[0], &operands[3], &operands[4]);")
(define_insn "*movdi_31"
- [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,Q,S,d,o,!*f,!*f,!*f,!R,!T,Q")
- (match_operand:DI 1 "general_operand" "Q,S,d,d,dPm,d,*f,R,T,*f,*f,Q"))]
+ [(set (match_operand:DI 0 "nonimmediate_operand"
+ "=d,d,Q,S,d ,o,!*f,!*f,!*f,!R,!T,d")
+ (match_operand:DI 1 "general_operand"
+ " Q,S,d,d,dPRT,d, *f, R, T,*f,*f,b"))]
"!TARGET_64BIT"
"@
lm\t%0,%N0,%S1
std\t%1,%0
stdy\t%1,%0
#"
- [(set_attr "op_type" "RS,RSY,RS,RSY,*,*,RR,RX,RXY,RX,RXY,SS")
- (set_attr "type" "lm,lm,stm,stm,*,*,floaddf,floaddf,floaddf,fstoredf,fstoredf,*")])
+ [(set_attr "op_type" "RS,RSY,RS,RSY,*,*,RR,RX,RXY,RX,RXY,*")
+ (set_attr "type" "lm,lm,stm,stm,*,*,floaddf,floaddf,floaddf,fstoredf,fstoredf,*")
+ (set_attr "cpu_facility" "*,*,*,*,*,*,*,*,*,*,*,z10")])
+
+; For a load from a symbol ref we can use one of the target registers
+; together with larl to load the address.
+(define_split
+ [(set (match_operand:DI 0 "register_operand" "")
+ (match_operand:DI 1 "memory_operand" ""))]
+ "!TARGET_64BIT && reload_completed && TARGET_Z10
+ && larl_operand (XEXP (operands[1], 0), SImode)"
+ [(set (match_dup 2) (match_dup 3))
+ (set (match_dup 0) (match_dup 1))]
+{
+ operands[2] = operand_subword (operands[0], 1, 0, DImode);
+ operands[3] = XEXP (operands[1], 0);
+ operands[1] = replace_equiv_address (operands[1], operands[2]);
+})
(define_split
[(set (match_operand:DI 0 "nonimmediate_operand" "")
operands[1] = replace_equiv_address (operands[1], addr);
})
-(define_expand "reload_outdi"
- [(parallel [(match_operand:DI 0 "" "")
- (match_operand:DI 1 "register_operand" "d")
- (match_operand:SI 2 "register_operand" "=&a")])]
- "!TARGET_64BIT"
-{
- gcc_assert (MEM_P (operands[0]));
- s390_load_address (operands[2], find_replacement (&XEXP (operands[0], 0)));
- operands[0] = replace_equiv_address (operands[0], operands[2]);
- emit_move_insn (operands[0], operands[1]);
- DONE;
-})
-
(define_peephole2
[(set (match_operand:DI 0 "register_operand" "")
(mem:DI (match_operand 1 "address_operand" "")))]
la\t%0,%a1
lay\t%0,%a1"
[(set_attr "op_type" "RX,RXY")
- (set_attr "type" "la")])
+ (set_attr "type" "la")
+ (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")])
(define_peephole2
[(parallel
[(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))]
"")
-(define_expand "reload_indi"
- [(parallel [(match_operand:DI 0 "register_operand" "=a")
- (match_operand:DI 1 "s390_plus_operand" "")
- (match_operand:DI 2 "register_operand" "=&a")])]
- "TARGET_64BIT"
-{
- s390_expand_plus_operand (operands[0], operands[1], operands[2]);
- DONE;
-})
-
;
; movsi instruction pattern(s).
;
""
{
/* Handle symbolic constants. */
- if (!TARGET_64BIT && SYMBOLIC_CONST (operands[1]))
+ if (!TARGET_64BIT
+ && (SYMBOLIC_CONST (operands[1])
+ || (GET_CODE (operands[1]) == PLUS
+ && XEXP (operands[1], 0) == pic_offset_table_rtx
+ && SYMBOLIC_CONST (XEXP(operands[1], 1)))))
emit_symbolic_move (operands);
})
&& !FP_REG_P (operands[0])"
"larl\t%0,%1"
[(set_attr "op_type" "RIL")
- (set_attr "type" "larl")])
+ (set_attr "type" "larl")
+ (set_attr "z10prop" "z10_fwd_A1")])
(define_insn "*movsi_zarch"
[(set (match_operand:SI 0 "nonimmediate_operand"
- "=d,d,d,d,d,d,d,d,R,T,!*f,!*f,!*f,!R,!T,d,t,Q,t,?Q")
+ "=d,d,d,d,d,d,d,d,d,R,T,!*f,!*f,!*f,!R,!T,d,t,Q,b,Q,t")
(match_operand:SI 1 "general_operand"
- "K,N0HS0,N1HS0,Os,L,d,R,T,d,d,*f,R,T,*f,*f,t,d,t,Q,?Q"))]
+ "K,N0HS0,N1HS0,Os,L,b,d,R,T,d,d,*f,R,T,*f,*f,t,d,t,d,K,Q"))]
"TARGET_ZARCH"
"@
lhi\t%0,%h1
llill\t%0,%i1
iilf\t%0,%o1
lay\t%0,%a1
+ lrl\t%0,%1
lr\t%0,%1
l\t%0,%1
ly\t%0,%1
ear\t%0,%1
sar\t%0,%1
stam\t%1,%1,%S0
- lam\t%0,%0,%S1
- #"
- [(set_attr "op_type" "RI,RI,RI,RIL,RXY,RR,RX,RXY,RX,RXY,
- RR,RX,RXY,RX,RXY,RRE,RRE,RS,RS,SS")
- (set_attr "type" "*,*,*,*,la,lr,load,load,store,store,
- floadsf,floadsf,floadsf,fstoresf,fstoresf,*,*,*,*,*")])
+ strl\t%1,%0
+ mvhi\t%0,%1
+ lam\t%0,%0,%S1"
+ [(set_attr "op_type" "RI,RI,RI,RIL,RXY,RIL,RR,RX,RXY,RX,RXY,
+ RR,RX,RXY,RX,RXY,RRE,RRE,RS,RIL,SIL,RS")
+ (set_attr "type" "*,
+ *,
+ *,
+ *,
+ la,
+ larl,
+ lr,
+ load,
+ load,
+ store,
+ store,
+ floadsf,
+ floadsf,
+ floadsf,
+ fstoresf,
+ fstoresf,
+ *,
+ *,
+ *,
+ larl,
+ *,
+ *")
+ (set_attr "cpu_facility" "*,*,*,extimm,longdisp,z10,*,*,longdisp,*,longdisp,
+ *,*,longdisp,*,longdisp,*,*,*,z10,z10,*")
+ (set_attr "z10prop" "z10_fwd_A1,
+ z10_fwd_E1,
+ z10_fwd_E1,
+ z10_fwd_A1,
+ z10_fwd_A1,
+ z10_fwd_A3,
+ z10_fr_E1,
+ z10_fwd_A3,
+ z10_fwd_A3,
+ z10_rec,
+ z10_rec,
+ *,
+ *,
+ *,
+ *,
+ *,
+ z10_super_E1,
+ z10_super,
+ *,
+ z10_rec,
+ z10_super,
+ *")])
(define_insn "*movsi_esa"
- [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,R,!*f,!*f,!R,d,t,Q,t,?Q")
- (match_operand:SI 1 "general_operand" "K,d,R,d,*f,R,*f,t,d,t,Q,?Q"))]
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,R,!*f,!*f,!R,d,t,Q,t")
+ (match_operand:SI 1 "general_operand" "K,d,R,d,*f,R,*f,t,d,t,Q"))]
"!TARGET_ZARCH"
"@
lhi\t%0,%h1
ear\t%0,%1
sar\t%0,%1
stam\t%1,%1,%S0
- lam\t%0,%0,%S1
- #"
- [(set_attr "op_type" "RI,RR,RX,RX,RR,RX,RX,RRE,RRE,RS,RS,SS")
- (set_attr "type" "*,lr,load,store,floadsf,floadsf,fstoresf,*,*,*,*,*")])
+ lam\t%0,%0,%S1"
+ [(set_attr "op_type" "RI,RR,RX,RX,RR,RX,RX,RRE,RRE,RS,RS")
+ (set_attr "type" "*,lr,load,store,floadsf,floadsf,fstoresf,*,*,*,*")
+ (set_attr "z10prop" "z10_fwd_A1,
+ z10_fr_E1,
+ z10_fwd_A3,
+ z10_rec,
+ *,
+ *,
+ *,
+ z10_super_E1,
+ z10_super,
+ *,
+ *")
+])
(define_peephole2
[(set (match_operand:SI 0 "register_operand" "")
la\t%0,%a1
lay\t%0,%a1"
[(set_attr "op_type" "RX,RXY")
- (set_attr "type" "la")])
+ (set_attr "type" "la")
+ (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")])
(define_peephole2
[(parallel
la\t%0,%a1
lay\t%0,%a1"
[(set_attr "op_type" "RX,RXY")
- (set_attr "type" "la")])
+ (set_attr "type" "la")
+ (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")])
(define_insn_and_split "*la_31_and_cc"
[(set (match_operand:SI 0 "register_operand" "=d")
la\t%0,%a1
lay\t%0,%a1"
[(set_attr "op_type" "RX")
- (set_attr "type" "la")])
-
-(define_expand "reload_insi"
- [(parallel [(match_operand:SI 0 "register_operand" "=a")
- (match_operand:SI 1 "s390_plus_operand" "")
- (match_operand:SI 2 "register_operand" "=&a")])]
- "!TARGET_64BIT"
-{
- s390_expand_plus_operand (operands[0], operands[1], operands[2]);
- DONE;
-})
+ (set_attr "type" "la")
+ (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")])
;
; movhi instruction pattern(s).
{
/* Make it explicit that loading a register from memory
always sign-extends (at least) to SImode. */
- if (optimize && !no_new_pseudos
+ if (optimize && can_create_pseudo_p ()
&& register_operand (operands[0], VOIDmode)
&& GET_CODE (operands[1]) == MEM)
{
})
(define_insn "*movhi"
- [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,d,R,T,?Q")
- (match_operand:HI 1 "general_operand" "d,n,R,T,d,d,?Q"))]
+ [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,d,d,R,T,b,Q")
+ (match_operand:HI 1 "general_operand" " d,n,R,T,b,d,d,d,K"))]
""
"@
lr\t%0,%1
lhi\t%0,%h1
lh\t%0,%1
lhy\t%0,%1
+ lhrl\t%0,%1
sth\t%1,%0
sthy\t%1,%0
- #"
- [(set_attr "op_type" "RR,RI,RX,RXY,RX,RXY,SS")
- (set_attr "type" "lr,*,*,*,store,store,*")])
+ sthrl\t%1,%0
+ mvhhi\t%0,%1"
+ [(set_attr "op_type" "RR,RI,RX,RXY,RIL,RX,RXY,RIL,SIL")
+ (set_attr "type" "lr,*,*,*,larl,store,store,store,*")
+ (set_attr "cpu_facility" "*,*,*,*,z10,*,*,z10,z10")
+ (set_attr "z10prop" "z10_fr_E1,
+ z10_fwd_A1,
+ z10_super_E1,
+ z10_super_E1,
+ z10_super_E1,
+ z10_rec,
+ z10_rec,
+ z10_rec,
+ z10_super")])
(define_peephole2
[(set (match_operand:HI 0 "register_operand" "")
{
/* On z/Architecture, zero-extending from memory to register
is just as fast as a QImode load. */
- if (TARGET_ZARCH && optimize && !no_new_pseudos
+ if (TARGET_ZARCH && optimize && can_create_pseudo_p ()
&& register_operand (operands[0], VOIDmode)
&& GET_CODE (operands[1]) == MEM)
{
})
(define_insn "*movqi"
- [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,d,R,T,Q,S,?Q")
- (match_operand:QI 1 "general_operand" "d,n,R,T,d,d,n,n,?Q"))]
+ [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,d,R,T,Q,S")
+ (match_operand:QI 1 "general_operand" "d,n,R,T,d,d,n,n"))]
""
"@
lr\t%0,%1
stc\t%1,%0
stcy\t%1,%0
mvi\t%S0,%b1
- mviy\t%S0,%b1
- #"
- [(set_attr "op_type" "RR,RI,RX,RXY,RX,RXY,SI,SIY,SS")
- (set_attr "type" "lr,*,*,*,store,store,store,store,*")])
+ mviy\t%S0,%b1"
+ [(set_attr "op_type" "RR,RI,RX,RXY,RX,RXY,SI,SIY")
+ (set_attr "type" "lr,*,*,*,store,store,store,store")
+ (set_attr "z10prop" "z10_fr_E1,
+ z10_fwd_A1,
+ z10_super_E1,
+ z10_super_E1,
+ z10_rec,
+ z10_rec,
+ z10_super,
+ z10_super")])
(define_peephole2
[(set (match_operand:QI 0 "nonimmediate_operand" "")
"@
ic\t%0,%1
icy\t%0,%1"
- [(set_attr "op_type" "RX,RXY")])
+ [(set_attr "op_type" "RX,RXY")
+ (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
;
; movstricthi instruction pattern(s).
"@
icm\t%0,3,%S1
icmy\t%0,3,%S1"
- [(set_attr "op_type" "RS,RSY")])
+ [(set_attr "op_type" "RS,RSY")
+ (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
;
; movstrictsi instruction pattern(s).
ly\t%0,%1
ear\t%0,%1"
[(set_attr "op_type" "RR,RX,RXY,RRE")
- (set_attr "type" "lr,load,load,*")])
+ (set_attr "type" "lr,load,load,*")
+ (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_super_E1")])
+
+;
+; mov(tf|td) instruction pattern(s).
+;
+
+(define_expand "mov<mode>"
+ [(set (match_operand:TD_TF 0 "nonimmediate_operand" "")
+ (match_operand:TD_TF 1 "general_operand" ""))]
+ ""
+ "")
+
+(define_insn "*mov<mode>_64"
+ [(set (match_operand:TD_TF 0 "nonimmediate_operand" "=f,f,f,o, d,QS, d,o")
+ (match_operand:TD_TF 1 "general_operand" " G,f,o,f,QS, d,dRT,d"))]
+ "TARGET_64BIT"
+ "@
+ lzxr\t%0
+ lxr\t%0,%1
+ #
+ #
+ lmg\t%0,%N0,%S1
+ stmg\t%1,%N1,%S0
+ #
+ #"
+ [(set_attr "op_type" "RRE,RRE,*,*,RSY,RSY,*,*")
+ (set_attr "type" "fsimptf,fsimptf,*,*,lm,stm,*,*")])
+
+(define_insn "*mov<mode>_31"
+ [(set (match_operand:TD_TF 0 "nonimmediate_operand" "=f,f,f,o")
+ (match_operand:TD_TF 1 "general_operand" " G,f,o,f"))]
+ "!TARGET_64BIT"
+ "@
+ lzxr\t%0
+ lxr\t%0,%1
+ #
+ #"
+ [(set_attr "op_type" "RRE,RRE,*,*")
+ (set_attr "type" "fsimptf,fsimptf,*,*")])
+
+; TFmode in GPRs splitters
+
+(define_split
+ [(set (match_operand:TD_TF 0 "nonimmediate_operand" "")
+ (match_operand:TD_TF 1 "general_operand" ""))]
+ "TARGET_64BIT && reload_completed
+ && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 0)"
+ [(set (match_dup 2) (match_dup 4))
+ (set (match_dup 3) (match_dup 5))]
+{
+ operands[2] = operand_subword (operands[0], 0, 0, <MODE>mode);
+ operands[3] = operand_subword (operands[0], 1, 0, <MODE>mode);
+ operands[4] = operand_subword (operands[1], 0, 0, <MODE>mode);
+ operands[5] = operand_subword (operands[1], 1, 0, <MODE>mode);
+})
+
+(define_split
+ [(set (match_operand:TD_TF 0 "nonimmediate_operand" "")
+ (match_operand:TD_TF 1 "general_operand" ""))]
+ "TARGET_64BIT && reload_completed
+ && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 1)"
+ [(set (match_dup 2) (match_dup 4))
+ (set (match_dup 3) (match_dup 5))]
+{
+ operands[2] = operand_subword (operands[0], 1, 0, <MODE>mode);
+ operands[3] = operand_subword (operands[0], 0, 0, <MODE>mode);
+ operands[4] = operand_subword (operands[1], 1, 0, <MODE>mode);
+ operands[5] = operand_subword (operands[1], 0, 0, <MODE>mode);
+})
+
+(define_split
+ [(set (match_operand:TD_TF 0 "register_operand" "")
+ (match_operand:TD_TF 1 "memory_operand" ""))]
+ "TARGET_64BIT && reload_completed
+ && !FP_REG_P (operands[0])
+ && !s_operand (operands[1], VOIDmode)"
+ [(set (match_dup 0) (match_dup 1))]
+{
+ rtx addr = operand_subword (operands[0], 1, 0, <MODE>mode);
+ s390_load_address (addr, XEXP (operands[1], 0));
+ operands[1] = replace_equiv_address (operands[1], addr);
+})
+
+; TFmode in BFPs splitters
+
+(define_split
+ [(set (match_operand:TD_TF 0 "register_operand" "")
+ (match_operand:TD_TF 1 "memory_operand" ""))]
+ "reload_completed && offsettable_memref_p (operands[1])
+ && FP_REG_P (operands[0])"
+ [(set (match_dup 2) (match_dup 4))
+ (set (match_dup 3) (match_dup 5))]
+{
+ operands[2] = simplify_gen_subreg (<HALF_TMODE>mode, operands[0],
+ <MODE>mode, 0);
+ operands[3] = simplify_gen_subreg (<HALF_TMODE>mode, operands[0],
+ <MODE>mode, 8);
+ operands[4] = adjust_address_nv (operands[1], <HALF_TMODE>mode, 0);
+ operands[5] = adjust_address_nv (operands[1], <HALF_TMODE>mode, 8);
+})
+
+(define_split
+ [(set (match_operand:TD_TF 0 "memory_operand" "")
+ (match_operand:TD_TF 1 "register_operand" ""))]
+ "reload_completed && offsettable_memref_p (operands[0])
+ && FP_REG_P (operands[1])"
+ [(set (match_dup 2) (match_dup 4))
+ (set (match_dup 3) (match_dup 5))]
+{
+ operands[2] = adjust_address_nv (operands[0], <HALF_TMODE>mode, 0);
+ operands[3] = adjust_address_nv (operands[0], <HALF_TMODE>mode, 8);
+ operands[4] = simplify_gen_subreg (<HALF_TMODE>mode, operands[1],
+ <MODE>mode, 0);
+ operands[5] = simplify_gen_subreg (<HALF_TMODE>mode, operands[1],
+ <MODE>mode, 8);
+})
;
-; movdf instruction pattern(s).
+; mov(df|dd) instruction pattern(s).
;
-(define_expand "movdf"
- [(set (match_operand:DF 0 "nonimmediate_operand" "")
- (match_operand:DF 1 "general_operand" ""))]
+(define_expand "mov<mode>"
+ [(set (match_operand:DD_DF 0 "nonimmediate_operand" "")
+ (match_operand:DD_DF 1 "general_operand" ""))]
""
"")
-(define_insn "*movdf_64"
- [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,f,R,T,d,d,m,?Q")
- (match_operand:DF 1 "general_operand" "G,f,R,T,f,f,d,m,d,?Q"))]
+(define_insn "*mov<mode>_64dfp"
+ [(set (match_operand:DD_DF 0 "nonimmediate_operand"
+ "=f,f,f,d,f,f,R,T,d, d,RT")
+ (match_operand:DD_DF 1 "general_operand"
+ " G,f,d,f,R,T,f,f,d,RT, d"))]
+ "TARGET_64BIT && TARGET_DFP"
+ "@
+ lzdr\t%0
+ ldr\t%0,%1
+ ldgr\t%0,%1
+ lgdr\t%0,%1
+ ld\t%0,%1
+ ldy\t%0,%1
+ std\t%1,%0
+ stdy\t%1,%0
+ lgr\t%0,%1
+ lg\t%0,%1
+ stg\t%1,%0"
+ [(set_attr "op_type" "RRE,RR,RRE,RRE,RX,RXY,RX,RXY,RRE,RXY,RXY")
+ (set_attr "type" "fsimpdf,floaddf,floaddf,floaddf,floaddf,floaddf,
+ fstoredf,fstoredf,lr,load,store")
+ (set_attr "z10prop" "*,
+ *,
+ *,
+ *,
+ *,
+ *,
+ *,
+ *,
+ z10_fr_E1,
+ z10_fwd_A3,
+ z10_rec")
+])
+
+(define_insn "*mov<mode>_64"
+ [(set (match_operand:DD_DF 0 "nonimmediate_operand" "=f,f,f,f,R,T,d, d,RT")
+ (match_operand:DD_DF 1 "general_operand" "G,f,R,T,f,f,d,RT, d"))]
"TARGET_64BIT"
"@
lzdr\t%0
stdy\t%1,%0
lgr\t%0,%1
lg\t%0,%1
- stg\t%1,%0
- #"
- [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RRE,RXY,RXY,SS")
- (set_attr "type" "fsimpdf,floaddf,floaddf,floaddf,fstoredf,fstoredf,lr,load,store,*")])
-
-(define_insn "*movdf_31"
- [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,f,R,T,d,d,Q,S,d,o,Q")
- (match_operand:DF 1 "general_operand" "G,f,R,T,f,f,Q,S,d,d,dPm,d,Q"))]
+ stg\t%1,%0"
+ [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RRE,RXY,RXY")
+ (set_attr "type" "fsimp<mode>,fload<mode>,fload<mode>,fload<mode>,
+ fstore<mode>,fstore<mode>,lr,load,store")
+ (set_attr "z10prop" "*,
+ *,
+ *,
+ *,
+ *,
+ *,
+ z10_fr_E1,
+ z10_fwd_A3,
+ z10_rec")])
+
+(define_insn "*mov<mode>_31"
+ [(set (match_operand:DD_DF 0 "nonimmediate_operand"
+ "=f,f,f,f,R,T,d,d,Q,S, d,o")
+ (match_operand:DD_DF 1 "general_operand"
+ " G,f,R,T,f,f,Q,S,d,d,dPRT,d"))]
"!TARGET_64BIT"
"@
lzdr\t%0
stm\t%1,%N1,%S0
stmy\t%1,%N1,%S0
#
- #
#"
- [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RS,RSY,RS,RSY,*,*,SS")
- (set_attr "type" "fsimpdf,floaddf,floaddf,floaddf,fstoredf,fstoredf,\
- lm,lm,stm,stm,*,*,*")])
+ [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RS,RSY,RS,RSY,*,*")
+ (set_attr "type" "fsimp<mode>,fload<mode>,fload<mode>,fload<mode>,
+ fstore<mode>,fstore<mode>,lm,lm,stm,stm,*,*")])
(define_split
- [(set (match_operand:DF 0 "nonimmediate_operand" "")
- (match_operand:DF 1 "general_operand" ""))]
+ [(set (match_operand:DD_DF 0 "nonimmediate_operand" "")
+ (match_operand:DD_DF 1 "general_operand" ""))]
"!TARGET_64BIT && reload_completed
- && s390_split_ok_p (operands[0], operands[1], DFmode, 0)"
+ && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 0)"
[(set (match_dup 2) (match_dup 4))
(set (match_dup 3) (match_dup 5))]
{
- operands[2] = operand_subword (operands[0], 0, 0, DFmode);
- operands[3] = operand_subword (operands[0], 1, 0, DFmode);
- operands[4] = operand_subword (operands[1], 0, 0, DFmode);
- operands[5] = operand_subword (operands[1], 1, 0, DFmode);
+ operands[2] = operand_subword (operands[0], 0, 0, <MODE>mode);
+ operands[3] = operand_subword (operands[0], 1, 0, <MODE>mode);
+ operands[4] = operand_subword (operands[1], 0, 0, <MODE>mode);
+ operands[5] = operand_subword (operands[1], 1, 0, <MODE>mode);
})
(define_split
- [(set (match_operand:DF 0 "nonimmediate_operand" "")
- (match_operand:DF 1 "general_operand" ""))]
+ [(set (match_operand:DD_DF 0 "nonimmediate_operand" "")
+ (match_operand:DD_DF 1 "general_operand" ""))]
"!TARGET_64BIT && reload_completed
- && s390_split_ok_p (operands[0], operands[1], DFmode, 1)"
+ && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 1)"
[(set (match_dup 2) (match_dup 4))
(set (match_dup 3) (match_dup 5))]
{
- operands[2] = operand_subword (operands[0], 1, 0, DFmode);
- operands[3] = operand_subword (operands[0], 0, 0, DFmode);
- operands[4] = operand_subword (operands[1], 1, 0, DFmode);
- operands[5] = operand_subword (operands[1], 0, 0, DFmode);
+ operands[2] = operand_subword (operands[0], 1, 0, <MODE>mode);
+ operands[3] = operand_subword (operands[0], 0, 0, <MODE>mode);
+ operands[4] = operand_subword (operands[1], 1, 0, <MODE>mode);
+ operands[5] = operand_subword (operands[1], 0, 0, <MODE>mode);
})
(define_split
- [(set (match_operand:DF 0 "register_operand" "")
- (match_operand:DF 1 "memory_operand" ""))]
+ [(set (match_operand:DD_DF 0 "register_operand" "")
+ (match_operand:DD_DF 1 "memory_operand" ""))]
"!TARGET_64BIT && reload_completed
&& !FP_REG_P (operands[0])
&& !s_operand (operands[1], VOIDmode)"
[(set (match_dup 0) (match_dup 1))]
{
- rtx addr = operand_subword (operands[0], 1, 0, DFmode);
+ rtx addr = operand_subword (operands[0], 1, 0, <MODE>mode);
s390_load_address (addr, XEXP (operands[1], 0));
operands[1] = replace_equiv_address (operands[1], addr);
})
-(define_expand "reload_outdf"
- [(parallel [(match_operand:DF 0 "" "")
- (match_operand:DF 1 "register_operand" "d")
- (match_operand:SI 2 "register_operand" "=&a")])]
- "!TARGET_64BIT"
-{
- gcc_assert (MEM_P (operands[0]));
- s390_load_address (operands[2], find_replacement (&XEXP (operands[0], 0)));
- operands[0] = replace_equiv_address (operands[0], operands[2]);
- emit_move_insn (operands[0], operands[1]);
- DONE;
-})
-
;
-; movsf instruction pattern(s).
+; mov(sf|sd) instruction pattern(s).
;
-(define_insn "movsf"
- [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,f,f,R,T,d,d,d,R,T,?Q")
- (match_operand:SF 1 "general_operand" "G,f,R,T,f,f,d,R,T,d,d,?Q"))]
+(define_insn "mov<mode>"
+ [(set (match_operand:SD_SF 0 "nonimmediate_operand"
+ "=f,f,f,f,R,T,d,d,d,R,T")
+ (match_operand:SD_SF 1 "general_operand"
+ " G,f,R,T,f,f,d,R,T,d,d"))]
""
"@
lzer\t%0
l\t%0,%1
ly\t%0,%1
st\t%1,%0
- sty\t%1,%0
- #"
- [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RR,RX,RXY,RX,RXY,SS")
- (set_attr "type" "fsimpsf,floadsf,floadsf,floadsf,fstoresf,fstoresf,
- lr,load,load,store,store,*")])
+ sty\t%1,%0"
+ [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RR,RX,RXY,RX,RXY")
+ (set_attr "type" "fsimp<mode>,fload<mode>,fload<mode>,fload<mode>,
+ fstore<mode>,fstore<mode>,lr,load,load,store,store")
+ (set_attr "z10prop" "*,
+ *,
+ *,
+ *,
+ *,
+ *,
+ z10_fr_E1,
+ z10_fwd_A3,
+ z10_fwd_A3,
+ z10_rec,
+ z10_rec")])
;
; movcc instruction pattern
l\t%1,%0
ly\t%1,%0"
[(set_attr "op_type" "RR,RI,RRE,RX,RXY,RX,RXY")
- (set_attr "type" "lr,*,*,store,store,load,load")])
+ (set_attr "type" "lr,*,*,store,store,load,load")
+ (set_attr "z10prop" "z10_fr_E1,z10_super,*,z10_rec,z10_rec,z10_fwd_A3,z10_fwd_A3")])
;
; Block move (MVC) patterns.
"mvc\t%O0(%2,%R0),%S1"
[(set_attr "op_type" "SS")])
-(define_split
- [(set (match_operand 0 "memory_operand" "")
- (match_operand 1 "memory_operand" ""))]
- "reload_completed
- && GET_MODE (operands[0]) == GET_MODE (operands[1])
- && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
- [(parallel
- [(set (match_dup 0) (match_dup 1))
- (use (match_dup 2))])]
-{
- operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
- operands[0] = adjust_address (operands[0], BLKmode, 0);
- operands[1] = adjust_address (operands[1], BLKmode, 0);
-})
-
(define_peephole2
[(parallel
[(set (match_operand:BLK 0 "memory_operand" "")
(use (match_operand 5 "const_int_operand" ""))])]
"s390_offset_p (operands[0], operands[3], operands[2])
&& s390_offset_p (operands[1], operands[4], operands[2])
- && !s390_overlap_p (operands[0], operands[1],
+ && !s390_overlap_p (operands[0], operands[1],
INTVAL (operands[2]) + INTVAL (operands[5]))
&& INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
[(parallel
FAIL;
operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
- if (no_new_pseudos)
+ if (!can_create_pseudo_p ())
{
if (GET_CODE (XEXP (operands[1], 0)) == REG)
{
operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
- if (no_new_pseudos)
+ if (!can_create_pseudo_p ())
{
if (GET_CODE (XEXP (operands[0], 0)) == REG)
{
;; String instructions.
;;
+(define_insn "*execute_rl"
+ [(match_parallel 0 ""
+ [(unspec [(match_operand 1 "register_operand" "a")
+ (match_operand 2 "" "")
+ (match_operand:SI 3 "larl_operand" "X")] UNSPEC_EXECUTE)])]
+ "TARGET_Z10 && GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
+ && GET_MODE_SIZE (GET_MODE (operands[1])) <= UNITS_PER_WORD"
+ "exrl\t%1,%3"
+ [(set_attr "op_type" "RIL")
+ (set_attr "type" "cs")])
+
(define_insn "*execute"
[(match_parallel 0 ""
[(unspec [(match_operand 1 "register_operand" "a")
(use (reg:SI 0))])
(parallel
[(set (match_operand:SI 0 "register_operand" "=d")
- (unspec:SI [(reg:CCU CC_REGNUM)] UNSPEC_CMPINT))
+ (unspec:SI [(reg:CCU CC_REGNUM)] UNSPEC_CCU_TO_INT))
(clobber (reg:CC CC_REGNUM))])]
""
{
"clst\t%0,%1\;jo\t.-4"
[(set_attr "length" "8")
(set_attr "type" "vs")])
-
+
;
; movstr instruction pattern.
;
(define_expand "movstr"
[(set (reg:SI 0) (const_int 0))
- (parallel
+ (parallel
[(clobber (match_dup 3))
(set (match_operand:BLK 1 "memory_operand" "")
(match_operand:BLK 2 "memory_operand" ""))
(set (match_operand 0 "register_operand" "")
- (unspec [(match_dup 1)
+ (unspec [(match_dup 1)
(match_dup 2)
(reg:SI 0)] UNSPEC_MVST))
(clobber (reg:CC CC_REGNUM))])]
(set (mem:BLK (match_operand:P 1 "register_operand" "0"))
(mem:BLK (match_operand:P 3 "register_operand" "2")))
(set (match_operand:P 0 "register_operand" "=d")
- (unspec [(mem:BLK (match_dup 1))
+ (unspec [(mem:BLK (match_dup 1))
(mem:BLK (match_dup 3))
(reg:SI 0)] UNSPEC_MVST))
(clobber (reg:CC CC_REGNUM))]
"mvst\t%1,%2\;jo\t.-4"
[(set_attr "length" "8")
(set_attr "type" "vs")])
-
+
;
; movmemM instruction pattern(s).
;
(define_expand "movmem<mode>"
- [(set (match_operand:BLK 0 "memory_operand" "")
- (match_operand:BLK 1 "memory_operand" ""))
- (use (match_operand:GPR 2 "general_operand" ""))
+ [(set (match_operand:BLK 0 "memory_operand" "") ; destination
+ (match_operand:BLK 1 "memory_operand" "")) ; source
+ (use (match_operand:GPR 2 "general_operand" "")) ; count
(match_operand 3 "" "")]
""
"s390_expand_movmem (operands[0], operands[1], operands[2]); DONE;")
"operands[3] = gen_rtx_SCRATCH (Pmode);")
(define_insn "*movmem_short"
- [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q")
- (match_operand:BLK 1 "memory_operand" "Q,Q,Q"))
- (use (match_operand 2 "nonmemory_operand" "n,a,a"))
- (use (match_operand 3 "immediate_operand" "X,R,X"))
- (clobber (match_scratch 4 "=X,X,&a"))]
+ [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q,Q")
+ (match_operand:BLK 1 "memory_operand" "Q,Q,Q,Q"))
+ (use (match_operand 2 "nonmemory_operand" "n,a,a,a"))
+ (use (match_operand 3 "immediate_operand" "X,R,X,X"))
+ (clobber (match_scratch 4 "=X,X,X,&a"))]
"(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode)
&& GET_MODE (operands[4]) == Pmode"
"#"
- [(set_attr "type" "cs")])
+ [(set_attr "type" "cs")
+ (set_attr "cpu_facility" "*,*,z10,*")])
(define_split
[(set (match_operand:BLK 0 "memory_operand" "")
(match_operand:BLK 1 "memory_operand" ""))
(use (match_operand 2 "register_operand" ""))
(use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
+ (clobber (scratch))]
+ "TARGET_Z10 && reload_completed"
+ [(parallel
+ [(unspec [(match_dup 2) (const_int 0)
+ (label_ref (match_dup 3))] UNSPEC_EXECUTE)
+ (set (match_dup 0) (match_dup 1))
+ (use (const_int 1))])]
+ "operands[3] = gen_label_rtx ();")
+
+(define_split
+ [(set (match_operand:BLK 0 "memory_operand" "")
+ (match_operand:BLK 1 "memory_operand" ""))
+ (use (match_operand 2 "register_operand" ""))
+ (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
(clobber (match_operand 3 "register_operand" ""))]
"reload_completed && TARGET_CPU_ZARCH"
[(set (match_dup 3) (label_ref (match_dup 4)))
(parallel
- [(unspec [(match_dup 2) (mem:BLK (match_dup 3))
+ [(unspec [(match_dup 2) (mem:BLK (match_dup 3))
(label_ref (match_dup 4))] UNSPEC_EXECUTE)
(set (match_dup 0) (match_dup 1))
(use (const_int 1))])]
rtx len0 = gen_lowpart (Pmode, reg0);
rtx len1 = gen_lowpart (Pmode, reg1);
- emit_insn (gen_rtx_CLOBBER (VOIDmode, reg0));
+ emit_clobber (reg0);
emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX));
emit_move_insn (len0, operands[2]);
- emit_insn (gen_rtx_CLOBBER (VOIDmode, reg1));
+ emit_clobber (reg1);
emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX));
emit_move_insn (len1, operands[2]);
[(set_attr "length" "8")
(set_attr "type" "vs")])
+
+;
+; Test data class.
+;
+
+(define_expand "signbit<mode>2"
+ [(set (reg:CCZ CC_REGNUM)
+ (unspec:CCZ [(match_operand:FP_ALL 1 "register_operand" "f")
+ (match_dup 2)]
+ UNSPEC_TDC_INSN))
+ (set (match_operand:SI 0 "register_operand" "=d")
+ (unspec:SI [(reg:CCZ CC_REGNUM)] UNSPEC_CCZ_TO_INT))]
+ "TARGET_HARD_FLOAT"
+{
+ operands[2] = GEN_INT (S390_TDC_SIGNBIT_SET);
+})
+
+(define_expand "isinf<mode>2"
+ [(set (reg:CCZ CC_REGNUM)
+ (unspec:CCZ [(match_operand:FP_ALL 1 "register_operand" "f")
+ (match_dup 2)]
+ UNSPEC_TDC_INSN))
+ (set (match_operand:SI 0 "register_operand" "=d")
+ (unspec:SI [(reg:CCZ CC_REGNUM)] UNSPEC_CCZ_TO_INT))]
+ "TARGET_HARD_FLOAT"
+{
+ operands[2] = GEN_INT (S390_TDC_INFINITY);
+})
+
+; This insn is used to generate all variants of the Test Data Class
+; instruction, namely tcxb, tcdb, and tceb. The insn's first operand
+; is the register to be tested and the second one is the bit mask
+; specifying the required test(s).
+;
+(define_insn "*TDC_insn_<mode>"
+ [(set (reg:CCZ CC_REGNUM)
+ (unspec:CCZ [(match_operand:FP_ALL 0 "register_operand" "f")
+ (match_operand:SI 1 "const_int_operand")] UNSPEC_TDC_INSN))]
+ "TARGET_HARD_FLOAT"
+ "t<_d>c<xde><bt>\t%0,%1"
+ [(set_attr "op_type" "RXE")
+ (set_attr "type" "fsimp<mode>")])
+
+(define_insn_and_split "*ccz_to_int"
+ [(set (match_operand:SI 0 "register_operand" "=d")
+ (unspec:SI [(match_operand:CCZ 1 "register_operand" "0")]
+ UNSPEC_CCZ_TO_INT))]
+ ""
+ "#"
+ "reload_completed"
+ [(set (match_dup 0) (lshiftrt:SI (match_dup 0) (const_int 28)))])
+
+
;
; setmemM instruction pattern(s).
;
"operands[2] = gen_rtx_SCRATCH (Pmode);")
(define_insn "*clrmem_short"
- [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q")
+ [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q,Q")
(const_int 0))
- (use (match_operand 1 "nonmemory_operand" "n,a,a"))
- (use (match_operand 2 "immediate_operand" "X,R,X"))
- (clobber (match_scratch 3 "=X,X,&a"))
+ (use (match_operand 1 "nonmemory_operand" "n,a,a,a"))
+ (use (match_operand 2 "immediate_operand" "X,R,X,X"))
+ (clobber (match_scratch 3 "=X,X,X,&a"))
(clobber (reg:CC CC_REGNUM))]
"(GET_MODE (operands[1]) == Pmode || GET_MODE (operands[1]) == VOIDmode)
&& GET_MODE (operands[3]) == Pmode"
"#"
- [(set_attr "type" "cs")])
+ [(set_attr "type" "cs")
+ (set_attr "cpu_facility" "*,*,z10,*")])
(define_split
[(set (match_operand:BLK 0 "memory_operand" "")
(const_int 0))
(use (match_operand 1 "register_operand" ""))
(use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
+ (clobber (scratch))
+ (clobber (reg:CC CC_REGNUM))]
+ "TARGET_Z10 && reload_completed"
+ [(parallel
+ [(unspec [(match_dup 1) (const_int 0)
+ (label_ref (match_dup 3))] UNSPEC_EXECUTE)
+ (set (match_dup 0) (const_int 0))
+ (use (const_int 1))
+ (clobber (reg:CC CC_REGNUM))])]
+ "operands[3] = gen_label_rtx ();")
+
+(define_split
+ [(set (match_operand:BLK 0 "memory_operand" "")
+ (const_int 0))
+ (use (match_operand 1 "register_operand" ""))
+ (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
(clobber (match_operand 2 "register_operand" ""))
(clobber (reg:CC CC_REGNUM))]
"reload_completed && TARGET_CPU_ZARCH"
[(set (match_dup 2) (label_ref (match_dup 3)))
(parallel
- [(unspec [(match_dup 1) (mem:BLK (match_dup 2))
+ [(unspec [(match_dup 1) (mem:BLK (match_dup 2))
(label_ref (match_dup 3))] UNSPEC_EXECUTE)
(set (match_dup 0) (const_int 0))
(use (const_int 1))
(clobber (reg:CC CC_REGNUM))])]
"operands[3] = gen_label_rtx ();")
-; Initialize a block of arbitrary length with (operands[2] % 256).
+; Initialize a block of arbitrary length with (operands[2] % 256).
(define_expand "setmem_long"
[(parallel
rtx addr0 = gen_lowpart (Pmode, gen_highpart (word_mode, reg0));
rtx len0 = gen_lowpart (Pmode, reg0);
- emit_insn (gen_rtx_CLOBBER (VOIDmode, reg0));
+ emit_clobber (reg0);
emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX));
emit_move_insn (len0, operands[1]);
(define_insn "*cmpmem_short"
[(set (reg:CCU CC_REGNUM)
- (compare:CCU (match_operand:BLK 0 "memory_operand" "Q,Q,Q")
- (match_operand:BLK 1 "memory_operand" "Q,Q,Q")))
- (use (match_operand 2 "nonmemory_operand" "n,a,a"))
- (use (match_operand 3 "immediate_operand" "X,R,X"))
- (clobber (match_scratch 4 "=X,X,&a"))]
+ (compare:CCU (match_operand:BLK 0 "memory_operand" "Q,Q,Q,Q")
+ (match_operand:BLK 1 "memory_operand" "Q,Q,Q,Q")))
+ (use (match_operand 2 "nonmemory_operand" "n,a,a,a"))
+ (use (match_operand 3 "immediate_operand" "X,R,X,X"))
+ (clobber (match_scratch 4 "=X,X,X,&a"))]
"(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode)
&& GET_MODE (operands[4]) == Pmode"
"#"
- [(set_attr "type" "cs")])
+ [(set_attr "type" "cs")
+ (set_attr "cpu_facility" "*,*,z10,*")])
(define_split
[(set (reg:CCU CC_REGNUM)
(match_operand:BLK 1 "memory_operand" "")))
(use (match_operand 2 "register_operand" ""))
(use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
+ (clobber (scratch))]
+ "TARGET_Z10 && reload_completed"
+ [(parallel
+ [(unspec [(match_dup 2) (const_int 0)
+ (label_ref (match_dup 4))] UNSPEC_EXECUTE)
+ (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
+ (use (const_int 1))])]
+ "operands[4] = gen_label_rtx ();")
+
+(define_split
+ [(set (reg:CCU CC_REGNUM)
+ (compare:CCU (match_operand:BLK 0 "memory_operand" "")
+ (match_operand:BLK 1 "memory_operand" "")))
+ (use (match_operand 2 "register_operand" ""))
+ (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
(clobber (match_operand 3 "register_operand" ""))]
"reload_completed && TARGET_CPU_ZARCH"
[(set (match_dup 3) (label_ref (match_dup 4)))
(parallel
- [(unspec [(match_dup 2) (mem:BLK (match_dup 3))
+ [(unspec [(match_dup 2) (mem:BLK (match_dup 3))
(label_ref (match_dup 4))] UNSPEC_EXECUTE)
(set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
(use (const_int 1))])]
rtx len0 = gen_lowpart (Pmode, reg0);
rtx len1 = gen_lowpart (Pmode, reg1);
- emit_insn (gen_rtx_CLOBBER (VOIDmode, reg0));
+ emit_clobber (reg0);
emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX));
emit_move_insn (len0, operands[2]);
- emit_insn (gen_rtx_CLOBBER (VOIDmode, reg1));
+ emit_clobber (reg1);
emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX));
emit_move_insn (len1, operands[2]);
(define_insn_and_split "cmpint"
[(set (match_operand:SI 0 "register_operand" "=d")
(unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
- UNSPEC_CMPINT))
+ UNSPEC_CCU_TO_INT))
(clobber (reg:CC CC_REGNUM))]
""
"#"
(define_insn_and_split "*cmpint_cc"
[(set (reg CC_REGNUM)
(compare (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
- UNSPEC_CMPINT)
+ UNSPEC_CCU_TO_INT)
(const_int 0)))
(set (match_operand:SI 0 "register_operand" "=d")
- (unspec:SI [(match_dup 1)] UNSPEC_CMPINT))]
+ (unspec:SI [(match_dup 1)] UNSPEC_CCU_TO_INT))]
"s390_match_ccmode (insn, CCSmode)"
"#"
"&& reload_completed"
(define_insn_and_split "*cmpint_sign"
[(set (match_operand:DI 0 "register_operand" "=d")
(sign_extend:DI (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
- UNSPEC_CMPINT)))
+ UNSPEC_CCU_TO_INT)))
(clobber (reg:CC CC_REGNUM))]
"TARGET_64BIT"
"#"
(define_insn_and_split "*cmpint_sign_cc"
[(set (reg CC_REGNUM)
- (compare (ashiftrt:DI (ashift:DI (subreg:DI
+ (compare (ashiftrt:DI (ashift:DI (subreg:DI
(unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
- UNSPEC_CMPINT) 0)
+ UNSPEC_CCU_TO_INT) 0)
(const_int 32)) (const_int 32))
(const_int 0)))
(set (match_operand:DI 0 "register_operand" "=d")
- (sign_extend:DI (unspec:SI [(match_dup 1)] UNSPEC_CMPINT)))]
+ (sign_extend:DI (unspec:SI [(match_dup 1)] UNSPEC_CCU_TO_INT)))]
"s390_match_ccmode (insn, CCSmode) && TARGET_64BIT"
"#"
"&& reload_completed"
"@
icm\t%0,%2,%S1
icmy\t%0,%2,%S1"
- [(set_attr "op_type" "RS,RSY")])
+ [(set_attr "op_type" "RS,RSY")
+ (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
(define_insn "*sethighpartdi_64"
[(set (match_operand:DI 0 "register_operand" "=d")
(clobber (reg:CC CC_REGNUM))]
"TARGET_64BIT"
"icmh\t%0,%2,%S1"
- [(set_attr "op_type" "RSY")])
+ [(set_attr "op_type" "RSY")
+ (set_attr "z10prop" "z10_super")])
(define_insn "*sethighpartdi_31"
[(set (match_operand:DI 0 "register_operand" "=d,d")
"@
icm\t%0,%2,%S1
icmy\t%0,%2,%S1"
- [(set_attr "op_type" "RS,RSY")])
+ [(set_attr "op_type" "RS,RSY")
+ (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
+
(define_insn_and_split "*extzv<mode>"
[(set (match_operand:GPR 0 "register_operand" "=d")
FAIL;
})
+(define_insn "*insv<mode>_z10"
+ [(set (zero_extract:GPR (match_operand:GPR 0 "nonimmediate_operand" "+d")
+ (match_operand 1 "const_int_operand" "I")
+ (match_operand 2 "const_int_operand" "I"))
+ (match_operand:GPR 3 "nonimmediate_operand" "d"))
+ (clobber (reg:CC CC_REGNUM))]
+ "TARGET_Z10
+ && (INTVAL (operands[1]) + INTVAL (operands[2])) <=
+ GET_MODE_BITSIZE (<MODE>mode)"
+{
+ int start = INTVAL (operands[2]);
+ int size = INTVAL (operands[1]);
+ int offset = 64 - GET_MODE_BITSIZE (<MODE>mode);
+
+ operands[2] = GEN_INT (offset + start); /* start bit position */
+ operands[1] = GEN_INT (offset + start + size - 1); /* end bit position */
+ operands[4] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) -
+ start - size); /* left shift count */
+
+ return "risbg\t%0,%3,%b2,%b1,%b4";
+}
+ [(set_attr "op_type" "RIE")
+ (set_attr "z10prop" "z10_super_E1")])
+
+; and op1 with a mask being 1 for the selected bits and 0 for the rest
+; and op3=op0 with a mask being 0 for the selected bits and 1 for the rest
+(define_insn "*insv<mode>_z10_noshift"
+ [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
+ (ior:GPR (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "d")
+ (match_operand 2 "const_int_operand" "n"))
+ (and:GPR (match_operand:GPR 3 "nonimmediate_operand" "0")
+ (match_operand 4 "const_int_operand" "n"))))
+ (clobber (reg:CC CC_REGNUM))]
+ "TARGET_Z10
+ && s390_contiguous_bitmask_p (INTVAL (operands[2]),
+ GET_MODE_BITSIZE (<MODE>mode), NULL, NULL)
+ && INTVAL (operands[2]) == ~(INTVAL (operands[4]))"
+
+{
+ int start;
+ int size;
+
+ s390_contiguous_bitmask_p (INTVAL (operands[2]),
+ GET_MODE_BITSIZE (<MODE>mode), &start, &size);
+
+ operands[5] = GEN_INT (64 - start - size); /* start bit position */
+ operands[6] = GEN_INT (64 - 1 - start); /* end bit position */
+ operands[7] = const0_rtx; /* left shift count */
+
+ return "risbg\t%0,%1,%b5,%b6,%b7";
+}
+ [(set_attr "op_type" "RIE")
+ (set_attr "z10prop" "z10_super_E1")])
+
+; and op1 with a mask being 1 for the selected bits and 0 for the rest
+(define_insn "*insv<mode>_or_z10_noshift"
+ [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
+ (ior:GPR (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "d")
+ (match_operand 2 "const_int_operand" "n"))
+ (match_operand:GPR 3 "nonimmediate_operand" "0")))
+ (clobber (reg:CC CC_REGNUM))]
+ "TARGET_Z10
+ && s390_contiguous_bitmask_p (INTVAL (operands[2]),
+ GET_MODE_BITSIZE (<MODE>mode), NULL, NULL)"
+{
+ int start;
+ int size;
+
+ s390_contiguous_bitmask_p (INTVAL (operands[2]),
+ GET_MODE_BITSIZE (<MODE>mode), &start, &size);
+
+ operands[4] = GEN_INT (64 - start - size); /* start bit position */
+ operands[5] = GEN_INT (64 - 1 - start); /* end bit position */
+ operands[6] = const0_rtx; /* left shift count */
+
+ return "rosbg\t%0,%1,%b4,%b5,%b6";
+}
+ [(set_attr "op_type" "RIE")])
+
(define_insn "*insv<mode>_mem_reg"
[(set (zero_extract:P (match_operand:QI 0 "memory_operand" "+Q,S")
(match_operand 1 "const_int_operand" "n,n")
int size = INTVAL (operands[1]) / BITS_PER_UNIT;
operands[1] = GEN_INT ((1ul << size) - 1);
- return (which_alternative == 0) ? "stcm\t%2,%1,%S0"
+ return (which_alternative == 0) ? "stcm\t%2,%1,%S0"
: "stcmy\t%2,%1,%S0";
}
- [(set_attr "op_type" "RS,RSY")])
+ [(set_attr "op_type" "RS,RSY")
+ (set_attr "z10prop" "z10_super,z10_super")])
(define_insn "*insvdi_mem_reghigh"
[(set (zero_extract:DI (match_operand:QI 0 "memory_operand" "+QS")
operands[1] = GEN_INT ((1ul << size) - 1);
return "stcmh\t%2,%1,%S0";
}
-[(set_attr "op_type" "RSY")])
+[(set_attr "op_type" "RSY")
+ (set_attr "z10prop" "z10_super")])
(define_insn "*insv<mode>_reg_imm"
[(set (zero_extract:P (match_operand:P 0 "register_operand" "+d")
default: gcc_unreachable();
}
}
- [(set_attr "op_type" "RI")])
+ [(set_attr "op_type" "RI")
+ (set_attr "z10prop" "z10_super_E1")])
+
+; Update the left-most 32 bit of a DI.
+(define_insn "*insv_h_di_reg_extimm"
+ [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+d")
+ (const_int 32)
+ (const_int 0))
+ (match_operand:DI 1 "const_int_operand" "n"))]
+ "TARGET_EXTIMM"
+ "iihf\t%0,%o1"
+ [(set_attr "op_type" "RIL")
+ (set_attr "z10prop" "z10_fwd_E1")])
-(define_insn "*insv<mode>_reg_extimm"
+; Update the right-most 32 bit of a DI, or the whole of a SI.
+(define_insn "*insv_l<mode>_reg_extimm"
[(set (zero_extract:P (match_operand:P 0 "register_operand" "+d")
(const_int 32)
(match_operand 1 "const_int_operand" "n"))
(match_operand:P 2 "const_int_operand" "n"))]
"TARGET_EXTIMM
- && INTVAL (operands[1]) >= 0
- && INTVAL (operands[1]) < BITS_PER_WORD
- && INTVAL (operands[1]) % 32 == 0"
-{
- switch (BITS_PER_WORD - INTVAL (operands[1]))
- {
- case 64: return "iihf\t%0,%o2"; break;
- case 32: return "iilf\t%0,%o2"; break;
- default: gcc_unreachable();
- }
-}
- [(set_attr "op_type" "RIL")])
+ && BITS_PER_WORD - INTVAL (operands[1]) == 32"
+ "iilf\t%0,%o2"
+ [(set_attr "op_type" "RIL")
+ (set_attr "z10prop" "z10_fwd_A1")])
;
; extendsidi2 instruction pattern(s).
{
if (!TARGET_64BIT)
{
- emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[0]));
+ emit_clobber (operands[0]);
emit_move_insn (gen_highpart (SImode, operands[0]), operands[1]);
emit_move_insn (gen_lowpart (SImode, operands[0]), const0_rtx);
emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (32)));
})
(define_insn "*extendsidi2"
- [(set (match_operand:DI 0 "register_operand" "=d,d")
- (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m")))]
+ [(set (match_operand:DI 0 "register_operand" "=d,d,d")
+ (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,RT,b")))]
"TARGET_64BIT"
"@
lgfr\t%0,%1
- lgf\t%0,%1"
- [(set_attr "op_type" "RRE,RXY")])
+ lgf\t%0,%1
+ lgfrl\t%0,%1"
+ [(set_attr "op_type" "RRE,RXY,RIL")
+ (set_attr "type" "*,*,larl")
+ (set_attr "cpu_facility" "*,*,z10")
+ (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")])
;
; extend(hi|qi)(si|di)2 instruction pattern(s).
;
(define_insn "*extendhidi2_extimm"
- [(set (match_operand:DI 0 "register_operand" "=d,d")
- (sign_extend:DI (match_operand:HI 1 "nonimmediate_operand" "d,m")))]
+ [(set (match_operand:DI 0 "register_operand" "=d,d,d")
+ (sign_extend:DI (match_operand:HI 1 "general_operand" "d,RT,b")))]
"TARGET_64BIT && TARGET_EXTIMM"
"@
lghr\t%0,%1
- lgh\t%0,%1"
- [(set_attr "op_type" "RRE,RXY")])
+ lgh\t%0,%1
+ lghrl\t%0,%1"
+ [(set_attr "op_type" "RRE,RXY,RIL")
+ (set_attr "type" "*,*,larl")
+ (set_attr "cpu_facility" "extimm,extimm,z10")
+ (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")])
(define_insn "*extendhidi2"
[(set (match_operand:DI 0 "register_operand" "=d")
- (sign_extend:DI (match_operand:HI 1 "memory_operand" "m")))]
+ (sign_extend:DI (match_operand:HI 1 "memory_operand" "RT")))]
"TARGET_64BIT"
"lgh\t%0,%1"
- [(set_attr "op_type" "RXY")])
+ [(set_attr "op_type" "RXY")
+ (set_attr "z10prop" "z10_super_E1")])
;
; extendhisi2 instruction pattern(s).
;
(define_insn "*extendhisi2_extimm"
- [(set (match_operand:SI 0 "register_operand" "=d,d,d")
- (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "d,R,T")))]
+ [(set (match_operand:SI 0 "register_operand" "=d,d,d,d")
+ (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" " d,R,T,b")))]
"TARGET_EXTIMM"
"@
lhr\t%0,%1
lh\t%0,%1
- lhy\t%0,%1"
- [(set_attr "op_type" "RRE,RX,RXY")])
+ lhy\t%0,%1
+ lhrl\t%0,%1"
+ [(set_attr "op_type" "RRE,RX,RXY,RIL")
+ (set_attr "type" "*,*,*,larl")
+ (set_attr "cpu_facility" "extimm,extimm,extimm,z10")
+ (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1")])
(define_insn "*extendhisi2"
[(set (match_operand:SI 0 "register_operand" "=d,d")
"@
lh\t%0,%1
lhy\t%0,%1"
- [(set_attr "op_type" "RX,RXY")])
+ [(set_attr "op_type" "RX,RXY")
+ (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
;
; extendqi(si|di)2 instruction pattern(s).
;
+; lbr, lgbr, lb, lgb
(define_insn "*extendqi<mode>2_extimm"
[(set (match_operand:GPR 0 "register_operand" "=d,d")
- (sign_extend:GPR (match_operand:QI 1 "nonimmediate_operand" "d,m")))]
+ (sign_extend:GPR (match_operand:QI 1 "nonimmediate_operand" "d,RT")))]
"TARGET_EXTIMM"
"@
l<g>br\t%0,%1
l<g>b\t%0,%1"
- [(set_attr "op_type" "RRE,RXY")])
+ [(set_attr "op_type" "RRE,RXY")
+ (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
+; lb, lgb
(define_insn "*extendqi<mode>2"
[(set (match_operand:GPR 0 "register_operand" "=d")
- (sign_extend:GPR (match_operand:QI 1 "memory_operand" "m")))]
+ (sign_extend:GPR (match_operand:QI 1 "memory_operand" "RT")))]
"!TARGET_EXTIMM && TARGET_LONG_DISPLACEMENT"
"l<g>b\t%0,%1"
- [(set_attr "op_type" "RXY")])
+ [(set_attr "op_type" "RXY")
+ (set_attr "z10prop" "z10_super_E1")])
(define_insn_and_split "*extendqi<mode>2_short_displ"
[(set (match_operand:GPR 0 "register_operand" "=d")
})
;
-; extendqihi2 instruction pattern(s).
-;
-
-
-;
; zero_extendsidi2 instruction pattern(s).
;
{
if (!TARGET_64BIT)
{
- emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[0]));
+ emit_clobber (operands[0]);
emit_move_insn (gen_lowpart (SImode, operands[0]), operands[1]);
emit_move_insn (gen_highpart (SImode, operands[0]), const0_rtx);
DONE;
})
(define_insn "*zero_extendsidi2"
- [(set (match_operand:DI 0 "register_operand" "=d,d")
- (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m")))]
+ [(set (match_operand:DI 0 "register_operand" "=d,d,d")
+ (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,RT,b")))]
"TARGET_64BIT"
"@
llgfr\t%0,%1
- llgf\t%0,%1"
- [(set_attr "op_type" "RRE,RXY")])
+ llgf\t%0,%1
+ llgfrl\t%0,%1"
+ [(set_attr "op_type" "RRE,RXY,RIL")
+ (set_attr "type" "*,*,larl")
+ (set_attr "cpu_facility" "*,*,z10")
+ (set_attr "z10prop" "z10_fwd_E1,z10_fwd_A3,z10_fwd_A3")])
;
; LLGT-type instructions (zero-extend from 31 bit to 64 bit).
(define_insn "*llgt_sidi"
[(set (match_operand:DI 0 "register_operand" "=d")
- (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "m") 0)
+ (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "RT") 0)
(const_int 2147483647)))]
"TARGET_64BIT"
"llgt\t%0,%1"
- [(set_attr "op_type" "RXE")])
+ [(set_attr "op_type" "RXE")
+ (set_attr "z10prop" "z10_super_E1")])
(define_insn_and_split "*llgt_sidi_split"
[(set (match_operand:DI 0 "register_operand" "=d")
- (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "m") 0)
+ (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "RT") 0)
(const_int 2147483647)))
(clobber (reg:CC CC_REGNUM))]
"TARGET_64BIT"
(define_insn "*llgt_sisi"
[(set (match_operand:SI 0 "register_operand" "=d,d")
- (and:SI (match_operand:SI 1 "nonimmediate_operand" "d,m")
+ (and:SI (match_operand:SI 1 "nonimmediate_operand" "d,RT")
(const_int 2147483647)))]
"TARGET_ZARCH"
"@
llgtr\t%0,%1
llgt\t%0,%1"
- [(set_attr "op_type" "RRE,RXE")])
+ [(set_attr "op_type" "RRE,RXE")
+ (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
(define_insn "*llgt_didi"
[(set (match_operand:DI 0 "register_operand" "=d,d")
"@
llgtr\t%0,%1
llgt\t%0,%N1"
- [(set_attr "op_type" "RRE,RXE")])
+ [(set_attr "op_type" "RRE,RXE")
+ (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
(define_split
[(set (match_operand:GPR 0 "register_operand" "")
}
else if (!TARGET_EXTIMM)
{
- rtx bitcount = GEN_INT (GET_MODE_BITSIZE(DImode) -
+ rtx bitcount = GEN_INT (GET_MODE_BITSIZE(DImode) -
GET_MODE_BITSIZE(<MODE>mode));
operands[1] = gen_lowpart (DImode, operands[1]);
emit_insn (gen_ashldi3 (operands[0], operands[1], bitcount));
if (!TARGET_EXTIMM)
{
operands[1] = gen_lowpart (SImode, operands[1]);
- emit_insn (gen_andsi3 (operands[0], operands[1],
+ emit_insn (gen_andsi3 (operands[0], operands[1],
GEN_INT ((1 << GET_MODE_BITSIZE(<MODE>mode)) - 1)));
DONE;
}
})
+; llhrl, llghrl
+(define_insn "*zero_extendhi<mode>2_z10"
+ [(set (match_operand:GPR 0 "register_operand" "=d,d,d")
+ (zero_extend:GPR (match_operand:HI 1 "nonimmediate_operand" "d,RT,b")))]
+ "TARGET_Z10"
+ "@
+ ll<g>hr\t%0,%1
+ ll<g>h\t%0,%1
+ ll<g>hrl\t%0,%1"
+ [(set_attr "op_type" "RXY,RRE,RIL")
+ (set_attr "type" "*,*,larl")
+ (set_attr "cpu_facility" "*,*,z10")
+ (set_attr "z10prop" "z10_super_E1,z10_fwd_A3,z10_fwd_A3")])
+
+; llhr, llcr, llghr, llgcr, llh, llc, llgh, llgc
(define_insn "*zero_extend<HQI:mode><GPR:mode>2_extimm"
[(set (match_operand:GPR 0 "register_operand" "=d,d")
- (zero_extend:GPR (match_operand:HQI 1 "nonimmediate_operand" "d,m")))]
+ (zero_extend:GPR (match_operand:HQI 1 "nonimmediate_operand" "d,RT")))]
"TARGET_EXTIMM"
"@
ll<g><hc>r\t%0,%1
ll<g><hc>\t%0,%1"
- [(set_attr "op_type" "RRE,RXY")])
+ [(set_attr "op_type" "RRE,RXY")
+ (set_attr "z10prop" "z10_super_E1,z10_fwd_A3")])
+; llgh, llgc
(define_insn "*zero_extend<HQI:mode><GPR:mode>2"
[(set (match_operand:GPR 0 "register_operand" "=d")
- (zero_extend:GPR (match_operand:HQI 1 "memory_operand" "m")))]
+ (zero_extend:GPR (match_operand:HQI 1 "memory_operand" "RT")))]
"TARGET_ZARCH && !TARGET_EXTIMM"
"llg<hc>\t%0,%1"
- [(set_attr "op_type" "RXY")])
+ [(set_attr "op_type" "RXY")
+ (set_attr "z10prop" "z10_fwd_A3")])
(define_insn_and_split "*zero_extendhisi2_31"
[(set (match_operand:SI 0 "register_operand" "=&d")
(define_insn_and_split "*zero_extendqisi2_31"
[(set (match_operand:SI 0 "register_operand" "=&d")
- (zero_extend:SI (match_operand:QI 1 "memory_operand" "m")))]
+ (zero_extend:SI (match_operand:QI 1 "memory_operand" "RT")))]
"!TARGET_ZARCH"
"#"
"&& reload_completed"
(define_insn "*zero_extendqihi2_64"
[(set (match_operand:HI 0 "register_operand" "=d")
- (zero_extend:HI (match_operand:QI 1 "memory_operand" "m")))]
+ (zero_extend:HI (match_operand:QI 1 "memory_operand" "RT")))]
"TARGET_ZARCH && !TARGET_EXTIMM"
"llgc\t%0,%1"
- [(set_attr "op_type" "RXY")])
+ [(set_attr "op_type" "RXY")
+ (set_attr "z10prop" "z10_fwd_A3")])
(define_insn_and_split "*zero_extendqihi2_31"
[(set (match_operand:HI 0 "register_operand" "=&d")
- (zero_extend:HI (match_operand:QI 1 "memory_operand" "m")))]
+ (zero_extend:HI (match_operand:QI 1 "memory_operand" "RT")))]
"!TARGET_ZARCH"
"#"
"&& reload_completed"
(set (strict_low_part (match_dup 2)) (match_dup 1))]
"operands[2] = gen_lowpart (QImode, operands[0]);")
-
;
-; fixuns_trunc(sf|df)(si|di)2 and fix_trunc(sf|df)(si|di)2 instruction pattern(s).
+; fixuns_trunc(dd|td)di2 instruction pattern(s).
;
-(define_expand "fixuns_trunc<FPR:mode><GPR:mode>2"
- [(set (match_operand:GPR 0 "register_operand" "")
- (unsigned_fix:GPR (match_operand:FPR 1 "register_operand" "")))]
- "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
+(define_expand "fixuns_truncdddi2"
+ [(parallel
+ [(set (match_operand:DI 0 "register_operand" "")
+ (unsigned_fix:DI (match_operand:DD 1 "register_operand" "")))
+ (clobber (match_scratch:TD 2 "=f"))])]
+
+ "TARGET_HARD_DFP"
{
rtx label1 = gen_label_rtx ();
rtx label2 = gen_label_rtx ();
- rtx temp = gen_reg_rtx (<FPR:MODE>mode);
+ rtx temp = gen_reg_rtx (TDmode);
REAL_VALUE_TYPE cmp, sub;
-
- operands[1] = force_reg (<FPR:MODE>mode, operands[1]);
- real_2expN (&cmp, GET_MODE_BITSIZE(<GPR:MODE>mode) - 1);
- real_2expN (&sub, GET_MODE_BITSIZE(<GPR:MODE>mode));
-
- emit_insn (gen_cmp<FPR:mode> (operands[1],
- CONST_DOUBLE_FROM_REAL_VALUE (cmp, <FPR:MODE>mode)));
+
+ decimal_real_from_string (&cmp, "9223372036854775808.0"); /* 2^63 */
+ decimal_real_from_string (&sub, "18446744073709551616.0"); /* 2^64 */
+
+ /* 2^63 can't be represented as 64bit DFP number with full precision. The
+ solution is doing the check and the subtraction in TD mode and using a
+ TD -> DI convert afterwards. */
+ emit_insn (gen_extendddtd2 (temp, operands[1]));
+ temp = force_reg (TDmode, temp);
+ emit_insn (gen_cmptd (temp,
+ CONST_DOUBLE_FROM_REAL_VALUE (cmp, TDmode)));
emit_jump_insn (gen_blt (label1));
- emit_insn (gen_sub<FPR:mode>3 (temp, operands[1],
- CONST_DOUBLE_FROM_REAL_VALUE (sub, <FPR:MODE>mode)));
- emit_insn (gen_fix_trunc<FPR:mode><GPR:mode>2_ieee (operands[0], temp,
- GEN_INT(7)));
+ emit_insn (gen_subtd3 (temp, temp,
+ CONST_DOUBLE_FROM_REAL_VALUE (sub, TDmode)));
+ emit_insn (gen_fix_trunctddi2_dfp (operands[0], temp, GEN_INT (11)));
emit_jump (label2);
emit_label (label1);
- emit_insn (gen_fix_trunc<FPR:mode><GPR:mode>2_ieee (operands[0],
- operands[1], GEN_INT(5)));
+ emit_insn (gen_fix_truncdddi2_dfp (operands[0], operands[1], GEN_INT (9)));
emit_label (label2);
DONE;
})
-(define_expand "fix_trunc<FPR:mode>di2"
+(define_expand "fixuns_trunctddi2"
[(set (match_operand:DI 0 "register_operand" "")
- (fix:DI (match_operand:FPR 1 "nonimmediate_operand" "")))]
- "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
+ (unsigned_fix:DI (match_operand:TD 1 "register_operand" "")))]
+ "TARGET_HARD_DFP"
{
- operands[1] = force_reg (<FPR:MODE>mode, operands[1]);
- emit_insn (gen_fix_trunc<FPR:mode>di2_ieee (operands[0], operands[1],
- GEN_INT(5)));
- DONE;
-})
+ rtx label1 = gen_label_rtx ();
+ rtx label2 = gen_label_rtx ();
+ rtx temp = gen_reg_rtx (TDmode);
+ REAL_VALUE_TYPE cmp, sub;
-(define_insn "fix_trunc<FPR:mode><GPR:mode>2_ieee"
- [(set (match_operand:GPR 0 "register_operand" "=d")
- (fix:GPR (match_operand:FPR 1 "register_operand" "f")))
- (unspec:GPR [(match_operand:GPR 2 "immediate_operand" "K")] UNSPEC_ROUND)
- (clobber (reg:CC CC_REGNUM))]
- "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
- "c<GPR:gf><FPR:de>br\t%0,%h2,%1"
- [(set_attr "op_type" "RRE")
- (set_attr "type" "ftoi")])
+ operands[1] = force_reg (TDmode, operands[1]);
+ decimal_real_from_string (&cmp, "9223372036854775808.0"); /* 2^63 */
+ decimal_real_from_string (&sub, "18446744073709551616.0"); /* 2^64 */
-;
-; fix_truncdfsi2 instruction pattern(s).
-;
+ emit_insn (gen_cmptd (operands[1],
+ CONST_DOUBLE_FROM_REAL_VALUE (cmp, TDmode)));
+ emit_jump_insn (gen_blt (label1));
+ emit_insn (gen_subtd3 (temp, operands[1],
+ CONST_DOUBLE_FROM_REAL_VALUE (sub, TDmode)));
+ emit_insn (gen_fix_trunctddi2_dfp (operands[0], temp, GEN_INT (11)));
+ emit_jump (label2);
-(define_expand "fix_truncdfsi2"
- [(set (match_operand:SI 0 "register_operand" "")
- (fix:SI (match_operand:DF 1 "nonimmediate_operand" "")))]
+ emit_label (label1);
+ emit_insn (gen_fix_trunctddi2_dfp (operands[0], operands[1], GEN_INT (9)));
+ emit_label (label2);
+ DONE;
+})
+
+;
+; fixuns_trunc(sf|df)(si|di)2 and fix_trunc(sf|df)(si|di)2
+; instruction pattern(s).
+;
+
+(define_expand "fixuns_trunc<BFP:mode><GPR:mode>2"
+ [(set (match_operand:GPR 0 "register_operand" "")
+ (unsigned_fix:GPR (match_operand:BFP 1 "register_operand" "")))]
"TARGET_HARD_FLOAT"
{
- if (TARGET_IBM_FLOAT)
- {
- /* This is the algorithm from POP chapter A.5.7.2. */
+ rtx label1 = gen_label_rtx ();
+ rtx label2 = gen_label_rtx ();
+ rtx temp = gen_reg_rtx (<BFP:MODE>mode);
+ REAL_VALUE_TYPE cmp, sub;
- rtx temp = assign_stack_local (BLKmode, 8, BITS_PER_WORD);
- rtx two31r = s390_gen_rtx_const_DI (0x4f000000, 0x08000000);
- rtx two32 = s390_gen_rtx_const_DI (0x4e000001, 0x00000000);
+ operands[1] = force_reg (<BFP:MODE>mode, operands[1]);
+ real_2expN (&cmp, GET_MODE_BITSIZE(<GPR:MODE>mode) - 1, <BFP:MODE>mode);
+ real_2expN (&sub, GET_MODE_BITSIZE(<GPR:MODE>mode), <BFP:MODE>mode);
- operands[1] = force_reg (DFmode, operands[1]);
- emit_insn (gen_fix_truncdfsi2_ibm (operands[0], operands[1],
- two31r, two32, temp));
- }
- else
- {
- operands[1] = force_reg (DFmode, operands[1]);
- emit_insn (gen_fix_truncdfsi2_ieee (operands[0], operands[1], GEN_INT (5)));
- }
+ emit_insn (gen_cmp<BFP:mode> (operands[1],
+ CONST_DOUBLE_FROM_REAL_VALUE (cmp, <BFP:MODE>mode)));
+ emit_jump_insn (gen_blt (label1));
+ emit_insn (gen_sub<BFP:mode>3 (temp, operands[1],
+ CONST_DOUBLE_FROM_REAL_VALUE (sub, <BFP:MODE>mode)));
+ emit_insn (gen_fix_trunc<BFP:mode><GPR:mode>2_bfp (operands[0], temp,
+ GEN_INT (7)));
+ emit_jump (label2);
+ emit_label (label1);
+ emit_insn (gen_fix_trunc<BFP:mode><GPR:mode>2_bfp (operands[0],
+ operands[1], GEN_INT (5)));
+ emit_label (label2);
DONE;
})
-(define_insn "fix_truncdfsi2_ibm"
- [(set (match_operand:SI 0 "register_operand" "=d")
- (fix:SI (match_operand:DF 1 "nonimmediate_operand" "+f")))
- (use (match_operand:DI 2 "immediate_operand" "m"))
- (use (match_operand:DI 3 "immediate_operand" "m"))
- (use (match_operand:BLK 4 "memory_operand" "m"))
- (clobber (reg:CC CC_REGNUM))]
- "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
+(define_expand "fix_trunc<DSF:mode><GPR:mode>2"
+ [(set (match_operand:GPR 0 "register_operand" "")
+ (fix:GPR (match_operand:DSF 1 "register_operand" "")))]
+ "TARGET_HARD_FLOAT"
{
- output_asm_insn ("sd\t%1,%2", operands);
- output_asm_insn ("aw\t%1,%3", operands);
- output_asm_insn ("std\t%1,%4", operands);
- output_asm_insn ("xi\t%N4,128", operands);
- return "l\t%0,%N4";
-}
- [(set_attr "length" "20")])
+ emit_insn (gen_fix_trunc<DSF:mode><GPR:mode>2_bfp (operands[0], operands[1],
+ GEN_INT (5)));
+ DONE;
+})
+
+; cgxbr, cgdbr, cgebr, cfxbr, cfdbr, cfebr
+(define_insn "fix_trunc<BFP:mode><GPR:mode>2_bfp"
+ [(set (match_operand:GPR 0 "register_operand" "=d")
+ (fix:GPR (match_operand:BFP 1 "register_operand" "f")))
+ (unspec:GPR [(match_operand:GPR 2 "immediate_operand" "K")] UNSPEC_ROUND)
+ (clobber (reg:CC CC_REGNUM))]
+ "TARGET_HARD_FLOAT"
+ "c<GPR:gf><BFP:xde>br\t%0,%h2,%1"
+ [(set_attr "op_type" "RRE")
+ (set_attr "type" "ftoi")])
+
;
-; fix_truncsfsi2 instruction pattern(s).
+; fix_trunc(td|dd)di2 instruction pattern(s).
;
-(define_expand "fix_truncsfsi2"
- [(set (match_operand:SI 0 "register_operand" "")
- (fix:SI (match_operand:SF 1 "nonimmediate_operand" "")))]
- "TARGET_HARD_FLOAT"
+(define_expand "fix_trunc<mode>di2"
+ [(set (match_operand:DI 0 "register_operand" "")
+ (fix:DI (match_operand:DFP 1 "nonimmediate_operand" "")))]
+ "TARGET_64BIT && TARGET_HARD_DFP"
{
- if (TARGET_IBM_FLOAT)
- {
- /* Convert to DFmode and then use the POP algorithm. */
- rtx temp = gen_reg_rtx (DFmode);
- emit_insn (gen_extendsfdf2 (temp, operands[1]));
- emit_insn (gen_fix_truncdfsi2 (operands[0], temp));
- }
- else
- {
- operands[1] = force_reg (SFmode, operands[1]);
- emit_insn (gen_fix_truncsfsi2_ieee (operands[0], operands[1], GEN_INT (5)));
- }
-
+ operands[1] = force_reg (<MODE>mode, operands[1]);
+ emit_insn (gen_fix_trunc<mode>di2_dfp (operands[0], operands[1],
+ GEN_INT (9)));
DONE;
})
-;
-; floatdi(df|sf)2 instruction pattern(s).
-;
+; cgxtr, cgdtr
+(define_insn "fix_trunc<DFP:mode>di2_dfp"
+ [(set (match_operand:DI 0 "register_operand" "=d")
+ (fix:DI (match_operand:DFP 1 "register_operand" "f")))
+ (unspec:DI [(match_operand:DI 2 "immediate_operand" "K")] UNSPEC_ROUND)
+ (clobber (reg:CC CC_REGNUM))]
+ "TARGET_64BIT && TARGET_HARD_DFP"
+ "cg<DFP:xde>tr\t%0,%h2,%1"
+ [(set_attr "op_type" "RRF")
+ (set_attr "type" "ftoidfp")])
-(define_insn "floatdi<mode>2"
- [(set (match_operand:FPR 0 "register_operand" "=f")
- (float:FPR (match_operand:DI 1 "register_operand" "d")))]
- "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
- "c<de>gbr\t%0,%1"
- [(set_attr "op_type" "RRE")
- (set_attr "type" "itof" )])
;
-; floatsidf2 instruction pattern(s).
+; fix_trunctf(si|di)2 instruction pattern(s).
;
-(define_expand "floatsidf2"
- [(set (match_operand:DF 0 "register_operand" "")
- (float:DF (match_operand:SI 1 "register_operand" "")))]
+(define_expand "fix_trunctf<mode>2"
+ [(parallel [(set (match_operand:GPR 0 "register_operand" "")
+ (fix:GPR (match_operand:TF 1 "register_operand" "")))
+ (unspec:GPR [(const_int 5)] UNSPEC_ROUND)
+ (clobber (reg:CC CC_REGNUM))])]
"TARGET_HARD_FLOAT"
-{
- if (TARGET_IBM_FLOAT)
- {
- /* This is the algorithm from POP chapter A.5.7.1. */
+ "")
- rtx temp = assign_stack_local (BLKmode, 8, BITS_PER_WORD);
- rtx two31 = s390_gen_rtx_const_DI (0x4e000000, 0x80000000);
- emit_insn (gen_floatsidf2_ibm (operands[0], operands[1], two31, temp));
- DONE;
- }
-})
+;
+; float(si|di)(tf|df|sf|td|dd)2 instruction pattern(s).
+;
-(define_insn "floatsidf2_ieee"
- [(set (match_operand:DF 0 "register_operand" "=f")
- (float:DF (match_operand:SI 1 "register_operand" "d")))]
- "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
- "cdfbr\t%0,%1"
+; cxgbr, cdgbr, cegbr, cxgtr, cdgtr
+(define_insn "floatdi<mode>2"
+ [(set (match_operand:FP 0 "register_operand" "=f")
+ (float:FP (match_operand:DI 1 "register_operand" "d")))]
+ "TARGET_64BIT && TARGET_HARD_FLOAT"
+ "c<xde>g<bt>r\t%0,%1"
[(set_attr "op_type" "RRE")
- (set_attr "type" "itof" )])
+ (set_attr "type" "itof<mode>" )])
+
+; cxfbr, cdfbr, cefbr
+(define_insn "floatsi<mode>2"
+ [(set (match_operand:BFP 0 "register_operand" "=f")
+ (float:BFP (match_operand:SI 1 "register_operand" "d")))]
+ "TARGET_HARD_FLOAT"
+ "c<xde>fbr\t%0,%1"
+ [(set_attr "op_type" "RRE")
+ (set_attr "type" "itof<mode>" )])
-(define_insn "floatsidf2_ibm"
- [(set (match_operand:DF 0 "register_operand" "=f")
- (float:DF (match_operand:SI 1 "register_operand" "d")))
- (use (match_operand:DI 2 "immediate_operand" "m"))
- (use (match_operand:BLK 3 "memory_operand" "m"))
- (clobber (reg:CC CC_REGNUM))]
- "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
-{
- output_asm_insn ("st\t%1,%N3", operands);
- output_asm_insn ("xi\t%N3,128", operands);
- output_asm_insn ("mvc\t%O3(4,%R3),%2", operands);
- output_asm_insn ("ld\t%0,%3", operands);
- return "sd\t%0,%2";
-}
- [(set_attr "length" "20")])
;
-; floatsisf2 instruction pattern(s).
+; truncdfsf2 instruction pattern(s).
;
-(define_expand "floatsisf2"
- [(set (match_operand:SF 0 "register_operand" "")
- (float:SF (match_operand:SI 1 "register_operand" "")))]
- "TARGET_HARD_FLOAT"
-{
- if (TARGET_IBM_FLOAT)
- {
- /* Use the POP algorithm to convert to DFmode and then truncate. */
- rtx temp = gen_reg_rtx (DFmode);
- emit_insn (gen_floatsidf2 (temp, operands[1]));
- emit_insn (gen_truncdfsf2 (operands[0], temp));
- DONE;
- }
-})
-
-(define_insn "floatsisf2_ieee"
+(define_insn "truncdfsf2"
[(set (match_operand:SF 0 "register_operand" "=f")
- (float:SF (match_operand:SI 1 "register_operand" "d")))]
- "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
- "cefbr\t%0,%1"
- [(set_attr "op_type" "RRE")
- (set_attr "type" "itof" )])
+ (float_truncate:SF (match_operand:DF 1 "register_operand" "f")))]
+ "TARGET_HARD_FLOAT"
+ "ledbr\t%0,%1"
+ [(set_attr "op_type" "RRE")
+ (set_attr "type" "ftruncdf")])
;
-; truncdfsf2 instruction pattern(s).
+; trunctf(df|sf)2 instruction pattern(s).
;
-(define_expand "truncdfsf2"
- [(set (match_operand:SF 0 "register_operand" "")
- (float_truncate:SF (match_operand:DF 1 "register_operand" "")))]
+; ldxbr, lexbr
+(define_insn "trunctf<mode>2"
+ [(set (match_operand:DSF 0 "register_operand" "=f")
+ (float_truncate:DSF (match_operand:TF 1 "register_operand" "f")))
+ (clobber (match_scratch:TF 2 "=f"))]
"TARGET_HARD_FLOAT"
- "")
+ "l<xde>xbr\t%2,%1\;l<xde>r\t%0,%2"
+ [(set_attr "length" "6")
+ (set_attr "type" "ftrunctf")])
-(define_insn "truncdfsf2_ieee"
- [(set (match_operand:SF 0 "register_operand" "=f")
- (float_truncate:SF (match_operand:DF 1 "register_operand" "f")))]
- "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
- "ledbr\t%0,%1"
- [(set_attr "op_type" "RRE")])
+;
+; trunctddd2 and truncddsd2 instruction pattern(s).
+;
+
+(define_insn "trunctddd2"
+ [(set (match_operand:DD 0 "register_operand" "=f")
+ (float_truncate:DD (match_operand:TD 1 "register_operand" "f")))
+ (clobber (match_scratch:TD 2 "=f"))]
+ "TARGET_HARD_DFP"
+ "ldxtr\t%2,0,%1,0\;ldr\t%0,%2"
+ [(set_attr "length" "6")
+ (set_attr "type" "ftruncdd")])
+
+(define_insn "truncddsd2"
+ [(set (match_operand:SD 0 "register_operand" "=f")
+ (float_truncate:SD (match_operand:DD 1 "register_operand" "f")))]
+ "TARGET_HARD_DFP"
+ "ledtr\t%0,0,%1,0"
+ [(set_attr "op_type" "RRF")
+ (set_attr "type" "ftruncsd")])
-(define_insn "truncdfsf2_ibm"
- [(set (match_operand:SF 0 "register_operand" "=f,f")
- (float_truncate:SF (match_operand:DF 1 "nonimmediate_operand" "f,R")))]
- "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
+;
+; extend(sf|df)(df|tf)2 instruction pattern(s).
+;
+
+; ldebr, ldeb, lxdbr, lxdb, lxebr, lxeb
+(define_insn "extend<DSF:mode><BFP:mode>2"
+ [(set (match_operand:BFP 0 "register_operand" "=f,f")
+ (float_extend:BFP (match_operand:DSF 1 "nonimmediate_operand" "f,R")))]
+ "TARGET_HARD_FLOAT
+ && GET_MODE_SIZE (<BFP:MODE>mode) > GET_MODE_SIZE (<DSF:MODE>mode)"
"@
- ler\t%0,%1
- le\t%0,%1"
- [(set_attr "op_type" "RR,RX")
- (set_attr "type" "floadsf")])
+ l<BFP:xde><DSF:xde>br\t%0,%1
+ l<BFP:xde><DSF:xde>b\t%0,%1"
+ [(set_attr "op_type" "RRE,RXE")
+ (set_attr "type" "fsimp<BFP:mode>, fload<BFP:mode>")])
;
-; extendsfdf2 instruction pattern(s).
+; extendddtd2 and extendsddd2 instruction pattern(s).
;
-(define_expand "extendsfdf2"
- [(set (match_operand:DF 0 "register_operand" "")
- (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "")))]
- "TARGET_HARD_FLOAT"
+(define_insn "extendddtd2"
+ [(set (match_operand:TD 0 "register_operand" "=f")
+ (float_extend:TD (match_operand:DD 1 "register_operand" "f")))]
+ "TARGET_HARD_DFP"
+ "lxdtr\t%0,%1,0"
+ [(set_attr "op_type" "RRF")
+ (set_attr "type" "fsimptf")])
+
+(define_insn "extendsddd2"
+ [(set (match_operand:DD 0 "register_operand" "=f")
+ (float_extend:DD (match_operand:SD 1 "register_operand" "f")))]
+ "TARGET_HARD_DFP"
+ "ldetr\t%0,%1,0"
+ [(set_attr "op_type" "RRF")
+ (set_attr "type" "fsimptf")])
+
+; Binary <-> Decimal floating point trunc patterns
+;
+
+(define_insn "*trunc<BFP:mode><DFP_ALL:mode>2"
+ [(set (reg:DFP_ALL FPR0_REGNUM)
+ (float_truncate:DFP_ALL (reg:BFP FPR2_REGNUM)))
+ (use (reg:SI GPR0_REGNUM))
+ (clobber (reg:CC CC_REGNUM))]
+ "TARGET_HARD_DFP"
+ "pfpo")
+
+(define_insn "*trunc<DFP_ALL:mode><BFP:mode>2"
+ [(set (reg:BFP FPR0_REGNUM)
+ (float_truncate:BFP (reg:DFP_ALL FPR2_REGNUM)))
+ (use (reg:SI GPR0_REGNUM))
+ (clobber (reg:CC CC_REGNUM))]
+ "TARGET_HARD_DFP"
+ "pfpo")
+
+(define_expand "trunc<BFP:mode><DFP_ALL:mode>2"
+ [(set (reg:BFP FPR2_REGNUM) (match_operand:BFP 1 "nonimmediate_operand" ""))
+ (set (reg:SI GPR0_REGNUM) (match_dup 2))
+ (parallel
+ [(set (reg:DFP_ALL FPR0_REGNUM)
+ (float_truncate:DFP_ALL (reg:BFP FPR2_REGNUM)))
+ (use (reg:SI GPR0_REGNUM))
+ (clobber (reg:CC CC_REGNUM))])
+ (set (match_operand:DFP_ALL 0 "nonimmediate_operand" "")
+ (reg:DFP_ALL FPR0_REGNUM))]
+ "TARGET_HARD_DFP
+ && GET_MODE_SIZE (<BFP:MODE>mode) > GET_MODE_SIZE (<DFP_ALL:MODE>mode)"
{
- if (TARGET_IBM_FLOAT)
- {
- emit_insn (gen_extendsfdf2_ibm (operands[0], operands[1]));
- DONE;
- }
+ HOST_WIDE_INT flags;
+
+ flags = (PFPO_CONVERT |
+ PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP0_TYPE_SHIFT |
+ PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP1_TYPE_SHIFT);
+
+ operands[2] = GEN_INT (flags);
})
-(define_insn "extendsfdf2_ieee"
- [(set (match_operand:DF 0 "register_operand" "=f,f")
- (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,R")))]
- "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
- "@
- ldebr\t%0,%1
- ldeb\t%0,%1"
- [(set_attr "op_type" "RRE,RXE")
- (set_attr "type" "floadsf")])
+(define_expand "trunc<DFP_ALL:mode><BFP:mode>2"
+ [(set (reg:DFP_ALL FPR2_REGNUM)
+ (match_operand:DFP_ALL 1 "nonimmediate_operand" ""))
+ (set (reg:SI GPR0_REGNUM) (match_dup 2))
+ (parallel
+ [(set (reg:BFP FPR0_REGNUM) (float_truncate:BFP (reg:DFP_ALL FPR2_REGNUM)))
+ (use (reg:SI GPR0_REGNUM))
+ (clobber (reg:CC CC_REGNUM))])
+ (set (match_operand:BFP 0 "nonimmediate_operand" "") (reg:BFP FPR0_REGNUM))]
+ "TARGET_HARD_DFP
+ && GET_MODE_SIZE (<DFP_ALL:MODE>mode) >= GET_MODE_SIZE (<BFP:MODE>mode)"
+{
+ HOST_WIDE_INT flags;
+
+ flags = (PFPO_CONVERT |
+ PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP0_TYPE_SHIFT |
+ PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP1_TYPE_SHIFT);
+
+ operands[2] = GEN_INT (flags);
+})
+
+;
+; Binary <-> Decimal floating point extend patterns
+;
-(define_insn "extendsfdf2_ibm"
- [(set (match_operand:DF 0 "register_operand" "=f,f")
- (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,R")))
+(define_insn "*extend<BFP:mode><DFP_ALL:mode>2"
+ [(set (reg:DFP_ALL FPR0_REGNUM) (float_extend:DFP_ALL (reg:BFP FPR2_REGNUM)))
+ (use (reg:SI GPR0_REGNUM))
(clobber (reg:CC CC_REGNUM))]
- "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
- "@
- sdr\t%0,%0\;ler\t%0,%1
- sdr\t%0,%0\;le\t%0,%1"
- [(set_attr "length" "4,6")
- (set_attr "type" "floadsf")])
+ "TARGET_HARD_DFP"
+ "pfpo")
+
+(define_insn "*extend<DFP_ALL:mode><BFP:mode>2"
+ [(set (reg:BFP FPR0_REGNUM) (float_extend:BFP (reg:DFP_ALL FPR2_REGNUM)))
+ (use (reg:SI GPR0_REGNUM))
+ (clobber (reg:CC CC_REGNUM))]
+ "TARGET_HARD_DFP"
+ "pfpo")
+
+(define_expand "extend<BFP:mode><DFP_ALL:mode>2"
+ [(set (reg:BFP FPR2_REGNUM) (match_operand:BFP 1 "nonimmediate_operand" ""))
+ (set (reg:SI GPR0_REGNUM) (match_dup 2))
+ (parallel
+ [(set (reg:DFP_ALL FPR0_REGNUM)
+ (float_extend:DFP_ALL (reg:BFP FPR2_REGNUM)))
+ (use (reg:SI GPR0_REGNUM))
+ (clobber (reg:CC CC_REGNUM))])
+ (set (match_operand:DFP_ALL 0 "nonimmediate_operand" "")
+ (reg:DFP_ALL FPR0_REGNUM))]
+ "TARGET_HARD_DFP
+ && GET_MODE_SIZE (<BFP:MODE>mode) <= GET_MODE_SIZE (<DFP_ALL:MODE>mode)"
+{
+ HOST_WIDE_INT flags;
+
+ flags = (PFPO_CONVERT |
+ PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP0_TYPE_SHIFT |
+ PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP1_TYPE_SHIFT);
+
+ operands[2] = GEN_INT (flags);
+})
+
+(define_expand "extend<DFP_ALL:mode><BFP:mode>2"
+ [(set (reg:DFP_ALL FPR2_REGNUM)
+ (match_operand:DFP_ALL 1 "nonimmediate_operand" ""))
+ (set (reg:SI GPR0_REGNUM) (match_dup 2))
+ (parallel
+ [(set (reg:BFP FPR0_REGNUM) (float_extend:BFP (reg:DFP_ALL FPR2_REGNUM)))
+ (use (reg:SI GPR0_REGNUM))
+ (clobber (reg:CC CC_REGNUM))])
+ (set (match_operand:BFP 0 "nonimmediate_operand" "") (reg:BFP FPR0_REGNUM))]
+ "TARGET_HARD_DFP
+ && GET_MODE_SIZE (<DFP_ALL:MODE>mode) < GET_MODE_SIZE (<BFP:MODE>mode)"
+{
+ HOST_WIDE_INT flags;
+
+ flags = (PFPO_CONVERT |
+ PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP0_TYPE_SHIFT |
+ PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP1_TYPE_SHIFT);
+
+ operands[2] = GEN_INT (flags);
+})
;;
(match_dup 7)))
(set (match_dup 6) (plus:DI (match_dup 7) (match_dup 8)))])
(parallel
- [(set (match_dup 3) (plus:DI (plus:DI (match_dup 4) (match_dup 5))
- (ltu:DI (reg:CCL1 CC_REGNUM) (const_int 0))))
+ [(set (match_dup 3) (plus:DI
+ (plus:DI (ltu:DI (reg:CCL1 CC_REGNUM) (const_int 0))
+ (match_dup 4)) (match_dup 5)))
(clobber (reg:CC CC_REGNUM))])]
"operands[3] = operand_subword (operands[0], 0, 0, TImode);
operands[4] = operand_subword (operands[1], 0, 0, TImode);
; adddi3 instruction pattern(s).
;
+(define_expand "adddi3"
+ [(parallel
+ [(set (match_operand:DI 0 "nonimmediate_operand" "")
+ (plus:DI (match_operand:DI 1 "nonimmediate_operand" "")
+ (match_operand:DI 2 "general_operand" "")))
+ (clobber (reg:CC CC_REGNUM))])]
+ ""
+ "")
+
(define_insn "*adddi3_sign"
[(set (match_operand:DI 0 "register_operand" "=d,d")
- (plus:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,m"))
+ (plus:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))
(match_operand:DI 1 "register_operand" "0,0")))
(clobber (reg:CC CC_REGNUM))]
"TARGET_64BIT"
(define_insn "*adddi3_zero_cc"
[(set (reg CC_REGNUM)
- (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))
+ (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))
(match_operand:DI 1 "register_operand" "0,0"))
(const_int 0)))
(set (match_operand:DI 0 "register_operand" "=d,d")
"@
algfr\t%0,%2
algf\t%0,%2"
- [(set_attr "op_type" "RRE,RXY")])
+ [(set_attr "op_type" "RRE,RXY")
+ (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
(define_insn "*adddi3_zero_cconly"
[(set (reg CC_REGNUM)
- (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))
+ (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))
(match_operand:DI 1 "register_operand" "0,0"))
(const_int 0)))
(clobber (match_scratch:DI 0 "=d,d"))]
"@
algfr\t%0,%2
algf\t%0,%2"
- [(set_attr "op_type" "RRE,RXY")])
+ [(set_attr "op_type" "RRE,RXY")
+ (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
(define_insn "*adddi3_zero"
[(set (match_operand:DI 0 "register_operand" "=d,d")
- (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))
+ (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))
(match_operand:DI 1 "register_operand" "0,0")))
(clobber (reg:CC CC_REGNUM))]
"TARGET_64BIT"
"@
algfr\t%0,%2
algf\t%0,%2"
- [(set_attr "op_type" "RRE,RXY")])
-
-(define_insn "*adddi3_imm_cc"
- [(set (reg CC_REGNUM)
- (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
- (match_operand:DI 2 "const_int_operand" "K,Os"))
- (const_int 0)))
- (set (match_operand:DI 0 "register_operand" "=d,d")
- (plus:DI (match_dup 1) (match_dup 2)))]
- "TARGET_64BIT
- && s390_match_ccmode (insn, CCAmode)
- && (CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'K', \"K\")
- || CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'O', \"Os\"))"
- "@
- aghi\t%0,%h2
- agfi\t%0,%2"
- [(set_attr "op_type" "RI,RIL")])
-
-(define_insn "*adddi3_carry1_cc"
- [(set (reg CC_REGNUM)
- (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0")
- (match_operand:DI 2 "general_operand" "d,Op,On,m"))
- (match_dup 1)))
- (set (match_operand:DI 0 "register_operand" "=d,d,d,d")
- (plus:DI (match_dup 1) (match_dup 2)))]
- "s390_match_ccmode (insn, CCL1mode) && TARGET_64BIT"
- "@
- algr\t%0,%2
- algfi\t%0,%2
- slgfi\t%0,%n2
- alg\t%0,%2"
- [(set_attr "op_type" "RRE,RIL,RIL,RXY")])
-
-(define_insn "*adddi3_carry1_cconly"
- [(set (reg CC_REGNUM)
- (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
- (match_operand:DI 2 "general_operand" "d,m"))
- (match_dup 1)))
- (clobber (match_scratch:DI 0 "=d,d"))]
- "s390_match_ccmode (insn, CCL1mode) && TARGET_64BIT"
- "@
- algr\t%0,%2
- alg\t%0,%2"
- [(set_attr "op_type" "RRE,RXY")])
-
-(define_insn "*adddi3_carry2_cc"
- [(set (reg CC_REGNUM)
- (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0")
- (match_operand:DI 2 "general_operand" "d,Op,On,m"))
- (match_dup 2)))
- (set (match_operand:DI 0 "register_operand" "=d,d,d,d")
- (plus:DI (match_dup 1) (match_dup 2)))]
- "s390_match_ccmode (insn, CCL1mode) && TARGET_64BIT"
- "@
- algr\t%0,%2
- algfi\t%0,%2
- slgfi\t%0,%n2
- alg\t%0,%2"
- [(set_attr "op_type" "RRE,RIL,RIL,RXY")])
-
-(define_insn "*adddi3_carry2_cconly"
- [(set (reg CC_REGNUM)
- (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
- (match_operand:DI 2 "general_operand" "d,m"))
- (match_dup 2)))
- (clobber (match_scratch:DI 0 "=d,d"))]
- "s390_match_ccmode (insn, CCL1mode) && TARGET_64BIT"
- "@
- algr\t%0,%2
- alg\t%0,%2"
- [(set_attr "op_type" "RRE,RXY")])
-
-(define_insn "*adddi3_cc"
- [(set (reg CC_REGNUM)
- (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0")
- (match_operand:DI 2 "general_operand" "d,Op,On,m"))
- (const_int 0)))
- (set (match_operand:DI 0 "register_operand" "=d,d,d,d")
- (plus:DI (match_dup 1) (match_dup 2)))]
- "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
- "@
- algr\t%0,%2
- algfi\t%0,%2
- slgfi\t%0,%n2
- alg\t%0,%2"
- [(set_attr "op_type" "RRE,RIL,RIL,RXY")])
-
-(define_insn "*adddi3_cconly"
- [(set (reg CC_REGNUM)
- (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
- (match_operand:DI 2 "general_operand" "d,m"))
- (const_int 0)))
- (clobber (match_scratch:DI 0 "=d,d"))]
- "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
- "@
- algr\t%0,%2
- alg\t%0,%2"
- [(set_attr "op_type" "RRE,RXY")])
-
-(define_insn "*adddi3_cconly2"
- [(set (reg CC_REGNUM)
- (compare (match_operand:DI 1 "nonimmediate_operand" "%0,0")
- (neg:SI (match_operand:DI 2 "general_operand" "d,m"))))
- (clobber (match_scratch:DI 0 "=d,d"))]
- "s390_match_ccmode(insn, CCLmode) && TARGET_64BIT"
- "@
- algr\t%0,%2
- alg\t%0,%2"
- [(set_attr "op_type" "RRE,RXY")])
-
-(define_insn "*adddi3_64"
- [(set (match_operand:DI 0 "register_operand" "=d,d,d,d,d")
- (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0,0")
- (match_operand:DI 2 "general_operand" "d,K,Op,On,m") ) )
- (clobber (reg:CC CC_REGNUM))]
- "TARGET_64BIT"
- "@
- agr\t%0,%2
- aghi\t%0,%h2
- algfi\t%0,%2
- slgfi\t%0,%n2
- ag\t%0,%2"
- [(set_attr "op_type" "RRE,RI,RIL,RIL,RXY")])
+ [(set_attr "op_type" "RRE,RXY")
+ (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
(define_insn_and_split "*adddi3_31z"
- [(set (match_operand:DI 0 "register_operand" "=&d")
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=&d")
(plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
(match_operand:DI 2 "general_operand" "do") ) )
(clobber (reg:CC CC_REGNUM))]
(match_dup 7)))
(set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))])
(parallel
- [(set (match_dup 3) (plus:SI (plus:SI (match_dup 4) (match_dup 5))
- (ltu:SI (reg:CCL1 CC_REGNUM) (const_int 0))))
+ [(set (match_dup 3) (plus:SI
+ (plus:SI (ltu:SI (reg:CCL1 CC_REGNUM) (const_int 0))
+ (match_dup 4)) (match_dup 5)))
(clobber (reg:CC CC_REGNUM))])]
"operands[3] = operand_subword (operands[0], 0, 0, DImode);
operands[4] = operand_subword (operands[1], 0, 0, DImode);
operands[8] = operand_subword (operands[2], 1, 0, DImode);")
(define_insn_and_split "*adddi3_31"
- [(set (match_operand:DI 0 "register_operand" "=&d")
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=&d")
(plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
(match_operand:DI 2 "general_operand" "do") ) )
(clobber (reg:CC CC_REGNUM))]
operands[8] = operand_subword (operands[2], 1, 0, DImode);
operands[9] = gen_label_rtx ();")
-(define_expand "adddi3"
+;
+; addsi3 instruction pattern(s).
+;
+
+(define_expand "addsi3"
[(parallel
- [(set (match_operand:DI 0 "register_operand" "")
- (plus:DI (match_operand:DI 1 "nonimmediate_operand" "")
- (match_operand:DI 2 "general_operand" "")))
+ [(set (match_operand:SI 0 "nonimmediate_operand" "")
+ (plus:SI (match_operand:SI 1 "nonimmediate_operand" "")
+ (match_operand:SI 2 "general_operand" "")))
(clobber (reg:CC CC_REGNUM))])]
""
"")
+(define_insn "*addsi3_sign"
+ [(set (match_operand:SI 0 "register_operand" "=d,d")
+ (plus:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T"))
+ (match_operand:SI 1 "register_operand" "0,0")))
+ (clobber (reg:CC CC_REGNUM))]
+ ""
+ "@
+ ah\t%0,%2
+ ahy\t%0,%2"
+ [(set_attr "op_type" "RX,RXY")])
+
;
-; addsi3 instruction pattern(s).
+; add(di|si)3 instruction pattern(s).
;
-(define_insn "*addsi3_imm_cc"
- [(set (reg CC_REGNUM)
- (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
- (match_operand:SI 2 "const_int_operand" "K,Os"))
- (const_int 0)))
- (set (match_operand:SI 0 "register_operand" "=d,d")
- (plus:SI (match_dup 1) (match_dup 2)))]
- "s390_match_ccmode (insn, CCAmode)
- && (CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'K', \"K\")
- || CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'O', \"Os\"))
- && INTVAL (operands[2]) != -((HOST_WIDE_INT)1 << 31)"
+; ar, ahi, alfi, slfi, a, ay, agr, aghi, algfi, slgfi, ag, asi, agsi
+(define_insn "*add<mode>3"
+ [(set (match_operand:GPR 0 "nonimmediate_operand" "=d,d,d,d,d,d,QS")
+ (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0,0,0,0,0")
+ (match_operand:GPR 2 "general_operand" "d,K,Op,On,R,T,C") ) )
+ (clobber (reg:CC CC_REGNUM))]
+ ""
"@
- ahi\t%0,%h2
- afi\t%0,%2"
- [(set_attr "op_type" "RI,RIL")])
-
-(define_insn "*addsi3_carry1_cc"
+ a<g>r\t%0,%2
+ a<g>hi\t%0,%h2
+ al<g>fi\t%0,%2
+ sl<g>fi\t%0,%n2
+ a<g>\t%0,%2
+ a<y>\t%0,%2
+ a<g>si\t%0,%c2"
+ [(set_attr "op_type" "RR<E>,RI,RIL,RIL,RX<Y>,RXY,SIY")
+ (set_attr "cpu_facility" "*,*,extimm,extimm,*,*,z10")
+ (set_attr "z10prop" "z10_super_E1,
+ z10_super_E1,
+ z10_super_E1,
+ z10_super_E1,
+ z10_super_E1,
+ z10_super_E1,
+ z10_super_E1")])
+
+; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg, alsi, algsi
+(define_insn "*add<mode>3_carry1_cc"
[(set (reg CC_REGNUM)
- (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
- (match_operand:SI 2 "general_operand" "d,Os,R,T"))
+ (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0,0,0,0")
+ (match_operand:GPR 2 "general_operand" "d,Op,On,R,T,C"))
(match_dup 1)))
- (set (match_operand:SI 0 "register_operand" "=d,d,d,d")
- (plus:SI (match_dup 1) (match_dup 2)))]
+ (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d,d,d,d,d")
+ (plus:GPR (match_dup 1) (match_dup 2)))]
"s390_match_ccmode (insn, CCL1mode)"
"@
- alr\t%0,%2
- alfi\t%0,%o2
- al\t%0,%2
- aly\t%0,%2"
- [(set_attr "op_type" "RR,RIL,RX,RXY")])
-
-(define_insn "*addsi3_carry1_cconly"
+ al<g>r\t%0,%2
+ al<g>fi\t%0,%2
+ sl<g>fi\t%0,%n2
+ al<g>\t%0,%2
+ al<y>\t%0,%2
+ al<g>si\t%0,%c2"
+ [(set_attr "op_type" "RR<E>,RIL,RIL,RX<Y>,RXY,SIY")
+ (set_attr "cpu_facility" "*,extimm,extimm,*,*,z10")
+ (set_attr "z10prop" "z10_super_E1,
+ z10_super_E1,
+ z10_super_E1,
+ z10_super_E1,
+ z10_super_E1,
+ z10_super_E1")])
+
+; alr, al, aly, algr, alg
+(define_insn "*add<mode>3_carry1_cconly"
[(set (reg CC_REGNUM)
- (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
- (match_operand:SI 2 "general_operand" "d,R,T"))
+ (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0")
+ (match_operand:GPR 2 "general_operand" "d,R,T"))
(match_dup 1)))
- (clobber (match_scratch:SI 0 "=d,d,d"))]
+ (clobber (match_scratch:GPR 0 "=d,d,d"))]
"s390_match_ccmode (insn, CCL1mode)"
"@
- alr\t%0,%2
- al\t%0,%2
- aly\t%0,%2"
- [(set_attr "op_type" "RR,RX,RXY")])
+ al<g>r\t%0,%2
+ al<g>\t%0,%2
+ al<y>\t%0,%2"
+ [(set_attr "op_type" "RR<E>,RX<Y>,RXY")
+ (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")])
-(define_insn "*addsi3_carry2_cc"
+; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg, alsi, algsi
+(define_insn "*add<mode>3_carry2_cc"
[(set (reg CC_REGNUM)
- (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
- (match_operand:SI 2 "general_operand" "d,Os,R,T"))
+ (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0,0,0,0")
+ (match_operand:GPR 2 "general_operand" "d,Op,On,R,T,C"))
(match_dup 2)))
- (set (match_operand:SI 0 "register_operand" "=d,d,d,d")
- (plus:SI (match_dup 1) (match_dup 2)))]
+ (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d,d,d,d,RS")
+ (plus:GPR (match_dup 1) (match_dup 2)))]
"s390_match_ccmode (insn, CCL1mode)"
"@
- alr\t%0,%2
- alfi\t%0,%o2
- al\t%0,%2
- aly\t%0,%2"
- [(set_attr "op_type" "RR,RIL,RX,RXY")])
-
-(define_insn "*addsi3_carry2_cconly"
+ al<g>r\t%0,%2
+ al<g>fi\t%0,%2
+ sl<g>fi\t%0,%n2
+ al<g>\t%0,%2
+ al<y>\t%0,%2
+ al<g>si\t%0,%c2"
+ [(set_attr "op_type" "RR<E>,RIL,RIL,RX<Y>,RXY,SIY")
+ (set_attr "cpu_facility" "*,extimm,extimm,*,*,z10")
+ (set_attr "z10prop" "z10_super_E1,
+ z10_super_E1,
+ z10_super_E1,
+ z10_super_E1,
+ z10_super_E1,
+ z10_super_E1")])
+
+; alr, al, aly, algr, alg
+(define_insn "*add<mode>3_carry2_cconly"
[(set (reg CC_REGNUM)
- (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
- (match_operand:SI 2 "general_operand" "d,R,T"))
+ (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0")
+ (match_operand:GPR 2 "general_operand" "d,R,T"))
(match_dup 2)))
- (clobber (match_scratch:SI 0 "=d,d,d"))]
+ (clobber (match_scratch:GPR 0 "=d,d,d"))]
"s390_match_ccmode (insn, CCL1mode)"
"@
- alr\t%0,%2
- al\t%0,%2
- aly\t%0,%2"
- [(set_attr "op_type" "RR,RX,RXY")])
+ al<g>r\t%0,%2
+ al<g>\t%0,%2
+ al<y>\t%0,%2"
+ [(set_attr "op_type" "RR<E>,RX<Y>,RXY")
+ (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")])
-(define_insn "*addsi3_cc"
+; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg, alsi, algsi
+(define_insn "*add<mode>3_cc"
[(set (reg CC_REGNUM)
- (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
- (match_operand:SI 2 "general_operand" "d,Os,R,T"))
+ (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0,0,0,0")
+ (match_operand:GPR 2 "general_operand" "d,Op,On,R,T,C"))
(const_int 0)))
- (set (match_operand:SI 0 "register_operand" "=d,d,d,d")
- (plus:SI (match_dup 1) (match_dup 2)))]
+ (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d,d,d,d,RS")
+ (plus:GPR (match_dup 1) (match_dup 2)))]
"s390_match_ccmode (insn, CCLmode)"
"@
- alr\t%0,%2
- alfi\t%0,%o2
- al\t%0,%2
- aly\t%0,%2"
- [(set_attr "op_type" "RR,RIL,RX,RXY")])
-
-(define_insn "*addsi3_cconly"
+ al<g>r\t%0,%2
+ al<g>fi\t%0,%2
+ sl<g>fi\t%0,%n2
+ al<g>\t%0,%2
+ al<y>\t%0,%2
+ al<g>si\t%0,%c2"
+ [(set_attr "op_type" "RR<E>,RIL,RIL,RX<Y>,RXY,SIY")
+ (set_attr "cpu_facility" "*,extimm,extimm,*,*,z10")
+ (set_attr "z10prop" "z10_super_E1,
+ z10_super_E1,
+ z10_super_E1,
+ z10_super_E1,
+ z10_super_E1,
+ z10_super_E1")])
+
+; alr, al, aly, algr, alg
+(define_insn "*add<mode>3_cconly"
[(set (reg CC_REGNUM)
- (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
- (match_operand:SI 2 "general_operand" "d,R,T"))
+ (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0")
+ (match_operand:GPR 2 "general_operand" "d,R,T"))
(const_int 0)))
- (clobber (match_scratch:SI 0 "=d,d,d"))]
+ (clobber (match_scratch:GPR 0 "=d,d,d"))]
"s390_match_ccmode (insn, CCLmode)"
"@
- alr\t%0,%2
- al\t%0,%2
- aly\t%0,%2"
- [(set_attr "op_type" "RR,RX,RXY")])
+ al<g>r\t%0,%2
+ al<g>\t%0,%2
+ al<y>\t%0,%2"
+ [(set_attr "op_type" "RR<E>,RX<Y>,RXY")
+ (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")])
-(define_insn "*addsi3_cconly2"
+; alr, al, aly, algr, alg
+(define_insn "*add<mode>3_cconly2"
[(set (reg CC_REGNUM)
- (compare (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
- (neg:SI (match_operand:SI 2 "general_operand" "d,R,T"))))
- (clobber (match_scratch:SI 0 "=d,d,d"))]
- "s390_match_ccmode (insn, CCLmode)"
- "@
- alr\t%0,%2
- al\t%0,%2
- aly\t%0,%2"
- [(set_attr "op_type" "RR,RX,RXY")])
-
-(define_insn "*addsi3_sign"
- [(set (match_operand:SI 0 "register_operand" "=d,d")
- (plus:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T"))
- (match_operand:SI 1 "register_operand" "0,0")))
- (clobber (reg:CC CC_REGNUM))]
- ""
- "@
- ah\t%0,%2
- ahy\t%0,%2"
- [(set_attr "op_type" "RX,RXY")])
-
-(define_insn "addsi3"
- [(set (match_operand:SI 0 "register_operand" "=d,d,d,d,d")
- (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0,0")
- (match_operand:SI 2 "general_operand" "d,K,Os,R,T")))
- (clobber (reg:CC CC_REGNUM))]
- ""
+ (compare (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0")
+ (neg:GPR (match_operand:GPR 2 "general_operand" "d,R,T"))))
+ (clobber (match_scratch:GPR 0 "=d,d,d"))]
+ "s390_match_ccmode(insn, CCLmode)"
+ "@
+ al<g>r\t%0,%2
+ al<g>\t%0,%2
+ al<y>\t%0,%2"
+ [(set_attr "op_type" "RR<E>,RX<Y>,RXY")
+ (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")])
+
+; ahi, afi, aghi, agfi, asi, agsi
+(define_insn "*add<mode>3_imm_cc"
+ [(set (reg CC_REGNUM)
+ (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0,0")
+ (match_operand:GPR 2 "const_int_operand" "K,Os,C"))
+ (const_int 0)))
+ (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d,QS")
+ (plus:GPR (match_dup 1) (match_dup 2)))]
+ "s390_match_ccmode (insn, CCAmode)
+ && (CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'K', \"K\")
+ || CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'O', \"Os\")
+ || CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'C', \"C\"))
+ && INTVAL (operands[2]) != -((HOST_WIDE_INT)1 << (GET_MODE_BITSIZE(<MODE>mode) - 1))"
"@
- ar\t%0,%2
- ahi\t%0,%h2
- afi\t%0,%2
- a\t%0,%2
- ay\t%0,%2"
- [(set_attr "op_type" "RR,RI,RIL,RX,RXY")])
+ a<g>hi\t%0,%h2
+ a<g>fi\t%0,%2
+ a<g>si\t%0,%c2"
+ [(set_attr "op_type" "RI,RIL,SIY")
+ (set_attr "cpu_facility" "*,extimm,z10")
+ (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")])
;
-; add(df|sf)3 instruction pattern(s).
+; add(tf|df|sf|td|dd)3 instruction pattern(s).
;
-(define_expand "add<mode>3"
- [(parallel
- [(set (match_operand:FPR 0 "register_operand" "=f,f")
- (plus:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
- (match_operand:FPR 2 "general_operand" "f,R")))
- (clobber (reg:CC CC_REGNUM))])]
- "TARGET_HARD_FLOAT"
- "")
-
-(define_insn "*add<mode>3"
- [(set (match_operand:FPR 0 "register_operand" "=f,f")
- (plus:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
- (match_operand:FPR 2 "general_operand" "f,R")))
+; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr
+(define_insn "add<mode>3"
+ [(set (match_operand:FP 0 "register_operand" "=f, f")
+ (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%<f0>,0")
+ (match_operand:FP 2 "general_operand" " f,<Rf>")))
(clobber (reg:CC CC_REGNUM))]
- "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
+ "TARGET_HARD_FLOAT"
"@
- a<de>br\t%0,%2
- a<de>b\t%0,%2"
- [(set_attr "op_type" "RRE,RXE")
+ a<xde><bt>r\t%0,<op1>%2
+ a<xde>b\t%0,%2"
+ [(set_attr "op_type" "<RRer>,RXE")
(set_attr "type" "fsimp<mode>")])
+; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr
(define_insn "*add<mode>3_cc"
[(set (reg CC_REGNUM)
- (compare (plus:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
- (match_operand:FPR 2 "general_operand" "f,R"))
- (match_operand:FPR 3 "const0_operand" "")))
- (set (match_operand:FPR 0 "register_operand" "=f,f")
- (plus:FPR (match_dup 1) (match_dup 2)))]
- "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
- "@
- a<de>br\t%0,%2
- a<de>b\t%0,%2"
- [(set_attr "op_type" "RRE,RXE")
+ (compare (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%<f0>,0")
+ (match_operand:FP 2 "general_operand" " f,<Rf>"))
+ (match_operand:FP 3 "const0_operand" "")))
+ (set (match_operand:FP 0 "register_operand" "=f,f")
+ (plus:FP (match_dup 1) (match_dup 2)))]
+ "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
+ "@
+ a<xde><bt>r\t%0,<op1>%2
+ a<xde>b\t%0,%2"
+ [(set_attr "op_type" "<RRer>,RXE")
(set_attr "type" "fsimp<mode>")])
+; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr
(define_insn "*add<mode>3_cconly"
[(set (reg CC_REGNUM)
- (compare (plus:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
- (match_operand:FPR 2 "general_operand" "f,R"))
- (match_operand:FPR 3 "const0_operand" "")))
- (clobber (match_scratch:FPR 0 "=f,f"))]
- "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
- "@
- a<de>br\t%0,%2
- a<de>b\t%0,%2"
- [(set_attr "op_type" "RRE,RXE")
- (set_attr "type" "fsimp<mode>")])
-
-(define_insn "*add<mode>3_ibm"
- [(set (match_operand:FPR 0 "register_operand" "=f,f")
- (plus:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
- (match_operand:FPR 2 "general_operand" "f,R")))
- (clobber (reg:CC CC_REGNUM))]
- "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
- "@
- a<de>r\t%0,%2
- a<de>\t%0,%2"
- [(set_attr "op_type" "RR,RX")
+ (compare (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%<f0>,0")
+ (match_operand:FP 2 "general_operand" " f,<Rf>"))
+ (match_operand:FP 3 "const0_operand" "")))
+ (clobber (match_scratch:FP 0 "=f,f"))]
+ "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
+ "@
+ a<xde><bt>r\t%0,<op1>%2
+ a<xde>b\t%0,%2"
+ [(set_attr "op_type" "<RRer>,RXE")
(set_attr "type" "fsimp<mode>")])
; subdi3 instruction pattern(s).
;
+(define_expand "subdi3"
+ [(parallel
+ [(set (match_operand:DI 0 "register_operand" "")
+ (minus:DI (match_operand:DI 1 "register_operand" "")
+ (match_operand:DI 2 "general_operand" "")))
+ (clobber (reg:CC CC_REGNUM))])]
+ ""
+ "")
+
(define_insn "*subdi3_sign"
[(set (match_operand:DI 0 "register_operand" "=d,d")
(minus:DI (match_operand:DI 1 "register_operand" "0,0")
- (sign_extend:DI (match_operand:SI 2 "general_operand" "d,m"))))
+ (sign_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))))
(clobber (reg:CC CC_REGNUM))]
"TARGET_64BIT"
"@
sgfr\t%0,%2
sgf\t%0,%2"
- [(set_attr "op_type" "RRE,RXY")])
+ [(set_attr "op_type" "RRE,RXY")
+ (set_attr "z10prop" "z10_c,*")])
(define_insn "*subdi3_zero_cc"
[(set (reg CC_REGNUM)
(compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
- (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m")))
+ (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT")))
(const_int 0)))
(set (match_operand:DI 0 "register_operand" "=d,d")
(minus:DI (match_dup 1) (zero_extend:DI (match_dup 2))))]
"@
slgfr\t%0,%2
slgf\t%0,%2"
- [(set_attr "op_type" "RRE,RXY")])
+ [(set_attr "op_type" "RRE,RXY")
+ (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")])
(define_insn "*subdi3_zero_cconly"
[(set (reg CC_REGNUM)
(compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
- (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m")))
+ (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT")))
(const_int 0)))
(clobber (match_scratch:DI 0 "=d,d"))]
"s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
"@
slgfr\t%0,%2
slgf\t%0,%2"
- [(set_attr "op_type" "RRE,RXY")])
+ [(set_attr "op_type" "RRE,RXY")
+ (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")])
(define_insn "*subdi3_zero"
[(set (match_operand:DI 0 "register_operand" "=d,d")
(minus:DI (match_operand:DI 1 "register_operand" "0,0")
- (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))))
+ (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))))
(clobber (reg:CC CC_REGNUM))]
"TARGET_64BIT"
"@
slgfr\t%0,%2
slgf\t%0,%2"
- [(set_attr "op_type" "RRE,RXY")])
-
-(define_insn "*subdi3_borrow_cc"
- [(set (reg CC_REGNUM)
- (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
- (match_operand:DI 2 "general_operand" "d,m"))
- (match_dup 1)))
- (set (match_operand:DI 0 "register_operand" "=d,d")
- (minus:DI (match_dup 1) (match_dup 2)))]
- "s390_match_ccmode (insn, CCL2mode) && TARGET_64BIT"
- "@
- slgr\t%0,%2
- slg\t%0,%2"
- [(set_attr "op_type" "RRE,RXY")])
-
-(define_insn "*subdi3_borrow_cconly"
- [(set (reg CC_REGNUM)
- (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
- (match_operand:DI 2 "general_operand" "d,m"))
- (match_dup 1)))
- (clobber (match_scratch:DI 0 "=d,d"))]
- "s390_match_ccmode (insn, CCL2mode) && TARGET_64BIT"
- "@
- slgr\t%0,%2
- slg\t%0,%2"
- [(set_attr "op_type" "RRE,RXY")])
-
-(define_insn "*subdi3_cc"
- [(set (reg CC_REGNUM)
- (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
- (match_operand:DI 2 "general_operand" "d,m"))
- (const_int 0)))
- (set (match_operand:DI 0 "register_operand" "=d,d")
- (minus:DI (match_dup 1) (match_dup 2)))]
- "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
- "@
- slgr\t%0,%2
- slg\t%0,%2"
- [(set_attr "op_type" "RRE,RXY")])
-
-(define_insn "*subdi3_cc2"
- [(set (reg CC_REGNUM)
- (compare (match_operand:DI 1 "register_operand" "0,0")
- (match_operand:DI 2 "general_operand" "d,m")))
- (set (match_operand:DI 0 "register_operand" "=d,d")
- (minus:DI (match_dup 1) (match_dup 2)))]
- "s390_match_ccmode (insn, CCL3mode) && TARGET_64BIT"
- "@
- slgr\t%0,%2
- slg\t%0,%2"
- [(set_attr "op_type" "RRE,RXY")])
-
-(define_insn "*subdi3_cconly"
- [(set (reg CC_REGNUM)
- (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
- (match_operand:DI 2 "general_operand" "d,m"))
- (const_int 0)))
- (clobber (match_scratch:DI 0 "=d,d"))]
- "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
- "@
- slgr\t%0,%2
- slg\t%0,%2"
- [(set_attr "op_type" "RRE,RXY")])
-
-(define_insn "*subdi3_cconly2"
- [(set (reg CC_REGNUM)
- (compare (match_operand:DI 1 "register_operand" "0,0")
- (match_operand:DI 2 "general_operand" "d,m")))
- (clobber (match_scratch:DI 0 "=d,d"))]
- "s390_match_ccmode (insn, CCL3mode) && TARGET_64BIT"
- "@
- slgr\t%0,%2
- slg\t%0,%2"
- [(set_attr "op_type" "RRE,RXY")])
-
-(define_insn "*subdi3_64"
- [(set (match_operand:DI 0 "register_operand" "=d,d")
- (minus:DI (match_operand:DI 1 "register_operand" "0,0")
- (match_operand:DI 2 "general_operand" "d,m") ) )
- (clobber (reg:CC CC_REGNUM))]
- "TARGET_64BIT"
- "@
- sgr\t%0,%2
- sg\t%0,%2"
- [(set_attr "op_type" "RRE,RRE")])
+ [(set_attr "op_type" "RRE,RXY")
+ (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")])
(define_insn_and_split "*subdi3_31z"
[(set (match_operand:DI 0 "register_operand" "=&d")
operands[8] = operand_subword (operands[2], 1, 0, DImode);
operands[9] = gen_label_rtx ();")
-(define_expand "subdi3"
+;
+; subsi3 instruction pattern(s).
+;
+
+(define_expand "subsi3"
[(parallel
- [(set (match_operand:DI 0 "register_operand" "")
- (minus:DI (match_operand:DI 1 "register_operand" "")
- (match_operand:DI 2 "general_operand" "")))
+ [(set (match_operand:SI 0 "register_operand" "")
+ (minus:SI (match_operand:SI 1 "register_operand" "")
+ (match_operand:SI 2 "general_operand" "")))
(clobber (reg:CC CC_REGNUM))])]
""
"")
+(define_insn "*subsi3_sign"
+ [(set (match_operand:SI 0 "register_operand" "=d,d")
+ (minus:SI (match_operand:SI 1 "register_operand" "0,0")
+ (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T"))))
+ (clobber (reg:CC CC_REGNUM))]
+ ""
+ "@
+ sh\t%0,%2
+ shy\t%0,%2"
+ [(set_attr "op_type" "RX,RXY")])
+
;
-; subsi3 instruction pattern(s).
+; sub(di|si)3 instruction pattern(s).
;
-(define_insn "*subsi3_borrow_cc"
+; sr, s, sy, sgr, sg
+(define_insn "*sub<mode>3"
+ [(set (match_operand:GPR 0 "register_operand" "=d,d,d")
+ (minus:GPR (match_operand:GPR 1 "register_operand" "0,0,0")
+ (match_operand:GPR 2 "general_operand" "d,R,T") ) )
+ (clobber (reg:CC CC_REGNUM))]
+ ""
+ "@
+ s<g>r\t%0,%2
+ s<g>\t%0,%2
+ s<y>\t%0,%2"
+ [(set_attr "op_type" "RR<E>,RX<Y>,RXY")
+ (set_attr "z10prop" "z10_super_c_E1,z10_super_E1,z10_super_E1")])
+
+; slr, sl, sly, slgr, slg
+(define_insn "*sub<mode>3_borrow_cc"
[(set (reg CC_REGNUM)
- (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0,0")
- (match_operand:SI 2 "general_operand" "d,R,T"))
+ (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,0,0")
+ (match_operand:GPR 2 "general_operand" "d,R,T"))
(match_dup 1)))
- (set (match_operand:SI 0 "register_operand" "=d,d,d")
- (minus:SI (match_dup 1) (match_dup 2)))]
+ (set (match_operand:GPR 0 "register_operand" "=d,d,d")
+ (minus:GPR (match_dup 1) (match_dup 2)))]
"s390_match_ccmode (insn, CCL2mode)"
"@
- slr\t%0,%2
- sl\t%0,%2
- sly\t%0,%2"
- [(set_attr "op_type" "RR,RX,RXY")])
+ sl<g>r\t%0,%2
+ sl<g>\t%0,%2
+ sl<y>\t%0,%2"
+ [(set_attr "op_type" "RR<E>,RX<Y>,RXY")
+ (set_attr "z10prop" "z10_super_c_E1,z10_super_E1,z10_super_E1")])
-(define_insn "*subsi3_borrow_cconly"
+; slr, sl, sly, slgr, slg
+(define_insn "*sub<mode>3_borrow_cconly"
[(set (reg CC_REGNUM)
- (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0,0")
- (match_operand:SI 2 "general_operand" "d,R,T"))
+ (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,0,0")
+ (match_operand:GPR 2 "general_operand" "d,R,T"))
(match_dup 1)))
- (clobber (match_scratch:SI 0 "=d,d,d"))]
+ (clobber (match_scratch:GPR 0 "=d,d,d"))]
"s390_match_ccmode (insn, CCL2mode)"
"@
- slr\t%0,%2
- sl\t%0,%2
- sly\t%0,%2"
- [(set_attr "op_type" "RR,RX,RXY")])
+ sl<g>r\t%0,%2
+ sl<g>\t%0,%2
+ sl<y>\t%0,%2"
+ [(set_attr "op_type" "RR<E>,RX<Y>,RXY")
+ (set_attr "z10prop" "z10_super_c_E1,z10_super_E1,z10_super_E1")])
-(define_insn "*subsi3_cc"
+; slr, sl, sly, slgr, slg
+(define_insn "*sub<mode>3_cc"
[(set (reg CC_REGNUM)
- (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0,0")
- (match_operand:SI 2 "general_operand" "d,R,T"))
+ (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,0,0")
+ (match_operand:GPR 2 "general_operand" "d,R,T"))
(const_int 0)))
- (set (match_operand:SI 0 "register_operand" "=d,d,d")
- (minus:SI (match_dup 1) (match_dup 2)))]
+ (set (match_operand:GPR 0 "register_operand" "=d,d,d")
+ (minus:GPR (match_dup 1) (match_dup 2)))]
"s390_match_ccmode (insn, CCLmode)"
"@
- slr\t%0,%2
- sl\t%0,%2
- sly\t%0,%2"
- [(set_attr "op_type" "RR,RX,RXY")])
+ sl<g>r\t%0,%2
+ sl<g>\t%0,%2
+ sl<y>\t%0,%2"
+ [(set_attr "op_type" "RR<E>,RX<Y>,RXY")
+ (set_attr "z10prop" "z10_super_c_E1,z10_super_E1,z10_super_E1")])
-(define_insn "*subsi3_cc2"
+; slr, sl, sly, slgr, slg
+(define_insn "*sub<mode>3_cc2"
[(set (reg CC_REGNUM)
- (compare (match_operand:SI 1 "register_operand" "0,0,0")
- (match_operand:SI 2 "general_operand" "d,R,T")))
- (set (match_operand:SI 0 "register_operand" "=d,d,d")
- (minus:SI (match_dup 1) (match_dup 2)))]
+ (compare (match_operand:GPR 1 "register_operand" "0,0,0")
+ (match_operand:GPR 2 "general_operand" "d,R,T")))
+ (set (match_operand:GPR 0 "register_operand" "=d,d,d")
+ (minus:GPR (match_dup 1) (match_dup 2)))]
"s390_match_ccmode (insn, CCL3mode)"
"@
- slr\t%0,%2
- sl\t%0,%2
- sly\t%0,%2"
- [(set_attr "op_type" "RR,RX,RXY")])
+ sl<g>r\t%0,%2
+ sl<g>\t%0,%2
+ sl<y>\t%0,%2"
+ [(set_attr "op_type" "RR<E>,RX<Y>,RXY")
+ (set_attr "z10prop" "z10_super_c_E1,z10_super_E1,z10_super_E1")])
-(define_insn "*subsi3_cconly"
+; slr, sl, sly, slgr, slg
+(define_insn "*sub<mode>3_cconly"
[(set (reg CC_REGNUM)
- (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0,0")
- (match_operand:SI 2 "general_operand" "d,R,T"))
+ (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,0,0")
+ (match_operand:GPR 2 "general_operand" "d,R,T"))
(const_int 0)))
- (clobber (match_scratch:SI 0 "=d,d,d"))]
+ (clobber (match_scratch:GPR 0 "=d,d,d"))]
"s390_match_ccmode (insn, CCLmode)"
"@
- slr\t%0,%2
- sl\t%0,%2
- sly\t%0,%2"
- [(set_attr "op_type" "RR,RX,RXY")])
+ sl<g>r\t%0,%2
+ sl<g>\t%0,%2
+ sl<y>\t%0,%2"
+ [(set_attr "op_type" "RR<E>,RX<Y>,RXY")
+ (set_attr "z10prop" "z10_super_c_E1,z10_super_E1,z10_super_E1")])
+
-(define_insn "*subsi3_cconly2"
+; slr, sl, sly, slgr, slg
+(define_insn "*sub<mode>3_cconly2"
[(set (reg CC_REGNUM)
- (compare (match_operand:SI 1 "register_operand" "0,0,0")
- (match_operand:SI 2 "general_operand" "d,R,T")))
- (clobber (match_scratch:SI 0 "=d,d,d"))]
+ (compare (match_operand:GPR 1 "register_operand" "0,0,0")
+ (match_operand:GPR 2 "general_operand" "d,R,T")))
+ (clobber (match_scratch:GPR 0 "=d,d,d"))]
"s390_match_ccmode (insn, CCL3mode)"
"@
- slr\t%0,%2
- sl\t%0,%2
- sly\t%0,%2"
- [(set_attr "op_type" "RR,RX,RXY")])
-
-(define_insn "*subsi3_sign"
- [(set (match_operand:SI 0 "register_operand" "=d,d")
- (minus:SI (match_operand:SI 1 "register_operand" "0,0")
- (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T"))))
- (clobber (reg:CC CC_REGNUM))]
- ""
- "@
- sh\t%0,%2
- shy\t%0,%2"
- [(set_attr "op_type" "RX,RXY")])
-
-(define_insn "subsi3"
- [(set (match_operand:SI 0 "register_operand" "=d,d,d")
- (minus:SI (match_operand:SI 1 "register_operand" "0,0,0")
- (match_operand:SI 2 "general_operand" "d,R,T")))
- (clobber (reg:CC CC_REGNUM))]
- ""
- "@
- sr\t%0,%2
- s\t%0,%2
- sy\t%0,%2"
- [(set_attr "op_type" "RR,RX,RXY")])
+ sl<g>r\t%0,%2
+ sl<g>\t%0,%2
+ sl<y>\t%0,%2"
+ [(set_attr "op_type" "RR<E>,RX<Y>,RXY")
+ (set_attr "z10prop" "z10_super_c_E1,z10_super_E1,z10_super_E1")])
;
-; sub(df|sf)3 instruction pattern(s).
+; sub(tf|df|sf|td|dd)3 instruction pattern(s).
;
-(define_expand "sub<mode>3"
- [(parallel
- [(set (match_operand:FPR 0 "register_operand" "=f,f")
- (minus:FPR (match_operand:FPR 1 "register_operand" "0,0")
- (match_operand:FPR 2 "general_operand" "f,R")))
- (clobber (reg:CC CC_REGNUM))])]
- "TARGET_HARD_FLOAT"
- "")
-
-(define_insn "*sub<mode>3"
- [(set (match_operand:FPR 0 "register_operand" "=f,f")
- (minus:FPR (match_operand:FPR 1 "register_operand" "0,0")
- (match_operand:FPR 2 "general_operand" "f,R")))
+; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr
+(define_insn "sub<mode>3"
+ [(set (match_operand:FP 0 "register_operand" "=f, f")
+ (minus:FP (match_operand:FP 1 "register_operand" "<f0>,0")
+ (match_operand:FP 2 "general_operand" "f,<Rf>")))
(clobber (reg:CC CC_REGNUM))]
- "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
+ "TARGET_HARD_FLOAT"
"@
- s<de>br\t%0,%2
- s<de>b\t%0,%2"
- [(set_attr "op_type" "RRE,RXE")
+ s<xde><bt>r\t%0,<op1>%2
+ s<xde>b\t%0,%2"
+ [(set_attr "op_type" "<RRer>,RXE")
(set_attr "type" "fsimp<mode>")])
+; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr
(define_insn "*sub<mode>3_cc"
[(set (reg CC_REGNUM)
- (compare (minus:FPR (match_operand:FPR 1 "nonimmediate_operand" "0,0")
- (match_operand:FPR 2 "general_operand" "f,R"))
- (match_operand:FPR 3 "const0_operand" "")))
- (set (match_operand:FPR 0 "register_operand" "=f,f")
- (minus:FPR (match_dup 1) (match_dup 2)))]
- "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
- "@
- s<de>br\t%0,%2
- s<de>b\t%0,%2"
- [(set_attr "op_type" "RRE,RXE")
+ (compare (minus:FP (match_operand:FP 1 "nonimmediate_operand" "<f0>,0")
+ (match_operand:FP 2 "general_operand" "f,<Rf>"))
+ (match_operand:FP 3 "const0_operand" "")))
+ (set (match_operand:FP 0 "register_operand" "=f,f")
+ (minus:FP (match_dup 1) (match_dup 2)))]
+ "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
+ "@
+ s<xde><bt>r\t%0,<op1>%2
+ s<xde>b\t%0,%2"
+ [(set_attr "op_type" "<RRer>,RXE")
(set_attr "type" "fsimp<mode>")])
+; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr
(define_insn "*sub<mode>3_cconly"
[(set (reg CC_REGNUM)
- (compare (minus:FPR (match_operand:FPR 1 "nonimmediate_operand" "0,0")
- (match_operand:FPR 2 "general_operand" "f,R"))
- (match_operand:FPR 3 "const0_operand" "")))
- (clobber (match_scratch:FPR 0 "=f,f"))]
- "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
- "@
- s<de>br\t%0,%2
- s<de>b\t%0,%2"
- [(set_attr "op_type" "RRE,RXE")
- (set_attr "type" "fsimp<mode>")])
-
-(define_insn "*sub<mode>3_ibm"
- [(set (match_operand:FPR 0 "register_operand" "=f,f")
- (minus:FPR (match_operand:FPR 1 "register_operand" "0,0")
- (match_operand:FPR 2 "general_operand" "f,R")))
- (clobber (reg:CC CC_REGNUM))]
- "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
- "@
- s<de>r\t%0,%2
- s<de>\t%0,%2"
- [(set_attr "op_type" "RR,RX")
+ (compare (minus:FP (match_operand:FP 1 "nonimmediate_operand" "<f0>,0")
+ (match_operand:FP 2 "general_operand" "f,<Rf>"))
+ (match_operand:FP 3 "const0_operand" "")))
+ (clobber (match_scratch:FP 0 "=f,f"))]
+ "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
+ "@
+ s<xde><bt>r\t%0,<op1>%2
+ s<xde>b\t%0,%2"
+ [(set_attr "op_type" "<RRer>,RXE")
(set_attr "type" "fsimp<mode>")])
; add(di|si)cc instruction pattern(s).
;
+; the following 4 patterns are used when the result of an add with
+; carry is checked for an overflow condition
+
+; op1 + op2 + c < op1
+
+; alcr, alc, alcgr, alcg
+(define_insn "*add<mode>3_alc_carry1_cc"
+ [(set (reg CC_REGNUM)
+ (compare
+ (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
+ (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
+ (match_operand:GPR 2 "general_operand" "d,RT"))
+ (match_dup 1)))
+ (set (match_operand:GPR 0 "register_operand" "=d,d")
+ (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))]
+ "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH"
+ "@
+ alc<g>r\t%0,%2
+ alc<g>\t%0,%2"
+ [(set_attr "op_type" "RRE,RXY")])
+
+; alcr, alc, alcgr, alcg
+(define_insn "*add<mode>3_alc_carry1_cconly"
+ [(set (reg CC_REGNUM)
+ (compare
+ (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
+ (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
+ (match_operand:GPR 2 "general_operand" "d,RT"))
+ (match_dup 1)))
+ (clobber (match_scratch:GPR 0 "=d,d"))]
+ "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH"
+ "@
+ alc<g>r\t%0,%2
+ alc<g>\t%0,%2"
+ [(set_attr "op_type" "RRE,RXY")])
+
+; op1 + op2 + c < op2
+
+; alcr, alc, alcgr, alcg
+(define_insn "*add<mode>3_alc_carry2_cc"
+ [(set (reg CC_REGNUM)
+ (compare
+ (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
+ (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
+ (match_operand:GPR 2 "general_operand" "d,RT"))
+ (match_dup 2)))
+ (set (match_operand:GPR 0 "register_operand" "=d,d")
+ (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))]
+ "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH"
+ "@
+ alc<g>r\t%0,%2
+ alc<g>\t%0,%2"
+ [(set_attr "op_type" "RRE,RXY")])
+
+; alcr, alc, alcgr, alcg
+(define_insn "*add<mode>3_alc_carry2_cconly"
+ [(set (reg CC_REGNUM)
+ (compare
+ (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
+ (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
+ (match_operand:GPR 2 "general_operand" "d,RT"))
+ (match_dup 2)))
+ (clobber (match_scratch:GPR 0 "=d,d"))]
+ "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH"
+ "@
+ alc<g>r\t%0,%2
+ alc<g>\t%0,%2"
+ [(set_attr "op_type" "RRE,RXY")])
+
+; alcr, alc, alcgr, alcg
(define_insn "*add<mode>3_alc_cc"
[(set (reg CC_REGNUM)
(compare
- (plus:GPR (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0")
- (match_operand:GPR 2 "general_operand" "d,m"))
- (match_operand:GPR 3 "s390_alc_comparison" ""))
+ (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
+ (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
+ (match_operand:GPR 2 "general_operand" "d,RT"))
(const_int 0)))
(set (match_operand:GPR 0 "register_operand" "=d,d")
- (plus:GPR (plus:GPR (match_dup 1) (match_dup 2)) (match_dup 3)))]
+ (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))]
"s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH"
"@
alc<g>r\t%0,%2
alc<g>\t%0,%2"
[(set_attr "op_type" "RRE,RXY")])
+; alcr, alc, alcgr, alcg
(define_insn "*add<mode>3_alc"
[(set (match_operand:GPR 0 "register_operand" "=d,d")
- (plus:GPR (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0")
- (match_operand:GPR 2 "general_operand" "d,m"))
- (match_operand:GPR 3 "s390_alc_comparison" "")))
+ (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
+ (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
+ (match_operand:GPR 2 "general_operand" "d,RT")))
(clobber (reg:CC CC_REGNUM))]
"TARGET_CPU_ZARCH"
"@
alc<g>\t%0,%2"
[(set_attr "op_type" "RRE,RXY")])
+; slbr, slb, slbgr, slbg
(define_insn "*sub<mode>3_slb_cc"
[(set (reg CC_REGNUM)
(compare
(minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0")
- (match_operand:GPR 2 "general_operand" "d,m"))
+ (match_operand:GPR 2 "general_operand" "d,RT"))
(match_operand:GPR 3 "s390_slb_comparison" ""))
(const_int 0)))
(set (match_operand:GPR 0 "register_operand" "=d,d")
"@
slb<g>r\t%0,%2
slb<g>\t%0,%2"
- [(set_attr "op_type" "RRE,RXY")])
+ [(set_attr "op_type" "RRE,RXY")
+ (set_attr "z10prop" "z10_c,*")])
+; slbr, slb, slbgr, slbg
(define_insn "*sub<mode>3_slb"
[(set (match_operand:GPR 0 "register_operand" "=d,d")
(minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0")
- (match_operand:GPR 2 "general_operand" "d,m"))
+ (match_operand:GPR 2 "general_operand" "d,RT"))
(match_operand:GPR 3 "s390_slb_comparison" "")))
(clobber (reg:CC CC_REGNUM))]
"TARGET_CPU_ZARCH"
"@
slb<g>r\t%0,%2
slb<g>\t%0,%2"
- [(set_attr "op_type" "RRE,RXY")])
+ [(set_attr "op_type" "RRE,RXY")
+ (set_attr "z10prop" "z10_c,*")])
(define_expand "add<mode>cc"
[(match_operand:GPR 0 "register_operand" "")
(match_operand:GPR 2 "register_operand" "")
(match_operand:GPR 3 "const_int_operand" "")]
"TARGET_CPU_ZARCH"
- "if (!s390_expand_addcc (GET_CODE (operands[1]),
- s390_compare_op0, s390_compare_op1,
- operands[0], operands[2],
+ "if (!s390_expand_addcc (GET_CODE (operands[1]),
+ s390_compare_op0, s390_compare_op1,
+ operands[0], operands[2],
operands[3])) FAIL; DONE;")
;
"&& reload_completed"
[(set (match_dup 0) (const_int 0))
(parallel
- [(set (match_dup 0) (plus:GPR (plus:GPR (match_dup 0) (match_dup 0))
- (match_dup 1)))
+ [(set (match_dup 0) (plus:GPR (plus:GPR (match_dup 1) (match_dup 0))
+ (match_dup 0)))
(clobber (reg:CC CC_REGNUM))])]
"")
[(set (match_dup 0) (xor:SI (match_dup 0) (const_int 1)))
(clobber (reg:CC CC_REGNUM))])]
""
-{
+{
if (!s390_compare_emitted || GET_MODE (s390_compare_emitted) != CCZ1mode)
FAIL;
operands[1] = s390_emit_compare (NE, s390_compare_op0, s390_compare_op1);
(define_insn_and_split "*sne"
[(set (match_operand:SI 0 "register_operand" "=d")
- (ne:SI (match_operand:CCZ1 1 "register_operand" "0")
+ (ne:SI (match_operand:CCZ1 1 "register_operand" "0")
(const_int 0)))
(clobber (reg:CC CC_REGNUM))]
""
(define_insn "*muldi3_sign"
[(set (match_operand:DI 0 "register_operand" "=d,d")
- (mult:DI (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "d,m"))
+ (mult:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))
(match_operand:DI 1 "register_operand" "0,0")))]
"TARGET_64BIT"
"@
msgfr\t%0,%2
msgf\t%0,%2"
- [(set_attr "op_type" "RRE,RXY")
- (set_attr "type" "imuldi")])
+ [(set_attr "op_type" "RRE,RXY")
+ (set_attr "type" "imuldi")])
(define_insn "muldi3"
- [(set (match_operand:DI 0 "register_operand" "=d,d,d")
- (mult:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0")
- (match_operand:DI 2 "general_operand" "d,K,m")))]
+ [(set (match_operand:DI 0 "register_operand" "=d,d,d,d")
+ (mult:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0")
+ (match_operand:DI 2 "general_operand" "d,K,RT,Os")))]
"TARGET_64BIT"
"@
msgr\t%0,%2
mghi\t%0,%h2
- msg\t%0,%2"
- [(set_attr "op_type" "RRE,RI,RXY")
- (set_attr "type" "imuldi")])
+ msg\t%0,%2
+ msgfi\t%0,%2"
+ [(set_attr "op_type" "RRE,RI,RXY,RIL")
+ (set_attr "type" "imuldi")
+ (set_attr "cpu_facility" "*,*,*,z10")])
;
; mulsi3 instruction pattern(s).
;
(define_insn "*mulsi3_sign"
- [(set (match_operand:SI 0 "register_operand" "=d")
- (mult:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R"))
- (match_operand:SI 1 "register_operand" "0")))]
+ [(set (match_operand:SI 0 "register_operand" "=d,d")
+ (mult:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T"))
+ (match_operand:SI 1 "register_operand" "0,0")))]
""
- "mh\t%0,%2"
- [(set_attr "op_type" "RX")
- (set_attr "type" "imulhi")])
+ "@
+ mh\t%0,%2
+ mhy\t%0,%2"
+ [(set_attr "op_type" "RX,RXY")
+ (set_attr "type" "imulhi")
+ (set_attr "cpu_facility" "*,z10")])
(define_insn "mulsi3"
- [(set (match_operand:SI 0 "register_operand" "=d,d,d,d")
- (mult:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
- (match_operand:SI 2 "general_operand" "d,K,R,T")))]
+ [(set (match_operand:SI 0 "register_operand" "=d,d,d,d,d")
+ (mult:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0,0")
+ (match_operand:SI 2 "general_operand" "d,K,R,T,Os")))]
""
"@
msr\t%0,%2
mhi\t%0,%h2
ms\t%0,%2
- msy\t%0,%2"
- [(set_attr "op_type" "RRE,RI,RX,RXY")
- (set_attr "type" "imulsi,imulhi,imulsi,imulsi")])
+ msy\t%0,%2
+ msfi\t%0,%2"
+ [(set_attr "op_type" "RRE,RI,RX,RXY,RIL")
+ (set_attr "type" "imulsi,imulhi,imulsi,imulsi,imulsi")
+ (set_attr "cpu_facility" "*,*,*,*,z10")])
;
; mulsidi3 instruction pattern(s).
;
(define_insn "mulsidi3"
- [(set (match_operand:DI 0 "register_operand" "=d,d")
+ [(set (match_operand:DI 0 "register_operand" "=d,d,d")
(mult:DI (sign_extend:DI
- (match_operand:SI 1 "register_operand" "%0,0"))
+ (match_operand:SI 1 "register_operand" "%0,0,0"))
(sign_extend:DI
- (match_operand:SI 2 "nonimmediate_operand" "d,R"))))]
+ (match_operand:SI 2 "nonimmediate_operand" "d,R,T"))))]
"!TARGET_64BIT"
"@
mr\t%0,%2
- m\t%0,%2"
- [(set_attr "op_type" "RR,RX")
- (set_attr "type" "imulsi")])
+ m\t%0,%2
+ mfy\t%0,%2"
+ [(set_attr "op_type" "RR,RX,RXY")
+ (set_attr "type" "imulsi")
+ (set_attr "cpu_facility" "*,*,z10")])
;
; umulsidi3 instruction pattern(s).
(mult:DI (zero_extend:DI
(match_operand:SI 1 "register_operand" "%0,0"))
(zero_extend:DI
- (match_operand:SI 2 "nonimmediate_operand" "d,m"))))]
+ (match_operand:SI 2 "nonimmediate_operand" "d,RT"))))]
"!TARGET_64BIT && TARGET_CPU_ZARCH"
"@
mlr\t%0,%2
(set_attr "type" "imulsi")])
;
-; mul(df|sf)3 instruction pattern(s).
+; mul(tf|df|sf|td|dd)3 instruction pattern(s).
;
-(define_expand "mul<mode>3"
- [(set (match_operand:FPR 0 "register_operand" "=f,f")
- (mult:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
- (match_operand:FPR 2 "general_operand" "f,R")))]
+; mxbr, mdbr, meebr, mxb, mxb, meeb, mdtr, mxtr
+(define_insn "mul<mode>3"
+ [(set (match_operand:FP 0 "register_operand" "=f,f")
+ (mult:FP (match_operand:FP 1 "nonimmediate_operand" "%<f0>,0")
+ (match_operand:FP 2 "general_operand" "f,<Rf>")))]
"TARGET_HARD_FLOAT"
- "")
-
-(define_insn "*mul<mode>3"
- [(set (match_operand:FPR 0 "register_operand" "=f,f")
- (mult:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
- (match_operand:FPR 2 "general_operand" "f,R")))]
- "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
- "@
- m<dee>br\t%0,%2
- m<dee>b\t%0,%2"
- [(set_attr "op_type" "RRE,RXE")
- (set_attr "type" "fmul<mode>")])
-
-(define_insn "*mul<mode>3_ibm"
- [(set (match_operand:FPR 0 "register_operand" "=f,f")
- (mult:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
- (match_operand:FPR 2 "general_operand" "f,R")))]
- "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
"@
- m<de>r\t%0,%2
- m<de>\t%0,%2"
- [(set_attr "op_type" "RR,RX")
+ m<xdee><bt>r\t%0,<op1>%2
+ m<xdee>b\t%0,%2"
+ [(set_attr "op_type" "<RRer>,RXE")
(set_attr "type" "fmul<mode>")])
+; madbr, maebr, maxb, madb, maeb
(define_insn "*fmadd<mode>"
- [(set (match_operand:FPR 0 "register_operand" "=f,f")
- (plus:FPR (mult:FPR (match_operand:FPR 1 "register_operand" "%f,f")
- (match_operand:FPR 2 "nonimmediate_operand" "f,R"))
- (match_operand:FPR 3 "register_operand" "0,0")))]
- "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT && TARGET_FUSED_MADD"
- "@
- ma<de>br\t%0,%1,%2
- ma<de>b\t%0,%1,%2"
+ [(set (match_operand:DSF 0 "register_operand" "=f,f")
+ (plus:DSF (mult:DSF (match_operand:DSF 1 "register_operand" "%f,f")
+ (match_operand:DSF 2 "nonimmediate_operand" "f,R"))
+ (match_operand:DSF 3 "register_operand" "0,0")))]
+ "TARGET_HARD_FLOAT && TARGET_FUSED_MADD"
+ "@
+ ma<xde>br\t%0,%1,%2
+ ma<xde>b\t%0,%1,%2"
[(set_attr "op_type" "RRE,RXE")
(set_attr "type" "fmul<mode>")])
+; msxbr, msdbr, msebr, msxb, msdb, mseb
(define_insn "*fmsub<mode>"
- [(set (match_operand:FPR 0 "register_operand" "=f,f")
- (minus:FPR (mult:FPR (match_operand:FPR 1 "register_operand" "f,f")
- (match_operand:FPR 2 "nonimmediate_operand" "f,R"))
- (match_operand:FPR 3 "register_operand" "0,0")))]
- "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT && TARGET_FUSED_MADD"
- "@
- ms<de>br\t%0,%1,%2
- ms<de>b\t%0,%1,%2"
+ [(set (match_operand:DSF 0 "register_operand" "=f,f")
+ (minus:DSF (mult:DSF (match_operand:DSF 1 "register_operand" "f,f")
+ (match_operand:DSF 2 "nonimmediate_operand" "f,R"))
+ (match_operand:DSF 3 "register_operand" "0,0")))]
+ "TARGET_HARD_FLOAT && TARGET_FUSED_MADD"
+ "@
+ ms<xde>br\t%0,%1,%2
+ ms<xde>b\t%0,%1,%2"
[(set_attr "op_type" "RRE,RXE")
(set_attr "type" "fmul<mode>")])
emit_insn (gen_divmodtidi3 (operands[4], operands[1], operands[2]));
insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4]));
- REG_NOTES (insn) =
- gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn));
+ set_unique_reg_note (insn, REG_EQUAL, div_equal);
insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4]));
- REG_NOTES (insn) =
- gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn));
+ set_unique_reg_note (insn, REG_EQUAL, mod_equal);
DONE;
})
(ashift:TI
(zero_extend:TI
(mod:DI (match_operand:DI 1 "register_operand" "0,0")
- (match_operand:DI 2 "general_operand" "d,m")))
+ (match_operand:DI 2 "general_operand" "d,RT")))
(const_int 64))
(zero_extend:TI (div:DI (match_dup 1) (match_dup 2)))))]
"TARGET_64BIT"
(zero_extend:TI
(mod:DI (match_operand:DI 1 "register_operand" "0,0")
(sign_extend:DI
- (match_operand:SI 2 "nonimmediate_operand" "d,m"))))
+ (match_operand:SI 2 "nonimmediate_operand" "d,RT"))))
(const_int 64))
(zero_extend:TI
(div:DI (match_dup 1) (sign_extend:DI (match_dup 2))))))]
gen_rtx_ZERO_EXTEND (TImode, div_equal));
operands[4] = gen_reg_rtx(TImode);
- emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[4]));
+ emit_clobber (operands[4]);
emit_move_insn (gen_lowpart (DImode, operands[4]), operands[1]);
emit_move_insn (gen_highpart (DImode, operands[4]), const0_rtx);
+
insn = emit_insn (gen_udivmodtidi3 (operands[4], operands[4], operands[2]));
- REG_NOTES (insn) =
- gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
+ set_unique_reg_note (insn, REG_EQUAL, equal);
insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4]));
- REG_NOTES (insn) =
- gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn));
+ set_unique_reg_note (insn, REG_EQUAL, div_equal);
insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4]));
- REG_NOTES (insn) =
- gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn));
+ set_unique_reg_note (insn, REG_EQUAL, mod_equal);
DONE;
})
(truncate:DI
(umod:TI (match_operand:TI 1 "register_operand" "0,0")
(zero_extend:TI
- (match_operand:DI 2 "nonimmediate_operand" "d,m")))))
+ (match_operand:DI 2 "nonimmediate_operand" "d,RT")))))
(const_int 64))
(zero_extend:TI
(truncate:DI
operands[4] = gen_reg_rtx(DImode);
emit_insn (gen_extendsidi2 (operands[4], operands[1]));
+
insn = emit_insn (gen_divmoddisi3 (operands[4], operands[4], operands[2]));
- REG_NOTES (insn) =
- gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
+ set_unique_reg_note (insn, REG_EQUAL, equal);
insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4]));
- REG_NOTES (insn) =
- gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn));
+ set_unique_reg_note (insn, REG_EQUAL, div_equal);
insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4]));
- REG_NOTES (insn) =
- gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn));
+ set_unique_reg_note (insn, REG_EQUAL, mod_equal);
DONE;
})
gen_rtx_ZERO_EXTEND (DImode, div_equal));
operands[4] = gen_reg_rtx(DImode);
- emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[4]));
+ emit_clobber (operands[4]);
emit_move_insn (gen_lowpart (SImode, operands[4]), operands[1]);
emit_move_insn (gen_highpart (SImode, operands[4]), const0_rtx);
+
insn = emit_insn (gen_udivmoddisi3 (operands[4], operands[4], operands[2]));
- REG_NOTES (insn) =
- gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
+ set_unique_reg_note (insn, REG_EQUAL, equal);
insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4]));
- REG_NOTES (insn) =
- gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn));
+ set_unique_reg_note (insn, REG_EQUAL, div_equal);
insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4]));
- REG_NOTES (insn) =
- gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn));
+ set_unique_reg_note (insn, REG_EQUAL, mod_equal);
DONE;
})
(truncate:SI
(umod:DI (match_operand:DI 1 "register_operand" "0,0")
(zero_extend:DI
- (match_operand:SI 2 "nonimmediate_operand" "d,m")))))
+ (match_operand:SI 2 "nonimmediate_operand" "d,RT")))))
(const_int 32))
(zero_extend:DI
(truncate:SI
emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
operands[2]));
- REG_NOTES (insn) =
- gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
+ set_unique_reg_note (insn, REG_EQUAL, equal);
insn = emit_move_insn (operands[0],
gen_lowpart (SImode, operands[3]));
- REG_NOTES (insn) =
- gen_rtx_EXPR_LIST (REG_EQUAL,
- udiv_equal, REG_NOTES (insn));
+ set_unique_reg_note (insn, REG_EQUAL, udiv_equal);
}
}
else
emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
operands[2]));
- REG_NOTES (insn) =
- gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
+ set_unique_reg_note (insn, REG_EQUAL, equal);
insn = emit_move_insn (operands[0],
gen_lowpart (SImode, operands[3]));
- REG_NOTES (insn) =
- gen_rtx_EXPR_LIST (REG_EQUAL,
- udiv_equal, REG_NOTES (insn));
+ set_unique_reg_note (insn, REG_EQUAL, udiv_equal);
+
emit_jump (label3);
emit_label (label1);
emit_move_insn (operands[0], operands[1]);
emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
operands[2]));
- REG_NOTES (insn) =
- gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
+ set_unique_reg_note (insn, REG_EQUAL, equal);
insn = emit_move_insn (operands[0],
gen_highpart (SImode, operands[3]));
- REG_NOTES (insn) =
- gen_rtx_EXPR_LIST (REG_EQUAL,
- umod_equal, REG_NOTES (insn));
+ set_unique_reg_note (insn, REG_EQUAL, umod_equal);
}
}
else
emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
operands[2]));
- REG_NOTES (insn) =
- gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
+ set_unique_reg_note (insn, REG_EQUAL, equal);
insn = emit_move_insn (operands[0],
gen_highpart (SImode, operands[3]));
- REG_NOTES (insn) =
- gen_rtx_EXPR_LIST (REG_EQUAL,
- umod_equal, REG_NOTES (insn));
+ set_unique_reg_note (insn, REG_EQUAL, umod_equal);
+
emit_jump (label3);
emit_label (label1);
emit_move_insn (operands[0], const0_rtx);
; div(df|sf)3 instruction pattern(s).
;
-(define_expand "div<mode>3"
- [(set (match_operand:FPR 0 "register_operand" "=f,f")
- (div:FPR (match_operand:FPR 1 "register_operand" "0,0")
- (match_operand:FPR 2 "general_operand" "f,R")))]
+; dxbr, ddbr, debr, dxb, ddb, deb, ddtr, dxtr
+(define_insn "div<mode>3"
+ [(set (match_operand:FP 0 "register_operand" "=f,f")
+ (div:FP (match_operand:FP 1 "register_operand" "<f0>,0")
+ (match_operand:FP 2 "general_operand" "f,<Rf>")))]
"TARGET_HARD_FLOAT"
- "")
-
-(define_insn "*div<mode>3"
- [(set (match_operand:FPR 0 "register_operand" "=f,f")
- (div:FPR (match_operand:FPR 1 "register_operand" "0,0")
- (match_operand:FPR 2 "general_operand" "f,R")))]
- "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
- "@
- d<de>br\t%0,%2
- d<de>b\t%0,%2"
- [(set_attr "op_type" "RRE,RXE")
- (set_attr "type" "fdiv<mode>")])
-
-(define_insn "*div<mode>3_ibm"
- [(set (match_operand:FPR 0 "register_operand" "=f,f")
- (div:FPR (match_operand:FPR 1 "register_operand" "0,0")
- (match_operand:FPR 2 "general_operand" "f,R")))]
- "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
"@
- d<de>r\t%0,%2
- d<de>\t%0,%2"
- [(set_attr "op_type" "RR,RX")
+ d<xde><bt>r\t%0,<op1>%2
+ d<xde>b\t%0,%2"
+ [(set_attr "op_type" "<RRer>,RXE")
(set_attr "type" "fdiv<mode>")])
(define_insn "*anddi3_cc"
[(set (reg CC_REGNUM)
(compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
- (match_operand:DI 2 "general_operand" "d,m"))
+ (match_operand:DI 2 "general_operand" "d,RT"))
(const_int 0)))
(set (match_operand:DI 0 "register_operand" "=d,d")
(and:DI (match_dup 1) (match_dup 2)))]
"@
ngr\t%0,%2
ng\t%0,%2"
- [(set_attr "op_type" "RRE,RXY")])
+ [(set_attr "op_type" "RRE,RXY")
+ (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
(define_insn "*anddi3_cconly"
[(set (reg CC_REGNUM)
(compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
- (match_operand:DI 2 "general_operand" "d,m"))
+ (match_operand:DI 2 "general_operand" "d,RT"))
(const_int 0)))
(clobber (match_scratch:DI 0 "=d,d"))]
"s390_match_ccmode(insn, CCTmode) && TARGET_64BIT
"@
ngr\t%0,%2
ng\t%0,%2"
- [(set_attr "op_type" "RRE,RXY")])
+ [(set_attr "op_type" "RRE,RXY")
+ (set_attr "z10prop" "z10_super_E1, z10_super_E1")])
-(define_insn "*anddi3_extimm"
+(define_insn "*anddi3"
[(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,d,d,d,d,d,AQ,Q")
(and:DI (match_operand:DI 1 "nonimmediate_operand"
"%d,o,0,0,0,0,0,0,0,0,0,0")
(match_operand:DI 2 "general_operand"
- "M,M,N0HDF,N1HDF,N2HDF,N3HDF,N0SDF,N1SDF,d,m,NxQDF,Q")))
+ "M,M,N0HDF,N1HDF,N2HDF,N3HDF,N0SDF,N1SDF,d,RT,NxQDF,Q")))
(clobber (reg:CC CC_REGNUM))]
- "TARGET_64BIT && TARGET_EXTIMM && s390_logical_operator_ok_p (operands)"
+ "TARGET_64BIT && s390_logical_operator_ok_p (operands)"
"@
#
#
ng\t%0,%2
#
#"
- [(set_attr "op_type" "RRE,RXE,RI,RI,RI,RI,RIL,RIL,RRE,RXY,SI,SS")])
-
-(define_insn "*anddi3"
- [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,d,d,d,AQ,Q")
- (and:DI (match_operand:DI 1 "nonimmediate_operand"
- "%d,o,0,0,0,0,0,0,0,0")
- (match_operand:DI 2 "general_operand"
- "M,M,N0HDF,N1HDF,N2HDF,N3HDF,d,m,NxQDF,Q")))
- (clobber (reg:CC CC_REGNUM))]
- "TARGET_64BIT && !TARGET_EXTIMM && s390_logical_operator_ok_p (operands)"
- "@
- #
- #
- nihh\t%0,%j2
- nihl\t%0,%j2
- nilh\t%0,%j2
- nill\t%0,%j2
- ngr\t%0,%2
- ng\t%0,%2
- #
- #"
- [(set_attr "op_type" "RRE,RXE,RI,RI,RI,RI,RRE,RXY,SI,SS")])
+ [(set_attr "op_type" "RRE,RXE,RI,RI,RI,RI,RIL,RIL,RRE,RXY,SI,SS")
+ (set_attr "cpu_facility" "*,*,*,*,*,*,extimm,extimm,*,*,*,*")
+ (set_attr "z10prop" "*,
+ *,
+ z10_super_E1,
+ z10_super_E1,
+ z10_super_E1,
+ z10_super_E1,
+ z10_super_E1,
+ z10_super_E1,
+ z10_super_E1,
+ z10_super_E1,
+ *,
+ *")])
(define_split
[(set (match_operand:DI 0 "s_operand" "")
nr\t%0,%2
n\t%0,%2
ny\t%0,%2"
- [(set_attr "op_type" "RIL,RR,RX,RXY")])
+ [(set_attr "op_type" "RIL,RR,RX,RXY")
+ (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1")])
(define_insn "*andsi3_cconly"
[(set (reg CC_REGNUM)
nr\t%0,%2
n\t%0,%2
ny\t%0,%2"
- [(set_attr "op_type" "RIL,RR,RX,RXY")])
+ [(set_attr "op_type" "RIL,RR,RX,RXY")
+ (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1")])
(define_insn "*andsi3_zarch"
[(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d,d,d,d,AQ,Q")
ny\t%0,%2
#
#"
- [(set_attr "op_type" "RRE,RXE,RI,RI,RIL,RR,RX,RXY,SI,SS")])
+ [(set_attr "op_type" "RRE,RXE,RI,RI,RIL,RR,RX,RXY,SI,SS")
+ (set_attr "z10prop" "*,
+ *,
+ z10_super_E1,
+ z10_super_E1,
+ z10_super_E1,
+ z10_super_E1,
+ z10_super_E1,
+ z10_super_E1,
+ *,
+ *")])
(define_insn "*andsi3_esa"
[(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,AQ,Q")
n\t%0,%2
#
#"
- [(set_attr "op_type" "RR,RX,SI,SS")])
+ [(set_attr "op_type" "RR,RX,SI,SS")
+ (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*")])
+
(define_split
[(set (match_operand:SI 0 "s_operand" "")
nill\t%0,%x2
#
#"
- [(set_attr "op_type" "RR,RI,SI,SS")])
+ [(set_attr "op_type" "RR,RI,SI,SS")
+ (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*")
+])
(define_insn "*andhi3_esa"
[(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q")
nr\t%0,%2
#
#"
- [(set_attr "op_type" "RR,SI,SS")])
+ [(set_attr "op_type" "RR,SI,SS")
+ (set_attr "z10prop" "z10_super_E1,*,*")
+])
(define_split
[(set (match_operand:HI 0 "s_operand" "")
ni\t%S0,%b2
niy\t%S0,%b2
#"
- [(set_attr "op_type" "RR,RI,SI,SIY,SS")])
+ [(set_attr "op_type" "RR,RI,SI,SIY,SS")
+ (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super,z10_super,*")])
(define_insn "*andqi3_esa"
[(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q")
nr\t%0,%2
ni\t%S0,%b2
#"
- [(set_attr "op_type" "RR,SI,SS")])
+ [(set_attr "op_type" "RR,SI,SS")
+ (set_attr "z10prop" "z10_super_E1,z10_super,*")])
;
; Block and (NC) patterns.
(clobber (reg:CC CC_REGNUM))])]
"s390_offset_p (operands[0], operands[3], operands[2])
&& s390_offset_p (operands[1], operands[4], operands[2])
- && !s390_overlap_p (operands[0], operands[1],
+ && !s390_overlap_p (operands[0], operands[1],
INTVAL (operands[2]) + INTVAL (operands[5]))
&& INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
[(parallel
(define_insn "*iordi3_cc"
[(set (reg CC_REGNUM)
(compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
- (match_operand:DI 2 "general_operand" "d,m"))
+ (match_operand:DI 2 "general_operand" "d,RT"))
(const_int 0)))
(set (match_operand:DI 0 "register_operand" "=d,d")
(ior:DI (match_dup 1) (match_dup 2)))]
"@
ogr\t%0,%2
og\t%0,%2"
- [(set_attr "op_type" "RRE,RXY")])
+ [(set_attr "op_type" "RRE,RXY")
+ (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
(define_insn "*iordi3_cconly"
[(set (reg CC_REGNUM)
(compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
- (match_operand:DI 2 "general_operand" "d,m"))
+ (match_operand:DI 2 "general_operand" "d,RT"))
(const_int 0)))
(clobber (match_scratch:DI 0 "=d,d"))]
"s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
"@
ogr\t%0,%2
og\t%0,%2"
- [(set_attr "op_type" "RRE,RXY")])
+ [(set_attr "op_type" "RRE,RXY")
+ (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
-(define_insn "*iordi3_extimm"
+(define_insn "*iordi3"
[(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,d,d,d,AQ,Q")
(ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0,0,0,0,0,0,0")
(match_operand:DI 2 "general_operand"
- "N0HD0,N1HD0,N2HD0,N3HD0,N0SD0,N1SD0,d,m,NxQD0,Q")))
+ "N0HD0,N1HD0,N2HD0,N3HD0,N0SD0,N1SD0,d,RT,NxQD0,Q")))
(clobber (reg:CC CC_REGNUM))]
- "TARGET_64BIT && TARGET_EXTIMM && s390_logical_operator_ok_p (operands)"
+ "TARGET_64BIT && s390_logical_operator_ok_p (operands)"
"@
oihh\t%0,%i2
oihl\t%0,%i2
og\t%0,%2
#
#"
- [(set_attr "op_type" "RI,RI,RI,RI,RIL,RIL,RRE,RXY,SI,SS")])
-
-(define_insn "*iordi3"
- [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,d,AQ,Q")
- (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0,0,0,0,0")
- (match_operand:DI 2 "general_operand"
- "N0HD0,N1HD0,N2HD0,N3HD0,d,m,NxQD0,Q")))
- (clobber (reg:CC CC_REGNUM))]
- "TARGET_64BIT && !TARGET_EXTIMM && s390_logical_operator_ok_p (operands)"
- "@
- oihh\t%0,%i2
- oihl\t%0,%i2
- oilh\t%0,%i2
- oill\t%0,%i2
- ogr\t%0,%2
- og\t%0,%2
- #
- #"
- [(set_attr "op_type" "RI,RI,RI,RI,RRE,RXY,SI,SS")])
+ [(set_attr "op_type" "RI,RI,RI,RI,RIL,RIL,RRE,RXY,SI,SS")
+ (set_attr "cpu_facility" "*,*,*,*,extimm,extimm,*,*,*,*")
+ (set_attr "z10prop" "z10_super_E1,
+ z10_super_E1,
+ z10_super_E1,
+ z10_super_E1,
+ z10_super_E1,
+ z10_super_E1,
+ z10_super_E1,
+ z10_super_E1,
+ *,
+ *")])
(define_split
[(set (match_operand:DI 0 "s_operand" "")
or\t%0,%2
o\t%0,%2
oy\t%0,%2"
- [(set_attr "op_type" "RIL,RR,RX,RXY")])
+ [(set_attr "op_type" "RIL,RR,RX,RXY")
+ (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1")])
(define_insn "*iorsi3_cconly"
[(set (reg CC_REGNUM)
or\t%0,%2
o\t%0,%2
oy\t%0,%2"
- [(set_attr "op_type" "RIL,RR,RX,RXY")])
+ [(set_attr "op_type" "RIL,RR,RX,RXY")
+ (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1")])
(define_insn "*iorsi3_zarch"
[(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d,d,AQ,Q")
oy\t%0,%2
#
#"
- [(set_attr "op_type" "RI,RI,RIL,RR,RX,RXY,SI,SS")])
+ [(set_attr "op_type" "RI,RI,RIL,RR,RX,RXY,SI,SS")
+ (set_attr "z10prop" "z10_super_E1,
+ z10_super_E1,
+ z10_super_E1,
+ z10_super_E1,
+ z10_super_E1,
+ z10_super_E1,
+ *,
+ *")])
(define_insn "*iorsi3_esa"
[(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,AQ,Q")
o\t%0,%2
#
#"
- [(set_attr "op_type" "RR,RX,SI,SS")])
+ [(set_attr "op_type" "RR,RX,SI,SS")
+ (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*")])
(define_split
[(set (match_operand:SI 0 "s_operand" "")
oill\t%0,%x2
#
#"
- [(set_attr "op_type" "RR,RI,SI,SS")])
+ [(set_attr "op_type" "RR,RI,SI,SS")
+ (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*")])
(define_insn "*iorhi3_esa"
[(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q")
or\t%0,%2
#
#"
- [(set_attr "op_type" "RR,SI,SS")])
+ [(set_attr "op_type" "RR,SI,SS")
+ (set_attr "z10prop" "z10_super_E1,*,*")])
(define_split
[(set (match_operand:HI 0 "s_operand" "")
oi\t%S0,%b2
oiy\t%S0,%b2
#"
- [(set_attr "op_type" "RR,RI,SI,SIY,SS")])
+ [(set_attr "op_type" "RR,RI,SI,SIY,SS")
+ (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super,z10_super,*")])
(define_insn "*iorqi3_esa"
[(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q")
or\t%0,%2
oi\t%S0,%b2
#"
- [(set_attr "op_type" "RR,SI,SS")])
+ [(set_attr "op_type" "RR,SI,SS")
+ (set_attr "z10prop" "z10_super_E1,z10_super,*")])
;
; Block inclusive or (OC) patterns.
(clobber (reg:CC CC_REGNUM))])]
"s390_offset_p (operands[0], operands[3], operands[2])
&& s390_offset_p (operands[1], operands[4], operands[2])
- && !s390_overlap_p (operands[0], operands[1],
+ && !s390_overlap_p (operands[0], operands[1],
INTVAL (operands[2]) + INTVAL (operands[5]))
&& INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
[(parallel
(define_insn "*xordi3_cc"
[(set (reg CC_REGNUM)
(compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
- (match_operand:DI 2 "general_operand" "d,m"))
+ (match_operand:DI 2 "general_operand" "d,RT"))
(const_int 0)))
(set (match_operand:DI 0 "register_operand" "=d,d")
(xor:DI (match_dup 1) (match_dup 2)))]
"@
xgr\t%0,%2
xg\t%0,%2"
- [(set_attr "op_type" "RRE,RXY")])
+ [(set_attr "op_type" "RRE,RXY")
+ (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
(define_insn "*xordi3_cconly"
[(set (reg CC_REGNUM)
(compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
- (match_operand:DI 2 "general_operand" "d,m"))
+ (match_operand:DI 2 "general_operand" "d,RT"))
(const_int 0)))
(clobber (match_scratch:DI 0 "=d,d"))]
"s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
"@
xgr\t%0,%2
- xr\t%0,%2"
- [(set_attr "op_type" "RRE,RXY")])
+ xg\t%0,%2"
+ [(set_attr "op_type" "RRE,RXY")
+ (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
-(define_insn "*xordi3_extimm"
+(define_insn "*xordi3"
[(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,AQ,Q")
(xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0,0,0")
- (match_operand:DI 2 "general_operand" "N0SD0,N1SD0,d,m,NxQD0,Q")))
+ (match_operand:DI 2 "general_operand" "N0SD0,N1SD0,d,RT,NxQD0,Q")))
(clobber (reg:CC CC_REGNUM))]
- "TARGET_64BIT && TARGET_EXTIMM && s390_logical_operator_ok_p (operands)"
+ "TARGET_64BIT && s390_logical_operator_ok_p (operands)"
"@
xihf\t%0,%k2
xilf\t%0,%k2
xg\t%0,%2
#
#"
- [(set_attr "op_type" "RIL,RIL,RRE,RXY,SI,SS")])
-
-(define_insn "*xordi3"
- [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,AQ,Q")
- (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0")
- (match_operand:DI 2 "general_operand" "d,m,NxQD0,Q")))
- (clobber (reg:CC CC_REGNUM))]
- "TARGET_64BIT && !TARGET_EXTIMM && s390_logical_operator_ok_p (operands)"
- "@
- xgr\t%0,%2
- xg\t%0,%2
- #
- #"
- [(set_attr "op_type" "RRE,RXY,SI,SS")])
+ [(set_attr "op_type" "RIL,RIL,RRE,RXY,SI,SS")
+ (set_attr "cpu_facility" "extimm,extimm,*,*,*,*")
+ (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1,*,*")])
(define_split
[(set (match_operand:DI 0 "s_operand" "")
xr\t%0,%2
x\t%0,%2
xy\t%0,%2"
- [(set_attr "op_type" "RIL,RR,RX,RXY")])
+ [(set_attr "op_type" "RIL,RR,RX,RXY")
+ (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1")])
(define_insn "*xorsi3_cconly"
[(set (reg CC_REGNUM)
xr\t%0,%2
x\t%0,%2
xy\t%0,%2"
- [(set_attr "op_type" "RIL,RR,RX,RXY")])
+ [(set_attr "op_type" "RIL,RR,RX,RXY")
+ (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1")])
(define_insn "*xorsi3"
[(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,AQ,Q")
xy\t%0,%2
#
#"
- [(set_attr "op_type" "RIL,RR,RX,RXY,SI,SS")])
+ [(set_attr "op_type" "RIL,RR,RX,RXY,SI,SS")
+ (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1,*,*")])
(define_split
[(set (match_operand:SI 0 "s_operand" "")
xr\t%0,%2
#
#"
- [(set_attr "op_type" "RIL,RR,SI,SS")])
+ [(set_attr "op_type" "RIL,RR,SI,SS")
+ (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*")])
(define_split
[(set (match_operand:HI 0 "s_operand" "")
xi\t%S0,%b2
xiy\t%S0,%b2
#"
- [(set_attr "op_type" "RIL,RR,SI,SIY,SS")])
+ [(set_attr "op_type" "RIL,RR,SI,SIY,SS")
+ (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super,z10_super,*")])
+
;
; Block exclusive or (XC) patterns.
(clobber (reg:CC CC_REGNUM))])]
"s390_offset_p (operands[0], operands[3], operands[2])
&& s390_offset_p (operands[1], operands[4], operands[2])
- && !s390_overlap_p (operands[0], operands[1],
+ && !s390_overlap_p (operands[0], operands[1],
INTVAL (operands[2]) + INTVAL (operands[5]))
&& INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
[(parallel
(neg:DI (sign_extend:DI (match_dup 1))))]
"TARGET_64BIT && s390_match_ccmode (insn, CCAmode)"
"lcgfr\t%0,%1"
- [(set_attr "op_type" "RRE")])
-
+ [(set_attr "op_type" "RRE")
+ (set_attr "z10prop" "z10_c")])
+
(define_insn "*negdi2_sign"
[(set (match_operand:DI 0 "register_operand" "=d")
(neg:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))))
(clobber (reg:CC CC_REGNUM))]
"TARGET_64BIT"
"lcgfr\t%0,%1"
- [(set_attr "op_type" "RRE")])
+ [(set_attr "op_type" "RRE")
+ (set_attr "z10prop" "z10_c")])
+; lcr, lcgr
(define_insn "*neg<mode>2_cc"
[(set (reg CC_REGNUM)
(compare (neg:GPR (match_operand:GPR 1 "register_operand" "d"))
(neg:GPR (match_dup 1)))]
"s390_match_ccmode (insn, CCAmode)"
"lc<g>r\t%0,%1"
- [(set_attr "op_type" "RR<E>")])
-
+ [(set_attr "op_type" "RR<E>")
+ (set_attr "z10prop" "z10_super_c_E1")])
+
+; lcr, lcgr
(define_insn "*neg<mode>2_cconly"
[(set (reg CC_REGNUM)
(compare (neg:GPR (match_operand:GPR 1 "register_operand" "d"))
(clobber (match_scratch:GPR 0 "=d"))]
"s390_match_ccmode (insn, CCAmode)"
"lc<g>r\t%0,%1"
- [(set_attr "op_type" "RR<E>")])
-
+ [(set_attr "op_type" "RR<E>")
+ (set_attr "z10prop" "z10_super_c_E1")])
+
+; lcr, lcgr
(define_insn "*neg<mode>2"
[(set (match_operand:GPR 0 "register_operand" "=d")
(neg:GPR (match_operand:GPR 1 "register_operand" "d")))
(clobber (reg:CC CC_REGNUM))]
""
"lc<g>r\t%0,%1"
- [(set_attr "op_type" "RR<E>")])
+ [(set_attr "op_type" "RR<E>")
+ (set_attr "z10prop" "z10_super_c_E1")])
(define_insn_and_split "*negdi2_31"
[(set (match_operand:DI 0 "register_operand" "=d")
(define_expand "neg<mode>2"
[(parallel
- [(set (match_operand:FPR 0 "register_operand" "=f")
- (neg:FPR (match_operand:FPR 1 "register_operand" "f")))
+ [(set (match_operand:BFP 0 "register_operand" "=f")
+ (neg:BFP (match_operand:BFP 1 "register_operand" "f")))
(clobber (reg:CC CC_REGNUM))])]
"TARGET_HARD_FLOAT"
"")
+; lcxbr, lcdbr, lcebr
(define_insn "*neg<mode>2_cc"
[(set (reg CC_REGNUM)
- (compare (neg:FPR (match_operand:FPR 1 "register_operand" "f"))
- (match_operand:FPR 2 "const0_operand" "")))
- (set (match_operand:FPR 0 "register_operand" "=f")
- (neg:FPR (match_dup 1)))]
- "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
- "lc<de>br\t%0,%1"
+ (compare (neg:BFP (match_operand:BFP 1 "register_operand" "f"))
+ (match_operand:BFP 2 "const0_operand" "")))
+ (set (match_operand:BFP 0 "register_operand" "=f")
+ (neg:BFP (match_dup 1)))]
+ "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
+ "lc<xde>br\t%0,%1"
[(set_attr "op_type" "RRE")
(set_attr "type" "fsimp<mode>")])
-
+
+; lcxbr, lcdbr, lcebr
(define_insn "*neg<mode>2_cconly"
[(set (reg CC_REGNUM)
- (compare (neg:FPR (match_operand:FPR 1 "register_operand" "f"))
- (match_operand:FPR 2 "const0_operand" "")))
- (clobber (match_scratch:FPR 0 "=f"))]
- "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
- "lc<de>br\t%0,%1"
+ (compare (neg:BFP (match_operand:BFP 1 "register_operand" "f"))
+ (match_operand:BFP 2 "const0_operand" "")))
+ (clobber (match_scratch:BFP 0 "=f"))]
+ "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
+ "lc<xde>br\t%0,%1"
[(set_attr "op_type" "RRE")
(set_attr "type" "fsimp<mode>")])
-
-(define_insn "*neg<mode>2"
- [(set (match_operand:FPR 0 "register_operand" "=f")
- (neg:FPR (match_operand:FPR 1 "register_operand" "f")))
- (clobber (reg:CC CC_REGNUM))]
- "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
- "lc<de>br\t%0,%1"
+
+; lcdfr
+(define_insn "*neg<mode>2_nocc"
+ [(set (match_operand:FP 0 "register_operand" "=f")
+ (neg:FP (match_operand:FP 1 "register_operand" "<fT0>")))]
+ "TARGET_DFP"
+ "lcdfr\t%0,%1"
[(set_attr "op_type" "RRE")
(set_attr "type" "fsimp<mode>")])
-(define_insn "*neg<mode>2_ibm"
- [(set (match_operand:FPR 0 "register_operand" "=f")
- (neg:FPR (match_operand:FPR 1 "register_operand" "f")))
+; lcxbr, lcdbr, lcebr
+(define_insn "*neg<mode>2"
+ [(set (match_operand:BFP 0 "register_operand" "=f")
+ (neg:BFP (match_operand:BFP 1 "register_operand" "f")))
(clobber (reg:CC CC_REGNUM))]
- "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
- "lc<de>r\t%0,%1"
- [(set_attr "op_type" "RR")
+ "TARGET_HARD_FLOAT"
+ "lc<xde>br\t%0,%1"
+ [(set_attr "op_type" "RRE")
(set_attr "type" "fsimp<mode>")])
(abs:DI (sign_extend:DI (match_dup 1))))]
"TARGET_64BIT && s390_match_ccmode (insn, CCAmode)"
"lpgfr\t%0,%1"
- [(set_attr "op_type" "RRE")])
+ [(set_attr "op_type" "RRE")
+ (set_attr "z10prop" "z10_c")])
(define_insn "*absdi2_sign"
[(set (match_operand:DI 0 "register_operand" "=d")
(clobber (reg:CC CC_REGNUM))]
"TARGET_64BIT"
"lpgfr\t%0,%1"
- [(set_attr "op_type" "RRE")])
+ [(set_attr "op_type" "RRE")
+ (set_attr "z10prop" "z10_c")])
+; lpr, lpgr
(define_insn "*abs<mode>2_cc"
[(set (reg CC_REGNUM)
(compare (abs:GPR (match_operand:DI 1 "register_operand" "d"))
(abs:GPR (match_dup 1)))]
"s390_match_ccmode (insn, CCAmode)"
"lp<g>r\t%0,%1"
- [(set_attr "op_type" "RR<E>")])
-
+ [(set_attr "op_type" "RR<E>")
+ (set_attr "z10prop" "z10_c")])
+
+; lpr, lpgr
(define_insn "*abs<mode>2_cconly"
[(set (reg CC_REGNUM)
(compare (abs:GPR (match_operand:GPR 1 "register_operand" "d"))
(clobber (match_scratch:GPR 0 "=d"))]
"s390_match_ccmode (insn, CCAmode)"
"lp<g>r\t%0,%1"
- [(set_attr "op_type" "RR<E>")])
-
+ [(set_attr "op_type" "RR<E>")
+ (set_attr "z10prop" "z10_c")])
+
+; lpr, lpgr
(define_insn "abs<mode>2"
[(set (match_operand:GPR 0 "register_operand" "=d")
(abs:GPR (match_operand:GPR 1 "register_operand" "d")))
(clobber (reg:CC CC_REGNUM))]
""
"lp<g>r\t%0,%1"
- [(set_attr "op_type" "RR<E>")])
+ [(set_attr "op_type" "RR<E>")
+ (set_attr "z10prop" "z10_c")])
;
; abs(df|sf)2 instruction pattern(s).
(define_expand "abs<mode>2"
[(parallel
- [(set (match_operand:FPR 0 "register_operand" "=f")
- (abs:FPR (match_operand:FPR 1 "register_operand" "f")))
+ [(set (match_operand:BFP 0 "register_operand" "=f")
+ (abs:BFP (match_operand:BFP 1 "register_operand" "f")))
(clobber (reg:CC CC_REGNUM))])]
"TARGET_HARD_FLOAT"
"")
+; lpxbr, lpdbr, lpebr
(define_insn "*abs<mode>2_cc"
[(set (reg CC_REGNUM)
- (compare (abs:FPR (match_operand:FPR 1 "register_operand" "f"))
- (match_operand:FPR 2 "const0_operand" "")))
- (set (match_operand:FPR 0 "register_operand" "=f")
- (abs:FPR (match_dup 1)))]
- "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
- "lp<de>br\t%0,%1"
+ (compare (abs:BFP (match_operand:BFP 1 "register_operand" "f"))
+ (match_operand:BFP 2 "const0_operand" "")))
+ (set (match_operand:BFP 0 "register_operand" "=f")
+ (abs:BFP (match_dup 1)))]
+ "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
+ "lp<xde>br\t%0,%1"
[(set_attr "op_type" "RRE")
(set_attr "type" "fsimp<mode>")])
-
+
+; lpxbr, lpdbr, lpebr
(define_insn "*abs<mode>2_cconly"
[(set (reg CC_REGNUM)
- (compare (abs:FPR (match_operand:FPR 1 "register_operand" "f"))
- (match_operand:FPR 2 "const0_operand" "")))
- (clobber (match_scratch:FPR 0 "=f"))]
- "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
- "lp<de>br\t%0,%1"
+ (compare (abs:BFP (match_operand:BFP 1 "register_operand" "f"))
+ (match_operand:BFP 2 "const0_operand" "")))
+ (clobber (match_scratch:BFP 0 "=f"))]
+ "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
+ "lp<xde>br\t%0,%1"
[(set_attr "op_type" "RRE")
(set_attr "type" "fsimp<mode>")])
-
-(define_insn "*abs<mode>2"
- [(set (match_operand:FPR 0 "register_operand" "=f")
- (abs:FPR (match_operand:FPR 1 "register_operand" "f")))
- (clobber (reg:CC CC_REGNUM))]
- "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
- "lp<de>br\t%0,%1"
+
+; lpdfr
+(define_insn "*abs<mode>2_nocc"
+ [(set (match_operand:FP 0 "register_operand" "=f")
+ (abs:FP (match_operand:FP 1 "register_operand" "<fT0>")))]
+ "TARGET_DFP"
+ "lpdfr\t%0,%1"
[(set_attr "op_type" "RRE")
(set_attr "type" "fsimp<mode>")])
-(define_insn "*abs<mode>2_ibm"
- [(set (match_operand:FPR 0 "register_operand" "=f")
- (abs:FPR (match_operand:FPR 1 "register_operand" "f")))
+; lpxbr, lpdbr, lpebr
+(define_insn "*abs<mode>2"
+ [(set (match_operand:BFP 0 "register_operand" "=f")
+ (abs:BFP (match_operand:BFP 1 "register_operand" "f")))
(clobber (reg:CC CC_REGNUM))]
- "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
- "lp<de>r\t%0,%1"
- [(set_attr "op_type" "RR")
+ "TARGET_HARD_FLOAT"
+ "lp<xde>br\t%0,%1"
+ [(set_attr "op_type" "RRE")
(set_attr "type" "fsimp<mode>")])
+
;;
;;- Negated absolute value instructions
;;
(neg:DI (abs:DI (sign_extend:DI (match_dup 1)))))]
"TARGET_64BIT && s390_match_ccmode (insn, CCAmode)"
"lngfr\t%0,%1"
- [(set_attr "op_type" "RRE")])
-
+ [(set_attr "op_type" "RRE")
+ (set_attr "z10prop" "z10_c")])
+
(define_insn "*negabsdi2_sign"
[(set (match_operand:DI 0 "register_operand" "=d")
(neg:DI (abs:DI (sign_extend:DI
(clobber (reg:CC CC_REGNUM))]
"TARGET_64BIT"
"lngfr\t%0,%1"
- [(set_attr "op_type" "RRE")])
+ [(set_attr "op_type" "RRE")
+ (set_attr "z10prop" "z10_c")])
+; lnr, lngr
(define_insn "*negabs<mode>2_cc"
[(set (reg CC_REGNUM)
(compare (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d")))
(neg:GPR (abs:GPR (match_dup 1))))]
"s390_match_ccmode (insn, CCAmode)"
"ln<g>r\t%0,%1"
- [(set_attr "op_type" "RR<E>")])
-
+ [(set_attr "op_type" "RR<E>")
+ (set_attr "z10prop" "z10_c")])
+
+; lnr, lngr
(define_insn "*negabs<mode>2_cconly"
[(set (reg CC_REGNUM)
(compare (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d")))
(clobber (match_scratch:GPR 0 "=d"))]
"s390_match_ccmode (insn, CCAmode)"
"ln<g>r\t%0,%1"
- [(set_attr "op_type" "RR<E>")])
-
+ [(set_attr "op_type" "RR<E>")
+ (set_attr "z10prop" "z10_c")])
+
+; lnr, lngr
(define_insn "*negabs<mode>2"
[(set (match_operand:GPR 0 "register_operand" "=d")
(neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d"))))
(clobber (reg:CC CC_REGNUM))]
""
"ln<g>r\t%0,%1"
- [(set_attr "op_type" "RR<E>")])
+ [(set_attr "op_type" "RR<E>")
+ (set_attr "z10prop" "z10_c")])
;
; Floating point
;
+; lnxbr, lndbr, lnebr
(define_insn "*negabs<mode>2_cc"
[(set (reg CC_REGNUM)
- (compare (neg:FPR (abs:FPR (match_operand:FPR 1 "register_operand" "f")))
- (match_operand:FPR 2 "const0_operand" "")))
- (set (match_operand:FPR 0 "register_operand" "=f")
- (neg:FPR (abs:FPR (match_dup 1))))]
- "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
- "ln<de>br\t%0,%1"
+ (compare (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f")))
+ (match_operand:BFP 2 "const0_operand" "")))
+ (set (match_operand:BFP 0 "register_operand" "=f")
+ (neg:BFP (abs:BFP (match_dup 1))))]
+ "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
+ "ln<xde>br\t%0,%1"
[(set_attr "op_type" "RRE")
(set_attr "type" "fsimp<mode>")])
-
+
+; lnxbr, lndbr, lnebr
(define_insn "*negabs<mode>2_cconly"
[(set (reg CC_REGNUM)
- (compare (neg:FPR (abs:FPR (match_operand:FPR 1 "register_operand" "f")))
- (match_operand:FPR 2 "const0_operand" "")))
- (clobber (match_scratch:FPR 0 "=f"))]
- "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
- "ln<de>br\t%0,%1"
+ (compare (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f")))
+ (match_operand:BFP 2 "const0_operand" "")))
+ (clobber (match_scratch:BFP 0 "=f"))]
+ "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
+ "ln<xde>br\t%0,%1"
+ [(set_attr "op_type" "RRE")
+ (set_attr "type" "fsimp<mode>")])
+
+; lndfr
+(define_insn "*negabs<mode>2_nocc"
+ [(set (match_operand:FP 0 "register_operand" "=f")
+ (neg:FP (abs:FP (match_operand:BFP 1 "register_operand" "<fT0>"))))]
+ "TARGET_DFP"
+ "lndfr\t%0,%1"
[(set_attr "op_type" "RRE")
(set_attr "type" "fsimp<mode>")])
-
+
+; lnxbr, lndbr, lnebr
(define_insn "*negabs<mode>2"
- [(set (match_operand:FPR 0 "register_operand" "=f")
- (neg:FPR (abs:FPR (match_operand:FPR 1 "register_operand" "f"))))
+ [(set (match_operand:BFP 0 "register_operand" "=f")
+ (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f"))))
(clobber (reg:CC CC_REGNUM))]
- "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
- "ln<de>br\t%0,%1"
+ "TARGET_HARD_FLOAT"
+ "ln<xde>br\t%0,%1"
[(set_attr "op_type" "RRE")
(set_attr "type" "fsimp<mode>")])
;;
+;;- Copy sign instructions
+;;
+
+; cpsdr
+(define_insn "copysign<mode>3"
+ [(set (match_operand:FP 0 "register_operand" "=f")
+ (unspec:FP [(match_operand:FP 1 "register_operand" "<fT0>")
+ (match_operand:FP 2 "register_operand" "f")]
+ UNSPEC_COPYSIGN))]
+ "TARGET_DFP"
+ "cpsdr\t%0,%2,%1"
+ [(set_attr "op_type" "RRF")
+ (set_attr "type" "fsimp<mode>")])
+
+;;
;;- Square root instructions.
;;
; sqrt(df|sf)2 instruction pattern(s).
;
+; sqxbr, sqdbr, sqebr, sqdb, sqeb
(define_insn "sqrt<mode>2"
- [(set (match_operand:FPR 0 "register_operand" "=f,f")
- (sqrt:FPR (match_operand:FPR 1 "general_operand" "f,R")))]
- "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
+ [(set (match_operand:BFP 0 "register_operand" "=f,f")
+ (sqrt:BFP (match_operand:BFP 1 "general_operand" "f,<Rf>")))]
+ "TARGET_HARD_FLOAT"
"@
- sq<de>br\t%0,%1
- sq<de>b\t%0,%1"
+ sq<xde>br\t%0,%1
+ sq<xde>b\t%0,%1"
[(set_attr "op_type" "RRE,RXE")
(set_attr "type" "fsqrt<mode>")])
emit_insn (gen_clztidi2 (wide_reg, operands[1], msb));
- insn = emit_move_insn (operands[0], gen_highpart (DImode, wide_reg));
- REG_NOTES (insn) =
- gen_rtx_EXPR_LIST (REG_EQUAL, clz_equal, REG_NOTES (insn));
+ insn = emit_move_insn (operands[0], gen_highpart (DImode, wide_reg));
+ set_unique_reg_note (insn, REG_EQUAL, clz_equal);
DONE;
})
(define_insn "clztidi2"
[(set (match_operand:TI 0 "register_operand" "=d")
(ior:TI
- (ashift:TI
- (zero_extend:TI
+ (ashift:TI
+ (zero_extend:TI
(xor:DI (match_operand:DI 1 "register_operand" "d")
(lshiftrt (match_operand:DI 2 "const_int_operand" "")
(subreg:SI (clz:DI (match_dup 1)) 4))))
-
+
(const_int 64))
(zero_extend:TI (clz:DI (match_dup 1)))))
(clobber (reg:CC CC_REGNUM))]
- "(unsigned HOST_WIDE_INT) INTVAL (operands[2])
+ "(unsigned HOST_WIDE_INT) INTVAL (operands[2])
== (unsigned HOST_WIDE_INT) 1 << 63
&& TARGET_EXTIMM && TARGET_64BIT"
"flogr\t%0,%1"
; rotl(di|si)3 instruction pattern(s).
;
+; rll, rllg
(define_insn "rotl<mode>3"
[(set (match_operand:GPR 0 "register_operand" "=d")
(rotate:GPR (match_operand:GPR 1 "register_operand" "d")
"TARGET_CPU_ZARCH"
"rll<g>\t%0,%1,%Y2"
[(set_attr "op_type" "RSE")
- (set_attr "atype" "reg")])
+ (set_attr "atype" "reg")
+ (set_attr "z10prop" "z10_super_E1")])
+; rll, rllg
(define_insn "*rotl<mode>3_and"
[(set (match_operand:GPR 0 "register_operand" "=d")
(rotate:GPR (match_operand:GPR 1 "register_operand" "d")
"TARGET_CPU_ZARCH && (INTVAL (operands[3]) & 63) == 63"
"rll<g>\t%0,%1,%Y2"
[(set_attr "op_type" "RSE")
- (set_attr "atype" "reg")])
+ (set_attr "atype" "reg")
+ (set_attr "z10prop" "z10_super_E1")])
;;
""
"")
+; sldl, srdl
(define_insn "*<shift>di3_31"
[(set (match_operand:DI 0 "register_operand" "=d")
(SHIFT:DI (match_operand:DI 1 "register_operand" "0")
[(set_attr "op_type" "RS")
(set_attr "atype" "reg")])
+; sll, srl, sllg, srlg
(define_insn "*<shift><mode>3"
[(set (match_operand:GPR 0 "register_operand" "=d")
(SHIFT:GPR (match_operand:GPR 1 "register_operand" "<d0>")
""
"s<lr>l<g>\t%0,<1>%Y2"
[(set_attr "op_type" "RS<E>")
- (set_attr "atype" "reg")])
+ (set_attr "atype" "reg")
+ (set_attr "z10prop" "z10_super_E1")])
+; sldl, srdl
(define_insn "*<shift>di3_31_and"
[(set (match_operand:DI 0 "register_operand" "=d")
(SHIFT:DI (match_operand:DI 1 "register_operand" "0")
[(set_attr "op_type" "RS")
(set_attr "atype" "reg")])
+; sll, srl, sllg, srlg
(define_insn "*<shift><mode>3_and"
[(set (match_operand:GPR 0 "register_operand" "=d")
(SHIFT:GPR (match_operand:GPR 1 "register_operand" "<d0>")
"(INTVAL (operands[3]) & 63) == 63"
"s<lr>l<g>\t%0,<1>%Y2"
[(set_attr "op_type" "RS<E>")
- (set_attr "atype" "reg")])
+ (set_attr "atype" "reg")
+ (set_attr "z10prop" "z10_super_E1")])
;
; ashr(di|si)3 instruction pattern(s).
[(set_attr "op_type" "RS")
(set_attr "atype" "reg")])
+; sra, srag
(define_insn "*ashr<mode>3_cc"
[(set (reg CC_REGNUM)
(compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>")
"s390_match_ccmode(insn, CCSmode)"
"sra<g>\t%0,<1>%Y2"
[(set_attr "op_type" "RS<E>")
- (set_attr "atype" "reg")])
+ (set_attr "atype" "reg")
+ (set_attr "z10prop" "z10_super_E1")])
+; sra, srag
(define_insn "*ashr<mode>3_cconly"
[(set (reg CC_REGNUM)
(compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>")
"s390_match_ccmode(insn, CCSmode)"
"sra<g>\t%0,<1>%Y2"
[(set_attr "op_type" "RS<E>")
- (set_attr "atype" "reg")])
+ (set_attr "atype" "reg")
+ (set_attr "z10prop" "z10_super_E1")])
+; sra, srag
(define_insn "*ashr<mode>3"
[(set (match_operand:GPR 0 "register_operand" "=d")
(ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>")
""
"sra<g>\t%0,<1>%Y2"
[(set_attr "op_type" "RS<E>")
- (set_attr "atype" "reg")])
+ (set_attr "atype" "reg")
+ (set_attr "z10prop" "z10_super_E1")])
; shift pattern with implicit ANDs
[(set_attr "op_type" "RS")
(set_attr "atype" "reg")])
+; sra, srag
(define_insn "*ashr<mode>3_cc_and"
[(set (reg CC_REGNUM)
(compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>")
"s390_match_ccmode(insn, CCSmode) && (INTVAL (operands[3]) & 63) == 63"
"sra<g>\t%0,<1>%Y2"
[(set_attr "op_type" "RS<E>")
- (set_attr "atype" "reg")])
+ (set_attr "atype" "reg")
+ (set_attr "z10prop" "z10_super_E1")])
+; sra, srag
(define_insn "*ashr<mode>3_cconly_and"
[(set (reg CC_REGNUM)
(compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>")
"s390_match_ccmode(insn, CCSmode) && (INTVAL (operands[3]) & 63) == 63"
"sra<g>\t%0,<1>%Y2"
[(set_attr "op_type" "RS<E>")
- (set_attr "atype" "reg")])
+ (set_attr "atype" "reg")
+ (set_attr "z10prop" "z10_super_E1")])
+; sra, srag
(define_insn "*ashr<mode>3_and"
[(set (match_operand:GPR 0 "register_operand" "=d")
(ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>")
"(INTVAL (operands[3]) & 63) == 63"
"sra<g>\t%0,<1>%Y2"
[(set_attr "op_type" "RS<E>")
- (set_attr "atype" "reg")])
+ (set_attr "atype" "reg")
+ (set_attr "z10prop" "z10_super_E1")])
;;
""
{
if (operands[1] != const0_rtx) FAIL;
- operands[0] = s390_emit_compare (GET_CODE (operands[0]),
+ operands[0] = s390_emit_compare (GET_CODE (operands[0]),
s390_compare_op0, s390_compare_op1);
})
[(set_attr "op_type" "RI")
(set_attr "type" "branch")])
+; crt, cgrt, cit, cgit
+(define_insn "*cmp_and_trap_signed_int<mode>"
+ [(trap_if (match_operator 0 "s390_signed_integer_comparison"
+ [(match_operand:GPR 1 "register_operand" "d,d")
+ (match_operand:GPR 2 "nonmemory_operand" "d,K")])
+ (const_int 0))]
+ "TARGET_Z10"
+ "@
+ c<g>rt%C0\t%1,%2
+ c<g>it%C0\t%1,%h2"
+ [(set_attr "op_type" "RRF,RIE")
+ (set_attr "type" "branch")
+ (set_attr "z10prop" "z10_super_c,z10_super")])
+
+; clrt, clgrt, clfit, clgit
+(define_insn "*cmp_and_trap_unsigned_int<mode>"
+ [(trap_if (match_operator 0 "s390_unsigned_integer_comparison"
+ [(match_operand:GPR 1 "register_operand" "d,d")
+ (match_operand:GPR 2 "nonmemory_operand" "d,D")])
+ (const_int 0))]
+ "TARGET_Z10"
+ "@
+ cl<g>rt%C0\t%1,%2
+ cl<gf>it%C0\t%1,%x2"
+ [(set_attr "op_type" "RRF,RIE")
+ (set_attr "type" "branch")
+ (set_attr "z10prop" "z10_super_c,z10_super")])
+
;;
;;- Loop instructions.
;;
(define_insn_and_split "doloop_si64"
[(set (pc)
(if_then_else
- (ne (match_operand:SI 1 "register_operand" "d,d")
+ (ne (match_operand:SI 1 "register_operand" "d,d,d")
(const_int 1))
(label_ref (match_operand 0 "" ""))
(pc)))
- (set (match_operand:SI 2 "nonimmediate_operand" "=1,?*m*d")
+ (set (match_operand:SI 2 "nonimmediate_operand" "=1,?X,?X")
(plus:SI (match_dup 1) (const_int -1)))
- (clobber (match_scratch:SI 3 "=X,&1"))
+ (clobber (match_scratch:SI 3 "=X,&1,&?d"))
(clobber (reg:CC CC_REGNUM))]
"TARGET_CPU_ZARCH"
{
"&& reload_completed
&& (! REG_P (operands[2])
|| ! rtx_equal_p (operands[1], operands[2]))"
- [(parallel [(set (reg:CCAN CC_REGNUM)
+ [(set (match_dup 3) (match_dup 1))
+ (parallel [(set (reg:CCAN CC_REGNUM)
(compare:CCAN (plus:SI (match_dup 3) (const_int -1))
(const_int 0)))
(set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))])
(pc)))]
""
[(set_attr "op_type" "RI")
+ ; Strictly speaking, the z10 properties are valid for brct only, however, it does not
+ ; hurt us in the (rare) case of ahi.
+ (set_attr "z10prop" "z10_super_E1")
(set_attr "type" "branch")
(set (attr "length")
(if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
(define_insn_and_split "doloop_si31"
[(set (pc)
(if_then_else
- (ne (match_operand:SI 1 "register_operand" "d,d")
+ (ne (match_operand:SI 1 "register_operand" "d,d,d")
(const_int 1))
(label_ref (match_operand 0 "" ""))
(pc)))
- (set (match_operand:SI 2 "nonimmediate_operand" "=1,?*m*d")
+ (set (match_operand:SI 2 "nonimmediate_operand" "=1,?X,?X")
(plus:SI (match_dup 1) (const_int -1)))
- (clobber (match_scratch:SI 3 "=X,&1"))
+ (clobber (match_scratch:SI 3 "=X,&1,&?d"))
(clobber (reg:CC CC_REGNUM))]
"!TARGET_CPU_ZARCH"
{
"&& reload_completed
&& (! REG_P (operands[2])
|| ! rtx_equal_p (operands[1], operands[2]))"
- [(parallel [(set (reg:CCAN CC_REGNUM)
+ [(set (match_dup 3) (match_dup 1))
+ (parallel [(set (reg:CCAN CC_REGNUM)
(compare:CCAN (plus:SI (match_dup 3) (const_int -1))
(const_int 0)))
(set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))])
(pc)))]
""
[(set_attr "op_type" "RI")
+ ; Strictly speaking, the z10 properties are valid for brct only, however, it does not
+ ; hurt us in the (rare) case of ahi.
+ (set_attr "z10prop" "z10_super_E1")
(set_attr "type" "branch")
(set (attr "length")
(if_then_else (eq (symbol_ref "flag_pic") (const_int 0))
(define_insn "*doloop_si_long"
[(set (pc)
(if_then_else
- (ne (match_operand:SI 1 "register_operand" "d,d")
+ (ne (match_operand:SI 1 "register_operand" "d")
(const_int 1))
- (match_operand 0 "address_operand" "U,U")
+ (match_operand 0 "address_operand" "U")
(pc)))
- (set (match_operand:SI 2 "register_operand" "=1,?*m*d")
+ (set (match_operand:SI 2 "register_operand" "=1")
(plus:SI (match_dup 1) (const_int -1)))
- (clobber (match_scratch:SI 3 "=X,&1"))
+ (clobber (match_scratch:SI 3 "=X"))
(clobber (reg:CC CC_REGNUM))]
"!TARGET_CPU_ZARCH"
{
(if_then_else (match_operand 0 "register_operand" "")
(const_string "RR") (const_string "RX")))
(set_attr "type" "branch")
- (set_attr "atype" "agen")])
+ (set_attr "atype" "agen")
+ (set_attr "z10prop" "z10_c")])
(define_insn_and_split "doloop_di"
[(set (pc)
(if_then_else
- (ne (match_operand:DI 1 "register_operand" "d,d")
+ (ne (match_operand:DI 1 "register_operand" "d,d,d")
(const_int 1))
(label_ref (match_operand 0 "" ""))
(pc)))
- (set (match_operand:DI 2 "nonimmediate_operand" "=1,?*m*d")
+ (set (match_operand:DI 2 "nonimmediate_operand" "=1,?X,?X")
(plus:DI (match_dup 1) (const_int -1)))
- (clobber (match_scratch:DI 3 "=X,&1"))
+ (clobber (match_scratch:DI 3 "=X,&1,&?d"))
(clobber (reg:CC CC_REGNUM))]
"TARGET_64BIT"
{
"&& reload_completed
&& (! REG_P (operands[2])
|| ! rtx_equal_p (operands[1], operands[2]))"
- [(parallel [(set (reg:CCAN CC_REGNUM)
+ [(set (match_dup 3) (match_dup 1))
+ (parallel [(set (reg:CCAN CC_REGNUM)
(compare:CCAN (plus:DI (match_dup 3) (const_int -1))
(const_int 0)))
(set (match_dup 3) (plus:DI (match_dup 3) (const_int -1)))])
(pc)))]
""
[(set_attr "op_type" "RI")
+ ; Strictly speaking, the z10 properties are valid for brct only, however, it does not
+ ; hurt us in the (rare) case of ahi.
+ (set_attr "z10prop" "z10_super_E1")
(set_attr "type" "branch")
(set (attr "length")
(if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
(define_insn "*tls_load_64"
[(set (match_operand:DI 0 "register_operand" "=d")
- (unspec:DI [(match_operand:DI 1 "memory_operand" "m")
+ (unspec:DI [(match_operand:DI 1 "memory_operand" "RT")
(match_operand:DI 2 "" "")]
UNSPEC_TLS_LOAD))]
"TARGET_64BIT"
"lg\t%0,%1%J2"
- [(set_attr "op_type" "RXE")])
+ [(set_attr "op_type" "RXE")
+ (set_attr "z10prop" "z10_fwd_A3")])
(define_insn "*tls_load_31"
[(set (match_operand:SI 0 "register_operand" "=d,d")
"@
l\t%0,%1%J2
ly\t%0,%1%J2"
- [(set_attr "op_type" "RX,RXY")])
+ [(set_attr "op_type" "RX,RXY")
+ (set_attr "type" "load")
+ (set_attr "z10prop" "z10_fwd_A3,z10_fwd_A3")])
(define_insn "*bras_tls"
[(set (match_operand 0 "" "")
;
(define_expand "memory_barrier"
- [(set (mem:BLK (match_dup 0))
- (unspec_volatile:BLK [(mem:BLK (match_dup 0))] UNSPECV_MB))]
+ [(set (match_dup 0)
+ (unspec:BLK [(match_dup 0)] UNSPEC_MB))]
""
{
- operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (DImode));
+ operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
MEM_VOLATILE_P (operands[0]) = 1;
})
(define_insn "*memory_barrier"
[(set (match_operand:BLK 0 "" "")
- (unspec_volatile:BLK [(match_operand:BLK 1 "" "")] UNSPECV_MB))]
+ (unspec:BLK [(match_dup 0)] UNSPEC_MB))]
""
"bcr\t15,0"
[(set_attr "op_type" "RR")])
+; Although bcr is superscalar on Z10, this variant will never become part of
+; an execution group.
+
;
; compare and swap patterns.
;
(set (reg:CCZ1 CC_REGNUM)
(compare:CCZ1 (match_dup 1) (match_dup 2)))])]
""
- "s390_expand_cs_hqi (<MODE>mode, operands[0], operands[1],
+ "s390_expand_cs_hqi (<MODE>mode, operands[0], operands[1],
operands[2], operands[3]); DONE;")
(define_expand "sync_compare_and_swap_cc<mode>"
s390_compare_emitted = operands[4];
})
+; cds, cdsg
(define_insn "*sync_compare_and_swap<mode>"
[(set (match_operand:DP 0 "register_operand" "=r")
(match_operand:DP 1 "memory_operand" "+Q"))
[(set_attr "op_type" "RS<TE>")
(set_attr "type" "sem")])
+; cs, csg
(define_insn "*sync_compare_and_swap<mode>"
[(set (match_operand:GPR 0 "register_operand" "=r")
(match_operand:GPR 1 "memory_operand" "+Q"))
UNSPECV_CAS))
(set (reg:CCZ1 CC_REGNUM)
(compare:CCZ1 (match_dup 1) (match_dup 2)))]
- ""
+ ""
"cs<g>\t%0,%3,%S1"
[(set_attr "op_type" "RS<E>")
(set_attr "type" "sem")])
(match_operand:HQI 1 "memory_operand")
(match_operand:HQI 2 "general_operand")]
""
- "s390_expand_atomic (<MODE>mode, SET, operands[0], operands[1],
+ "s390_expand_atomic (<MODE>mode, SET, operands[0], operands[1],
operands[2], false); DONE;")
(define_expand "sync_<atomic><mode>"
(ATOMIC:HQI (match_dup 0)
(match_operand:HQI 1 "general_operand")))]
""
- "s390_expand_atomic (<MODE>mode, <CODE>, NULL_RTX, operands[0],
+ "s390_expand_atomic (<MODE>mode, <CODE>, NULL_RTX, operands[0],
operands[1], false); DONE;")
(define_expand "sync_old_<atomic><mode>"
(ATOMIC:HQI (match_dup 1)
(match_operand:HQI 2 "general_operand")))]
""
- "s390_expand_atomic (<MODE>mode, <CODE>, operands[0], operands[1],
+ "s390_expand_atomic (<MODE>mode, <CODE>, operands[0], operands[1],
operands[2], false); DONE;")
(define_expand "sync_new_<atomic><mode>"
[(set (match_operand:HQI 0 "register_operand")
(ATOMIC:HQI (match_operand:HQI 1 "memory_operand")
- (match_operand:HQI 2 "general_operand")))
+ (match_operand:HQI 2 "general_operand")))
(set (match_dup 1) (ATOMIC:HQI (match_dup 1) (match_dup 2)))]
""
- "s390_expand_atomic (<MODE>mode, <CODE>, operands[0], operands[1],
+ "s390_expand_atomic (<MODE>mode, <CODE>, operands[0], operands[1],
operands[2], true); DONE;")
;;
"flag_pic"
{
emit_insn (s390_load_got ());
- emit_insn (gen_rtx_USE (VOIDmode, pic_offset_table_rtx));
+ emit_use (pic_offset_table_rtx);
DONE;
})
if (TARGET_BACKCHAIN)
temp = force_reg (Pmode, operand_subword (operands[1], 0, 0, mode));
-
+
emit_move_insn (base, operand_subword (operands[1], 2, 0, mode));
emit_move_insn (operands[0], operand_subword (operands[1], 1, 0, mode));
if (temp)
emit_move_insn (s390_back_chain_rtx (), temp);
- emit_insn (gen_rtx_USE (VOIDmode, base));
+ emit_use (base);
DONE;
})
[(const_int 0)]
""
"lr\t0,0"
+ [(set_attr "op_type" "RR")
+ (set_attr "z10prop" "z10_fr_E1")])
+
+(define_insn "nop1"
+ [(const_int 1)]
+ ""
+ "lr\t1,1"
[(set_attr "op_type" "RR")])
"TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
"larl\t%0,%1"
[(set_attr "op_type" "RIL")
- (set_attr "type" "larl")])
+ (set_attr "type" "larl")
+ (set_attr "z10prop" "z10_fwd_A1")])
(define_insn "main_pool"
[(set (match_operand 0 "register_operand" "=a")
{
gcc_unreachable ();
}
- [(set (attr "type")
+ [(set (attr "type")
(if_then_else (ne (symbol_ref "TARGET_CPU_ZARCH") (const_int 0))
(const_string "larl") (const_string "la")))])
"TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
"larl\t%0,%1"
[(set_attr "op_type" "RIL")
- (set_attr "type" "larl")])
+ (set_attr "type" "larl")
+ (set_attr "z10prop" "z10_fwd_A1")])
(define_insn "pool"
[(unspec_volatile [(match_operand 0 "const_int_operand" "n")] UNSPECV_POOL)]
""
"clc\t%O0(%G0,%R0),%S1"
[(set_attr "op_type" "SS")])
+
+; This is used in s390_emit_prologue in order to prevent insns
+; adjusting the stack pointer to be moved over insns writing stack
+; slots using a copy of the stack pointer in a different register.
+(define_insn "stack_tie"
+ [(set (match_operand:BLK 0 "memory_operand" "+m")
+ (unspec:BLK [(match_dup 0)] UNSPEC_TIE))]
+ ""
+ ""
+ [(set_attr "length" "0")])
+
+
+;
+; Data prefetch patterns
+;
+
+(define_insn "prefetch"
+ [(prefetch (match_operand 0 "address_operand" "UW,X")
+ (match_operand:SI 1 "const_int_operand" "n,n")
+ (match_operand:SI 2 "const_int_operand" "n,n"))]
+ "TARGET_Z10"
+{
+ if (larl_operand (operands[0], Pmode))
+ return INTVAL (operands[1]) == 1 ? "pfdrl\t2,%a0" : "pfdrl\t1,%a0";
+
+ if (s390_mem_constraint ("W", operands[0])
+ || s390_mem_constraint ("U", operands[0]))
+ return INTVAL (operands[1]) == 1 ? "pfd\t2,%a0" : "pfd\t1,%a0";
+
+ /* This point might be reached if op0 is a larl operand with an
+ uneven addend. In this case we simply omit issuing a prefetch
+ instruction. */
+
+ return "";
+}
+ [(set_attr "type" "load,larl")
+ (set_attr "op_type" "RXY,RIL")
+ (set_attr "z10prop" "z10_super")])
+
+
+;
+; Byte swap instructions
+;
+
+(define_insn "bswap<mode>2"
+ [(set (match_operand:GPR 0 "register_operand" "=d, d")
+ (bswap:GPR (match_operand:GPR 1 "nonimmediate_operand" " d,RT")))]
+ ""
+ "@
+ lrv<g>r\t%0,%1
+ lrv<g>\t%0,%1"
+ [(set_attr "type" "*,load")
+ (set_attr "op_type" "RRE,RXY")
+ (set_attr "z10prop" "z10_super")])
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