(UNSPEC_TLSGOTTPREL 28)
(UNSPEC_TLSTLS 29)
(UNSPEC_FIX_TRUNC_TF 30) ; fadd, rounding towards zero
- (UNSPEC_MV_CR_GT 31) ; move_from_CR_eq_bit
+ (UNSPEC_MV_CR_GT 31) ; move_from_CR_gt_bit
(UNSPEC_STFIWX 32)
(UNSPEC_POPCNTB 33)
(UNSPEC_FRES 34)
(include "power5.md")
(include "predicates.md")
+(include "constraints.md")
(include "darwin.md")
(plus:SDI (match_operand:SDI 1 "gpc_reg_operand" "")
(match_operand:SDI 2 "reg_or_add_cint_operand" "")))]
""
- "
{
if (<MODE>mode == DImode && ! TARGET_POWERPC64)
{
HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
HOST_WIDE_INT rest = trunc_int_for_mode (val - low, <MODE>mode);
- if (<MODE>mode == DImode && !CONST_OK_FOR_LETTER_P (rest, 'L'))
+ if (<MODE>mode == DImode && !satisfies_constraint_L (GEN_INT (rest)))
FAIL;
/* The ordering here is important for the prolog expander.
emit_insn (gen_add<mode>3 (operands[0], tmp, GEN_INT (low)));
DONE;
}
-}")
+})
;; Discourage ai/addic because of carry but provide it in an alternative
;; allowing register zero as source.
""
[(set (match_dup 0) (plus:GPR (match_dup 1) (match_dup 3)))
(set (match_dup 0) (plus:GPR (match_dup 0) (match_dup 4)))]
-"
{
HOST_WIDE_INT val = INTVAL (operands[2]);
HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
HOST_WIDE_INT rest = trunc_int_for_mode (val - low, <MODE>mode);
operands[4] = GEN_INT (low);
- if (<MODE>mode == SImode || CONST_OK_FOR_LETTER_P (rest, 'L'))
+ if (<MODE>mode == SImode || satisfies_constraint_L (GEN_INT (rest)))
operands[3] = GEN_INT (rest);
else if (! no_new_pseudos)
{
}
else
FAIL;
-}")
+})
(define_insn "one_cmpl<mode>2"
[(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
"")
(define_insn "*movcc_internal1"
- [(set (match_operand:CC 0 "nonimmediate_operand" "=y,x,?y,r,r,r,r,q,cl,r,m")
- (match_operand:CC 1 "nonimmediate_operand" "y,r,r,x,y,r,h,r,r,m,r"))]
+ [(set (match_operand:CC 0 "nonimmediate_operand" "=y,x,?y,y,r,r,r,r,r,q,cl,r,m")
+ (match_operand:CC 1 "general_operand" "y,r,r,O,x,y,r,I,h,r,r,m,r"))]
"register_operand (operands[0], CCmode)
|| register_operand (operands[1], CCmode)"
"@
mcrf %0,%1
mtcrf 128,%1
{rlinm|rlwinm} %1,%1,%F0,0xffffffff\;mtcrf %R0,%1\;{rlinm|rlwinm} %1,%1,%f0,0xffffffff
+ crxor %0,%0,%0
mfcr %0%Q1
mfcr %0%Q1\;{rlinm|rlwinm} %0,%0,%f1,0xf0000000
mr %0,%1
+ {lil|li} %0,%1
mf%1 %0
mt%0 %1
mt%0 %1
{l%U1%X1|lwz%U1%X1} %0,%1
{st%U0%U1|stw%U0%U1} %1,%0"
[(set (attr "type")
- (cond [(eq_attr "alternative" "0")
+ (cond [(eq_attr "alternative" "0,3")
(const_string "cr_logical")
(eq_attr "alternative" "1,2")
(const_string "mtcr")
- (eq_attr "alternative" "5,7")
+ (eq_attr "alternative" "6,7,9")
(const_string "integer")
- (eq_attr "alternative" "6")
- (const_string "mfjmpr")
(eq_attr "alternative" "8")
+ (const_string "mfjmpr")
+ (eq_attr "alternative" "10")
(const_string "mtjmpr")
- (eq_attr "alternative" "9")
+ (eq_attr "alternative" "11")
(const_string "load")
- (eq_attr "alternative" "10")
+ (eq_attr "alternative" "12")
(const_string "store")
(ne (symbol_ref "TARGET_MFCRF") (const_int 0))
(const_string "mfcrf")
]
(const_string "mfcr")))
- (set_attr "length" "4,4,12,4,8,4,4,4,4,4,4")])
+ (set_attr "length" "4,4,12,4,4,8,4,4,4,4,4,4,4")])
\f
;; For floating-point, we normally deal with the floating-point registers
;; unless -msoft-float is used. The sole exception is that parameter passing
"")
(define_expand "floatsitf2"
- [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
- (float:TF (match_operand:SI 1 "gpc_reg_operand" "r")))]
+ [(set (match_operand:TF 0 "gpc_reg_operand" "")
+ (float:TF (match_operand:SI 1 "gpc_reg_operand" "")))]
"!TARGET_IEEEQUAD
&& TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
{
[(match_parallel 0 "store_multiple_operation"
[(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
(match_operand:SI 2 "gpc_reg_operand" "r"))
- (clobber (match_scratch:SI 3 "X"))
+ (clobber (match_scratch:SI 3 "=X"))
(set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
(match_operand:SI 4 "gpc_reg_operand" "r"))
(set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
[(match_parallel 0 "store_multiple_operation"
[(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
(match_operand:SI 2 "gpc_reg_operand" "r"))
- (clobber (match_scratch:SI 3 "X"))
+ (clobber (match_scratch:SI 3 "=X"))
(set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
(match_operand:SI 4 "gpc_reg_operand" "r"))
(set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
[(match_parallel 0 "store_multiple_operation"
[(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
(match_operand:SI 2 "gpc_reg_operand" "r"))
- (clobber (match_scratch:SI 3 "X"))
+ (clobber (match_scratch:SI 3 "=X"))
(set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
(match_operand:SI 4 "gpc_reg_operand" "r"))
(set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
[(match_parallel 0 "store_multiple_operation"
[(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
(match_operand:SI 2 "gpc_reg_operand" "r"))
- (clobber (match_scratch:SI 3 "X"))
+ (clobber (match_scratch:SI 3 "=X"))
(set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
(match_operand:SI 4 "gpc_reg_operand" "r"))
(set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
[(match_parallel 0 "store_multiple_operation"
[(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
(match_operand:SI 2 "gpc_reg_operand" "r"))
- (clobber (match_scratch:SI 3 "X"))
+ (clobber (match_scratch:SI 3 "=X"))
(set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
(match_operand:SI 4 "gpc_reg_operand" "r"))
(set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
[(match_parallel 0 "store_multiple_operation"
[(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
(match_operand:SI 2 "gpc_reg_operand" "r"))
- (clobber (match_scratch:SI 3 "X"))
+ (clobber (match_scratch:SI 3 "=X"))
(set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
(match_operand:SI 4 "gpc_reg_operand" "r"))
(set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
[(match_parallel 0 "store_multiple_operation"
[(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
(match_operand:SI 2 "gpc_reg_operand" "r"))
- (clobber (match_scratch:SI 3 "q"))
+ (clobber (match_scratch:SI 3 "=q"))
(set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
(match_operand:SI 4 "gpc_reg_operand" "r"))
(set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
[(match_parallel 0 "store_multiple_operation"
[(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
(match_operand:SI 2 "gpc_reg_operand" "r"))
- (clobber (match_scratch:SI 3 "q"))
+ (clobber (match_scratch:SI 3 "=q"))
(set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
(match_operand:SI 4 "gpc_reg_operand" "r"))
(set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
[(match_parallel 0 "store_multiple_operation"
[(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
(match_operand:SI 2 "gpc_reg_operand" "r"))
- (clobber (match_scratch:SI 3 "q"))
+ (clobber (match_scratch:SI 3 "=q"))
(set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
(match_operand:SI 4 "gpc_reg_operand" "r"))
(set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
[(match_parallel 0 "store_multiple_operation"
[(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
(match_operand:SI 2 "gpc_reg_operand" "r"))
- (clobber (match_scratch:SI 3 "q"))
+ (clobber (match_scratch:SI 3 "=q"))
(set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
(match_operand:SI 4 "gpc_reg_operand" "r"))
(set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
[(match_parallel 0 "store_multiple_operation"
[(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
(match_operand:SI 2 "gpc_reg_operand" "r"))
- (clobber (match_scratch:SI 3 "q"))
+ (clobber (match_scratch:SI 3 "=q"))
(set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
(match_operand:SI 4 "gpc_reg_operand" "r"))
(set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
[(match_parallel 0 "store_multiple_operation"
[(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
(match_operand:SI 2 "gpc_reg_operand" "r"))
- (clobber (match_scratch:SI 3 "q"))
+ (clobber (match_scratch:SI 3 "=q"))
(set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
(match_operand:SI 4 "gpc_reg_operand" "r"))
(set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
(clobber (reg:SI 10))
(clobber (reg:SI 11))
(clobber (reg:SI 12))
- (clobber (match_scratch:SI 5 "X"))]
+ (clobber (match_scratch:SI 5 "=X"))]
"TARGET_STRING && ! TARGET_POWER
&& ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32)
|| INTVAL (operands[2]) == 0)
(clobber (reg:SI 8))
(clobber (reg:SI 9))
(clobber (reg:SI 10))
- (clobber (match_scratch:SI 5 "X"))]
+ (clobber (match_scratch:SI 5 "=X"))]
"TARGET_STRING && ! TARGET_POWER
&& INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 32
&& (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10)
(clobber (reg:SI 6))
(clobber (reg:SI 7))
(clobber (reg:SI 8))
- (clobber (match_scratch:SI 5 "X"))]
+ (clobber (match_scratch:SI 5 "=X"))]
"TARGET_STRING && ! TARGET_POWER
&& INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
&& (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8)
(use (match_operand:SI 2 "immediate_operand" "i"))
(use (match_operand:SI 3 "immediate_operand" "i"))
(clobber (match_scratch:DI 4 "=&r"))
- (clobber (match_scratch:SI 5 "X"))]
+ (clobber (match_scratch:SI 5 "=X"))]
"TARGET_STRING && ! TARGET_POWER && ! TARGET_POWERPC64
&& INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
"{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
(use (match_operand:SI 2 "immediate_operand" "i"))
(use (match_operand:SI 3 "immediate_operand" "i"))
(clobber (match_scratch:SI 4 "=&r"))
- (clobber (match_scratch:SI 5 "X"))]
+ (clobber (match_scratch:SI 5 "=X"))]
"TARGET_STRING && ! TARGET_POWER
&& INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
"{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
"operands[0] = widen_memory_access (operands[0], V2DFmode, 0);
operands[1] = gen_rtx_REG (V2DFmode, REGNO (operands[1]));")
-;; after inserting conditional returns we can sometimes have
+;; After inserting conditional returns we can sometimes have
;; unnecessary register moves. Unfortunately we cannot have a
;; modeless peephole here, because some single SImode sets have early
;; clobber outputs. Although those sets expand to multi-ppc-insn
;; sequences, using get_attr_length here will smash the operands
;; array. Neither is there an early_cobbler_p predicate.
+;; Disallow subregs for E500 so we don't munge frob_di_df_2.
(define_peephole2
[(set (match_operand:DF 0 "gpc_reg_operand" "")
(match_operand:DF 1 "any_operand" ""))
(set (match_operand:DF 2 "gpc_reg_operand" "")
(match_dup 0))]
- "peep2_reg_dead_p (2, operands[0])"
+ "!(TARGET_E500_DOUBLE && GET_CODE (operands[2]) == SUBREG)
+ && peep2_reg_dead_p (2, operands[0])"
[(set (match_dup 2) (match_dup 1))])
(define_peephole2
;; operands[2] is the value FUNCTION_ARG returns for the VOID argument
;; which indicates how to set cr1
-(define_insn "*call_indirect_nonlocal_sysv"
- [(call (mem:SI (match_operand:SI 0 "register_operand" "c,*l,c,*l"))
+(define_insn "*call_indirect_nonlocal_sysv<mode>"
+ [(call (mem:SI (match_operand:P 0 "register_operand" "c,*l,c,*l"))
(match_operand 1 "" "g,g,g,g"))
(use (match_operand:SI 2 "immediate_operand" "O,O,n,n"))
(clobber (match_scratch:SI 3 "=l,l,l,l"))]
[(set_attr "type" "jmpreg,jmpreg,jmpreg,jmpreg")
(set_attr "length" "4,4,8,8")])
-(define_insn "*call_nonlocal_sysv"
- [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s,s"))
+(define_insn "*call_nonlocal_sysv<mode>"
+ [(call (mem:SI (match_operand:P 0 "symbol_ref_operand" "s,s"))
(match_operand 1 "" "g,g"))
(use (match_operand:SI 2 "immediate_operand" "O,n"))
(clobber (match_scratch:SI 3 "=l,l"))]
[(set_attr "type" "branch,branch")
(set_attr "length" "4,8")])
-(define_insn "*call_value_indirect_nonlocal_sysv"
+(define_insn "*call_value_indirect_nonlocal_sysv<mode>"
[(set (match_operand 0 "" "")
- (call (mem:SI (match_operand:SI 1 "register_operand" "c,*l,c,*l"))
+ (call (mem:SI (match_operand:P 1 "register_operand" "c,*l,c,*l"))
(match_operand 2 "" "g,g,g,g")))
(use (match_operand:SI 3 "immediate_operand" "O,O,n,n"))
(clobber (match_scratch:SI 4 "=l,l,l,l"))]
[(set_attr "type" "jmpreg,jmpreg,jmpreg,jmpreg")
(set_attr "length" "4,4,8,8")])
-(define_insn "*call_value_nonlocal_sysv"
+(define_insn "*call_value_nonlocal_sysv<mode>"
[(set (match_operand 0 "" "")
- (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s,s"))
+ (call (mem:SI (match_operand:P 1 "symbol_ref_operand" "s,s"))
(match_operand 2 "" "g,g")))
(use (match_operand:SI 3 "immediate_operand" "O,n"))
(clobber (match_scratch:SI 4 "=l,l"))]
[(set_attr "type" "branch")
(set_attr "length" "4")])
-(define_insn "*sibcall_nonlocal_sysv"
- [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s,s"))
+(define_insn "*sibcall_nonlocal_sysv<mode>"
+ [(call (mem:SI (match_operand:P 0 "symbol_ref_operand" "s,s"))
(match_operand 1 "" ""))
(use (match_operand 2 "immediate_operand" "O,n"))
(use (match_operand:SI 3 "register_operand" "l,l"))
}")
-(define_insn "*sibcall_value_nonlocal_sysv"
+(define_insn "*sibcall_value_nonlocal_sysv<mode>"
[(set (match_operand 0 "" "")
- (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s,s"))
+ (call (mem:SI (match_operand:P 1 "symbol_ref_operand" "s,s"))
(match_operand 2 "" "")))
(use (match_operand:SI 3 "immediate_operand" "O,n"))
(use (match_operand:SI 4 "register_operand" "l,l"))
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