* config/darwin.c, config/darwin.h, config/freebsd-spec.h,

[pf3gnuchains/gcc-fork.git] / gcc / config / rs6000 / rs6000.h

diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index 63c1b83..0ccec58 100644 (file)
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -1,6 +1,6 @@
 /* Definitions of target machine for GNU compiler, for IBM RS/6000.
    Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
-   2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
+   2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
    Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
 
    This file is part of GCC.
@@ -1429,6 +1429,8 @@ enum reg_class
 #define CLASS_MAX_NREGS(CLASS, MODE)                                   \
  (((CLASS) == FLOAT_REGS)                                              \
   ? ((GET_MODE_SIZE (MODE) + UNITS_PER_FP_WORD - 1) / UNITS_PER_FP_WORD) \
+  : (TARGET_E500_DOUBLE && (CLASS) == GENERAL_REGS && (MODE) == DFmode) \
+  ? 1                                                                   \
   : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
 
 
@@ -1442,6 +1444,8 @@ enum reg_class
    ? reg_classes_intersect_p (FLOAT_REGS, CLASS)                         \
    : (TARGET_E500_DOUBLE && (((TO) == DFmode) + ((FROM) == DFmode)) == 1) \
    ? reg_classes_intersect_p (GENERAL_REGS, CLASS)                       \
+   : (TARGET_E500_DOUBLE && (((TO) == DImode) + ((FROM) == DImode)) == 1) \
+   ? reg_classes_intersect_p (GENERAL_REGS, CLASS)                       \
    : (TARGET_SPE && (SPE_VECTOR_MODE (FROM) + SPE_VECTOR_MODE (TO)) == 1) \
    ? reg_classes_intersect_p (GENERAL_REGS, CLASS)                       \
    : 0)
@@ -2588,6 +2592,7 @@ extern char rs6000_reg_names[][8];        /* register names (0 vs. %r0).  */
   {"current_file_function_operand", {SYMBOL_REF}},                        \
   {"input_operand", {SUBREG, MEM, REG, CONST_INT,                         \
                     CONST_DOUBLE, SYMBOL_REF}},                           \
+  {"rs6000_nonimmediate_operand", {SUBREG, MEM, REG}},                    \
   {"load_multiple_operation", {PARALLEL}},                                \
   {"store_multiple_operation", {PARALLEL}},                               \
   {"lmw_operation", {PARALLEL}},                                          \