;;- Machine description for the pdp11 for GNU C compiler
-;; Copyright (C) 1994, 1995, 1997 Free Software Foundation, Inc.
+;; Copyright (C) 1994, 1995, 1997, 1998, 1999, 2000, 2001
+;; Free Software Foundation, Inc.
;; Contributed by Michael K. Gschwind (mike@vlsivie.tuwien.ac.at).
-;; This file is part of GNU CC.
+;; This file is part of GCC.
-;; GNU CC is free software; you can redistribute it and/or modify
+;; GCC is free software; you can redistribute it and/or modify
;; it under the terms of the GNU General Public License as published by
-;; the Free Software Foundation; either version 1, or (at your option)
+;; the Free Software Foundation; either version 2, or (at your option)
;; any later version.
-;; GNU CC is distributed in the hope that it will be useful,
+;; GCC is distributed in the hope that it will be useful,
;; but WITHOUT ANY WARRANTY; without even the implied warranty of
;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
;; GNU General Public License for more details.
;; You should have received a copy of the GNU General Public License
-;; along with GNU CC; see the file COPYING. If not, write to
-;; the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
+;; along with GCC; see the file COPYING. If not, write to
+;; the Free Software Foundation, 59 Temple Place - Suite 330,
+;; Boston, MA 02111-1307, USA.
;; HI is 16 bit
"*
{
cc_status.flags = CC_IN_FPU;
- return \"cmpd %0, %1\;cfcc\";
+ return \"{cmpd|cmpf} %0, %1\;cfcc\";
}"
[(set_attr "length" "2,3,6")])
"*
{
cc_status.flags = CC_IN_FPU;
- return \"tstd %0\;cfcc\";
+ return \"{tstd|tstf} %0\;cfcc\";
}"
[(set_attr "length" "2,3")])
(define_insn ""
[(set (pc)
(if_then_else
- (ne (plus:HI (match_operand:HI 0 "register_operand" "r")
+ (ne (plus:HI (match_operand:HI 0 "register_operand" "+r")
(const_int -1))
(const_int 0))
(label_ref (match_operand 1 "" ""))
;; Move instructions
(define_insn "movdi"
- [(set (match_operand:DI 0 "general_operand" "=g")
- (match_operand:DI 1 "general_operand" "g"))]
+ [(set (match_operand:DI 0 "general_operand" "=g,rm,o")
+ (match_operand:DI 1 "general_operand" "m,r,a"))]
""
"* return output_move_quad (operands);"
;; what's the mose expensive code - say twice movsi = 16
- [(set_attr "length" "16")])
+ [(set_attr "length" "16,16,16")])
(define_insn "movsi"
[(set (match_operand:SI 0 "general_operand" "=r,r,r,rm,m")
[(set_attr "length" "1,2,2,3")])
(define_insn "movqi"
- [(set (match_operand:QI 0 "general_operand" "=rR,rR,Q,Q")
- (match_operand:QI 1 "general_operand" "rRN,Qi,rRN,Qi"))]
+ [(set (match_operand:QI 0 "nonimmediate_operand" "=g")
+ (match_operand:QI 1 "general_operand" "g"))]
""
"*
{
return \"movb %1, %0\";
}"
- [(set_attr "length" "1,2,2,3")])
+ [(set_attr "length" "1")])
;; do we have to supply all these moves? e.g. to
;; NO_LOAD_FPU_REGs ?
(define_insn "movdf"
- [(set (match_operand:DF 0 "general_operand" "=f,R,f,Q,f,m")
- (match_operand:DF 1 "general_operand" "fR,f,Q,f,F,m"))]
+ [(set (match_operand:DF 0 "general_operand" "=a,fR,a,Q,m")
+ (match_operand:DF 1 "general_operand" "fFR,a,Q,a,m"))]
""
- "* return output_move_quad (operands);"
+ "* if (which_alternative ==0)
+ return \"ldd %1, %0\";
+ else if (which_alternative == 1)
+ return \"std %1, %0\";
+ else
+ return output_move_quad (operands); "
;; just a guess..
- [(set_attr "length" "1,1,2,2,5,16")])
+ [(set_attr "length" "1,1,5,5,16")])
(define_insn "movsf"
[(set (match_operand:SF 0 "general_operand" "=g,r,g")
"
{
operands[0]
- = change_address (operands[0], VOIDmode,
- copy_to_mode_reg (Pmode, XEXP (operands[0], 0)));
+ = replace_equiv_address (operands[0],
+ copy_to_mode_reg (Pmode, XEXP (operands[0], 0)));
operands[1]
- = change_address (operands[1], VOIDmode,
- copy_to_mode_reg (Pmode, XEXP (operands[1], 0)));
+ = replace_equiv_address (operands[1],
+ copy_to_mode_reg (Pmode, XEXP (operands[1], 0)));
operands[5] = XEXP (operands[0], 0);
operands[6] = XEXP (operands[1], 0);
"TARGET_FPU"
"* if (which_alternative ==0)
{
- output_asm_insn(\"stcdf %1, -(sp)\", operands);
+ output_asm_insn(\"{stcdf|movfo} %1, -(sp)\", operands);
output_asm_insn(\"mov (sp)+, %0\", operands);
- operands[0] = gen_rtx(REG, HImode, REGNO (operands[0])+1);
+ operands[0] = gen_rtx_REG (HImode, REGNO (operands[0])+1);
output_asm_insn(\"mov (sp)+, %0\", operands);
return \"\";
}
else if (which_alternative == 1)
- return \"stcdf %1, %0\";
+ return \"{stcdf|movfo} %1, %0\";
else
- return \"stcdf %1, %0\";
+ return \"{stcdf|movfo} %1, %0\";
"
[(set_attr "length" "3,1,2")])
[(set (match_operand:HI 0 "general_operand" "=r")
(zero_extend:HI (match_operand:QI 1 "general_operand" "0")))]
""
- "bic $(256*255), %0"
+ "bic $0177400, %0"
[(set_attr "length" "2")])
(define_expand "zero_extendhisi2"
[(set (subreg:HI
(match_dup 0)
- 1)
+ 2)
(match_operand:HI 1 "register_operand" "r"))
(set (subreg:HI
(match_operand:SI 0 "register_operand" "=r")
(float_extend:DF (match_operand:SF 1 "general_operand" "r,R,Q")))]
"TARGET_FPU"
"@
- mov %1, -(sp)\;ldcfd (sp)+,%0
- ldcfd %1, %0
- ldcfd %1, %0"
+ mov %1, -(sp)\;{ldcfd|movof} (sp)+,%0
+ {ldcfd|movof} %1, %0
+ {ldcfd|movof} %1, %0"
[(set_attr "length" "2,1,2")])
;; does movb sign extend in register-to-register move?
/* make register pair available */
latehalf[0] = operands[0];
- operands[0] = gen_rtx(REG, HImode, REGNO (operands[0])+1);
-
+ operands[0] = gen_rtx_REG (HImode, REGNO (operands[0])+ 1);
+
output_asm_insn(\"movb %1, %0\", operands);
output_asm_insn(\"sxt %0\", latehalf);
/* we don't want to mess with auto increment */
- switch(which_alternative)
+ switch (which_alternative)
{
case 0:
latehalf[0] = operands[0];
- operands[0] = adj_offsettable_operand(operands[0], 2);
+ operands[0] = adjust_address(operands[0], HImode, 2);
output_asm_insn(\"mov %1, %0\", operands);
output_asm_insn(\"sxt %0\", latehalf);
/* make register pair available */
latehalf[0] = operands[0];
- operands[0] = gen_rtx(REG, HImode, REGNO (operands[0])+1);
+ operands[0] = gen_rtx_REG (HImode, REGNO (operands[0]) + 1);
output_asm_insn(\"mov %1, %0\", operands);
output_asm_insn(\"sxt %0\", latehalf);
"(! TARGET_40_PLUS)"
"*
{
- static count = 0;
+ static int count = 0;
char buf[100];
rtx lateoperands[2];
lateoperands[0] = operands[0];
- operands[0] = gen_rtx(REG, HImode, REGNO (operands[0])+1);
+ operands[0] = gen_rtx_REG (HImode, REGNO (operands[0]) + 1);
output_asm_insn(\"tst %0\", operands);
sprintf(buf, \"bge extendhisi%d\", count);
rtx latehalf[2];
latehalf[0] = NULL;
- latehalf[1] = gen_rtx(REG, HImode, REGNO (operands[0])+1);
+ latehalf[1] = gen_rtx_REG (HImode, REGNO (operands[1]) + 1);
output_asm_insn(\"mov %1, -(sp)\", latehalf);
output_asm_insn(\"mov %1, -(sp)\", operands);
output_asm_insn(\"setl\", operands);
- output_asm_insn(\"ldcld (sp)+, %0\", operands);
+ output_asm_insn(\"{ldcld|movif} (sp)+, %0\", operands);
output_asm_insn(\"seti\", operands);
return \"\";
}
else if (which_alternative == 1)
- return \"setl\;ldcld %1, %0\;seti\";
+ return \"setl\;{ldcld|movif} %1, %0\;seti\";
else
- return \"setl\;ldcld %1, %0\;seti\";
+ return \"setl\;{ldcld|movif} %1, %0\;seti\";
"
[(set_attr "length" "5,3,4")])
[(set (match_operand:DF 0 "register_operand" "=a,a")
(float:DF (match_operand:HI 1 "general_operand" "rR,Qi")))]
"TARGET_FPU"
- "ldcid %1, %0"
+ "{ldcid|movif} %1, %0"
[(set_attr "length" "1,2")])
;; cut float to int
"* if (which_alternative ==0)
{
output_asm_insn(\"setl\", operands);
- output_asm_insn(\"stcdl %1, -(sp)\", operands);
+ output_asm_insn(\"{stcdl|movfi} %1, -(sp)\", operands);
output_asm_insn(\"seti\", operands);
output_asm_insn(\"mov (sp)+, %0\", operands);
- operands[0] = gen_rtx(REG, HImode, REGNO (operands[0])+1);
+ operands[0] = gen_rtx_REG (HImode, REGNO (operands[0]) + 1);
output_asm_insn(\"mov (sp)+, %0\", operands);
return \"\";
}
else if (which_alternative == 1)
- return \"setl\;stcdl %1, %0\;seti\";
+ return \"setl\;{stcdl|movfi} %1, %0\;seti\";
else
- return \"setl\;stcdl %1, %0\;seti\";
+ return \"setl\;{stcdl|movfi} %1, %0\;seti\";
"
[(set_attr "length" "5,3,4")])
[(set (match_operand:HI 0 "general_operand" "=rR,Q")
(fix:HI (fix:DF (match_operand:DF 1 "register_operand" "a,a"))))]
"TARGET_FPU"
- "stcdi %1, %0"
+ "{stcdi|movfi} %1, %0"
[(set_attr "length" "1,2")])
\f
(plus:DF (match_operand:DF 1 "register_operand" "%0,0,0")
(match_operand:DF 2 "general_operand" "fR,Q,F")))]
"TARGET_FPU"
- "addd %2, %0"
+ "{addd|addf} %2, %0"
[(set_attr "length" "1,2,5")])
(define_insn "addsi3"
or is lateoperands the low word?? - looks like it! */
- unsigned int i;
rtx lateoperands[3];
lateoperands[0] = operands[0];
if (REG_P (operands[0]))
- operands[0] = gen_rtx(REG, HImode, REGNO(operands[0]) + 1);
+ operands[0] = gen_rtx_REG (HImode, REGNO (operands[0]) + 1);
else
- operands[0] = adj_offsettable_operand (operands[0], 2);
+ operands[0] = adjust_address (operands[0], HImode, 2);
if (! CONSTANT_P(operands[2]))
{
lateoperands[2] = operands[2];
if (REG_P (operands[2]))
- operands[2] = gen_rtx(REG, HImode, REGNO(operands[2]) + 1);
+ operands[2] = gen_rtx_REG (HImode, REGNO (operands[2]) + 1);
else
- operands[2] = adj_offsettable_operand(operands[2], 2);
+ operands[2] = adjust_address (operands[2], HImode, 2);
output_asm_insn (\"add %2, %0\", operands);
output_asm_insn (\"adc %0\", lateoperands);
return \"\";
}
- lateoperands[2] = GEN_INT ((INTVAL(operands[2]) >> 16) & 0xffff);
- operands[2] = GEN_INT (INTVAL(operands[2]) & 0xffff);
+ lateoperands[2] = GEN_INT ((INTVAL (operands[2]) >> 16) & 0xffff);
+ operands[2] = GEN_INT (INTVAL (operands[2]) & 0xffff);
if (INTVAL(operands[2]))
{
"*
{
if (GET_CODE (operands[2]) == CONST_INT)
- if (INTVAL(operands[2]) == 1)
- return \"inc %0\";
- else if (INTVAL(operands[2]) == -1)
- return \"dec %0\";
+ {
+ if (INTVAL(operands[2]) == 1)
+ return \"inc %0\";
+ else if (INTVAL(operands[2]) == -1)
+ return \"dec %0\";
+ }
return \"add %2, %0\";
}"
"*
{
if (GET_CODE (operands[2]) == CONST_INT)
- if (INTVAL(operands[2]) == 1)
- return \"incb %0\";
- else if (INTVAL(operands[2]) == -1)
- return \"decb %0\";
+ {
+ if (INTVAL(operands[2]) == 1)
+ return \"incb %0\";
+ else if (INTVAL(operands[2]) == -1)
+ return \"decb %0\";
+ }
- return \"addb %2, %0\";
+ return \"add %2, %0\";
}"
[(set_attr "length" "1,2,2,3")])
(minus:DF (match_operand:DF 1 "register_operand" "0,0")
(match_operand:DF 2 "general_operand" "fR,Q")))]
"TARGET_FPU"
- "subd %2, %0"
+ "{subd|subf} %2, %0"
[(set_attr "length" "1,2")])
(define_insn "subsi3"
or is lateoperands the low word?? - looks like it! */
- unsigned int i;
rtx lateoperands[3];
lateoperands[0] = operands[0];
if (REG_P (operands[0]))
- operands[0] = gen_rtx(REG, HImode, REGNO(operands[0]) + 1);
+ operands[0] = gen_rtx_REG (HImode, REGNO (operands[0]) + 1);
else
- operands[0] = adj_offsettable_operand (operands[0], 2);
+ operands[0] = adjust_address (operands[0], HImode, 2);
lateoperands[2] = operands[2];
if (REG_P (operands[2]))
- operands[2] = gen_rtx(REG, HImode, REGNO(operands[2]) + 1);
+ operands[2] = gen_rtx_REG (HImode, REGNO (operands[2]) + 1);
else
- operands[2] = adj_offsettable_operand(operands[2], 2);
+ operands[2] = adjust_address (operands[2], HImode, 2);
output_asm_insn (\"sub %2, %0\", operands);
output_asm_insn (\"sbc %0\", lateoperands);
if (GET_CODE (operands[2]) == CONST_INT)
abort();
- return \"subb %2, %0\";
+ return \"sub %2, %0\";
}"
[(set_attr "length" "1,2,2,3")])
;;;;- and instructions
-;; Bit-and on the pdp (like on the vax) is done with a clear-bits insn.
-(define_expand "andsi3"
- [(set (match_operand:SI 0 "general_operand" "=g")
- (and:SI (match_operand:SI 1 "general_operand" "0")
- (not:SI (match_operand:SI 2 "general_operand" "g"))))]
- ""
- "
-{
- extern rtx expand_unop ();
- if (GET_CODE (operands[2]) == CONST_INT)
- operands[2] = GEN_INT (~INTVAL (operands[2]));
- else
- operands[2] = expand_unop (SImode, one_cmpl_optab, operands[2], 0, 1);
-}")
+;; Bit-and on the pdp (like on the VAX) is done with a clear-bits insn.
-(define_expand "andhi3"
- [(set (match_operand:HI 0 "general_operand" "=g")
- (and:HI (match_operand:HI 1 "general_operand" "0")
- (not:HI (match_operand:HI 2 "general_operand" "g"))))]
- ""
- "
-{
- extern rtx expand_unop ();
- if (GET_CODE (operands[2]) == CONST_INT)
- operands[2] = GEN_INT (~INTVAL (operands[2]));
- else
- operands[2] = expand_unop (HImode, one_cmpl_optab, operands[2], 0, 1);
-}")
-
-(define_expand "andqi3"
- [(set (match_operand:QI 0 "general_operand" "=g")
- (and:QI (match_operand:QI 1 "general_operand" "0")
- (not:QI (match_operand:QI 2 "general_operand" "g"))))]
- ""
- "
-{
- extern rtx expand_unop ();
- rtx op = operands[2];
- if (GET_CODE (op) == CONST_INT)
- operands[2] = GEN_INT (((1 << 8) - 1) & ~INTVAL (op));
- else
- operands[2] = expand_unop (QImode, one_cmpl_optab, op, 0, 1);
-}")
-
-(define_insn "andcbsi3"
+(define_insn "andsi3"
[(set (match_operand:SI 0 "general_operand" "=r,r,o,o,r,r,r,o,o,o")
(and:SI (match_operand:SI 1 "general_operand" "%0,0,0,0,0,0,0,0,0,0")
(not:SI (match_operand:SI 2 "general_operand" "r,o,r,o,I,J,K,I,J,K"))))]
or is lateoperands the low word?? - looks like it! */
- unsigned int i;
rtx lateoperands[3];
lateoperands[0] = operands[0];
if (REG_P (operands[0]))
- operands[0] = gen_rtx(REG, HImode, REGNO(operands[0]) + 1);
+ operands[0] = gen_rtx_REG (HImode, REGNO (operands[0]) + 1);
else
- operands[0] = adj_offsettable_operand (operands[0], 2);
+ operands[0] = adjust_address (operands[0], HImode, 2);
if (! CONSTANT_P(operands[2]))
{
lateoperands[2] = operands[2];
if (REG_P (operands[2]))
- operands[2] = gen_rtx(REG, HImode, REGNO(operands[2]) + 1);
+ operands[2] = gen_rtx_REG (HImode, REGNO (operands[2]) + 1);
else
- operands[2] = adj_offsettable_operand(operands[2], 2);
+ operands[2] = adjust_address (operands[2], HImode, 2);
output_asm_insn (\"bic %2, %0\", operands);
output_asm_insn (\"bic %2, %0\", lateoperands);
return \"\";
}
- lateoperands[2] = GEN_INT ((INTVAL(operands[2]) >> 16) & 0xffff);
- operands[2] = GEN_INT (INTVAL(operands[2]) & 0xffff);
+ lateoperands[2] = GEN_INT ((INTVAL (operands[2]) >> 16) & 0xffff);
+ operands[2] = GEN_INT (INTVAL (operands[2]) & 0xffff);
/* these have different lengths, so we should have
different constraints! */
}"
[(set_attr "length" "2,4,4,6,2,2,4,3,3,6")])
-(define_insn "andcbhi3"
+(define_insn "andhi3"
[(set (match_operand:HI 0 "general_operand" "=rR,rR,Q,Q")
(and:HI (match_operand:HI 1 "general_operand" "0,0,0,0")
(not:HI (match_operand:HI 2 "general_operand" "rR,Qi,rR,Qi"))))]
"bic %2, %0"
[(set_attr "length" "1,2,2,3")])
-(define_insn "andcbqi3"
+(define_insn "andqi3"
[(set (match_operand:QI 0 "general_operand" "=rR,rR,Q,Q")
(and:QI (match_operand:QI 1 "general_operand" "0,0,0,0")
(not:QI (match_operand:QI 2 "general_operand" "rR,Qi,rR,Qi"))))]
or is lateoperands the low word?? - looks like it! */
- unsigned int i;
rtx lateoperands[3];
lateoperands[0] = operands[0];
if (REG_P (operands[0]))
- operands[0] = gen_rtx(REG, HImode, REGNO(operands[0]) + 1);
+ operands[0] = gen_rtx_REG (HImode, REGNO (operands[0]) + 1);
else
- operands[0] = adj_offsettable_operand (operands[0], 2);
+ operands[0] = adjust_address (operands[0], HImode, 2);
if (! CONSTANT_P(operands[2]))
- {
- lateoperands[2] = operands[2];
+ {
+ lateoperands[2] = operands[2];
- if (REG_P (operands[2]))
- operands[2] = gen_rtx(REG, HImode, REGNO(operands[2]) + 1);
- else
- operands[2] = adj_offsettable_operand(operands[2], 2);
+ if (REG_P (operands[2]))
+ operands[2] = gen_rtx_REG (HImode, REGNO (operands[2]) + 1);
+ else
+ operands[2] = adjust_address (operands[2], HImode, 2);
- output_asm_insn (\"bis %2, %0\", operands);
- output_asm_insn (\"bis %2, %0\", lateoperands);
- return \"\";
- }
+ output_asm_insn (\"bis %2, %0\", operands);
+ output_asm_insn (\"bis %2, %0\", lateoperands);
+ return \"\";
+ }
- lateoperands[2] = GEN_INT ((INTVAL(operands[2]) >> 16) & 0xffff);
- operands[2] = GEN_INT (INTVAL(operands[2]) & 0xffff);
+ lateoperands[2] = GEN_INT ((INTVAL (operands[2]) >> 16) & 0xffff);
+ operands[2] = GEN_INT (INTVAL (operands[2]) & 0xffff);
/* these have different lengths, so we should have
different constraints! */
;;- xor instructions
(define_insn "xorsi3"
- [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
- (xor:SI (match_operand:SI 1 "register_operand" "%0,0,0,0")
- (match_operand:SI 2 "arith_operand" "r,I,J,K")))]
+ [(set (match_operand:SI 0 "register_operand" "=r")
+ (xor:SI (match_operand:SI 1 "register_operand" "%0")
+ (match_operand:SI 2 "arith_operand" "r")))]
"TARGET_40_PLUS"
"*
{ /* Here we trust that operands don't overlap */
- unsigned int i;
rtx lateoperands[3];
lateoperands[0] = operands[0];
- operands[0] = gen_rtx(REG, HImode, REGNO(operands[0]) + 1);
+ operands[0] = gen_rtx_REG (HImode, REGNO (operands[0]) + 1);
if (REG_P(operands[2]))
- {
- lateoperands[2] = operands[2];
- operands[2] = gen_rtx(REG, HImode, REGNO(operands[2]) + 1);
-
- output_asm_insn (\"xor %2, %0\", operands);
- output_asm_insn (\"xor %2, %0\", lateoperands);
-
- return \"\";
- }
+ {
+ lateoperands[2] = operands[2];
+ operands[2] = gen_rtx_REG (HImode, REGNO (operands[2]) + 1);
- lateoperands[2] = GEN_INT ((INTVAL(operands[2]) >> 16) & 0xffff);
- operands[2] = GEN_INT (INTVAL(operands[2]) & 0xffff);
-
- if (INTVAL(operands[2]))
- output_asm_insn (\"xor %2, %0\", operands);
+ output_asm_insn (\"xor %2, %0\", operands);
+ output_asm_insn (\"xor %2, %0\", lateoperands);
- if (INTVAL(lateoperands[2]))
- output_asm_insn (\"xor %2, %0\", lateoperands);
+ return \"\";
+ }
- return \"\";
}"
- [(set_attr "length" "2,1,1,2")])
+ [(set_attr "length" "2")])
(define_insn "xorhi3"
[(set (match_operand:HI 0 "general_operand" "=rR,Q")
[(set_attr "length" "1,2")])
(define_insn "one_cmplqi2"
- [(set (match_operand:QI 0 "general_operand" "=rR,Q")
- (not:QI (match_operand:QI 1 "general_operand" "0,0")))]
+ [(set (match_operand:QI 0 "general_operand" "=rR,rR")
+ (not:QI (match_operand:QI 1 "general_operand" "0,g")))]
""
- "comb %0"
+ "@
+ comb %0
+ movb %1, %0\; comb %0"
[(set_attr "length" "1,2")])
;;- arithmetic shift instructions
"asr %0"
[(set_attr "length" "1,2")])
+;; lsr
+(define_insn ""
+ [(set (match_operand:HI 0 "general_operand" "=rR,Q")
+ (lshiftrt:HI (match_operand:HI 1 "general_operand" "0,0")
+ (const_int 1)))]
+ ""
+ "clc\;ror %0"
+ [(set_attr "length" "1,2")])
+
+(define_insn "lshrsi3"
+ [(set (match_operand:SI 0 "register_operand" "=r")
+ (lshiftrt:SI (match_operand:SI 1 "general_operand" "0")
+ (const_int 1)))]
+ ""
+{
+
+ rtx lateoperands[2];
+
+ lateoperands[0] = operands[0];
+ operands[0] = gen_rtx_REG (HImode, REGNO (operands[0]) + 1);
+
+ lateoperands[1] = operands[1];
+ operands[1] = gen_rtx_REG (HImode, REGNO (operands[1]) + 1);
+
+ output_asm_insn (\"clc\", operands);
+ output_asm_insn (\"ror %0\", lateoperands);
+ output_asm_insn (\"ror %0\", operands);
+
+ return \"\";
+}
+ [(set_attr "length" "5")])
+
;; shift is by arbitrary count is expensive,
;; shift by one cheap - so let's do that, if
;; space doesn't matter
"*
{
if (GET_CODE(operands[2]) == CONST_INT)
- if (INTVAL(operands[2]) == 1)
- return \"asl %0\";
- else if (INTVAL(operands[2]) == -1)
- return \"asr %0\";
+ {
+ if (INTVAL(operands[2]) == 1)
+ return \"asl %0\";
+ else if (INTVAL(operands[2]) == -1)
+ return \"asr %0\";
+ }
return \"ash %2,%0\";
}"
[(set (match_operand:DF 0 "general_operand" "=fR,Q")
(abs:DF (match_operand:DF 1 "general_operand" "0,0")))]
"TARGET_FPU"
- "absd %0"
+ "{absd|absf} %0"
[(set_attr "length" "1,2")])
(define_insn "abshi2"
"TARGET_ABSHI_BUILTIN"
"*
{
- static count = 0;
+ static int count = 0;
char buf[200];
output_asm_insn(\"tst %0\", operands);
;
; /* allow REG_NOTES to be set on last insn (labels don't have enough
; fields, and can't be used for REG_NOTES anyway). */
-; emit_insn (gen_rtx (USE, VOIDmode, stack_pointer_rtx));
+; emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
; DONE;
;}")
[(set (match_operand:DF 0 "general_operand" "=fR,Q")
(neg:DF (match_operand:DF 1 "register_operand" "0,0")))]
"TARGET_FPU"
- "negd %0"
+ "{negd|negf} %0"
[(set_attr "length" "1,2")])
+(define_insn "negsi2"
+ [(set (match_operand:SI 0 "register_operand" "=r")
+ (neg:SI (match_operand:SI 1 "general_operand" "0")))]
+ ""
+{
+
+ rtx lateoperands[2];
+
+ lateoperands[0] = operands[0];
+ operands[0] = gen_rtx_REG (HImode, REGNO (operands[0]) + 1);
+
+ lateoperands[1] = operands[1];
+ operands[1] = gen_rtx_REG (HImode, REGNO (operands[1]) + 1);
+
+ output_asm_insn (\"com %0\", operands);
+ output_asm_insn (\"com %0\", lateoperands);
+ output_asm_insn (\"inc %0\", operands);
+ output_asm_insn (\"adc %0\", lateoperands);
+
+ return \"\";
+}
+ [(set_attr "length" "5")])
+
(define_insn "neghi2"
[(set (match_operand:HI 0 "general_operand" "=rR,Q")
(neg:HI (match_operand:HI 1 "general_operand" "0,0")))]
;;- jump to subroutine
(define_insn "call"
- [(call (match_operand:HI 0 "general_operand" "R,Q")
+ [(call (match_operand:HI 0 "general_operand" "rR,Q")
(match_operand:HI 1 "general_operand" "g,g"))
;; (use (reg:HI 0)) what was that ???
]
;;- jump to subroutine
(define_insn "call_value"
[(set (match_operand 0 "" "")
- (call (match_operand:HI 1 "general_operand" "R,Q")
+ (call (match_operand:HI 1 "general_operand" "rR,Q")
(match_operand:HI 2 "general_operand" "g,g")))
;; (use (reg:HI 0)) - what was that ????
]
(mult:DF (match_operand:DF 1 "register_operand" "%0,0,0")
(match_operand:DF 2 "general_operand" "fR,Q,F")))]
"TARGET_FPU"
- "muld %2, %0"
+ "{muld|mulf} %2, %0"
[(set_attr "length" "1,2,5")])
;; 16 bit result multiply:
(div:DF (match_operand:DF 1 "register_operand" "0,0,0")
(match_operand:DF 2 "general_operand" "fR,Q,F")))]
"TARGET_FPU"
- "divd %2, %0"
+ "{divd|divf} %2, %0"
[(set_attr "length" "1,2,5")])
[(set_attr "length" "2")])
(define_expand "modhi3"
- [(set (subreg:HI (match_dup 1) 1)
+ [(set (subreg:HI (match_dup 1) 2)
(mod:HI (match_operand:SI 1 "general_operand" "0")
(match_operand:HI 2 "general_operand" "g")))
(set (match_operand:HI 0 "general_operand" "=r")
- (subreg:HI (match_dup 1) 1))]
+ (subreg:HI (match_dup 1) 2))]
"TARGET_45"
"")
(define_insn ""
- [(set (subreg:HI (match_operand:SI 0 "general_operand" "=r") 1)
+ [(set (subreg:HI (match_operand:SI 0 "general_operand" "=r") 2)
(mod:HI (match_operand:SI 1 "general_operand" "0")
(match_operand:HI 2 "general_operand" "g")))]
"TARGET_45"
; [(parallel [(set (subreg:HI (match_dup 1) 0)
; (div:HI (match_operand:SI 1 "general_operand" "0")
; (match_operand:HI 2 "general_operand" "g")))
-; (set (subreg:HI (match_dup 1) 1)
+; (set (subreg:HI (match_dup 1) 2)
; (mod:HI (match_dup 1)
; (match_dup 2)))])
; (set (match_operand:HI 3 "general_operand" "=r")
-; (subreg:HI (match_dup 1) 1))
+; (subreg:HI (match_dup 1) 2))
; (set (match_operand:HI 0 "general_operand" "=r")
; (subreg:HI (match_dup 1) 0))]
; "TARGET_45"
; [(set (subreg:HI (match_operand:SI 0 "general_operand" "=r") 0)
; (div:HI (match_operand:SI 1 "general_operand" "0")
; (match_operand:HI 2 "general_operand" "g")))
-; (set (subreg:HI (match_dup 0) 1)
+; (set (subreg:HI (match_dup 0) 2)
; (mod:HI (match_dup 1)
; (match_dup 2)))]
; "TARGET_45"
OSDN Git Service
