-/* Configuration for GNU C-compiler for PA-RISC.
- Copyright (C) 1999, 2000 Free Software Foundation, Inc.
+/* Configuration for GCC-compiler for PA-RISC.
+ Copyright (C) 1999, 2000, 2003, 2004 Free Software Foundation, Inc.
-This file is part of GNU CC.
+This file is part of GCC.
-GNU CC is free software; you can redistribute it and/or modify
+GCC is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
any later version.
-GNU CC is distributed in the hope that it will be useful,
+GCC is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING. If not, write to
+along with GCC; see the file COPYING. If not, write to
the Free Software Foundation, 59 Temple Place - Suite 330,
Boston, MA 02111-1307, USA. */
#define CONDITIONAL_REGISTER_USAGE \
{ \
+ int i; \
if (TARGET_DISABLE_FPREGS || TARGET_SOFT_FLOAT)\
{ \
for (i = FP_REG_FIRST; i < FP_REG_LAST; i++)\
fixed_regs[i] = call_used_regs[i] = 1; \
} \
if (flag_pic) \
- { \
- fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
- fixed_regs[PIC_OFFSET_TABLE_REGNUM_SAVED] = 1;\
- } \
+ fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
}
/* Allocate the call used registers first. This should minimize
registers will generally not be allocated across a call).
Experimentation has shown slightly better results by allocating
- FP registers first.
-
- FP registers are ordered so that all L registers are selected before
- R registers. This works around a false dependency interlock on the
- PA8000 when accessing the high and low parts of an FP register
- independently. */
+ FP registers first. We allocate the caller-saved registers more
+ or less in reverse order to their allocation as arguments. */
#define REG_ALLOC_ORDER \
{ \
/* caller-saved fp regs. */ \
50, 51, 52, 53, 54, 55, 56, 57, \
- 58, 59, 36, 37, 38, 39, 32, 33, \
- 34, 35, \
+ 58, 59, 39, 38, 37, 36, 35, 34, \
+ 33, 32, \
/* caller-saved general regs. */ \
- 19, 20, 21, 22, 23, 24, 25, 26, \
- 27, 28, 29, 31, 2, \
+ 28, 31, 19, 20, 21, 22, 23, 24, \
+ 25, 26, 29, 2, \
/* callee-saved fp regs. */ \
40, 41, 42, 43, 44, 45, 46, 47, \
48, 49, \
3, 4, 5, 6, 7, 8, 9, 10, \
11, 12, 13, 14, 15, 16, 17, 18, \
/* special registers. */ \
- 1, 30, 0, 60}
+ 1, 27, 30, 0, 60}
/* Return number of consecutive hard regs needed starting at reg REGNO
but can be less for certain modes in special long registers.
For PA64, GPRs and FPRs hold 64 bits worth (we ignore the 32bit
- addressability of the FPRs). ie, we pretend each register holds
+ addressability of the FPRs). i.e., we pretend each register holds
precisely WORD_SIZE bits. */
#define HARD_REGNO_NREGS(REGNO, MODE) \
((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
#define HARD_REGNO_MODE_OK(REGNO, MODE) \
((REGNO) == 0 \
? (MODE) == CCmode || (MODE) == CCFPmode \
- /* Make wide modes be in aligned registers. */ \
+ /* Make wide modes be in aligned registers. */ \
: (GET_MODE_SIZE (MODE) <= UNITS_PER_WORD \
|| (GET_MODE_SIZE (MODE) <= 2 * UNITS_PER_WORD && ((REGNO) & 1) == 0)))
Registers 0 - 31 remain unchanged.
- Registers 32 - 60 are mapped to 72, 74, 76 ...
-
- Register 88 is mapped to 32. */
+ Registers 32 - 59 are mapped to 72, 74, 76 ...
+ Register 60 is mapped to 32. */
#define DBX_REGISTER_NUMBER(REGNO) \
- ((REGNO) <= 31 ? (REGNO) : \
- ((REGNO) > 31 && (REGNO) <= 60 ? (REGNO - 32) * 2 + 72 : 32))
+ ((REGNO) <= 31 ? (REGNO) : ((REGNO) < 60 ? (REGNO - 32) * 2 + 72 : 32))
+
+/* We must not use the DBX register numbers for the DWARF 2 CFA column
+ numbers because that maps to numbers beyond FIRST_PSEUDO_REGISTER.
+ Instead use the identity mapping. */
+#define DWARF_FRAME_REGNUM(REG) REG
/* Define the classes of registers for register constraints in the
machine description. Also define ranges of constants.
#define N_REG_CLASSES (int) LIM_REG_CLASSES
-/* Give names of register classes as strings for dump file. */
+/* Give names of register classes as strings for dump file. */
#define REG_CLASS_NAMES \
{"NO_REGS", "R1_REGS", "GENERAL_REGS", "FPUPPER_REGS", "FP_REGS", \
/* Define which registers fit in which classes.
This is an initializer for a vector of HARD_REG_SET
of length N_REG_CLASSES. Register 0, the "condition code" register,
- is in no class. */
+ is in no class. */
#define REG_CLASS_CONTENTS \
{{0x00000000, 0x00000000}, /* NO_REGS */ \
{0x00000000, 0x10000000}, /* SHIFT_REGS */ \
{0xfffffffe, 0x1fffffff}} /* ALL_REGS */
-/* This may not actually be necessary anymore. But until I can prove
- otherwise it will stay. */
-#define CLASS_CANNOT_CHANGE_SIZE (FP_REGS)
+/* Defines invalid mode changes.
+
+ SImode loads to floating-point registers are not zero-extended.
+ The definition for LOAD_EXTEND_OP specifies that integer loads
+ narrower than BITS_PER_WORD will be zero-extended. As a result,
+ we inhibit changes from SImode unless they are to a mode that is
+ identical in size. */
+
+#define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
+ ((FROM) == SImode && GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO) \
+ ? reg_classes_intersect_p (CLASS, FP_REGS) : 0)
-/* The same information, inverted:
- Return the class number of the smallest class containing
+/* Return the class number of the smallest class containing
reg number REGNO. This could be a conditional expression
or could index an array. */
/* Get reg_class from a letter such as appears in the machine description. */
-/* Keep 'x' for backward compatibility with user asm. */
+/* Keep 'x' for backward compatibility with user asm. */
#define REG_CLASS_FROM_LETTER(C) \
((C) == 'f' ? FP_REGS : \
(C) == 'y' ? FP_REGS : \
"%fr28", "%fr29", "%fr30", "%fr31", "SAR"}
#define ADDITIONAL_REGISTER_NAMES \
- {{"%cr11",88}}
+ {{"%cr11",60}}
#define FP_SAVED_REG_LAST 49
#define FP_SAVED_REG_FIRST 40
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