;; Mips.md Machine Description for MIPS based processors
;; Copyright (C) 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
-;; 1999, 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
+;; 1999, 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
;; Contributed by A. Lichnewsky, lich@inria.inria.fr
;; Changes by Michael Meissner, meissner@osf.org
-;; 64 bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and
+;; 64-bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and
;; Brendan Eich, brendan@microunity.com.
;; This file is part of GCC.
;; You should have received a copy of the GNU General Public License
;; along with GCC; see the file COPYING. If not, write to
-;; the Free Software Foundation, 59 Temple Place - Suite 330,
-;; Boston, MA 02111-1307, USA.
+;; the Free Software Foundation, 51 Franklin Street, Fifth Floor,
+;; Boston, MA 02110-1301, USA.
(define_constants
[(UNSPEC_LOAD_DF_LOW 0)
(UNSPEC_LOAD_GOT 24)
(UNSPEC_GP 25)
(UNSPEC_MFHILO 26)
+ (UNSPEC_TLS_LDM 27)
+ (UNSPEC_TLS_GET_TP 28)
+ (UNSPEC_MFHC1 31)
+ (UNSPEC_MTHC1 32)
(UNSPEC_ADDRESS_FIRST 100)
;; For MIPS Paired-Singled Floating Point Instructions.
- (UNSPEC_C_F 201)
- (UNSPEC_C_UN 202)
- (UNSPEC_C_EQ 203)
- (UNSPEC_C_UEQ 204)
- (UNSPEC_C_OLT 205)
- (UNSPEC_C_ULT 206)
- (UNSPEC_C_OLE 207)
- (UNSPEC_C_ULE 208)
- (UNSPEC_C_SF 209)
- (UNSPEC_C_NGLE 210)
- (UNSPEC_C_SEQ 211)
- (UNSPEC_C_NGL 212)
- (UNSPEC_C_LT 213)
- (UNSPEC_C_NGE 214)
- (UNSPEC_C_LE 215)
- (UNSPEC_C_NGT 216)
+ (UNSPEC_MOVE_TF_PS 200)
+ (UNSPEC_C 201)
;; MIPS64/MIPS32R2 alnv.ps
- (UNSPEC_ALNV_PS 217)
+ (UNSPEC_ALNV_PS 202)
;; MIPS-3D instructions
-
- (UNSPEC_CABS_F 218)
- (UNSPEC_CABS_UN 219)
- (UNSPEC_CABS_EQ 220)
- (UNSPEC_CABS_UEQ 221)
- (UNSPEC_CABS_OLT 222)
- (UNSPEC_CABS_ULT 223)
- (UNSPEC_CABS_OLE 224)
- (UNSPEC_CABS_ULE 225)
- (UNSPEC_CABS_SF 226)
- (UNSPEC_CABS_NGLE 227)
- (UNSPEC_CABS_SEQ 228)
- (UNSPEC_CABS_NGL 229)
- (UNSPEC_CABS_LT 230)
- (UNSPEC_CABS_NGE 231)
- (UNSPEC_CABS_LE 232)
- (UNSPEC_CABS_NGT 233)
-
- (UNSPEC_ADDR_PS 234)
- (UNSPEC_CVT_PW_PS 235)
- (UNSPEC_CVT_PS_PW 236)
- (UNSPEC_MULR_PS 237)
-
- (UNSPEC_RECIP1_S 238)
- (UNSPEC_RECIP1_D 239)
- (UNSPEC_RECIP1_PS 240)
- (UNSPEC_RECIP2_S 241)
- (UNSPEC_RECIP2_D 242)
- (UNSPEC_RECIP2_PS 243)
-
- (UNSPEC_RSQRT1_S 244)
- (UNSPEC_RSQRT1_D 245)
- (UNSPEC_RSQRT1_PS 246)
- (UNSPEC_RSQRT2_S 247)
- (UNSPEC_RSQRT2_D 248)
- (UNSPEC_RSQRT2_PS 249)
-
- (UNSPEC_MOVE_TF_PS 250)
+ (UNSPEC_CABS 203)
+
+ (UNSPEC_ADDR_PS 204)
+ (UNSPEC_CVT_PW_PS 205)
+ (UNSPEC_CVT_PS_PW 206)
+ (UNSPEC_MULR_PS 207)
+ (UNSPEC_ABS_PS 208)
+
+ (UNSPEC_RSQRT1 209)
+ (UNSPEC_RSQRT2 210)
+ (UNSPEC_RECIP1 211)
+ (UNSPEC_RECIP2 212)
+ (UNSPEC_SINGLE_CC 213)
+ (UNSPEC_SCC 214)
+
+ ;; MIPS DSP ASE Revision 0.98 3/24/2005
+ (UNSPEC_ADDQ 300)
+ (UNSPEC_ADDQ_S 301)
+ (UNSPEC_SUBQ 302)
+ (UNSPEC_SUBQ_S 303)
+ (UNSPEC_ADDSC 304)
+ (UNSPEC_ADDWC 305)
+ (UNSPEC_MODSUB 306)
+ (UNSPEC_RADDU_W_QB 307)
+ (UNSPEC_ABSQ_S 308)
+ (UNSPEC_PRECRQ_QB_PH 309)
+ (UNSPEC_PRECRQ_PH_W 310)
+ (UNSPEC_PRECRQ_RS_PH_W 311)
+ (UNSPEC_PRECRQU_S_QB_PH 312)
+ (UNSPEC_PRECEQ_W_PHL 313)
+ (UNSPEC_PRECEQ_W_PHR 314)
+ (UNSPEC_PRECEQU_PH_QBL 315)
+ (UNSPEC_PRECEQU_PH_QBR 316)
+ (UNSPEC_PRECEQU_PH_QBLA 317)
+ (UNSPEC_PRECEQU_PH_QBRA 318)
+ (UNSPEC_PRECEU_PH_QBL 319)
+ (UNSPEC_PRECEU_PH_QBR 320)
+ (UNSPEC_PRECEU_PH_QBLA 321)
+ (UNSPEC_PRECEU_PH_QBRA 322)
+ (UNSPEC_SHLL 323)
+ (UNSPEC_SHLL_S 324)
+ (UNSPEC_SHRL_QB 325)
+ (UNSPEC_SHRA_PH 326)
+ (UNSPEC_SHRA_R 327)
+ (UNSPEC_MULEU_S_PH_QBL 328)
+ (UNSPEC_MULEU_S_PH_QBR 329)
+ (UNSPEC_MULQ_RS_PH 330)
+ (UNSPEC_MULEQ_S_W_PHL 331)
+ (UNSPEC_MULEQ_S_W_PHR 332)
+ (UNSPEC_DPAU_H_QBL 333)
+ (UNSPEC_DPAU_H_QBR 334)
+ (UNSPEC_DPSU_H_QBL 335)
+ (UNSPEC_DPSU_H_QBR 336)
+ (UNSPEC_DPAQ_S_W_PH 337)
+ (UNSPEC_DPSQ_S_W_PH 338)
+ (UNSPEC_MULSAQ_S_W_PH 339)
+ (UNSPEC_DPAQ_SA_L_W 340)
+ (UNSPEC_DPSQ_SA_L_W 341)
+ (UNSPEC_MAQ_S_W_PHL 342)
+ (UNSPEC_MAQ_S_W_PHR 343)
+ (UNSPEC_MAQ_SA_W_PHL 344)
+ (UNSPEC_MAQ_SA_W_PHR 345)
+ (UNSPEC_BITREV 346)
+ (UNSPEC_INSV 347)
+ (UNSPEC_REPL_QB 348)
+ (UNSPEC_REPL_PH 349)
+ (UNSPEC_CMP_EQ 350)
+ (UNSPEC_CMP_LT 351)
+ (UNSPEC_CMP_LE 352)
+ (UNSPEC_CMPGU_EQ_QB 353)
+ (UNSPEC_CMPGU_LT_QB 354)
+ (UNSPEC_CMPGU_LE_QB 355)
+ (UNSPEC_PICK 356)
+ (UNSPEC_PACKRL_PH 357)
+ (UNSPEC_EXTR_W 358)
+ (UNSPEC_EXTR_R_W 359)
+ (UNSPEC_EXTR_RS_W 360)
+ (UNSPEC_EXTR_S_H 361)
+ (UNSPEC_EXTP 362)
+ (UNSPEC_EXTPDP 363)
+ (UNSPEC_SHILO 364)
+ (UNSPEC_MTHLIP 365)
+ (UNSPEC_WRDSP 366)
+ (UNSPEC_RDDSP 367)
+
+ ;; MIPS DSP ASE REV 2 Revision 0.02 11/24/2006
+ (UNSPEC_ABSQ_S_QB 400)
+ (UNSPEC_ADDU_PH 401)
+ (UNSPEC_ADDU_S_PH 402)
+ (UNSPEC_ADDUH_QB 403)
+ (UNSPEC_ADDUH_R_QB 404)
+ (UNSPEC_APPEND 405)
+ (UNSPEC_BALIGN 406)
+ (UNSPEC_CMPGDU_EQ_QB 407)
+ (UNSPEC_CMPGDU_LT_QB 408)
+ (UNSPEC_CMPGDU_LE_QB 409)
+ (UNSPEC_DPA_W_PH 410)
+ (UNSPEC_DPS_W_PH 411)
+ (UNSPEC_MADD 412)
+ (UNSPEC_MADDU 413)
+ (UNSPEC_MSUB 414)
+ (UNSPEC_MSUBU 415)
+ (UNSPEC_MUL_PH 416)
+ (UNSPEC_MUL_S_PH 417)
+ (UNSPEC_MULQ_RS_W 418)
+ (UNSPEC_MULQ_S_PH 419)
+ (UNSPEC_MULQ_S_W 420)
+ (UNSPEC_MULSA_W_PH 421)
+ (UNSPEC_MULT 422)
+ (UNSPEC_MULTU 423)
+ (UNSPEC_PRECR_QB_PH 424)
+ (UNSPEC_PRECR_SRA_PH_W 425)
+ (UNSPEC_PRECR_SRA_R_PH_W 426)
+ (UNSPEC_PREPEND 427)
+ (UNSPEC_SHRA_QB 428)
+ (UNSPEC_SHRA_R_QB 429)
+ (UNSPEC_SHRL_PH 430)
+ (UNSPEC_SUBU_PH 431)
+ (UNSPEC_SUBU_S_PH 432)
+ (UNSPEC_SUBUH_QB 433)
+ (UNSPEC_SUBUH_R_QB 434)
+ (UNSPEC_ADDQH_PH 435)
+ (UNSPEC_ADDQH_R_PH 436)
+ (UNSPEC_ADDQH_W 437)
+ (UNSPEC_ADDQH_R_W 438)
+ (UNSPEC_SUBQH_PH 439)
+ (UNSPEC_SUBQH_R_PH 440)
+ (UNSPEC_SUBQH_W 441)
+ (UNSPEC_SUBQH_R_W 442)
+ (UNSPEC_DPAX_W_PH 443)
+ (UNSPEC_DPSX_W_PH 444)
+ (UNSPEC_DPAQX_S_W_PH 445)
+ (UNSPEC_DPAQX_SA_W_PH 446)
+ (UNSPEC_DPSQX_S_W_PH 447)
+ (UNSPEC_DPSQX_SA_W_PH 448)
]
)
(include "predicates.md")
+(include "constraints.md")
\f
;; ....................
;;
;; This attribute is YES if the instruction is a jal macro (not a
;; real jal instruction).
;;
-;; jal is always a macro in SVR4 PIC since it includes an instruction to
-;; restore $gp. Direct jals are also macros in NewABI PIC since they
-;; load the target address into $25.
+;; jal is always a macro for o32 and o64 abicalls because it includes an
+;; instruction to restore $gp. Direct jals are also macros for -mshared
+;; abicalls because they first load the target address into $25.
(define_attr "jal_macro" "no,yes"
(cond [(eq_attr "jal" "direct")
- (symbol_ref "TARGET_ABICALLS != 0")
+ (symbol_ref "TARGET_ABICALLS
+ && (TARGET_OLDABI || !TARGET_ABSOLUTE_ABICALLS)")
(eq_attr "jal" "indirect")
- (symbol_ref "(TARGET_ABICALLS && !TARGET_NEWABI) != 0")]
+ (symbol_ref "TARGET_ABICALLS && TARGET_OLDABI")]
(const_string "no")))
;; Classification of each insn.
;; slt set less than instructions
;; clz the clz and clo instructions
;; trap trap if instructions
-;; imul integer multiply
+;; imul integer multiply 2 operands
+;; imul3 integer multiply 3 operands
;; imadd integer multiply-add
;; idiv integer divide
;; fmove floating point register move
;; fmadd floating point multiply-add
;; fdiv floating point divide
;; frdiv floating point reciprocal divide
+;; frdiv1 floating point reciprocal divide step 1
+;; frdiv2 floating point reciprocal divide step 2
;; fabs floating point absolute value
;; fneg floating point negation
;; fcmp floating point compare
;; fcvt floating point convert
;; fsqrt floating point square root
;; frsqrt floating point reciprocal square root
+;; frsqrt1 floating point reciprocal square root step1
+;; frsqrt2 floating point reciprocal square root step2
;; multi multiword sequence (or user asm statements)
;; nop no operation
(define_attr "type"
- "unknown,branch,jump,call,load,fpload,fpidxload,store,fpstore,fpidxstore,prefetch,prefetchx,condmove,xfer,mthilo,mfhilo,const,arith,shift,slt,clz,trap,imul,imadd,idiv,fmove,fadd,fmul,fmadd,fdiv,frdiv,fabs,fneg,fcmp,fcvt,fsqrt,frsqrt,multi,nop"
+ "unknown,branch,jump,call,load,fpload,fpidxload,store,fpstore,fpidxstore,prefetch,prefetchx,condmove,xfer,mthilo,mfhilo,const,arith,shift,slt,clz,trap,imul,imul3,imadd,idiv,fmove,fadd,fmul,fmadd,fdiv,frdiv,frdiv1,frdiv2,fabs,fneg,fcmp,fcvt,fsqrt,frsqrt,frsqrt1,frsqrt2,multi,nop"
(cond [(eq_attr "jal" "!unset") (const_string "call")
(eq_attr "got" "load") (const_string "load")]
(const_string "unknown")))
(define_attr "mode" "unknown,none,QI,HI,SI,DI,SF,DF,FPSW"
(const_string "unknown"))
+;; Mode for conversion types (fcvt)
+;; I2S integer to float single (SI/DI to SF)
+;; I2D integer to float double (SI/DI to DF)
+;; S2I float to integer (SF to SI/DI)
+;; D2I float to integer (DF to SI/DI)
+;; D2S double to float single
+;; S2D float single to double
+
+(define_attr "cnv_mode" "unknown,I2S,I2D,S2I,D2I,D2S,S2D"
+ (const_string "unknown"))
+
;; Is this an extended instruction in mips16 mode?
(define_attr "extended_mips16" "no,yes"
(const_string "no"))
;; VR4120 errata MD(4): if there are consecutive dmult instructions,
;; the result of the second one is missed. The assembler should work
;; around this by inserting a nop after the first dmult.
- (and (eq_attr "type" "imul")
+ (and (eq_attr "type" "imul,imul3")
(and (eq_attr "mode" "DI")
(ne (symbol_ref "TARGET_FIX_VR4120") (const_int 0))))
(const_int 8)
;; Attribute describing the processor. This attribute must match exactly
;; with the processor_type enumeration in mips.h.
(define_attr "cpu"
- "default,4kc,5kc,20kc,m4k,r3000,r3900,r6000,r4000,r4100,r4111,r4120,r4130,r4300,r4600,r4650,r5000,r5400,r5500,r7000,r8000,r9000,sb1,sr71000"
+ "r3000,4kc,4kp,5kc,5kf,20kc,24kc,24kf,24kx,m4k,r3900,r6000,r4000,r4100,r4111,r4120,r4130,r4300,r4600,r4650,r5000,r5400,r5500,r7000,r8000,r9000,sb1,sb1a,sr71000"
(const (symbol_ref "mips_tune")))
;; The type of hardware hazard associated with this instruction.
;; True if an instruction might assign to hi or lo when reloaded.
;; This is used by the TUNE_MACC_CHAINS code.
(define_attr "may_clobber_hilo" "no,yes"
- (if_then_else (eq_attr "type" "imul,imadd,idiv,mthilo")
+ (if_then_else (eq_attr "type" "imul,imul3,imadd,idiv,mthilo")
(const_string "yes")
(const_string "no")))
;; Describe a user's asm statement.
(define_asm_attributes
- [(set_attr "type" "multi")])
+ [(set_attr "type" "multi")
+ (set_attr "can_delay" "no")])
\f
;; This mode macro allows 32-bit and 64-bit GPR patterns to be generated
;; from the same template.
;; conditional-move-type condition is needed.
(define_mode_macro MOVECC [SI (DI "TARGET_64BIT") (CC "TARGET_HARD_FLOAT")])
+;; This mode macro allows the QI and HI extension patterns to be defined from
+;; the same template.
+(define_mode_macro SHORT [QI HI])
+
;; This mode macro allows :ANYF to be used wherever a scalar or vector
;; floating-point mode is allowed.
(define_mode_macro ANYF [(SF "TARGET_HARD_FLOAT")
;; 32-bit version and "dsubu" in the 64-bit version.
(define_mode_attr d [(SI "") (DI "d")])
+;; This attribute gives the length suffix for a sign- or zero-extension
+;; instruction.
+(define_mode_attr size [(QI "b") (HI "h")])
+
+;; This attributes gives the mode mask of a SHORT.
+(define_mode_attr mask [(QI "0x00ff") (HI "0xffff")])
+
;; Mode attributes for GPR loads and stores.
(define_mode_attr load [(SI "lw") (DI "ld")])
(define_mode_attr store [(SI "sw") (DI "sd")])
;; Similarly for MIPS IV indexed FPR loads and stores.
-(define_mode_attr loadx [(SF "lwxc1") (DF "ldxc1")])
-(define_mode_attr storex [(SF "swxc1") (DF "sdxc1")])
+(define_mode_attr loadx [(SF "lwxc1") (DF "ldxc1") (V2SF "ldxc1")])
+(define_mode_attr storex [(SF "swxc1") (DF "sdxc1") (V2SF "sdxc1")])
;; The unextended ranges of the MIPS16 addiu and daddiu instructions
;; are different. Some forms of unextended addiu have an 8-bit immediate
;; floating-point mode.
(define_mode_attr UNITMODE [(SF "SF") (DF "DF") (V2SF "SF")])
+;; This attribute works around the early SB-1 rev2 core "F2" erratum:
+;;
+;; In certain cases, div.s and div.ps may have a rounding error
+;; and/or wrong inexact flag.
+;;
+;; Therefore, we only allow div.s if not working around SB-1 rev2
+;; errata or if a slight loss of precision is OK.
+(define_mode_attr divide_condition
+ [DF (SF "!TARGET_FIX_SB1 || flag_unsafe_math_optimizations")
+ (V2SF "TARGET_SB1 && (!TARGET_FIX_SB1 || flag_unsafe_math_optimizations)")])
+
+; This attribute gives the condition for which sqrt instructions exist.
+(define_mode_attr sqrt_condition
+ [(SF "!ISA_MIPS1") (DF "!ISA_MIPS1") (V2SF "TARGET_SB1")])
+
+; This attribute gives the condition for which recip and rsqrt instructions
+; exist.
+(define_mode_attr recip_condition
+ [(SF "ISA_HAS_FP4") (DF "ISA_HAS_FP4") (V2SF "TARGET_SB1")])
+
;; This code macro allows all branch instructions to be generated from
;; a single define_expand template.
(define_code_macro any_cond [unordered ordered unlt unge uneq ltgt unle ungt
;; from the same template.
(define_code_macro any_shift [ashift ashiftrt lshiftrt])
+;; This code macro allows all native floating-point comparisons to be
+;; generated from the same template.
+(define_code_macro fcond [unordered uneq unlt unle eq lt le])
+
+;; This code macro is used for comparisons that can be implemented
+;; by swapping the operands.
+(define_code_macro swapped_fcond [ge gt unge ungt])
+
;; <u> expands to an empty string when doing a signed operation and
;; "u" when doing an unsigned operation.
(define_code_attr u [(sign_extend "") (zero_extend "u")])
(define_code_attr insn [(ashift "sll")
(ashiftrt "sra")
(lshiftrt "srl")])
+
+;; <fcond> is the c.cond.fmt condition associated with a particular code.
+(define_code_attr fcond [(unordered "un")
+ (uneq "ueq")
+ (unlt "ult")
+ (unle "ule")
+ (eq "eq")
+ (lt "lt")
+ (le "le")])
+
+;; Similar, but for swapped conditions.
+(define_code_attr swapped_fcond [(ge "le")
+ (gt "lt")
+ (unge "ule")
+ (ungt "ult")])
\f
;; .........................
;;
(define_cpu_unit "alu" "alu")
(define_cpu_unit "imuldiv" "imuldiv")
+(include "4k.md")
+(include "5k.md")
+(include "24k.md")
(include "3000.md")
(include "4000.md")
(include "4100.md")
(plus:SI (match_dup 0)
(match_operand:SI 1 "const_int_operand")))]
"TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
- && GET_CODE (operands[0]) == REG
+ && REG_P (operands[0])
&& M16_REG_P (REGNO (operands[0]))
&& GET_CODE (operands[1]) == CONST_INT
&& ((INTVAL (operands[1]) > 0x7f
(plus:SI (match_operand:SI 1 "register_operand")
(match_operand:SI 2 "const_int_operand")))]
"TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
- && GET_CODE (operands[0]) == REG
+ && REG_P (operands[0])
&& M16_REG_P (REGNO (operands[0]))
- && GET_CODE (operands[1]) == REG
+ && REG_P (operands[1])
&& M16_REG_P (REGNO (operands[1]))
&& REGNO (operands[0]) != REGNO (operands[1])
&& GET_CODE (operands[2]) == CONST_INT
(plus:DI (match_dup 0)
(match_operand:DI 1 "const_int_operand")))]
"TARGET_MIPS16 && TARGET_64BIT && reload_completed && !TARGET_DEBUG_D_MODE
- && GET_CODE (operands[0]) == REG
+ && REG_P (operands[0])
&& M16_REG_P (REGNO (operands[0]))
&& GET_CODE (operands[1]) == CONST_INT
&& ((INTVAL (operands[1]) > 0xf
(plus:DI (match_operand:DI 1 "register_operand")
(match_operand:DI 2 "const_int_operand")))]
"TARGET_MIPS16 && TARGET_64BIT && reload_completed && !TARGET_DEBUG_D_MODE
- && GET_CODE (operands[0]) == REG
+ && REG_P (operands[0])
&& M16_REG_P (REGNO (operands[0]))
- && GET_CODE (operands[1]) == REG
+ && REG_P (operands[1])
&& M16_REG_P (REGNO (operands[1]))
&& REGNO (operands[0]) != REGNO (operands[1])
&& GET_CODE (operands[2]) == CONST_INT
;; These processors have PRId values of 0x00004220 and 0x00004300,
;; respectively.
-(define_expand "mul<mode>3"
- [(set (match_operand:GPR 0 "register_operand")
- (mult:GPR (match_operand:GPR 1 "register_operand")
- (match_operand:GPR 2 "register_operand")))]
+(define_expand "mulsi3"
+ [(set (match_operand:SI 0 "register_operand")
+ (mult:SI (match_operand:SI 1 "register_operand")
+ (match_operand:SI 2 "register_operand")))]
""
{
- if (GENERATE_MULT3_<MODE>)
- emit_insn (gen_mul<mode>3_mult3 (operands[0], operands[1], operands[2]));
- else if (!TARGET_FIX_R4000)
- emit_insn (gen_mul<mode>3_internal (operands[0], operands[1],
- operands[2]));
+ if (ISA_HAS_MUL3)
+ emit_insn (gen_mulsi3_mult3 (operands[0], operands[1], operands[2]));
+ else if (TARGET_FIX_R4000)
+ emit_insn (gen_mulsi3_r4000 (operands[0], operands[1], operands[2]));
else
- emit_insn (gen_mul<mode>3_r4000 (operands[0], operands[1], operands[2]));
+ emit_insn (gen_mulsi3_internal (operands[0], operands[1], operands[2]));
+ DONE;
+})
+
+(define_expand "muldi3"
+ [(set (match_operand:DI 0 "register_operand")
+ (mult:DI (match_operand:DI 1 "register_operand")
+ (match_operand:DI 2 "register_operand")))]
+ "TARGET_64BIT"
+{
+ if (TARGET_FIX_R4000)
+ emit_insn (gen_muldi3_r4000 (operands[0], operands[1], operands[2]));
+ else
+ emit_insn (gen_muldi3_internal (operands[0], operands[1], operands[2]));
DONE;
})
(match_operand:SI 2 "register_operand" "d,d")))
(clobber (match_scratch:SI 3 "=h,h"))
(clobber (match_scratch:SI 4 "=l,X"))]
- "GENERATE_MULT3_SI"
+ "ISA_HAS_MUL3"
{
if (which_alternative == 1)
return "mult\t%1,%2";
- if (TARGET_MAD
- || TARGET_MIPS5400
- || TARGET_MIPS5500
- || TARGET_MIPS7000
- || TARGET_MIPS9000
- || ISA_MIPS32
- || ISA_MIPS32R2
- || ISA_MIPS64)
- return "mul\t%0,%1,%2";
- return "mult\t%0,%1,%2";
+ if (TARGET_MIPS3900)
+ return "mult\t%0,%1,%2";
+ return "mul\t%0,%1,%2";
}
- [(set_attr "type" "imul")
+ [(set_attr "type" "imul3,imul")
(set_attr "mode" "SI")])
-(define_insn "muldi3_mult3"
- [(set (match_operand:DI 0 "register_operand" "=d")
- (mult:DI (match_operand:DI 1 "register_operand" "d")
- (match_operand:DI 2 "register_operand" "d")))
- (clobber (match_scratch:DI 3 "=h"))
- (clobber (match_scratch:DI 4 "=l"))]
- "TARGET_64BIT && GENERATE_MULT3_DI"
- "dmult\t%0,%1,%2"
- [(set_attr "type" "imul")
- (set_attr "mode" "DI")])
-
;; If a register gets allocated to LO, and we spill to memory, the reload
;; will include a move from LO to a GPR. Merge it into the multiplication
;; if it can set the GPR directly.
(clobber (scratch:SI))])
(set (match_operand:SI 4 "register_operand")
(unspec [(match_dup 0) (match_dup 3)] UNSPEC_MFHILO))]
- "GENERATE_MULT3_SI && peep2_reg_dead_p (2, operands[0])"
+ "ISA_HAS_MUL3 && peep2_reg_dead_p (2, operands[0])"
[(parallel
[(set (match_dup 4)
(mult:SI (match_dup 1)
(clobber (match_operand:SI 3 "register_operand"))])
(set (match_operand:SI 4 "register_operand")
(unspec:SI [(match_dup 0) (match_dup 3)] UNSPEC_MFHILO))]
- "ISA_HAS_MACC && !GENERATE_MULT3_SI"
+ "ISA_HAS_MACC && !ISA_HAS_MUL3"
[(set (match_dup 0)
(const_int 0))
(parallel
(match_operand:SI 4 "macc_msac_operand"))
(clobber (match_operand:SI 5 "register_operand"))
(clobber (match_dup 1))])]
- "GENERATE_MULT3_SI
+ "ISA_HAS_MUL3
&& true_regnum (operands[1]) == LO_REGNUM
&& peep2_reg_dead_p (2, operands[1])
&& GP_REG_P (true_regnum (operands[3]))"
(match_dup 0)
(set (match_operand:SI 5 "register_operand")
(unspec:SI [(match_dup 1) (match_dup 4)] UNSPEC_MFHILO))]
- "GENERATE_MULT3_SI && peep2_reg_dead_p (3, operands[1])"
+ "ISA_HAS_MUL3 && peep2_reg_dead_p (3, operands[1])"
[(parallel [(set (match_dup 0)
(match_dup 6))
(clobber (match_dup 4))
"@
muls\t$0,%1,%2
muls\t%0,%1,%2"
- [(set_attr "type" "imul")
+ [(set_attr "type" "imul,imul3")
(set_attr "mode" "SI")])
;; ??? We could define a mulditi3 pattern when TARGET_64BIT.
[(set (match_operand:DI 0 "register_operand" "=x")
(mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
(any_extend:DI (match_operand:SI 2 "register_operand" "d"))))]
- "!TARGET_64BIT && !TARGET_FIX_R4000"
+ "!TARGET_64BIT && !TARGET_FIX_R4000 && !TARGET_DSPR2"
"mult<u>\t%1,%2"
[(set_attr "type" "imul")
(set_attr "mode" "SI")])
(any_extend:DI (match_operand:SI 2 "register_operand" "d"))))
(clobber (match_scratch:DI 3 "=x"))]
"!TARGET_64BIT && TARGET_FIX_R4000"
- "mult\t%1,%2\;mflo\t%L0;mfhi\t%M0"
+ "mult<u>\t%1,%2\;mflo\t%L0;mfhi\t%M0"
[(set_attr "type" "imul")
(set_attr "mode" "SI")
(set_attr "length" "12")])
"@
mult<u>\t%1,%2
mulhi<u>\t%0,%1,%2"
- [(set_attr "type" "imul")
+ [(set_attr "type" "imul,imul3")
(set_attr "mode" "SI")])
(define_insn "*<su>mulsi3_highpart_neg_mulhi_internal"
"@
mulshi<u>\t%.,%1,%2
mulshi<u>\t%0,%1,%2"
- [(set_attr "type" "imul")
+ [(set_attr "type" "imul,imul3")
(set_attr "mode" "SI")])
;; Disable unsigned multiplication for -mfix-vr4120. This is for VR4120
[(set_attr "type" "imul")
(set_attr "mode" "DI")])
-;; The R4650 supports a 32 bit multiply/ 64 bit accumulate
-;; instruction. The HI/LO registers are used as a 64 bit accumulator.
+;; The R4650 supports a 32-bit multiply/ 64-bit accumulate
+;; instruction. The HI/LO registers are used as a 64-bit accumulator.
(define_insn "madsi"
[(set (match_operand:SI 0 "register_operand" "+l")
(match_operand:ANYF 2 "register_operand" "f"))
(match_operand:ANYF 3 "register_operand" "f"))))]
"ISA_HAS_NMADD_NMSUB && TARGET_FUSED_MADD
- && HONOR_SIGNED_ZEROS (<MODE>mode)"
+ && HONOR_SIGNED_ZEROS (<MODE>mode)
+ && !HONOR_NANS (<MODE>mode)"
"nmadd.<fmt>\t%0,%3,%1,%2"
[(set_attr "type" "fmadd")
(set_attr "mode" "<UNITMODE>")])
(match_operand:ANYF 2 "register_operand" "f"))
(match_operand:ANYF 3 "register_operand" "f")))]
"ISA_HAS_NMADD_NMSUB && TARGET_FUSED_MADD
- && !HONOR_SIGNED_ZEROS (<MODE>mode)"
+ && !HONOR_SIGNED_ZEROS (<MODE>mode)
+ && !HONOR_NANS (<MODE>mode)"
"nmadd.<fmt>\t%0,%3,%1,%2"
[(set_attr "type" "fmadd")
(set_attr "mode" "<UNITMODE>")])
(match_operand:ANYF 3 "register_operand" "f"))
(match_operand:ANYF 1 "register_operand" "f"))))]
"ISA_HAS_NMADD_NMSUB && TARGET_FUSED_MADD
- && HONOR_SIGNED_ZEROS (<MODE>mode)"
+ && HONOR_SIGNED_ZEROS (<MODE>mode)
+ && !HONOR_NANS (<MODE>mode)"
"nmsub.<fmt>\t%0,%1,%2,%3"
[(set_attr "type" "fmadd")
(set_attr "mode" "<UNITMODE>")])
(mult:ANYF (match_operand:ANYF 2 "register_operand" "f")
(match_operand:ANYF 3 "register_operand" "f"))))]
"ISA_HAS_NMADD_NMSUB && TARGET_FUSED_MADD
- && !HONOR_SIGNED_ZEROS (<MODE>mode)"
+ && !HONOR_SIGNED_ZEROS (<MODE>mode)
+ && !HONOR_NANS (<MODE>mode)"
"nmsub.<fmt>\t%0,%1,%2,%3"
[(set_attr "type" "fmadd")
(set_attr "mode" "<UNITMODE>")])
;; ....................
;;
-(define_expand "divdf3"
- [(set (match_operand:DF 0 "register_operand")
- (div:DF (match_operand:DF 1 "reg_or_1_operand")
- (match_operand:DF 2 "register_operand")))]
- "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
+(define_expand "div<mode>3"
+ [(set (match_operand:ANYF 0 "register_operand")
+ (div:ANYF (match_operand:ANYF 1 "reg_or_1_operand")
+ (match_operand:ANYF 2 "register_operand")))]
+ "<divide_condition>"
{
- if (const_1_operand (operands[1], DFmode))
+ if (const_1_operand (operands[1], <MODE>mode))
if (!(ISA_HAS_FP4 && flag_unsafe_math_optimizations))
- operands[1] = force_reg (DFmode, operands[1]);
+ operands[1] = force_reg (<MODE>mode, operands[1]);
})
-;; This pattern works around the early SB-1 rev2 core "F1" erratum:
+;; These patterns work around the early SB-1 rev2 core "F1" erratum:
;;
;; If an mfc1 or dmfc1 happens to access the floating point register
;; file at the same time a long latency operation (div, sqrt, recip,
;; The workaround is to insert an unconditional 'mov' from/to the
;; long latency op destination register.
-(define_insn "*divdf3"
- [(set (match_operand:DF 0 "register_operand" "=f")
- (div:DF (match_operand:DF 1 "register_operand" "f")
- (match_operand:DF 2 "register_operand" "f")))]
- "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
-{
- if (TARGET_FIX_SB1)
- return "div.d\t%0,%1,%2\;mov.d\t%0,%0";
- else
- return "div.d\t%0,%1,%2";
-}
- [(set_attr "type" "fdiv")
- (set_attr "mode" "DF")
- (set (attr "length")
- (if_then_else (ne (symbol_ref "TARGET_FIX_SB1") (const_int 0))
- (const_int 8)
- (const_int 4)))])
-
-
-;; This pattern works around the early SB-1 rev2 core "F2" erratum:
-;;
-;; In certain cases, div.s and div.ps may have a rounding error
-;; and/or wrong inexact flag.
-;;
-;; Therefore, we only allow div.s if not working around SB-1 rev2
-;; errata, or if working around those errata and a slight loss of
-;; precision is OK (i.e., flag_unsafe_math_optimizations is set).
-(define_expand "divsf3"
- [(set (match_operand:SF 0 "register_operand")
- (div:SF (match_operand:SF 1 "reg_or_1_operand")
- (match_operand:SF 2 "register_operand")))]
- "TARGET_HARD_FLOAT && (!TARGET_FIX_SB1 || flag_unsafe_math_optimizations)"
-{
- if (const_1_operand (operands[1], SFmode))
- if (!(ISA_HAS_FP4 && flag_unsafe_math_optimizations))
- operands[1] = force_reg (SFmode, operands[1]);
-})
-
-;; This pattern works around the early SB-1 rev2 core "F1" erratum (see
-;; "divdf3" comment for details).
-;;
-;; This pattern works around the early SB-1 rev2 core "F2" erratum (see
-;; "divsf3" comment for details).
-(define_insn "*divsf3"
- [(set (match_operand:SF 0 "register_operand" "=f")
- (div:SF (match_operand:SF 1 "register_operand" "f")
- (match_operand:SF 2 "register_operand" "f")))]
- "TARGET_HARD_FLOAT && (!TARGET_FIX_SB1 || flag_unsafe_math_optimizations)"
-{
- if (TARGET_FIX_SB1)
- return "div.s\t%0,%1,%2\;mov.s\t%0,%0";
- else
- return "div.s\t%0,%1,%2";
-}
- [(set_attr "type" "fdiv")
- (set_attr "mode" "SF")
- (set (attr "length")
- (if_then_else (ne (symbol_ref "TARGET_FIX_SB1") (const_int 0))
- (const_int 8)
- (const_int 4)))])
-
-;; This pattern works around the early SB-1 rev2 core "F1" erratum (see
-;; "divdf3" comment for details).
-(define_insn ""
- [(set (match_operand:DF 0 "register_operand" "=f")
- (div:DF (match_operand:DF 1 "const_1_operand" "")
- (match_operand:DF 2 "register_operand" "f")))]
- "ISA_HAS_FP4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && flag_unsafe_math_optimizations"
+(define_insn "*div<mode>3"
+ [(set (match_operand:ANYF 0 "register_operand" "=f")
+ (div:ANYF (match_operand:ANYF 1 "register_operand" "f")
+ (match_operand:ANYF 2 "register_operand" "f")))]
+ "<divide_condition>"
{
if (TARGET_FIX_SB1)
- return "recip.d\t%0,%2\;mov.d\t%0,%0";
+ return "div.<fmt>\t%0,%1,%2\;mov.<fmt>\t%0,%0";
else
- return "recip.d\t%0,%2";
+ return "div.<fmt>\t%0,%1,%2";
}
- [(set_attr "type" "frdiv")
- (set_attr "mode" "DF")
+ [(set_attr "type" "fdiv")
+ (set_attr "mode" "<UNITMODE>")
(set (attr "length")
(if_then_else (ne (symbol_ref "TARGET_FIX_SB1") (const_int 0))
(const_int 8)
(const_int 4)))])
-;; This pattern works around the early SB-1 rev2 core "F1" erratum (see
-;; "divdf3" comment for details).
-(define_insn ""
- [(set (match_operand:SF 0 "register_operand" "=f")
- (div:SF (match_operand:SF 1 "const_1_operand" "")
- (match_operand:SF 2 "register_operand" "f")))]
- "ISA_HAS_FP4 && TARGET_HARD_FLOAT && flag_unsafe_math_optimizations"
+(define_insn "*recip<mode>3"
+ [(set (match_operand:ANYF 0 "register_operand" "=f")
+ (div:ANYF (match_operand:ANYF 1 "const_1_operand" "")
+ (match_operand:ANYF 2 "register_operand" "f")))]
+ "<recip_condition> && flag_unsafe_math_optimizations"
{
if (TARGET_FIX_SB1)
- return "recip.s\t%0,%2\;mov.s\t%0,%0";
+ return "recip.<fmt>\t%0,%2\;mov.<fmt>\t%0,%0";
else
- return "recip.s\t%0,%2";
+ return "recip.<fmt>\t%0,%2";
}
- [(set_attr "type" "frdiv")
- (set_attr "mode" "SF")
+ [(set_attr "type" "frdiv")
+ (set_attr "mode" "<UNITMODE>")
(set (attr "length")
(if_then_else (ne (symbol_ref "TARGET_FIX_SB1") (const_int 0))
(const_int 8)
;;
;; ....................
-;; This pattern works around the early SB-1 rev2 core "F1" erratum (see
-;; "divdf3" comment for details).
-(define_insn "sqrtdf2"
- [(set (match_operand:DF 0 "register_operand" "=f")
- (sqrt:DF (match_operand:DF 1 "register_operand" "f")))]
- "TARGET_HARD_FLOAT && HAVE_SQRT_P() && TARGET_DOUBLE_FLOAT"
-{
- if (TARGET_FIX_SB1)
- return "sqrt.d\t%0,%1\;mov.d\t%0,%0";
- else
- return "sqrt.d\t%0,%1";
-}
- [(set_attr "type" "fsqrt")
- (set_attr "mode" "DF")
- (set (attr "length")
- (if_then_else (ne (symbol_ref "TARGET_FIX_SB1") (const_int 0))
- (const_int 8)
- (const_int 4)))])
-
-;; This pattern works around the early SB-1 rev2 core "F1" erratum (see
-;; "divdf3" comment for details).
-(define_insn "sqrtsf2"
- [(set (match_operand:SF 0 "register_operand" "=f")
- (sqrt:SF (match_operand:SF 1 "register_operand" "f")))]
- "TARGET_HARD_FLOAT && HAVE_SQRT_P()"
-{
- if (TARGET_FIX_SB1)
- return "sqrt.s\t%0,%1\;mov.s\t%0,%0";
- else
- return "sqrt.s\t%0,%1";
-}
- [(set_attr "type" "fsqrt")
- (set_attr "mode" "SF")
- (set (attr "length")
- (if_then_else (ne (symbol_ref "TARGET_FIX_SB1") (const_int 0))
- (const_int 8)
- (const_int 4)))])
-
-;; This pattern works around the early SB-1 rev2 core "F1" erratum (see
-;; "divdf3" comment for details).
-(define_insn ""
- [(set (match_operand:DF 0 "register_operand" "=f")
- (div:DF (match_operand:DF 1 "const_1_operand" "")
- (sqrt:DF (match_operand:DF 2 "register_operand" "f"))))]
- "ISA_HAS_FP4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && flag_unsafe_math_optimizations"
-{
- if (TARGET_FIX_SB1)
- return "rsqrt.d\t%0,%2\;mov.d\t%0,%0";
- else
- return "rsqrt.d\t%0,%2";
-}
- [(set_attr "type" "frsqrt")
- (set_attr "mode" "DF")
- (set (attr "length")
- (if_then_else (ne (symbol_ref "TARGET_FIX_SB1") (const_int 0))
- (const_int 8)
- (const_int 4)))])
+;; These patterns work around the early SB-1 rev2 core "F1" erratum (see
+;; "*div[sd]f3" comment for details).
-;; This pattern works around the early SB-1 rev2 core "F1" erratum (see
-;; "divdf3" comment for details).
-(define_insn ""
- [(set (match_operand:SF 0 "register_operand" "=f")
- (div:SF (match_operand:SF 1 "const_1_operand" "")
- (sqrt:SF (match_operand:SF 2 "register_operand" "f"))))]
- "ISA_HAS_FP4 && TARGET_HARD_FLOAT && flag_unsafe_math_optimizations"
+(define_insn "sqrt<mode>2"
+ [(set (match_operand:ANYF 0 "register_operand" "=f")
+ (sqrt:ANYF (match_operand:ANYF 1 "register_operand" "f")))]
+ "<sqrt_condition>"
{
if (TARGET_FIX_SB1)
- return "rsqrt.s\t%0,%2\;mov.s\t%0,%0";
+ return "sqrt.<fmt>\t%0,%1\;mov.<fmt>\t%0,%0";
else
- return "rsqrt.s\t%0,%2";
+ return "sqrt.<fmt>\t%0,%1";
}
- [(set_attr "type" "frsqrt")
- (set_attr "mode" "SF")
+ [(set_attr "type" "fsqrt")
+ (set_attr "mode" "<UNITMODE>")
(set (attr "length")
(if_then_else (ne (symbol_ref "TARGET_FIX_SB1") (const_int 0))
(const_int 8)
(const_int 4)))])
-;; This pattern works around the early SB-1 rev2 core "F1" erratum (see
-;; "divdf3" comment for details).
-(define_insn ""
- [(set (match_operand:DF 0 "register_operand" "=f")
- (sqrt:DF (div:DF (match_operand:DF 1 "const_1_operand" "")
- (match_operand:DF 2 "register_operand" "f"))))]
- "ISA_HAS_FP4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && flag_unsafe_math_optimizations"
+(define_insn "*rsqrt<mode>a"
+ [(set (match_operand:ANYF 0 "register_operand" "=f")
+ (div:ANYF (match_operand:ANYF 1 "const_1_operand" "")
+ (sqrt:ANYF (match_operand:ANYF 2 "register_operand" "f"))))]
+ "<recip_condition> && flag_unsafe_math_optimizations"
{
if (TARGET_FIX_SB1)
- return "rsqrt.d\t%0,%2\;mov.d\t%0,%0";
+ return "rsqrt.<fmt>\t%0,%2\;mov.<fmt>\t%0,%0";
else
- return "rsqrt.d\t%0,%2";
+ return "rsqrt.<fmt>\t%0,%2";
}
- [(set_attr "type" "frsqrt")
- (set_attr "mode" "DF")
+ [(set_attr "type" "frsqrt")
+ (set_attr "mode" "<UNITMODE>")
(set (attr "length")
(if_then_else (ne (symbol_ref "TARGET_FIX_SB1") (const_int 0))
(const_int 8)
(const_int 4)))])
-;; This pattern works around the early SB-1 rev2 core "F1" erratum (see
-;; "divdf3" comment for details).
-(define_insn ""
- [(set (match_operand:SF 0 "register_operand" "=f")
- (sqrt:SF (div:SF (match_operand:SF 1 "const_1_operand" "")
- (match_operand:SF 2 "register_operand" "f"))))]
- "ISA_HAS_FP4 && TARGET_HARD_FLOAT && flag_unsafe_math_optimizations"
+(define_insn "*rsqrt<mode>b"
+ [(set (match_operand:ANYF 0 "register_operand" "=f")
+ (sqrt:ANYF (div:ANYF (match_operand:ANYF 1 "const_1_operand" "")
+ (match_operand:ANYF 2 "register_operand" "f"))))]
+ "<recip_condition> && flag_unsafe_math_optimizations"
{
if (TARGET_FIX_SB1)
- return "rsqrt.s\t%0,%2\;mov.s\t%0,%0";
+ return "rsqrt.<fmt>\t%0,%2\;mov.<fmt>\t%0,%0";
else
- return "rsqrt.s\t%0,%2";
+ return "rsqrt.<fmt>\t%0,%2";
}
- [(set_attr "type" "frsqrt")
- (set_attr "mode" "SF")
+ [(set_attr "type" "frsqrt")
+ (set_attr "mode" "<UNITMODE>")
(set (attr "length")
(if_then_else (ne (symbol_ref "TARGET_FIX_SB1") (const_int 0))
(const_int 8)
;; Do not use the integer abs macro instruction, since that signals an
;; exception on -2147483648 (sigh).
-(define_insn "abs<mode>2"
- [(set (match_operand:GPR 0 "register_operand" "=d")
- (abs:GPR (match_operand:GPR 1 "register_operand" "d")))]
- "!TARGET_MIPS16"
-{
- if (REGNO (operands[0]) == REGNO (operands[1]) && GENERATE_BRANCHLIKELY)
- return "%(bltzl\t%1,1f\;<d>subu\t%0,%.,%0\n%~1:%)";
- else
- return "%(bgez\t%1,1f\;move\t%0,%1\;<d>subu\t%0,%.,%0\n%~1:%)";
-}
- [(set_attr "type" "multi")
- (set_attr "mode" "<MODE>")
- (set_attr "length" "12")])
+;; abs.fmt is an arithmetic instruction and treats all NaN inputs as
+;; invalid; it does not clear their sign bits. We therefore can't use
+;; abs.fmt if the signs of NaNs matter.
(define_insn "abs<mode>2"
[(set (match_operand:ANYF 0 "register_operand" "=f")
(abs:ANYF (match_operand:ANYF 1 "register_operand" "f")))]
- ""
+ "!HONOR_NANS (<MODE>mode)"
"abs.<fmt>\t%0,%1"
[(set_attr "type" "fabs")
(set_attr "mode" "<UNITMODE>")])
\f
;;
-;; ....................
-;;
-;; FIND FIRST BIT INSTRUCTION
-;;
-;; ....................
-;;
-
-(define_insn "ffs<mode>2"
- [(set (match_operand:GPR 0 "register_operand" "=&d")
- (ffs:GPR (match_operand:GPR 1 "register_operand" "d")))
- (clobber (match_scratch:GPR 2 "=&d"))
- (clobber (match_scratch:GPR 3 "=&d"))]
- "!TARGET_MIPS16"
-{
- if (optimize && find_reg_note (insn, REG_DEAD, operands[1]))
- return "%(\
-move\t%0,%.\;\
-beq\t%1,%.,2f\n\
-%~1:\tand\t%2,%1,0x0001\;\
-<d>addu\t%0,%0,1\;\
-beq\t%2,%.,1b\;\
-<d>srl\t%1,%1,1\n\
-%~2:%)";
-
- return "%(\
-move\t%0,%.\;\
-move\t%3,%1\;\
-beq\t%3,%.,2f\n\
-%~1:\tand\t%2,%3,0x0001\;\
-<d>addu\t%0,%0,1\;\
-beq\t%2,%.,1b\;\
-<d>srl\t%3,%3,1\n\
-%~2:%)";
-}
- [(set_attr "type" "multi")
- (set_attr "mode" "<MODE>")
- (set_attr "length" "28")])
-\f
-;;
;; ...................
;;
;; Count leading zeroes.
[(set_attr "type" "arith")
(set_attr "mode" "DI")])
+;; neg.fmt is an arithmetic instruction and treats all NaN inputs as
+;; invalid; it does not flip their sign bit. We therefore can't use
+;; neg.fmt if the signs of NaNs matter.
+
(define_insn "neg<mode>2"
[(set (match_operand:ANYF 0 "register_operand" "=f")
(neg:ANYF (match_operand:ANYF 1 "register_operand" "f")))]
- ""
+ "!HONOR_NANS (<MODE>mode)"
"neg.<fmt>\t%0,%1"
[(set_attr "type" "fneg")
(set_attr "mode" "<UNITMODE>")])
"TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
"cvt.s.d\t%0,%1"
[(set_attr "type" "fcvt")
+ (set_attr "cnv_mode" "D2S")
(set_attr "mode" "SF")])
;; Integer truncation patterns. Truncating SImode values to smaller
;; ....................
;; Extension insns.
-;; Those for integer source operand are ordered widest source type first.
(define_insn_and_split "zero_extendsidi2"
- [(set (match_operand:DI 0 "register_operand" "=d")
- (zero_extend:DI (match_operand:SI 1 "register_operand" "d")))]
+ [(set (match_operand:DI 0 "register_operand" "=d,d")
+ (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,W")))]
"TARGET_64BIT"
- "#"
- "&& reload_completed"
+ "@
+ #
+ lwu\t%0,%1"
+ "&& reload_completed && REG_P (operands[1])"
[(set (match_dup 0)
(ashift:DI (match_dup 1) (const_int 32)))
(set (match_dup 0)
(lshiftrt:DI (match_dup 0) (const_int 32)))]
- "operands[1] = gen_lowpart (DImode, operands[1]);"
- [(set_attr "type" "multi")
+ { operands[1] = gen_lowpart (DImode, operands[1]); }
+ [(set_attr "type" "multi,load")
(set_attr "mode" "DI")
- (set_attr "length" "8")])
+ (set_attr "length" "8,*")])
-(define_insn "*zero_extendsidi2_mem"
- [(set (match_operand:DI 0 "register_operand" "=d")
- (zero_extend:DI (match_operand:SI 1 "memory_operand" "W")))]
+;; Combine is not allowed to convert this insn into a zero_extendsidi2
+;; because of TRULY_NOOP_TRUNCATION.
+
+(define_insn_and_split "*clear_upper32"
+ [(set (match_operand:DI 0 "register_operand" "=d,d")
+ (and:DI (match_operand:DI 1 "nonimmediate_operand" "d,o")
+ (const_int 4294967295)))]
"TARGET_64BIT"
- "lwu\t%0,%1"
- [(set_attr "type" "load")
- (set_attr "mode" "DI")])
+{
+ if (which_alternative == 0)
+ return "#";
-(define_expand "zero_extendhisi2"
- [(set (match_operand:SI 0 "register_operand")
- (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand")))]
+ operands[1] = gen_lowpart (SImode, operands[1]);
+ return "lwu\t%0,%1";
+}
+ "&& reload_completed && REG_P (operands[1])"
+ [(set (match_dup 0)
+ (ashift:DI (match_dup 1) (const_int 32)))
+ (set (match_dup 0)
+ (lshiftrt:DI (match_dup 0) (const_int 32)))]
+ ""
+ [(set_attr "type" "multi,load")
+ (set_attr "mode" "DI")
+ (set_attr "length" "8,*")])
+
+(define_expand "zero_extend<SHORT:mode><GPR:mode>2"
+ [(set (match_operand:GPR 0 "register_operand")
+ (zero_extend:GPR (match_operand:SHORT 1 "nonimmediate_operand")))]
""
{
- if (TARGET_MIPS16 && GET_CODE (operands[1]) != MEM)
+ if (TARGET_MIPS16 && !GENERATE_MIPS16E
+ && !memory_operand (operands[1], <SHORT:MODE>mode))
{
- rtx op = gen_lowpart (SImode, operands[1]);
- rtx temp = force_reg (SImode, GEN_INT (0xffff));
-
- emit_insn (gen_andsi3 (operands[0], op, temp));
+ emit_insn (gen_and<GPR:mode>3 (operands[0],
+ gen_lowpart (<GPR:MODE>mode, operands[1]),
+ force_reg (<GPR:MODE>mode,
+ GEN_INT (<SHORT:mask>))));
DONE;
}
})
-(define_insn ""
- [(set (match_operand:SI 0 "register_operand" "=d,d")
- (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "d,m")))]
+(define_insn "*zero_extend<SHORT:mode><GPR:mode>2"
+ [(set (match_operand:GPR 0 "register_operand" "=d,d")
+ (zero_extend:GPR
+ (match_operand:SHORT 1 "nonimmediate_operand" "d,m")))]
"!TARGET_MIPS16"
"@
- andi\t%0,%1,0xffff
- lhu\t%0,%1"
- [(set_attr "type" "arith,load")
- (set_attr "mode" "SI")
- (set_attr "length" "4,*")])
-
-(define_insn ""
- [(set (match_operand:SI 0 "register_operand" "=d")
- (zero_extend:SI (match_operand:HI 1 "memory_operand" "m")))]
- "TARGET_MIPS16"
- "lhu\t%0,%1"
- [(set_attr "type" "load")
- (set_attr "mode" "SI")])
-
-(define_expand "zero_extendhidi2"
- [(set (match_operand:DI 0 "register_operand")
- (zero_extend:DI (match_operand:HI 1 "nonimmediate_operand")))]
- "TARGET_64BIT"
-{
- if (TARGET_MIPS16 && GET_CODE (operands[1]) != MEM)
- {
- rtx op = gen_lowpart (DImode, operands[1]);
- rtx temp = force_reg (DImode, GEN_INT (0xffff));
-
- emit_insn (gen_anddi3 (operands[0], op, temp));
- DONE;
- }
-})
+ andi\t%0,%1,<SHORT:mask>
+ l<SHORT:size>u\t%0,%1"
+ [(set_attr "type" "arith,load")
+ (set_attr "mode" "<GPR:MODE>")])
-(define_insn ""
- [(set (match_operand:DI 0 "register_operand" "=d,d")
- (zero_extend:DI (match_operand:HI 1 "nonimmediate_operand" "d,m")))]
- "TARGET_64BIT && !TARGET_MIPS16"
- "@
- andi\t%0,%1,0xffff
- lhu\t%0,%1"
- [(set_attr "type" "arith,load")
- (set_attr "mode" "DI")
- (set_attr "length" "4,*")])
+(define_insn "*zero_extend<SHORT:mode><GPR:mode>2_mips16e"
+ [(set (match_operand:GPR 0 "register_operand" "=d")
+ (zero_extend:GPR (match_operand:SHORT 1 "register_operand" "0")))]
+ "GENERATE_MIPS16E"
+ "ze<SHORT:size>\t%0"
+ [(set_attr "type" "arith")
+ (set_attr "mode" "<GPR:MODE>")])
-(define_insn ""
- [(set (match_operand:DI 0 "register_operand" "=d")
- (zero_extend:DI (match_operand:HI 1 "memory_operand" "m")))]
- "TARGET_64BIT && TARGET_MIPS16"
- "lhu\t%0,%1"
- [(set_attr "type" "load")
- (set_attr "mode" "DI")])
+(define_insn "*zero_extend<SHORT:mode><GPR:mode>2_mips16"
+ [(set (match_operand:GPR 0 "register_operand" "=d")
+ (zero_extend:GPR (match_operand:SHORT 1 "memory_operand" "m")))]
+ "TARGET_MIPS16"
+ "l<SHORT:size>u\t%0,%1"
+ [(set_attr "type" "load")
+ (set_attr "mode" "<GPR:MODE>")])
(define_expand "zero_extendqihi2"
[(set (match_operand:HI 0 "register_operand")
(zero_extend:HI (match_operand:QI 1 "nonimmediate_operand")))]
""
{
- if (TARGET_MIPS16 && GET_CODE (operands[1]) != MEM)
+ if (TARGET_MIPS16 && !memory_operand (operands[1], QImode))
{
- rtx op0 = gen_lowpart (SImode, operands[0]);
- rtx op1 = gen_lowpart (SImode, operands[1]);
- rtx temp = force_reg (SImode, GEN_INT (0xff));
-
- emit_insn (gen_andsi3 (op0, op1, temp));
+ emit_insn (gen_zero_extendqisi2 (gen_lowpart (SImode, operands[0]),
+ operands[1]));
DONE;
}
})
-(define_insn ""
+(define_insn "*zero_extendqihi2"
[(set (match_operand:HI 0 "register_operand" "=d,d")
(zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "d,m")))]
"!TARGET_MIPS16"
"@
andi\t%0,%1,0x00ff
lbu\t%0,%1"
- [(set_attr "type" "arith,load")
- (set_attr "mode" "HI")
- (set_attr "length" "4,*")])
+ [(set_attr "type" "arith,load")
+ (set_attr "mode" "HI")])
-(define_insn ""
+(define_insn "*zero_extendqihi2_mips16"
[(set (match_operand:HI 0 "register_operand" "=d")
(zero_extend:HI (match_operand:QI 1 "memory_operand" "m")))]
"TARGET_MIPS16"
"lbu\t%0,%1"
- [(set_attr "type" "load")
- (set_attr "mode" "HI")])
-
-(define_expand "zero_extendqisi2"
- [(set (match_operand:SI 0 "register_operand")
- (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand")))]
- ""
-{
- if (TARGET_MIPS16 && GET_CODE (operands[1]) != MEM)
- {
- rtx op = gen_lowpart (SImode, operands[1]);
- rtx temp = force_reg (SImode, GEN_INT (0xff));
-
- emit_insn (gen_andsi3 (operands[0], op, temp));
- DONE;
- }
-})
-
-(define_insn ""
- [(set (match_operand:SI 0 "register_operand" "=d,d")
- (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "d,m")))]
- "!TARGET_MIPS16"
- "@
- andi\t%0,%1,0x00ff
- lbu\t%0,%1"
- [(set_attr "type" "arith,load")
- (set_attr "mode" "SI")
- (set_attr "length" "4,*")])
-
-(define_insn ""
- [(set (match_operand:SI 0 "register_operand" "=d")
- (zero_extend:SI (match_operand:QI 1 "memory_operand" "m")))]
- "TARGET_MIPS16"
- "lbu\t%0,%1"
- [(set_attr "type" "load")
- (set_attr "mode" "SI")])
-
-(define_expand "zero_extendqidi2"
- [(set (match_operand:DI 0 "register_operand")
- (zero_extend:DI (match_operand:QI 1 "nonimmediate_operand")))]
- "TARGET_64BIT"
-{
- if (TARGET_MIPS16 && GET_CODE (operands[1]) != MEM)
- {
- rtx op = gen_lowpart (DImode, operands[1]);
- rtx temp = force_reg (DImode, GEN_INT (0xff));
-
- emit_insn (gen_anddi3 (operands[0], op, temp));
- DONE;
- }
-})
-
-(define_insn ""
- [(set (match_operand:DI 0 "register_operand" "=d,d")
- (zero_extend:DI (match_operand:QI 1 "nonimmediate_operand" "d,m")))]
- "TARGET_64BIT && !TARGET_MIPS16"
- "@
- andi\t%0,%1,0x00ff
- lbu\t%0,%1"
- [(set_attr "type" "arith,load")
- (set_attr "mode" "DI")
- (set_attr "length" "4,*")])
-
-(define_insn ""
- [(set (match_operand:DI 0 "register_operand" "=d")
- (zero_extend:DI (match_operand:QI 1 "memory_operand" "m")))]
- "TARGET_64BIT && TARGET_MIPS16"
- "lbu\t%0,%1"
- [(set_attr "type" "load")
- (set_attr "mode" "DI")])
+ [(set_attr "type" "load")
+ (set_attr "mode" "HI")])
\f
;;
;; ....................
"TARGET_64BIT"
"@
#
- lw\t%0,%1"
- "&& reload_completed && register_operand (operands[1], VOIDmode)"
- [(const_int 0)]
-{
- emit_note (NOTE_INSN_DELETED);
- DONE;
-}
- [(set_attr "type" "arith,load")
- (set_attr "mode" "DI")])
-
-;; These patterns originally accepted general_operands, however, slightly
-;; better code is generated by only accepting register_operands, and then
-;; letting combine generate the lh and lb insns.
-
-;; These expanders originally put values in registers first. We split
-;; all non-mem patterns after reload.
-
-(define_expand "extendhidi2"
- [(set (match_operand:DI 0 "register_operand")
- (sign_extend:DI (match_operand:HI 1 "nonimmediate_operand")))]
- "TARGET_64BIT"
- "")
-
-(define_insn "*extendhidi2"
- [(set (match_operand:DI 0 "register_operand" "=d")
- (sign_extend:DI (match_operand:HI 1 "register_operand" "d")))]
- "TARGET_64BIT"
- "#")
-
-(define_split
- [(set (match_operand:DI 0 "register_operand")
- (sign_extend:DI (match_operand:HI 1 "register_operand")))]
- "TARGET_64BIT && reload_completed"
- [(set (match_dup 0)
- (ashift:DI (match_dup 1) (const_int 48)))
- (set (match_dup 0)
- (ashiftrt:DI (match_dup 0) (const_int 48)))]
- "operands[1] = gen_lowpart (DImode, operands[1]);")
-
-(define_insn "*extendhidi2_mem"
- [(set (match_operand:DI 0 "register_operand" "=d")
- (sign_extend:DI (match_operand:HI 1 "memory_operand" "m")))]
- "TARGET_64BIT"
- "lh\t%0,%1"
- [(set_attr "type" "load")
- (set_attr "mode" "DI")])
-
-(define_expand "extendhisi2"
- [(set (match_operand:SI 0 "register_operand")
- (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand")))]
- ""
-{
- if (ISA_HAS_SEB_SEH)
- {
- emit_insn (gen_extendhisi2_hw (operands[0],
- force_reg (HImode, operands[1])));
- DONE;
- }
-})
-
-(define_insn "*extendhisi2"
- [(set (match_operand:SI 0 "register_operand" "=d")
- (sign_extend:SI (match_operand:HI 1 "register_operand" "d")))]
- ""
- "#")
-
-(define_split
- [(set (match_operand:SI 0 "register_operand")
- (sign_extend:SI (match_operand:HI 1 "register_operand")))]
- "reload_completed"
- [(set (match_dup 0)
- (ashift:SI (match_dup 1) (const_int 16)))
- (set (match_dup 0)
- (ashiftrt:SI (match_dup 0) (const_int 16)))]
- "operands[1] = gen_lowpart (SImode, operands[1]);")
-
-(define_insn "extendhisi2_mem"
- [(set (match_operand:SI 0 "register_operand" "=d")
- (sign_extend:SI (match_operand:HI 1 "memory_operand" "m")))]
- ""
- "lh\t%0,%1"
- [(set_attr "type" "load")
- (set_attr "mode" "SI")])
-
-(define_insn "extendhisi2_hw"
- [(set (match_operand:SI 0 "register_operand" "=r")
- (sign_extend:SI (match_operand:HI 1 "register_operand" "r")))]
- "ISA_HAS_SEB_SEH"
- "seh\t%0,%1"
- [(set_attr "type" "arith")
- (set_attr "mode" "SI")])
-
-(define_expand "extendqihi2"
- [(set (match_operand:HI 0 "register_operand")
- (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand")))]
- ""
- "")
-
-(define_insn "*extendqihi2"
- [(set (match_operand:HI 0 "register_operand" "=d")
- (sign_extend:HI (match_operand:QI 1 "register_operand" "d")))]
- ""
- "#")
-
-(define_split
- [(set (match_operand:HI 0 "register_operand")
- (sign_extend:HI (match_operand:QI 1 "register_operand")))]
- "reload_completed"
- [(set (match_dup 0)
- (ashift:SI (match_dup 1) (const_int 24)))
- (set (match_dup 0)
- (ashiftrt:SI (match_dup 0) (const_int 24)))]
- "operands[0] = gen_lowpart (SImode, operands[0]);
- operands[1] = gen_lowpart (SImode, operands[1]);")
-
-(define_insn "*extendqihi2_internal_mem"
- [(set (match_operand:HI 0 "register_operand" "=d")
- (sign_extend:HI (match_operand:QI 1 "memory_operand" "m")))]
- ""
- "lb\t%0,%1"
- [(set_attr "type" "load")
- (set_attr "mode" "SI")])
-
-
-(define_expand "extendqisi2"
- [(set (match_operand:SI 0 "register_operand")
- (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand")))]
- ""
-{
- if (ISA_HAS_SEB_SEH)
- {
- emit_insn (gen_extendqisi2_hw (operands[0],
- force_reg (QImode, operands[1])));
- DONE;
- }
-})
-
-(define_insn "*extendqisi2"
- [(set (match_operand:SI 0 "register_operand" "=d")
- (sign_extend:SI (match_operand:QI 1 "register_operand" "d")))]
- ""
- "#")
-
-(define_split
- [(set (match_operand:SI 0 "register_operand")
- (sign_extend:SI (match_operand:QI 1 "register_operand")))]
- "reload_completed"
- [(set (match_dup 0)
- (ashift:SI (match_dup 1) (const_int 24)))
- (set (match_dup 0)
- (ashiftrt:SI (match_dup 0) (const_int 24)))]
- "operands[1] = gen_lowpart (SImode, operands[1]);")
-
-(define_insn "*extendqisi2_mem"
- [(set (match_operand:SI 0 "register_operand" "=d")
- (sign_extend:SI (match_operand:QI 1 "memory_operand" "m")))]
- ""
- "lb\t%0,%1"
- [(set_attr "type" "load")
- (set_attr "mode" "SI")])
-
-(define_insn "extendqisi2_hw"
- [(set (match_operand:SI 0 "register_operand" "=r")
- (sign_extend:SI (match_operand:QI 1 "register_operand" "r")))]
- "ISA_HAS_SEB_SEH"
- "seb\t%0,%1"
- [(set_attr "type" "arith")
- (set_attr "mode" "SI")])
+ lw\t%0,%1"
+ "&& reload_completed && register_operand (operands[1], VOIDmode)"
+ [(const_int 0)]
+{
+ emit_note (NOTE_INSN_DELETED);
+ DONE;
+}
+ [(set_attr "type" "arith,load")
+ (set_attr "mode" "DI")])
-(define_expand "extendqidi2"
- [(set (match_operand:DI 0 "register_operand")
- (sign_extend:DI (match_operand:QI 1 "nonimmediate_operand")))]
- "TARGET_64BIT"
+(define_expand "extend<SHORT:mode><GPR:mode>2"
+ [(set (match_operand:GPR 0 "register_operand")
+ (sign_extend:GPR (match_operand:SHORT 1 "nonimmediate_operand")))]
"")
-(define_insn "*extendqidi2"
- [(set (match_operand:DI 0 "register_operand" "=d")
- (sign_extend:DI (match_operand:QI 1 "register_operand" "d")))]
- "TARGET_64BIT"
- "#")
+(define_insn "*extend<SHORT:mode><GPR:mode>2_mips16e"
+ [(set (match_operand:GPR 0 "register_operand" "=d,d")
+ (sign_extend:GPR (match_operand:SHORT 1 "nonimmediate_operand" "0,m")))]
+ "GENERATE_MIPS16E"
+ "@
+ se<SHORT:size>\t%0
+ l<SHORT:size>\t%0,%1"
+ [(set_attr "type" "arith,load")
+ (set_attr "mode" "<GPR:MODE>")])
-(define_split
- [(set (match_operand:DI 0 "register_operand")
- (sign_extend:DI (match_operand:QI 1 "register_operand")))]
- "TARGET_64BIT && reload_completed"
- [(set (match_dup 0)
- (ashift:DI (match_dup 1) (const_int 56)))
- (set (match_dup 0)
- (ashiftrt:DI (match_dup 0) (const_int 56)))]
- "operands[1] = gen_lowpart (DImode, operands[1]);")
+(define_insn_and_split "*extend<SHORT:mode><GPR:mode>2"
+ [(set (match_operand:GPR 0 "register_operand" "=d,d")
+ (sign_extend:GPR
+ (match_operand:SHORT 1 "nonimmediate_operand" "d,m")))]
+ "!ISA_HAS_SEB_SEH && !GENERATE_MIPS16E"
+ "@
+ #
+ l<SHORT:size>\t%0,%1"
+ "&& reload_completed && REG_P (operands[1])"
+ [(set (match_dup 0) (ashift:GPR (match_dup 1) (match_dup 2)))
+ (set (match_dup 0) (ashiftrt:GPR (match_dup 0) (match_dup 2)))]
+{
+ operands[1] = gen_lowpart (<GPR:MODE>mode, operands[1]);
+ operands[2] = GEN_INT (GET_MODE_BITSIZE (<GPR:MODE>mode)
+ - GET_MODE_BITSIZE (<SHORT:MODE>mode));
+}
+ [(set_attr "type" "arith,load")
+ (set_attr "mode" "<GPR:MODE>")
+ (set_attr "length" "8,*")])
-(define_insn "*extendqidi2_mem"
- [(set (match_operand:DI 0 "register_operand" "=d")
- (sign_extend:DI (match_operand:QI 1 "memory_operand" "m")))]
- "TARGET_64BIT"
- "lb\t%0,%1"
- [(set_attr "type" "load")
- (set_attr "mode" "DI")])
+(define_insn "*extend<SHORT:mode><GPR:mode>2_se<SHORT:size>"
+ [(set (match_operand:GPR 0 "register_operand" "=d,d")
+ (sign_extend:GPR
+ (match_operand:SHORT 1 "nonimmediate_operand" "d,m")))]
+ "ISA_HAS_SEB_SEH"
+ "@
+ se<SHORT:size>\t%0,%1
+ l<SHORT:size>\t%0,%1"
+ [(set_attr "type" "arith,load")
+ (set_attr "mode" "<GPR:MODE>")])
+
+;; This pattern generates the same code as extendqisi2; split it into
+;; that form after reload.
+(define_insn_and_split "extendqihi2"
+ [(set (match_operand:HI 0 "register_operand" "=d,d")
+ (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "d,m")))]
+ ""
+ "#"
+ "reload_completed"
+ [(set (match_dup 0) (sign_extend:SI (match_dup 1)))]
+ { operands[0] = gen_lowpart (SImode, operands[0]); }
+ [(set_attr "type" "arith,load")
+ (set_attr "mode" "SI")
+ (set_attr "length" "8,*")])
(define_insn "extendsfdf2"
[(set (match_operand:DF 0 "register_operand" "=f")
"TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
"cvt.d.s\t%0,%1"
[(set_attr "type" "fcvt")
+ (set_attr "cnv_mode" "S2D")
(set_attr "mode" "DF")])
\f
;;
"trunc.w.d %0,%1"
[(set_attr "type" "fcvt")
(set_attr "mode" "DF")
+ (set_attr "cnv_mode" "D2I")
(set_attr "length" "4")])
(define_insn "fix_truncdfsi2_macro"
}
[(set_attr "type" "fcvt")
(set_attr "mode" "DF")
+ (set_attr "cnv_mode" "D2I")
(set_attr "length" "36")])
(define_expand "fix_truncsfsi2"
"TARGET_HARD_FLOAT && ISA_HAS_TRUNC_W"
"trunc.w.s %0,%1"
[(set_attr "type" "fcvt")
- (set_attr "mode" "DF")
+ (set_attr "mode" "SF")
+ (set_attr "cnv_mode" "S2I")
(set_attr "length" "4")])
(define_insn "fix_truncsfsi2_macro"
return "trunc.w.s %0,%1,%2";
}
[(set_attr "type" "fcvt")
- (set_attr "mode" "DF")
+ (set_attr "mode" "SF")
+ (set_attr "cnv_mode" "S2I")
(set_attr "length" "36")])
"trunc.l.d %0,%1"
[(set_attr "type" "fcvt")
(set_attr "mode" "DF")
+ (set_attr "cnv_mode" "D2I")
(set_attr "length" "4")])
"trunc.l.s %0,%1"
[(set_attr "type" "fcvt")
(set_attr "mode" "SF")
+ (set_attr "cnv_mode" "S2I")
(set_attr "length" "4")])
"cvt.d.w\t%0,%1"
[(set_attr "type" "fcvt")
(set_attr "mode" "DF")
+ (set_attr "cnv_mode" "I2D")
(set_attr "length" "4")])
"cvt.d.l\t%0,%1"
[(set_attr "type" "fcvt")
(set_attr "mode" "DF")
+ (set_attr "cnv_mode" "I2D")
(set_attr "length" "4")])
"cvt.s.w\t%0,%1"
[(set_attr "type" "fcvt")
(set_attr "mode" "SF")
+ (set_attr "cnv_mode" "I2S")
(set_attr "length" "4")])
"cvt.s.l\t%0,%1"
[(set_attr "type" "fcvt")
(set_attr "mode" "SF")
+ (set_attr "cnv_mode" "I2S")
(set_attr "length" "4")])
(define_expand "extzv"
[(set (match_operand 0 "register_operand")
- (zero_extract (match_operand:QI 1 "memory_operand")
+ (zero_extract (match_operand 1 "nonimmediate_operand")
(match_operand 2 "immediate_operand")
(match_operand 3 "immediate_operand")))]
"!TARGET_MIPS16"
INTVAL (operands[2]),
INTVAL (operands[3])))
DONE;
+ else if (mips_use_ins_ext_p (operands[1], operands[2], operands[3]))
+ {
+ if (GET_MODE (operands[0]) == DImode)
+ emit_insn (gen_extzvdi (operands[0], operands[1], operands[2],
+ operands[3]));
+ else
+ emit_insn (gen_extzvsi (operands[0], operands[1], operands[2],
+ operands[3]));
+ DONE;
+ }
else
FAIL;
})
+(define_insn "extzv<mode>"
+ [(set (match_operand:GPR 0 "register_operand" "=d")
+ (zero_extract:GPR (match_operand:GPR 1 "register_operand" "d")
+ (match_operand:SI 2 "immediate_operand" "I")
+ (match_operand:SI 3 "immediate_operand" "I")))]
+ "mips_use_ins_ext_p (operands[1], operands[2], operands[3])"
+ "<d>ext\t%0,%1,%3,%2"
+ [(set_attr "type" "arith")
+ (set_attr "mode" "<MODE>")])
+
+
(define_expand "insv"
- [(set (zero_extract (match_operand:QI 0 "memory_operand")
+ [(set (zero_extract (match_operand 0 "nonimmediate_operand")
(match_operand 1 "immediate_operand")
(match_operand 2 "immediate_operand"))
(match_operand 3 "reg_or_0_operand"))]
INTVAL (operands[1]),
INTVAL (operands[2])))
DONE;
- else
- FAIL;
+ else if (mips_use_ins_ext_p (operands[0], operands[1], operands[2]))
+ {
+ if (GET_MODE (operands[0]) == DImode)
+ emit_insn (gen_insvdi (operands[0], operands[1], operands[2],
+ operands[3]));
+ else
+ emit_insn (gen_insvsi (operands[0], operands[1], operands[2],
+ operands[3]));
+ DONE;
+ }
+ else
+ FAIL;
})
+(define_insn "insv<mode>"
+ [(set (zero_extract:GPR (match_operand:GPR 0 "register_operand" "+d")
+ (match_operand:SI 1 "immediate_operand" "I")
+ (match_operand:SI 2 "immediate_operand" "I"))
+ (match_operand:GPR 3 "reg_or_0_operand" "dJ"))]
+ "mips_use_ins_ext_p (operands[0], operands[1], operands[2])"
+ "<d>ins\t%0,%z3,%2,%1"
+ [(set_attr "type" "arith")
+ (set_attr "mode" "<MODE>")])
+
;; Unaligned word moves generated by the bit field patterns.
;;
;; As far as the rtl is concerned, both the left-part and right-part
(unspec:GPR [(match_operand:BLK 1 "memory_operand" "m")
(match_operand:QI 2 "memory_operand" "m")]
UNSPEC_LOAD_LEFT))]
- "!TARGET_MIPS16"
+ "!TARGET_MIPS16 && mips_mem_fits_mode_p (<MODE>mode, operands[1])"
"<load>l\t%0,%2"
[(set_attr "type" "load")
- (set_attr "mode" "<MODE>")
- (set_attr "hazard" "none")])
+ (set_attr "mode" "<MODE>")])
(define_insn "mov_<load>r"
[(set (match_operand:GPR 0 "register_operand" "=d")
(match_operand:QI 2 "memory_operand" "m")
(match_operand:GPR 3 "register_operand" "0")]
UNSPEC_LOAD_RIGHT))]
- "!TARGET_MIPS16"
+ "!TARGET_MIPS16 && mips_mem_fits_mode_p (<MODE>mode, operands[1])"
"<load>r\t%0,%2"
[(set_attr "type" "load")
(set_attr "mode" "<MODE>")])
(unspec:BLK [(match_operand:GPR 1 "reg_or_0_operand" "dJ")
(match_operand:QI 2 "memory_operand" "m")]
UNSPEC_STORE_LEFT))]
- "!TARGET_MIPS16"
+ "!TARGET_MIPS16 && mips_mem_fits_mode_p (<MODE>mode, operands[0])"
"<store>l\t%z1,%2"
[(set_attr "type" "store")
(set_attr "mode" "<MODE>")])
(match_operand:QI 2 "memory_operand" "m")
(match_dup 0)]
UNSPEC_STORE_RIGHT))]
- "!TARGET_MIPS16"
+ "!TARGET_MIPS16 && mips_mem_fits_mode_p (<MODE>mode, operands[0])"
"<store>r\t%z1,%2"
[(set_attr "type" "store")
(set_attr "mode" "<MODE>")])
;; dsll op0,op0,16
;; daddiu op0,op0,%hi(op1)
;; dsll op0,op0,16
+;;
+;; The split is deferred until after flow2 to allow the peephole2 below
+;; to take effect.
(define_insn_and_split "*lea_high64"
[(set (match_operand:DI 0 "register_operand" "=d")
(high:DI (match_operand:DI 1 "general_symbolic_operand" "")))]
"TARGET_EXPLICIT_RELOCS && ABI_HAS_64BIT_SYMBOLS"
"#"
- "&& reload_completed"
+ "&& flow2_completed"
[(set (match_dup 0) (high:DI (match_dup 2)))
(set (match_dup 0) (lo_sum:DI (match_dup 0) (match_dup 2)))
(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 16)))
}
[(set_attr "length" "20")])
+;; Use a scratch register to reduce the latency of the above pattern
+;; on superscalar machines. The optimized sequence is:
+;;
+;; lui op1,%highest(op2)
+;; lui op0,%hi(op2)
+;; daddiu op1,op1,%higher(op2)
+;; dsll32 op1,op1,0
+;; daddu op1,op1,op0
+(define_peephole2
+ [(set (match_operand:DI 1 "register_operand")
+ (high:DI (match_operand:DI 2 "general_symbolic_operand")))
+ (match_scratch:DI 0 "d")]
+ "TARGET_EXPLICIT_RELOCS && ABI_HAS_64BIT_SYMBOLS"
+ [(set (match_dup 1) (high:DI (match_dup 3)))
+ (set (match_dup 0) (high:DI (match_dup 4)))
+ (set (match_dup 1) (lo_sum:DI (match_dup 1) (match_dup 3)))
+ (set (match_dup 1) (ashift:DI (match_dup 1) (const_int 32)))
+ (set (match_dup 1) (plus:DI (match_dup 1) (match_dup 0)))]
+{
+ operands[3] = mips_unspec_address (operands[2], SYMBOL_64_HIGH);
+ operands[4] = mips_unspec_address (operands[2], SYMBOL_64_LOW);
+})
+
;; On most targets, the expansion of (lo_sum (high X) X) for a 64-bit
;; SYMBOL_GENERAL X will take 6 cycles. This next pattern allows combine
;; to merge the HIGH and LO_SUM parts of a move if the HIGH part is only
;; We could use MEMs, but an unspec gives more optimization
;; opportunities.
-(define_insn "*load_got<mode>"
+(define_insn "load_got<mode>"
[(set (match_operand:P 0 "register_operand" "=d")
(unspec:P [(match_operand:P 1 "register_operand" "d")
(match_operand:P 2 "immediate_operand" "")]
UNSPEC_LOAD_GOT))]
- "TARGET_ABICALLS"
+ ""
"<load>\t%0,%R2(%1)"
[(set_attr "type" "load")
(set_attr "mode" "<MODE>")
(set_attr "mode" "<MODE>")
(set_attr "length" "8")])
+;; Allow combine to split complex const_int load sequences, using operand 2
+;; to store the intermediate results. See move_operand for details.
+(define_split
+ [(set (match_operand:GPR 0 "register_operand")
+ (match_operand:GPR 1 "splittable_const_int_operand"))
+ (clobber (match_operand:GPR 2 "register_operand"))]
+ ""
+ [(const_int 0)]
+{
+ mips_move_integer (operands[0], operands[2], INTVAL (operands[1]));
+ DONE;
+})
+
+;; Likewise, for symbolic operands.
+(define_split
+ [(set (match_operand:P 0 "register_operand")
+ (match_operand:P 1 "splittable_symbolic_operand"))
+ (clobber (match_operand:P 2 "register_operand"))]
+ ""
+ [(set (match_dup 0) (match_dup 1))]
+ { operands[1] = mips_split_symbol (operands[2], operands[1]); })
+
;; 64-bit integer moves
;; Unlike most other insns, the move insns can't be split with
(set_attr "mode" "<MODE>")])
(define_insn "*movdi_32bit"
- [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,m,*x,*d,*B*C*D,*B*C*D,*d,*m")
- (match_operand:DI 1 "move_operand" "d,i,m,d,*J*d,*x,*d,*m,*B*C*D,*B*C*D"))]
- "!TARGET_64BIT && !TARGET_MIPS16
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,m,*a,*d,*B*C*D,*B*C*D,*d,*m")
+ (match_operand:DI 1 "move_operand" "d,i,m,d,*J*d,*a,*d,*m,*B*C*D,*B*C*D"))]
+ "!TARGET_64BIT && !TARGET_FLOAT64 && !TARGET_MIPS16
&& (register_operand (operands[0], DImode)
|| reg_or_0_operand (operands[1], DImode))"
{ return mips_output_move (operands[0], operands[1]); }
(set_attr "mode" "DI")
(set_attr "length" "8,16,*,*,8,8,8,*,8,*")])
+(define_insn "*movdi_gp32_fp64"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,m,*a,*d,*f,*f,*f,*d,*m")
+ (match_operand:DI 1 "move_operand" "d,i,m,d,*J*d,*a,*f,*J*d,*m,*f,*f"))]
+ "!TARGET_64BIT && TARGET_FLOAT64 && !TARGET_MIPS16
+ && (register_operand (operands[0], DImode)
+ || reg_or_0_operand (operands[1], DImode))"
+ { return mips_output_move (operands[0], operands[1]); }
+ [(set_attr "type" "arith,arith,load,store,mthilo,mfhilo,fmove,xfer,fpload,xfer,fpstore")
+ (set_attr "mode" "DI")
+ (set_attr "length" "8,16,*,*,8,8,4,8,*,8,*")])
+
(define_insn "*movdi_32bit_mips16"
[(set (match_operand:DI 0 "nonimmediate_operand" "=d,y,d,d,d,d,m,*d")
(match_operand:DI 1 "move_operand" "d,d,y,K,N,m,d,*x"))]
(match_operand:DI 1 "const_int_operand"))))]
"TARGET_64BIT && TARGET_MIPS16 && reload_completed
&& !TARGET_DEBUG_D_MODE
- && GET_CODE (operands[0]) == REG
+ && REG_P (operands[0])
&& M16_REG_P (REGNO (operands[0]))
&& GET_CODE (operands[1]) == CONST_INT
&& ((INTVAL (operands[1]) < 0
;; in FP registers (off by default, use -mdebugh to enable).
(define_insn "*movsi_internal"
- [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,e,d,m,*f,*f,*f,*d,*m,*d,*z,*x,*B*C*D,*B*C*D,*d,*m")
- (match_operand:SI 1 "move_operand" "d,U,T,m,dJ,*f,*d*J,*m,*f,*f,*z,*d,*J*d,*d,*m,*B*C*D,*B*C*D"))]
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,e,d,m,*f,*f,*f,*d,*m,*d,*z,*a,*d,*B*C*D,*B*C*D,*d,*m")
+ (match_operand:SI 1 "move_operand" "d,U,T,m,dJ,*f,*d*J,*m,*f,*f,*z,*d,*J*d,*A,*d,*m,*B*C*D,*B*C*D"))]
"!TARGET_MIPS16
&& (register_operand (operands[0], SImode)
|| reg_or_0_operand (operands[1], SImode))"
{ return mips_output_move (operands[0], operands[1]); }
- [(set_attr "type" "arith,const,const,load,store,fmove,xfer,fpload,xfer,fpstore,xfer,xfer,mthilo,xfer,load,xfer,store")
+ [(set_attr "type" "arith,const,const,load,store,fmove,xfer,fpload,xfer,fpstore,xfer,xfer,mthilo,mfhilo,xfer,load,xfer,store")
(set_attr "mode" "SI")
- (set_attr "length" "4,*,*,*,*,4,4,*,4,*,4,4,4,4,*,4,*")])
+ (set_attr "length" "4,*,*,*,*,4,4,*,4,*,4,4,4,4,4,*,4,*")])
(define_insn "*movsi_mips16"
[(set (match_operand:SI 0 "nonimmediate_operand" "=d,y,d,d,d,d,d,m")
(mem:SI (plus:SI (match_dup 0)
(match_operand:SI 1 "const_int_operand"))))]
"TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
- && GET_CODE (operands[0]) == REG
+ && REG_P (operands[0])
&& M16_REG_P (REGNO (operands[0]))
&& GET_CODE (operands[1]) == CONST_INT
&& ((INTVAL (operands[1]) < 0
[(set (match_operand:SI 0 "register_operand")
(match_operand:SI 1 "const_int_operand"))]
"TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
- && GET_CODE (operands[0]) == REG
+ && REG_P (operands[0])
&& M16_REG_P (REGNO (operands[0]))
&& GET_CODE (operands[1]) == CONST_INT
&& INTVAL (operands[1]) >= 0x100
;; the sum of two general registers. We use two versions for each of
;; these four instructions: one where the two general registers are
;; SImode, and one where they are DImode. This is because general
-;; registers will be in SImode when they hold 32 bit values, but,
-;; since the 32 bit values are always sign extended, the [ls][wd]xc1
+;; registers will be in SImode when they hold 32-bit values, but,
+;; since the 32-bit values are always sign extended, the [ls][wd]xc1
;; instructions will still work correctly.
;; ??? Perhaps it would be better to support these instructions by
(mem:HI (plus:SI (match_dup 0)
(match_operand:SI 1 "const_int_operand"))))]
"TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
- && GET_CODE (operands[0]) == REG
+ && REG_P (operands[0])
&& M16_REG_P (REGNO (operands[0]))
&& GET_CODE (operands[1]) == CONST_INT
&& ((INTVAL (operands[1]) < 0
(mem:QI (plus:SI (match_dup 0)
(match_operand:SI 1 "const_int_operand"))))]
"TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
- && GET_CODE (operands[0]) == REG
+ && REG_P (operands[0])
&& M16_REG_P (REGNO (operands[0]))
&& GET_CODE (operands[1]) == CONST_INT
&& ((INTVAL (operands[1]) < 0
})
(define_insn "*movsf_hardfloat"
- [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,f,m,*f,*d,*d,*d,*m")
- (match_operand:SF 1 "move_operand" "f,G,m,fG,*d,*f,*G*d,*m,*d"))]
+ [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,f,m,m,*f,*d,*d,*d,*m")
+ (match_operand:SF 1 "move_operand" "f,G,m,f,G,*d,*f,*G*d,*m,*d"))]
"TARGET_HARD_FLOAT
&& (register_operand (operands[0], SFmode)
|| reg_or_0_operand (operands[1], SFmode))"
{ return mips_output_move (operands[0], operands[1]); }
- [(set_attr "type" "fmove,xfer,fpload,fpstore,xfer,xfer,arith,load,store")
+ [(set_attr "type" "fmove,xfer,fpload,fpstore,store,xfer,xfer,arith,load,store")
(set_attr "mode" "SF")
- (set_attr "length" "4,4,*,*,4,4,4,*,*")])
+ (set_attr "length" "4,4,*,*,*,4,4,4,*,*")])
(define_insn "*movsf_softfloat"
[(set (match_operand:SF 0 "nonimmediate_operand" "=d,d,m")
})
(define_insn "*movdf_hardfloat_64bit"
- [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,m,*f,*d,*d,*d,*m")
- (match_operand:DF 1 "move_operand" "f,G,m,fG,*d,*f,*d*G,*m,*d"))]
+ [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,m,m,*f,*d,*d,*d,*m")
+ (match_operand:DF 1 "move_operand" "f,G,m,f,G,*d,*f,*d*G,*m,*d"))]
"TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_64BIT
&& (register_operand (operands[0], DFmode)
|| reg_or_0_operand (operands[1], DFmode))"
{ return mips_output_move (operands[0], operands[1]); }
- [(set_attr "type" "fmove,xfer,fpload,fpstore,xfer,xfer,arith,load,store")
+ [(set_attr "type" "fmove,xfer,fpload,fpstore,store,xfer,xfer,arith,load,store")
(set_attr "mode" "DF")
- (set_attr "length" "4,4,*,*,4,4,4,*,*")])
+ (set_attr "length" "4,4,*,*,*,4,4,4,*,*")])
+;; This pattern applies to both !TARGET_FLOAT64 and TARGET_FLOAT64.
(define_insn "*movdf_hardfloat_32bit"
- [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,m,*f,*d,*d,*d,*m")
- (match_operand:DF 1 "move_operand" "f,G,m,fG,*d,*f,*d*G,*m,*d"))]
+ [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,m,m,*f,*d,*d,*d,*m")
+ (match_operand:DF 1 "move_operand" "f,G,m,f,G,*d,*f,*d*G,*m,*d"))]
"TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && !TARGET_64BIT
&& (register_operand (operands[0], DFmode)
|| reg_or_0_operand (operands[1], DFmode))"
{ return mips_output_move (operands[0], operands[1]); }
- [(set_attr "type" "fmove,xfer,fpload,fpstore,xfer,xfer,arith,load,store")
+ [(set_attr "type" "fmove,xfer,fpload,fpstore,store,xfer,xfer,arith,load,store")
(set_attr "mode" "DF")
- (set_attr "length" "4,8,*,*,8,8,8,*,*")])
+ (set_attr "length" "4,8,*,*,*,8,8,8,*,*")])
(define_insn "*movdf_softfloat"
[(set (match_operand:DF 0 "nonimmediate_operand" "=d,d,m,d,f,f")
})
(define_insn "movv2sf_hardfloat_64bit"
- [(set (match_operand:V2SF 0 "nonimmediate_operand" "=f,f,f,m,*f,*d,*d,*d,*m")
- (match_operand:V2SF 1 "move_operand" "f,YG,m,fYG,*d,*f,*d*YG,*m,*d"))]
+ [(set (match_operand:V2SF 0 "nonimmediate_operand" "=f,f,f,m,m,*f,*d,*d,*d,*m")
+ (match_operand:V2SF 1 "move_operand" "f,YG,m,f,YG,*d,*f,*d*YG,*m,*d"))]
"TARGET_PAIRED_SINGLE_FLOAT
&& TARGET_64BIT
&& (register_operand (operands[0], V2SFmode)
|| reg_or_0_operand (operands[1], V2SFmode))"
{ return mips_output_move (operands[0], operands[1]); }
- [(set_attr "type" "fmove,xfer,fpload,fpstore,xfer,xfer,arith,load,store")
+ [(set_attr "type" "fmove,xfer,fpload,fpstore,store,xfer,xfer,arith,load,store")
(set_attr "mode" "SF")
- (set_attr "length" "4,4,*,*,4,4,4,*,*")])
+ (set_attr "length" "4,4,*,*,*,4,4,4,*,*")])
;; The HI and LO registers are not truly independent. If we move an mthi
;; instruction before an mflo instruction, it will make the result of the
;;
;; We cope with this by making the mflo and mfhi patterns use both HI and LO.
;; Operand 1 is the register we want, operand 2 is the other one.
+;;
+;; When generating VR4120 or VR4130 code, we use macc{,hi} and
+;; dmacc{,hi} instead of mfhi and mflo. This avoids both the normal
+;; MIPS III hi/lo hazards and the errata related to -mfix-vr4130.
+
+(define_expand "mfhilo_<mode>"
+ [(set (match_operand:GPR 0 "register_operand")
+ (unspec:GPR [(match_operand:GPR 1 "register_operand")
+ (match_operand:GPR 2 "register_operand")]
+ UNSPEC_MFHILO))])
-(define_insn "mfhilo_<mode>"
+(define_insn "*mfhilo_<mode>"
[(set (match_operand:GPR 0 "register_operand" "=d,d")
(unspec:GPR [(match_operand:GPR 1 "register_operand" "h,l")
(match_operand:GPR 2 "register_operand" "l,h")]
UNSPEC_MFHILO))]
- ""
+ "!ISA_HAS_MACCHI"
"mf%1\t%0"
[(set_attr "type" "mfhilo")
(set_attr "mode" "<MODE>")])
+(define_insn "*mfhilo_<mode>_macc"
+ [(set (match_operand:GPR 0 "register_operand" "=d,d")
+ (unspec:GPR [(match_operand:GPR 1 "register_operand" "h,l")
+ (match_operand:GPR 2 "register_operand" "l,h")]
+ UNSPEC_MFHILO))]
+ "ISA_HAS_MACCHI"
+{
+ if (REGNO (operands[1]) == HI_REGNUM)
+ return "<d>macchi\t%0,%.,%.";
+ else
+ return "<d>macc\t%0,%.,%.";
+}
+ [(set_attr "type" "mfhilo")
+ (set_attr "mode" "<MODE>")])
+
;; Patterns for loading or storing part of a paired floating point
;; register. We need them because odd-numbered floating-point registers
;; are not fully independent: see mips_split_64bit_move.
[(set_attr "type" "xfer,fpstore")
(set_attr "mode" "SF")])
+;; Move operand 1 to the high word of operand 0 using mthc1, preserving the
+;; value in the low word.
+(define_insn "mthc1"
+ [(set (match_operand:DF 0 "register_operand" "=f")
+ (unspec:DF [(match_operand:SI 1 "general_operand" "dJ")
+ (match_operand:DF 2 "register_operand" "0")]
+ UNSPEC_MTHC1))]
+ "TARGET_HARD_FLOAT && !TARGET_64BIT && ISA_HAS_MXHC1"
+ "mthc1\t%z1,%0"
+ [(set_attr "type" "xfer")
+ (set_attr "mode" "SF")])
+
+;; Move high word of operand 1 to operand 0 using mfhc1. The corresponding
+;; low-word move is done in the normal way.
+(define_insn "mfhc1"
+ [(set (match_operand:SI 0 "register_operand" "=d")
+ (unspec:SI [(match_operand:DF 1 "register_operand" "f")]
+ UNSPEC_MFHC1))]
+ "TARGET_HARD_FLOAT && !TARGET_64BIT && ISA_HAS_MXHC1"
+ "mfhc1\t%0,%1"
+ [(set_attr "type" "xfer")
+ (set_attr "mode" "SF")])
+
;; Insn to initialize $gp for n32/n64 abicalls. Operand 0 is the offset
;; of _gp from the start of this function. Operand 1 is the incoming
;; function address.
(define_insn_and_split "loadgp"
[(unspec_volatile [(match_operand 0 "" "")
(match_operand 1 "register_operand" "")] UNSPEC_LOADGP)]
- "TARGET_ABICALLS && TARGET_NEWABI"
+ "mips_current_loadgp_style () == LOADGP_NEWABI"
"#"
""
[(set (match_dup 2) (match_dup 3))
}
[(set_attr "length" "12")])
+;; Likewise, for -mno-shared code. Operand 0 is the __gnu_local_gp symbol.
+(define_insn_and_split "loadgp_noshared"
+ [(unspec_volatile [(match_operand 0 "" "")] UNSPEC_LOADGP)]
+ "mips_current_loadgp_style () == LOADGP_ABSOLUTE"
+ "#"
+ ""
+ [(const_int 0)]
+{
+ emit_move_insn (pic_offset_table_rtx, operands[0]);
+ DONE;
+}
+ [(set_attr "length" "8")])
+
;; The use of gp is hidden when not using explicit relocations.
;; This blockage instruction prevents the gp load from being
;; scheduled after an implicit use of gp. It also prevents
[(set (match_operand:GPR 0 "register_operand" "=d")
(rotatert:GPR (match_operand:GPR 1 "register_operand" "d")
(match_operand:SI 2 "arith_operand" "dI")))]
- "ISA_HAS_ROTR_<MODE>"
+ "ISA_HAS_ROR"
{
- if ((GET_CODE (operands[2]) == CONST_INT)
- && (INTVAL (operands[2]) < 0
- || INTVAL (operands[2]) >= GET_MODE_BITSIZE (<MODE>mode)))
- abort ();
+ if (GET_CODE (operands[2]) == CONST_INT)
+ gcc_assert (INTVAL (operands[2]) >= 0
+ && INTVAL (operands[2]) < GET_MODE_BITSIZE (<MODE>mode));
return "<d>ror\t%0,%1,%2";
}
DONE;
})
-(define_expand "cmpdf"
- [(set (cc0)
- (compare:CC (match_operand:DF 0 "register_operand")
- (match_operand:DF 1 "register_operand")))]
- "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
-{
- cmp_operands[0] = operands[0];
- cmp_operands[1] = operands[1];
- DONE;
-})
-
-(define_expand "cmpsf"
+(define_expand "cmp<mode>"
[(set (cc0)
- (compare:CC (match_operand:SF 0 "register_operand")
- (match_operand:SF 1 "register_operand")))]
- "TARGET_HARD_FLOAT"
+ (compare:CC (match_operand:SCALARF 0 "register_operand")
+ (match_operand:SCALARF 1 "register_operand")))]
+ ""
{
cmp_operands[0] = operands[0];
cmp_operands[1] = operands[1];
;; Conditional branches on floating-point equality tests.
-(define_insn "branch_fp"
+(define_insn "*branch_fp"
[(set (pc)
(if_then_else
- (match_operator:CC 0 "comparison_operator"
- [(match_operand:CC 2 "register_operand" "z")
- (const_int 0)])
+ (match_operator 0 "equality_operator"
+ [(match_operand:CC 2 "register_operand" "z")
+ (const_int 0)])
(label_ref (match_operand 1 "" ""))
(pc)))]
"TARGET_HARD_FLOAT"
{
- return mips_output_conditional_branch (insn,
- operands,
- /*two_operands_p=*/0,
- /*float_p=*/1,
- /*inverted_p=*/0,
- get_attr_length (insn));
+ return mips_output_conditional_branch (insn, operands,
+ MIPS_BRANCH ("b%F0", "%Z2%1"),
+ MIPS_BRANCH ("b%W0", "%Z2%1"));
}
- [(set_attr "type" "branch")
- (set_attr "mode" "none")])
+ [(set_attr "type" "branch")
+ (set_attr "mode" "none")])
-(define_insn "branch_fp_inverted"
+(define_insn "*branch_fp_inverted"
[(set (pc)
(if_then_else
- (match_operator:CC 0 "comparison_operator"
- [(match_operand:CC 2 "register_operand" "z")
- (const_int 0)])
+ (match_operator 0 "equality_operator"
+ [(match_operand:CC 2 "register_operand" "z")
+ (const_int 0)])
(pc)
(label_ref (match_operand 1 "" ""))))]
"TARGET_HARD_FLOAT"
{
- return mips_output_conditional_branch (insn,
- operands,
- /*two_operands_p=*/0,
- /*float_p=*/1,
- /*inverted_p=*/1,
- get_attr_length (insn));
+ return mips_output_conditional_branch (insn, operands,
+ MIPS_BRANCH ("b%W0", "%Z2%1"),
+ MIPS_BRANCH ("b%F0", "%Z2%1"));
}
- [(set_attr "type" "branch")
- (set_attr "mode" "none")])
+ [(set_attr "type" "branch")
+ (set_attr "mode" "none")])
-;; Conditional branches on comparisons with zero.
+;; Conditional branches on ordered comparisons with zero.
-(define_insn "*branch_zero<mode>"
+(define_insn "*branch_order<mode>"
[(set (pc)
(if_then_else
- (match_operator:GPR 0 "comparison_operator"
- [(match_operand:GPR 2 "register_operand" "d")
- (const_int 0)])
+ (match_operator 0 "order_operator"
+ [(match_operand:GPR 2 "register_operand" "d")
+ (const_int 0)])
(label_ref (match_operand 1 "" ""))
(pc)))]
"!TARGET_MIPS16"
-{
- return mips_output_conditional_branch (insn,
- operands,
- /*two_operands_p=*/0,
- /*float_p=*/0,
- /*inverted_p=*/0,
- get_attr_length (insn));
-}
+ { return mips_output_order_conditional_branch (insn, operands, false); }
[(set_attr "type" "branch")
(set_attr "mode" "none")])
-(define_insn "*branch_zero<mode>_inverted"
+(define_insn "*branch_order<mode>_inverted"
[(set (pc)
(if_then_else
- (match_operator:GPR 0 "comparison_operator"
- [(match_operand:GPR 2 "register_operand" "d")
- (const_int 0)])
+ (match_operator 0 "order_operator"
+ [(match_operand:GPR 2 "register_operand" "d")
+ (const_int 0)])
(pc)
(label_ref (match_operand 1 "" ""))))]
"!TARGET_MIPS16"
-{
- return mips_output_conditional_branch (insn,
- operands,
- /*two_operands_p=*/0,
- /*float_p=*/0,
- /*inverted_p=*/1,
- get_attr_length (insn));
-}
+ { return mips_output_order_conditional_branch (insn, operands, true); }
[(set_attr "type" "branch")
(set_attr "mode" "none")])
(define_insn "*branch_equality<mode>"
[(set (pc)
(if_then_else
- (match_operator:GPR 0 "equality_operator"
- [(match_operand:GPR 2 "register_operand" "d")
- (match_operand:GPR 3 "register_operand" "d")])
+ (match_operator 0 "equality_operator"
+ [(match_operand:GPR 2 "register_operand" "d")
+ (match_operand:GPR 3 "reg_or_0_operand" "dJ")])
(label_ref (match_operand 1 "" ""))
(pc)))]
"!TARGET_MIPS16"
{
- return mips_output_conditional_branch (insn,
- operands,
- /*two_operands_p=*/1,
- /*float_p=*/0,
- /*inverted_p=*/0,
- get_attr_length (insn));
+ return mips_output_conditional_branch (insn, operands,
+ MIPS_BRANCH ("b%C0", "%2,%z3,%1"),
+ MIPS_BRANCH ("b%N0", "%2,%z3,%1"));
}
[(set_attr "type" "branch")
(set_attr "mode" "none")])
(define_insn "*branch_equality<mode>_inverted"
[(set (pc)
(if_then_else
- (match_operator:GPR 0 "equality_operator"
- [(match_operand:GPR 2 "register_operand" "d")
- (match_operand:GPR 3 "register_operand" "d")])
+ (match_operator 0 "equality_operator"
+ [(match_operand:GPR 2 "register_operand" "d")
+ (match_operand:GPR 3 "reg_or_0_operand" "dJ")])
(pc)
(label_ref (match_operand 1 "" ""))))]
"!TARGET_MIPS16"
{
- return mips_output_conditional_branch (insn,
- operands,
- /*two_operands_p=*/1,
- /*float_p=*/0,
- /*inverted_p=*/1,
- get_attr_length (insn));
+ return mips_output_conditional_branch (insn, operands,
+ MIPS_BRANCH ("b%N0", "%2,%z3,%1"),
+ MIPS_BRANCH ("b%C0", "%2,%z3,%1"));
}
[(set_attr "type" "branch")
(set_attr "mode" "none")])
(define_insn "*branch_equality<mode>_mips16"
[(set (pc)
(if_then_else
- (match_operator:GPR 0 "equality_operator"
- [(match_operand:GPR 1 "register_operand" "d,t")
- (const_int 0)])
+ (match_operator 0 "equality_operator"
+ [(match_operand:GPR 1 "register_operand" "d,t")
+ (const_int 0)])
(match_operand 2 "pc_or_label_operand" "")
(match_operand 3 "pc_or_label_operand" "")))]
"TARGET_MIPS16"
gen_conditional_branch (operands, <CODE>);
DONE;
})
+
+;; Used to implement built-in functions.
+(define_expand "condjump"
+ [(set (pc)
+ (if_then_else (match_operand 0)
+ (label_ref (match_operand 1))
+ (pc)))])
\f
;;
;; ....................
;;
;; ....................
-(define_insn "sunordered_df"
- [(set (match_operand:CC 0 "register_operand" "=z")
- (unordered:CC (match_operand:DF 1 "register_operand" "f")
- (match_operand:DF 2 "register_operand" "f")))]
- "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
- "c.un.d\t%Z0%1,%2"
- [(set_attr "type" "fcmp")
- (set_attr "mode" "FPSW")])
-
-(define_insn "sunlt_df"
- [(set (match_operand:CC 0 "register_operand" "=z")
- (unlt:CC (match_operand:DF 1 "register_operand" "f")
- (match_operand:DF 2 "register_operand" "f")))]
- "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
- "c.ult.d\t%Z0%1,%2"
- [(set_attr "type" "fcmp")
- (set_attr "mode" "FPSW")])
-
-(define_insn "suneq_df"
- [(set (match_operand:CC 0 "register_operand" "=z")
- (uneq:CC (match_operand:DF 1 "register_operand" "f")
- (match_operand:DF 2 "register_operand" "f")))]
- "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
- "c.ueq.d\t%Z0%1,%2"
- [(set_attr "type" "fcmp")
- (set_attr "mode" "FPSW")])
-
-(define_insn "sunle_df"
- [(set (match_operand:CC 0 "register_operand" "=z")
- (unle:CC (match_operand:DF 1 "register_operand" "f")
- (match_operand:DF 2 "register_operand" "f")))]
- "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
- "c.ule.d\t%Z0%1,%2"
- [(set_attr "type" "fcmp")
- (set_attr "mode" "FPSW")])
-
-(define_insn "seq_df"
- [(set (match_operand:CC 0 "register_operand" "=z")
- (eq:CC (match_operand:DF 1 "register_operand" "f")
- (match_operand:DF 2 "register_operand" "f")))]
- "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
- "c.eq.d\t%Z0%1,%2"
- [(set_attr "type" "fcmp")
- (set_attr "mode" "FPSW")])
-
-(define_insn "slt_df"
- [(set (match_operand:CC 0 "register_operand" "=z")
- (lt:CC (match_operand:DF 1 "register_operand" "f")
- (match_operand:DF 2 "register_operand" "f")))]
- "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
- "c.lt.d\t%Z0%1,%2"
- [(set_attr "type" "fcmp")
- (set_attr "mode" "FPSW")])
-
-(define_insn "sle_df"
- [(set (match_operand:CC 0 "register_operand" "=z")
- (le:CC (match_operand:DF 1 "register_operand" "f")
- (match_operand:DF 2 "register_operand" "f")))]
- "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
- "c.le.d\t%Z0%1,%2"
- [(set_attr "type" "fcmp")
- (set_attr "mode" "FPSW")])
-
-(define_insn "sgt_df"
- [(set (match_operand:CC 0 "register_operand" "=z")
- (gt:CC (match_operand:DF 1 "register_operand" "f")
- (match_operand:DF 2 "register_operand" "f")))]
- "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
- "c.lt.d\t%Z0%2,%1"
- [(set_attr "type" "fcmp")
- (set_attr "mode" "FPSW")])
-
-(define_insn "sge_df"
- [(set (match_operand:CC 0 "register_operand" "=z")
- (ge:CC (match_operand:DF 1 "register_operand" "f")
- (match_operand:DF 2 "register_operand" "f")))]
- "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
- "c.le.d\t%Z0%2,%1"
- [(set_attr "type" "fcmp")
- (set_attr "mode" "FPSW")])
-
-(define_insn "sunordered_sf"
- [(set (match_operand:CC 0 "register_operand" "=z")
- (unordered:CC (match_operand:SF 1 "register_operand" "f")
- (match_operand:SF 2 "register_operand" "f")))]
- "TARGET_HARD_FLOAT"
- "c.un.s\t%Z0%1,%2"
- [(set_attr "type" "fcmp")
- (set_attr "mode" "FPSW")])
-
-(define_insn "sunlt_sf"
- [(set (match_operand:CC 0 "register_operand" "=z")
- (unlt:CC (match_operand:SF 1 "register_operand" "f")
- (match_operand:SF 2 "register_operand" "f")))]
- "TARGET_HARD_FLOAT"
- "c.ult.s\t%Z0%1,%2"
- [(set_attr "type" "fcmp")
- (set_attr "mode" "FPSW")])
-
-(define_insn "suneq_sf"
- [(set (match_operand:CC 0 "register_operand" "=z")
- (uneq:CC (match_operand:SF 1 "register_operand" "f")
- (match_operand:SF 2 "register_operand" "f")))]
- "TARGET_HARD_FLOAT"
- "c.ueq.s\t%Z0%1,%2"
- [(set_attr "type" "fcmp")
- (set_attr "mode" "FPSW")])
-
-(define_insn "sunle_sf"
- [(set (match_operand:CC 0 "register_operand" "=z")
- (unle:CC (match_operand:SF 1 "register_operand" "f")
- (match_operand:SF 2 "register_operand" "f")))]
- "TARGET_HARD_FLOAT"
- "c.ule.s\t%Z0%1,%2"
- [(set_attr "type" "fcmp")
- (set_attr "mode" "FPSW")])
-
-(define_insn "seq_sf"
- [(set (match_operand:CC 0 "register_operand" "=z")
- (eq:CC (match_operand:SF 1 "register_operand" "f")
- (match_operand:SF 2 "register_operand" "f")))]
- "TARGET_HARD_FLOAT"
- "c.eq.s\t%Z0%1,%2"
- [(set_attr "type" "fcmp")
- (set_attr "mode" "FPSW")])
-
-(define_insn "slt_sf"
- [(set (match_operand:CC 0 "register_operand" "=z")
- (lt:CC (match_operand:SF 1 "register_operand" "f")
- (match_operand:SF 2 "register_operand" "f")))]
- "TARGET_HARD_FLOAT"
- "c.lt.s\t%Z0%1,%2"
- [(set_attr "type" "fcmp")
- (set_attr "mode" "FPSW")])
-
-(define_insn "sle_sf"
- [(set (match_operand:CC 0 "register_operand" "=z")
- (le:CC (match_operand:SF 1 "register_operand" "f")
- (match_operand:SF 2 "register_operand" "f")))]
- "TARGET_HARD_FLOAT"
- "c.le.s\t%Z0%1,%2"
- [(set_attr "type" "fcmp")
- (set_attr "mode" "FPSW")])
-
-(define_insn "sgt_sf"
+(define_insn "s<code>_<mode>"
[(set (match_operand:CC 0 "register_operand" "=z")
- (gt:CC (match_operand:SF 1 "register_operand" "f")
- (match_operand:SF 2 "register_operand" "f")))]
- "TARGET_HARD_FLOAT"
- "c.lt.s\t%Z0%2,%1"
+ (fcond:CC (match_operand:SCALARF 1 "register_operand" "f")
+ (match_operand:SCALARF 2 "register_operand" "f")))]
+ ""
+ "c.<fcond>.<fmt>\t%Z0%1,%2"
[(set_attr "type" "fcmp")
(set_attr "mode" "FPSW")])
-(define_insn "sge_sf"
+(define_insn "s<code>_<mode>"
[(set (match_operand:CC 0 "register_operand" "=z")
- (ge:CC (match_operand:SF 1 "register_operand" "f")
- (match_operand:SF 2 "register_operand" "f")))]
- "TARGET_HARD_FLOAT"
- "c.le.s\t%Z0%2,%1"
+ (swapped_fcond:CC (match_operand:SCALARF 1 "register_operand" "f")
+ (match_operand:SCALARF 2 "register_operand" "f")))]
+ ""
+ "c.<swapped_fcond>.<fmt>\t%Z0%2,%1"
[(set_attr "type" "fcmp")
(set_attr "mode" "FPSW")])
\f
[(call (mem:SI (match_operand 0 "call_insn_operand" "j,S"))
(match_operand 1 "" ""))]
"TARGET_SIBCALLS && SIBLING_CALL_P (insn)"
- "@
- %*jr\t%0%/
- %*j\t%0%/"
+ { return MIPS_CALL ("j", operands, 0); }
[(set_attr "type" "call")])
(define_expand "sibcall_value"
(call (mem:SI (match_operand 1 "call_insn_operand" "j,S"))
(match_operand 2 "" "")))]
"TARGET_SIBCALLS && SIBLING_CALL_P (insn)"
- "@
- %*jr\t%1%/
- %*j\t%1%/"
+ { return MIPS_CALL ("j", operands, 1); }
[(set_attr "type" "call")])
(define_insn "sibcall_value_multiple_internal"
(call (mem:SI (match_dup 1))
(match_dup 2)))]
"TARGET_SIBCALLS && SIBLING_CALL_P (insn)"
- "@
- %*jr\t%1%/
- %*j\t%1%/"
+ { return MIPS_CALL ("j", operands, 1); }
[(set_attr "type" "call")])
(define_expand "call"
(match_operand 1 "" ""))
(clobber (reg:SI 31))]
""
- { return TARGET_SPLIT_CALLS ? "#" : "%*jal\t%0%/"; }
+ { return TARGET_SPLIT_CALLS ? "#" : MIPS_CALL ("jal", operands, 0); }
"reload_completed && TARGET_SPLIT_CALLS && (operands[2] = insn)"
[(const_int 0)]
{
(set_attr "extended_mips16" "no,yes")])
(define_insn "call_split"
- [(call (mem:SI (match_operand 0 "call_insn_operand" "c"))
+ [(call (mem:SI (match_operand 0 "call_insn_operand" "cS"))
(match_operand 1 "" ""))
(clobber (reg:SI 31))
(clobber (reg:SI 28))]
"TARGET_SPLIT_CALLS"
- "%*jalr\t%0%/"
+ { return MIPS_CALL ("jal", operands, 0); }
[(set_attr "type" "call")])
(define_expand "call_value"
(match_operand 2 "" "")))
(clobber (reg:SI 31))]
""
- { return TARGET_SPLIT_CALLS ? "#" : "%*jal\t%1%/"; }
+ { return TARGET_SPLIT_CALLS ? "#" : MIPS_CALL ("jal", operands, 1); }
"reload_completed && TARGET_SPLIT_CALLS && (operands[3] = insn)"
[(const_int 0)]
{
(define_insn "call_value_split"
[(set (match_operand 0 "register_operand" "=df")
- (call (mem:SI (match_operand 1 "call_insn_operand" "c"))
+ (call (mem:SI (match_operand 1 "call_insn_operand" "cS"))
(match_operand 2 "" "")))
(clobber (reg:SI 31))
(clobber (reg:SI 28))]
"TARGET_SPLIT_CALLS"
- "%*jalr\t%1%/"
+ { return MIPS_CALL ("jal", operands, 1); }
[(set_attr "type" "call")])
;; See comment for call_internal.
(match_dup 2)))
(clobber (reg:SI 31))]
""
- { return TARGET_SPLIT_CALLS ? "#" : "%*jal\t%1%/"; }
+ { return TARGET_SPLIT_CALLS ? "#" : MIPS_CALL ("jal", operands, 1); }
"reload_completed && TARGET_SPLIT_CALLS && (operands[4] = insn)"
[(const_int 0)]
{
(define_insn "call_value_multiple_split"
[(set (match_operand 0 "register_operand" "=df")
- (call (mem:SI (match_operand 1 "call_insn_operand" "c"))
+ (call (mem:SI (match_operand 1 "call_insn_operand" "cS"))
(match_operand 2 "" "")))
(set (match_operand 3 "register_operand" "=df")
(call (mem:SI (match_dup 1))
(clobber (reg:SI 31))
(clobber (reg:SI 28))]
"TARGET_SPLIT_CALLS"
- "%*jalr\t%1%/"
+ { return MIPS_CALL ("jal", operands, 1); }
[(set_attr "type" "call")])
;; Call subroutine returning any type.
[(set_attr "type" "condmove")
(set_attr "mode" "<GPR:MODE>")])
-(define_insn "*movsf_on_<MOVECC:mode>"
- [(set (match_operand:SF 0 "register_operand" "=f,f")
- (if_then_else:SF
- (match_operator:MOVECC 4 "equality_operator"
- [(match_operand:MOVECC 1 "register_operand" "<MOVECC:reg>,<MOVECC:reg>")
- (const_int 0)])
- (match_operand:SF 2 "register_operand" "f,0")
- (match_operand:SF 3 "register_operand" "0,f")))]
- "ISA_HAS_CONDMOVE && TARGET_HARD_FLOAT"
- "@
- mov%T4.s\t%0,%2,%1
- mov%t4.s\t%0,%3,%1"
- [(set_attr "type" "condmove")
- (set_attr "mode" "SF")])
-
-(define_insn "*movdf_on_<MOVECC:mode>"
- [(set (match_operand:DF 0 "register_operand" "=f,f")
- (if_then_else:DF
+(define_insn "*mov<SCALARF:mode>_on_<MOVECC:mode>"
+ [(set (match_operand:SCALARF 0 "register_operand" "=f,f")
+ (if_then_else:SCALARF
(match_operator:MOVECC 4 "equality_operator"
[(match_operand:MOVECC 1 "register_operand" "<MOVECC:reg>,<MOVECC:reg>")
(const_int 0)])
- (match_operand:DF 2 "register_operand" "f,0")
- (match_operand:DF 3 "register_operand" "0,f")))]
- "ISA_HAS_CONDMOVE && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
+ (match_operand:SCALARF 2 "register_operand" "f,0")
+ (match_operand:SCALARF 3 "register_operand" "0,f")))]
+ "ISA_HAS_CONDMOVE"
"@
- mov%T4.d\t%0,%2,%1
- mov%t4.d\t%0,%3,%1"
+ mov%T4.<fmt>\t%0,%2,%1
+ mov%t4.<fmt>\t%0,%3,%1"
[(set_attr "type" "condmove")
- (set_attr "mode" "DF")])
+ (set_attr "mode" "<SCALARF:MODE>")])
;; These are the main define_expand's used to make conditional moves.
DONE;
})
-(define_expand "movsfcc"
- [(set (match_dup 4) (match_operand 1 "comparison_operator"))
- (set (match_operand:SF 0 "register_operand")
- (if_then_else:SF (match_dup 5)
- (match_operand:SF 2 "register_operand")
- (match_operand:SF 3 "register_operand")))]
- "ISA_HAS_CONDMOVE && TARGET_HARD_FLOAT"
-{
- gen_conditional_move (operands);
- DONE;
-})
-
-(define_expand "movdfcc"
+(define_expand "mov<mode>cc"
[(set (match_dup 4) (match_operand 1 "comparison_operator"))
- (set (match_operand:DF 0 "register_operand")
- (if_then_else:DF (match_dup 5)
- (match_operand:DF 2 "register_operand")
- (match_operand:DF 3 "register_operand")))]
- "ISA_HAS_CONDMOVE && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
+ (set (match_operand:SCALARF 0 "register_operand")
+ (if_then_else:SCALARF (match_dup 5)
+ (match_operand:SCALARF 2 "register_operand")
+ (match_operand:SCALARF 3 "register_operand")))]
+ "ISA_HAS_CONDMOVE"
{
gen_conditional_move (operands);
DONE;
{
REAL_VALUE_TYPE d;
- if (GET_CODE (operands[0]) != CONST_DOUBLE)
- abort ();
+ gcc_assert (GET_CODE (operands[0]) == CONST_DOUBLE);
REAL_VALUE_FROM_CONST_DOUBLE (d, operands[0]);
assemble_real (d, GET_MODE (operands[0]),
GET_MODE_BITSIZE (GET_MODE (operands[0])));
[(match_dup 0)]
{ operands[0] = mips_rewrite_small_data (operands[0]); })
\f
+; Thread-Local Storage
+
+; The TLS base pointer is accessed via "rdhwr $v1, $29". No current
+; MIPS architecture defines this register, and no current
+; implementation provides it; instead, any OS which supports TLS is
+; expected to trap and emulate this instruction. rdhwr is part of the
+; MIPS 32r2 specification, but we use it on any architecture because
+; we expect it to be emulated. Use .set to force the assembler to
+; accept it.
+
+(define_insn "tls_get_tp_<mode>"
+ [(set (match_operand:P 0 "register_operand" "=v")
+ (unspec:P [(const_int 0)]
+ UNSPEC_TLS_GET_TP))]
+ "HAVE_AS_TLS && !TARGET_MIPS16"
+ ".set\tpush\;.set\tmips32r2\t\;rdhwr\t%0,$29\;.set\tpop"
+ [(set_attr "type" "unknown")
+ ; Since rdhwr always generates a trap for now, putting it in a delay
+ ; slot would make the kernel's emulation of it much slower.
+ (set_attr "can_delay" "no")
+ (set_attr "mode" "<MODE>")])
+\f
; The MIPS Paired-Single Floating Point and MIPS-3D Instructions.
(include "mips-ps-3d.md")
+
+; The MIPS DSP Instructions.
+
+(include "mips-dsp.md")
+
+; The MIPS DSP REV 2 Instructions.
+
+(include "mips-dspr2.md")
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