/* Definitions of target machine for GNU compiler. MIPS version.
Copyright (C) 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998
- 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
+ 1999, 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
Contributed by A. Lichnewsky (lich@inria.inria.fr).
Changed by Michael Meissner (meissner@osf.org).
64 bit r4000 support by Ian Lance Taylor (ian@cygnus.com) and
Brendan Eich (brendan@microunity.com).
-This file is part of GNU CC.
+This file is part of GCC.
-GNU CC is free software; you can redistribute it and/or modify
+GCC is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
any later version.
-GNU CC is distributed in the hope that it will be useful,
+GCC is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING. If not, write to
+along with GCC; see the file COPYING. If not, write to
the Free Software Foundation, 59 Temple Place - Suite 330,
Boston, MA 02111-1307, USA. */
extern const char *mips_tune_string; /* for -mtune=<xxx> */
extern const char *mips_isa_string; /* for -mips{1,2,3,4} */
extern const char *mips_abi_string; /* for -mabi={32,n32,64} */
-extern const char *mips_entry_string; /* for -mentry */
extern const char *mips_cache_flush_func;/* for -mflush-func= and -mno-flush-func */
extern int mips_string_length; /* length of strings for mips16 */
extern const struct mips_cpu_info mips_cpu_info_table[];
#define MASK_SOFT_FLOAT 0x00000100 /* software floating point */
#define MASK_FLOAT64 0x00000200 /* fp registers are 64 bits */
#define MASK_ABICALLS 0x00000400 /* emit .abicalls/.cprestore/.cpload */
-#define MASK_UNUSED1 0x00000800 /* Unused Mask. */
+#define MASK_XGOT 0x00000800 /* emit big-got PIC */
#define MASK_LONG_CALLS 0x00001000 /* Always call through a register */
#define MASK_64BIT 0x00002000 /* Use 64 bit GP registers and insns */
#define MASK_EMBEDDED_PIC 0x00004000 /* Generate embedded PIC code */
#define MASK_UNINIT_CONST_IN_RODATA \
0x00800000 /* Store uninitialized
consts in rodata */
+#define MASK_FIX_SB1 0x01000000 /* Work around SB-1 errata. */
/* Debug switches, not documented */
#define MASK_DEBUG 0 /* unused */
/* .abicalls, etc from Pyramid V.4 */
#define TARGET_ABICALLS (target_flags & MASK_ABICALLS)
+#define TARGET_XGOT (target_flags & MASK_XGOT)
/* software floating point */
#define TARGET_SOFT_FLOAT (target_flags & MASK_SOFT_FLOAT)
#define TARGET_BRANCHLIKELY (target_flags & MASK_BRANCHLIKELY)
+#define TARGET_FIX_SB1 (target_flags & MASK_FIX_SB1)
/* True if we should use NewABI-style relocation operators for
symbolic addresses. This is never true for mips16 code,
#define TARGET_NEWABI (mips_abi == ABI_N32 || mips_abi == ABI_64)
+/* IRIX specific stuff. */
+#define TARGET_IRIX 0
+#define TARGET_IRIX5 0
+#define TARGET_SGI_O32_AS (TARGET_IRIX && mips_abi == ABI_32 && !TARGET_GAS)
+
/* Define preprocessor macros for the -march and -mtune options.
PREFIX is either _MIPS_ARCH or _MIPS_TUNE, INFO is the selected
processor. If INFO's canonical name is "foo", define PREFIX to
{ \
builtin_define ("_LANGUAGE_OBJECTIVE_C"); \
builtin_define ("__LANGUAGE_OBJECTIVE_C"); \
- /* Bizzare, but needed at least for Irix. */ \
+ /* Bizarre, but needed at least for Irix. */ \
builtin_define_std ("LANGUAGE_C"); \
builtin_define ("_LANGUAGE_C"); \
} \
N_("Use GP relative sdata/sbss sections (now ignored)")}, \
{"gpopt", 0, \
N_("Use GP relative sdata/sbss sections (now ignored)")}, \
- {"no-gpOPT", 0, \
+ {"no-gpOPT", 0, \
N_("Don't use GP relative sdata/sbss sections (now ignored)")}, \
- {"no-gpopt", 0, \
+ {"no-gpopt", 0, \
N_("Don't use GP relative sdata/sbss sections (now ignored)")}, \
{"stats", 0, \
N_("Output compiler statistics (now ignored)")}, \
N_("Work around early 4300 hardware bug")}, \
{"no-fix4300", -MASK_4300_MUL_FIX, \
N_("Don't work around early 4300 hardware bug")}, \
+ {"fix-sb1", MASK_FIX_SB1, \
+ N_("Work around errata for early SB-1 revision 2 cores")}, \
+ {"no-fix-sb1", -MASK_FIX_SB1, \
+ N_("Don't work around errata for early SB-1 revision 2 cores")}, \
{"check-zero-division",-MASK_NO_CHECK_ZERO_DIV, \
N_("Trap on integer divide by zero")}, \
{"no-check-zero-division", MASK_NO_CHECK_ZERO_DIV, \
N_("Generate mips16 code") }, \
{"no-mips16", -MASK_MIPS16, \
N_("Generate normal-mode code") }, \
+ {"xgot", MASK_XGOT, \
+ N_("Lift restrictions on GOT size") }, \
+ {"no-xgot", -MASK_XGOT, \
+ N_("Do not lift restrictions on GOT size") }, \
{"debug", MASK_DEBUG, \
NULL}, \
{"debuga", MASK_DEBUG_A, \
N_("Specify an ABI"), 0}, \
{ "ips", &mips_isa_string, \
N_("Specify a Standard MIPS ISA"), 0}, \
- { "entry", &mips_entry_string, \
- N_("Use mips16 entry/exit psuedo ops"), 0}, \
{ "no-flush-func", &mips_cache_flush_func, \
N_("Don't call any cache flush functions"), 0}, \
{ "flush-func=", &mips_cache_flush_func, \
|| ISA_MIPS32R2 \
|| ISA_MIPS64)
-/* This is a catch all for the other new mips4 instructions: indexed load and
- indexed prefetch instructions, the FP madd and msub instructions,
- and the FP recip and recip sqrt instructions */
+/* This is a catch all for other mips4 instructions: indexed load, the
+ FP madd and msub instructions, and the FP recip and recip sqrt
+ instructions. */
#define ISA_HAS_FP4 ((ISA_MIPS4 \
|| ISA_MIPS64) \
&& !TARGET_MIPS16)
|| TARGET_SR71K \
))
-/* ISA has data prefetch instruction. */
+/* ISA has data prefetch instructions. This controls use of 'pref'. */
#define ISA_HAS_PREFETCH ((ISA_MIPS4 \
|| ISA_MIPS32 \
|| ISA_MIPS32R2 \
|| ISA_MIPS64) \
&& !TARGET_MIPS16)
+/* ISA has data indexed prefetch instructions. This controls use of
+ 'prefx', along with TARGET_HARD_FLOAT and TARGET_DOUBLE_FLOAT.
+ (prefx is a cop1x instruction, so can only be used if FP is
+ enabled.) */
+#define ISA_HAS_PREFETCHX ((ISA_MIPS4 \
+ || ISA_MIPS64) \
+ && !TARGET_MIPS16)
+
/* True if trunc.w.s and trunc.w.d are real (not synthetic)
instructions. Both require TARGET_HARD_FLOAT, and trunc.w.d
also requires TARGET_DOUBLE_FLOAT. */
#define ISA_HAS_FCMP_DELAY (mips_isa <= 3)
/* True if mflo and mfhi can be immediately followed by instructions
- which write to the HI and LO registers. Most targets require a
- two-instruction gap. */
-#define ISA_HAS_HILO_INTERLOCKS (TARGET_MIPS5500 || TARGET_SB1)
+ which write to the HI and LO registers.
+
+ According to MIPS specifications, MIPS ISAs I, II, and III need
+ (at least) two instructions between the reads of HI/LO and
+ instructions which write them, and later ISAs do not. Contradicting
+ the MIPS specifications, some MIPS IV processor user manuals (e.g.
+ the UM for the NEC Vr5000) document needing the instructions between
+ HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
+ MIPS64 and later ISAs to have the interlocks, plus any specific
+ earlier-ISA CPUs for which CPU documentation declares that the
+ instructions are really interlocked. */
+#define ISA_HAS_HILO_INTERLOCKS (ISA_MIPS32 \
+ || ISA_MIPS32R2 \
+ || ISA_MIPS64 \
+ || TARGET_MIPS5500)
\f
/* Add -G xx support. */
#endif
/* Beginning with gas 2.13, -mdebug must be passed to correctly handle COFF
- and stabs debugging info. */
+ debugging info. */
#if ((TARGET_CPU_DEFAULT | TARGET_DEFAULT) & MASK_GAS) != 0
/* GAS */
-#define MDEBUG_ASM_SPEC "%{!gdwarf*:-mdebug} %{gdwarf*:-no-mdebug}"
+#define MDEBUG_ASM_SPEC "%{gcoff*:-mdebug} \
+ %{!gcoff*:-no-mdebug}"
#else /* not GAS */
#define MDEBUG_ASM_SPEC ""
#endif /* not GAS */
%{membedded-pic} \
%{mabi=32:-32}%{mabi=n32:-n32}%{mabi=64:-64}%{mabi=n64:-64} \
%{mabi=eabi} %{mabi=o64} %{!mabi*: %(asm_abi_default_spec)} \
-%{mgp32} %{mgp64} %{march=*} \
+%{mgp32} %{mgp64} %{march=*} %{mxgot:-xgot} \
%(target_asm_spec) \
%(subtarget_asm_spec)"
is an initializer with a subgrouping for each command option.
Each subgrouping contains a string constant, that defines the
- specification name, and a string constant that used by the GNU CC driver
+ specification name, and a string constant that used by the GCC driver
program.
Do not define this macro if it does not need to do anything. */
\f
#define DBX_DEBUGGING_INFO 1 /* generate stabs (OSF/rose) */
#define MIPS_DEBUGGING_INFO 1 /* MIPS specific debugging info */
+#define DWARF2_DEBUGGING_INFO 1 /* dwarf2 debugging info */
+
+#ifndef PREFERRED_DEBUGGING_TYPE
+#define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
+#endif
/* By default, turn on GDB extensions. */
#define DEFAULT_GDB_EXTENSIONS 1
#define DBX_REGISTER_NUMBER(REGNO) mips_dbx_regno[ (REGNO) ]
/* The mapping from gcc register number to DWARF 2 CFA column number. */
-#define DWARF_FRAME_REGNUM(REG) \
- (REG == GP_REG_FIRST + 31 ? DWARF_FRAME_RETURN_COLUMN : REG)
+#define DWARF_FRAME_REGNUM(REG) (REG)
/* The DWARF 2 CFA column which tracks the return address. */
-#define DWARF_FRAME_RETURN_COLUMN (FP_REG_LAST + 1)
+#define DWARF_FRAME_RETURN_COLUMN (GP_REG_FIRST + 31)
+
+/* The DWARF 2 CFA column which tracks the return address from a
+ signal handler context. */
+#define SIGNAL_UNWIND_RETURN_COLUMN (FP_REG_LAST + 1)
/* Before the prologue, RA lives in r31. */
#define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (VOIDmode, GP_REG_FIRST + 31)
SFmode register saves. */
#define DWARF_CIE_DATA_ALIGNMENT 4
-#define FIND_BASE_TERM(X) mips_delegitimize_address (X)
-
/* Correct the offset of automatic variables and arguments. Note that
the MIPS debug format wants all automatic variables and arguments
to be in terms of the virtual frame pointer (stack pointer before
|| TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
-/* Force right-alignment for small varargs in 32 bit little_endian mode */
-
-#define PAD_VARARGS_DOWN (TARGET_64BIT ? BYTES_BIG_ENDIAN : !BYTES_BIG_ENDIAN)
-
-/* Arguments declared as 'char' or 'short' in a prototype should be
- passed as 'int's. */
-#define PROMOTE_PROTOTYPES 1
+#define PAD_VARARGS_DOWN \
+ (FUNCTION_ARG_PADDING (TYPE_MODE (type), type) == downward)
/* Define if operations between registers always perform the operation
on the full register even if a narrower mode is specified. */
#define WORD_REGISTER_OPERATIONS
-/* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
- will either zero-extend or sign-extend. The value of this macro should
- be the code that says which one of the two operations is implicitly
- done, NIL if none.
-
- When in 64 bit mode, mips_move_1word will sign extend SImode and CCmode
+/* When in 64 bit mode, move insns will sign extend SImode and CCmode
moves. All other references are zero extended. */
#define LOAD_EXTEND_OP(MODE) \
(TARGET_64BIT && ((MODE) == SImode || (MODE) == CCmode) \
/* Define if loading short immediate values into registers sign extends. */
#define SHORT_IMMEDIATES_SIGN_EXTEND
-
-
-/* Define this if function arguments should also be promoted using the above
- procedure. */
-#define PROMOTE_FUNCTION_ARGS
-
-/* Likewise, if the function return value is promoted. */
-#define PROMOTE_FUNCTION_RETURN
-
\f
/* Standard register usage. */
- 8 condition code registers
- 2 accumulator registers (hi and lo)
- 32 registers each for coprocessors 0, 2 and 3
- - 6 dummy entries that were used at various times in the past. */
+ - 3 fake registers:
+ - ARG_POINTER_REGNUM
+ - FRAME_POINTER_REGNUM
+ - FAKE_CALL_REGNO (see the comment above load_callsi for details)
+ - 3 dummy entries that were used at various times in the past. */
#define FIRST_PSEUDO_REGISTER 176
/* Register to use for pushing function arguments. */
#define STACK_POINTER_REGNUM (GP_REG_FIRST + 29)
-/* Base register for access to local variables of the function. We
- pretend that the frame pointer is $1, and then eliminate it to
- HARD_FRAME_POINTER_REGNUM. We can get away with this because $1 is
- a fixed register, and will not be used for anything else. */
-#define FRAME_POINTER_REGNUM (GP_REG_FIRST + 1)
+/* These two registers don't really exist: they get eliminated to either
+ the stack or hard frame pointer. */
+#define ARG_POINTER_REGNUM 77
+#define FRAME_POINTER_REGNUM 78
/* $30 is not available on the mips16, so we use $17 as the frame
pointer. */
This is computed in `reload', in reload1.c. */
#define FRAME_POINTER_REQUIRED (current_function_calls_alloca)
-/* Base register for access to arguments of the function. */
-#define ARG_POINTER_REGNUM GP_REG_FIRST
-
/* Register in which static-chain is passed to a function. */
#define STATIC_CHAIN_REGNUM (GP_REG_FIRST + 2)
-/* Pass structure addresses as an "invisible" first argument. */
-#define STRUCT_VALUE 0
+/* Registers used as temporaries in prologue/epilogue code. If we're
+ generating mips16 code, these registers must come from the core set
+ of 8. The prologue register mustn't conflict with any incoming
+ arguments, the static chain pointer, or the frame pointer. The
+ epilogue temporary mustn't conflict with the return registers, the
+ frame pointer, the EH stack adjustment, or the EH data registers. */
-/* Mips registers used in prologue/epilogue code when the stack frame
- is larger than 32K bytes. These registers must come from the
- scratch register set, and not used for passing and returning
- arguments and any other information used in the calling sequence
- (such as pic). Must start at 12, since t0/t3 are parameter passing
- registers in the 64 bit ABI. */
+#define MIPS_PROLOGUE_TEMP_REGNUM (GP_REG_FIRST + 3)
+#define MIPS_EPILOGUE_TEMP_REGNUM (GP_REG_FIRST + (TARGET_MIPS16 ? 6 : 8))
-#define MIPS_TEMP1_REGNUM (GP_REG_FIRST + 12)
-#define MIPS_TEMP2_REGNUM (GP_REG_FIRST + 13)
+#define MIPS_PROLOGUE_TEMP(MODE) gen_rtx_REG (MODE, MIPS_PROLOGUE_TEMP_REGNUM)
+#define MIPS_EPILOGUE_TEMP(MODE) gen_rtx_REG (MODE, MIPS_EPILOGUE_TEMP_REGNUM)
/* Define this macro if it is as good or better to call a constant
function address than to call an address kept in a register. */
sub-initializer must be suitable as an initializer for the type
`HARD_REG_SET' which is defined in `hard-reg-set.h'. */
-#define REG_CLASS_CONTENTS \
-{ \
+#define REG_CLASS_CONTENTS \
+{ \
{ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* no registers */ \
{ 0x0003000c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 nonarg regs */\
{ 0x000300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 registers */ \
{ 0x01000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 T register */ \
{ 0x010300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 and T regs */ \
{ 0x02000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* SVR4 PIC function address register */ \
- { 0xfdffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* Every other GPR */ \
+ { 0xfdffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* Every other GPR */ \
{ 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* integer registers */ \
{ 0x00000000, 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* floating registers*/ \
{ 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* hi register */ \
{ 0x00000000, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, /* lo register */ \
{ 0x00000000, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x00000000 }, /* mul/div registers */ \
- { 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000, 0x00000000 }, /* cop0 registers */ \
- { 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000 }, /* cop2 registers */ \
- { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff }, /* cop3 registers */ \
+ { 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000, 0x00000000 }, /* cop0 registers */ \
+ { 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000 }, /* cop2 registers */ \
+ { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff }, /* cop3 registers */ \
{ 0xffffffff, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* union classes */ \
{ 0xffffffff, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, \
{ 0x00000000, 0xffffffff, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, \
- { 0xffffffff, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000, 0x00000000 }, \
- { 0xffffffff, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000 }, \
- { 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff }, \
- { 0x00000000, 0x00000000, 0xffff0000, 0xffffffff, 0xffffffff, 0x0000ffff }, \
- { 0xffffffff, 0x00000000, 0xffff0000, 0xffffffff, 0xffffffff, 0x0000ffff }, \
+ { 0xffffffff, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000, 0x00000000 }, \
+ { 0xffffffff, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000 }, \
+ { 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff }, \
+ { 0x00000000, 0x00000000, 0xffff0000, 0xffffffff, 0xffffffff, 0x0000ffff }, \
+ { 0xffffffff, 0x00000000, 0xffff0000, 0xffffffff, 0xffffffff, 0x0000ffff }, \
{ 0x00000000, 0x00000000, 0x000007f8, 0x00000000, 0x00000000, 0x00000000 }, /* status registers */ \
{ 0xffffffff, 0xffffffff, 0xffff07ff, 0xffffffff, 0xffffffff, 0x0000ffff } /* all registers */ \
}
((C) == 'G' \
&& (VALUE) == CONST0_RTX (GET_MODE (VALUE)))
-/* True if OP is a constant that should not be moved into $25.
- We need this because many versions of gas treat 'la $25,foo' as
- part of a call sequence and allow a global 'foo' to be lazily bound. */
-
-#define DANGEROUS_FOR_LA25_P(OP) \
- (TARGET_ABICALLS \
- && !TARGET_EXPLICIT_RELOCS \
- && mips_global_pic_constant_p (OP))
-
/* Letters in the range `Q' through `U' may be defined in a
machine-dependent fashion to stand for arbitrary operand types.
The machine description macro `EXTRA_CONSTRAINT' is passed the
constraint has often been used in linux and glibc code.
`S' is for legitimate constant call addresses.
`T' is for constant move_operands that cannot be safely loaded into $25.
- `U' is for constant move_operands that can be safely loaded into $25. */
+ `U' is for constant move_operands that can be safely loaded into $25.
+ `W' is for memory references that are based on a member of BASE_REG_CLASS.
+ This is true for all non-mips16 references (although it can somtimes
+ be indirect if !TARGET_EXPLICIT_RELOCS). For mips16, it excludes
+ stack and constant-pool references. */
#define EXTRA_CONSTRAINT(OP,CODE) \
(((CODE) == 'Q') ? const_arith_operand (OP, VOIDmode) \
&& call_insn_operand (OP, VOIDmode)) \
: ((CODE) == 'T') ? (CONSTANT_P (OP) \
&& move_operand (OP, VOIDmode) \
- && DANGEROUS_FOR_LA25_P (OP)) \
+ && mips_dangerous_for_la25_p (OP)) \
: ((CODE) == 'U') ? (CONSTANT_P (OP) \
&& move_operand (OP, VOIDmode) \
- && !DANGEROUS_FOR_LA25_P (OP)) \
+ && !mips_dangerous_for_la25_p (OP)) \
+ : ((CODE) == 'W') ? (GET_CODE (OP) == MEM \
+ && memory_operand (OP, VOIDmode) \
+ && (!TARGET_MIPS16 \
+ || (!stack_operand (OP, VOIDmode) \
+ && !CONSTANT_P (XEXP (OP, 0))))) \
: FALSE)
-/* Given an rtx X being reloaded into a reg required to be
- in class CLASS, return the class of reg to actually use.
- In general this is just CLASS; but on some machines
- in some cases it is preferable to use a more restrictive class. */
+/* Say which of the above are memory constraints. */
+#define EXTRA_MEMORY_CONSTRAINT(C, STR) ((C) == 'R' || (C) == 'W')
#define PREFERRED_RELOAD_CLASS(X,CLASS) \
- ((CLASS) != ALL_REGS \
- ? (! TARGET_MIPS16 \
- ? (CLASS) \
- : ((CLASS) != GR_REGS \
- ? (CLASS) \
- : M16_REGS)) \
- : ((GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT \
- || GET_MODE_CLASS (GET_MODE (X)) == MODE_COMPLEX_FLOAT) \
- ? (TARGET_SOFT_FLOAT \
- ? (TARGET_MIPS16 ? M16_REGS : GR_REGS) \
- : FP_REGS) \
- : ((GET_MODE_CLASS (GET_MODE (X)) == MODE_INT \
- || GET_MODE (X) == VOIDmode) \
- ? (TARGET_MIPS16 ? M16_REGS : GR_REGS) \
- : (CLASS))))
+ mips_preferred_reload_class (X, CLASS)
/* Certain machines have the property that some registers cannot be
copied to some other registers without using memory. Define this
In mips16 mode, we need a frame pointer for a large frame; otherwise,
reload may be unable to compute the address of a local variable,
since there is no way to add a large constant to the stack pointer
- without using a temporary register.
-
- Also, for some mips16 instructions (eg lwu), we can't eliminate the
- frame pointer for the stack pointer. These instructions are
- only generated in TARGET_64BIT mode. */
+ without using a temporary register. */
#define CAN_ELIMINATE(FROM, TO) \
((TO) == HARD_FRAME_POINTER_REGNUM \
|| ((TO) == STACK_POINTER_REGNUM && !frame_pointer_needed \
- && !(TARGET_MIPS16 && TARGET_64BIT) \
&& (!TARGET_MIPS16 \
|| compute_frame_size (get_frame_size ()) < 32768)))
/* 1 if N is a possible register number for a function value.
On the MIPS, R2 R3 and F0 F2 are the only register thus used.
- Currently, R2 and F0 are only implemented here (C has no complex type) */
+ Currently, R2 and F0 are only implemented here (C has no complex type) */
#define FUNCTION_VALUE_REGNO_P(N) ((N) == GP_RETURN || (N) == FP_RETURN \
|| (LONG_DOUBLE_TYPE_SIZE == 128 && FP_RETURN != GP_RETURN \
|| (IN_RANGE((N), FP_ARG_FIRST, FP_ARG_LAST) \
&& ((N) % FP_INC == 0) && mips_abi != ABI_O64)) \
&& !fixed_regs[N])
-
-#define RETURN_IN_MEMORY(TYPE) mips_return_in_memory (TYPE)
-
-#define SETUP_INCOMING_VARARGS(CUM,MODE,TYPE,PRETEND_SIZE,NO_RTL) \
- (PRETEND_SIZE) = mips_setup_incoming_varargs (&(CUM), (MODE), \
- (TYPE), (NO_RTL))
\f
-#define STRICT_ARGUMENT_NAMING (mips_abi != ABI_32 && mips_abi != ABI_O64)
-
/* This structure has to cope with two different argument allocation
schemes. Most MIPS ABIs view the arguments as a struct, of which the
first N words go in registers and the rest go on the stack. If I < N,
/* True if the function has a prototype. */
int prototype;
-
- /* When a structure does not take up a full register, the argument
- should sometimes be shifted left so that it occupies the high part
- of the register. These two fields describe an array of ashl
- patterns for doing this. See function_arg_advance, which creates
- the shift patterns, and function_arg, which returns them when given
- a VOIDmode argument. */
- unsigned int num_adjusts;
- rtx adjust[BIGGEST_MAX_ARGS_IN_REGISTERS];
} CUMULATIVE_ARGS;
/* Initialize a variable CUM of type CUMULATIVE_ARGS
for a call to a function whose data type is FNTYPE.
- For a library call, FNTYPE is 0.
-
-*/
+ For a library call, FNTYPE is 0. */
-#define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT) \
+#define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
init_cumulative_args (&CUM, FNTYPE, LIBNAME) \
/* Update the data in CUM to advance over an argument
#define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \
function_arg_pass_by_reference (&CUM, MODE, TYPE, NAMED)
-#define FUNCTION_ARG_PADDING(MODE, TYPE) \
- (! BYTES_BIG_ENDIAN \
- ? upward \
- : (((MODE) == BLKmode \
- ? ((TYPE) && TREE_CODE (TYPE_SIZE (TYPE)) == INTEGER_CST \
- && int_size_in_bytes (TYPE) < (PARM_BOUNDARY / BITS_PER_UNIT))\
- : (GET_MODE_BITSIZE (MODE) < PARM_BOUNDARY \
- && (mips_abi == ABI_32 \
- || mips_abi == ABI_O64 \
- || mips_abi == ABI_EABI \
- || GET_MODE_CLASS (MODE) == MODE_INT))) \
- ? downward : upward))
+#define FUNCTION_ARG_PADDING(MODE, TYPE) \
+ (mips_pad_arg_upward (MODE, TYPE) ? upward : downward)
+
+#define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \
+ (mips_pad_reg_upward (MODE, TYPE) ? upward : downward)
#define FUNCTION_ARG_CALLEE_COPIES(CUM, MODE, TYPE, NAMED) \
(mips_abi == ABI_EABI && (NAMED) \
&& FUNCTION_ARG_PASS_BY_REFERENCE (CUM, MODE, TYPE, NAMED))
-/* Modified version of the macro in expr.h. */
+/* Modified version of the macro in expr.h. Only return true if
+ the type has a variable size or if the front end requires it
+ to be passed by reference. */
#define MUST_PASS_IN_STACK(MODE,TYPE) \
((TYPE) != 0 \
&& (TREE_CODE (TYPE_SIZE (TYPE)) != INTEGER_CST \
- || TREE_ADDRESSABLE (TYPE) \
- || ((MODE) == BLKmode \
- && mips_abi != ABI_32 && mips_abi != ABI_O64 \
- && ! ((TYPE) != 0 && TREE_CODE (TYPE_SIZE (TYPE)) == INTEGER_CST \
- && 0 == (int_size_in_bytes (TYPE) \
- % (PARM_BOUNDARY / BITS_PER_UNIT))) \
- && (FUNCTION_ARG_PADDING (MODE, TYPE) \
- == (BYTES_BIG_ENDIAN ? upward : downward)))))
+ || TREE_ADDRESSABLE (TYPE)))
/* True if using EABI and varargs can be passed in floating-point
registers. Under these conditions, we need a more complex form
: ((LOC) + 15) & ~15)
\f
-/* Define the `__builtin_va_list' type for the ABI. */
-#define BUILD_VA_LIST_TYPE(VALIST) \
- (VALIST) = mips_build_va_list ()
-
/* Implement `va_start' for varargs and stdarg. */
#define EXPAND_BUILTIN_VA_START(valist, nextarg) \
mips_va_start (valist, nextarg)
\
func_addr = plus_constant (ADDR, 32); \
chain_addr = plus_constant (func_addr, GET_MODE_SIZE (ptr_mode)); \
- emit_move_insn (gen_rtx_MEM (ptr_mode, func_addr), \
- gen_lowpart (ptr_mode, force_reg (Pmode, FUNC))); \
- emit_move_insn (gen_rtx_MEM (ptr_mode, chain_addr), \
- gen_lowpart (ptr_mode, force_reg (Pmode, CHAIN))); \
+ emit_move_insn (gen_rtx_MEM (ptr_mode, func_addr), FUNC); \
+ emit_move_insn (gen_rtx_MEM (ptr_mode, chain_addr), CHAIN); \
\
/* Flush both caches. We need to flush the data cache in case \
the system has a write-back cache. */ \
\f
/* Addressing modes, and classification of registers for them. */
-/* These assume that REGNO is a hard or pseudo reg number.
- They give nonzero only if REGNO is a hard reg of the suitable class
- or a pseudo reg currently allocated to a suitable hard reg.
- These definitions are NOT overridden anywhere. */
-
-#define BASE_REG_P(regno, mode) \
- (TARGET_MIPS16 \
- ? (M16_REG_P (regno) \
- || (regno) == FRAME_POINTER_REGNUM \
- || (regno) == ARG_POINTER_REGNUM \
- || ((regno) == STACK_POINTER_REGNUM \
- && (GET_MODE_SIZE (mode) == 4 \
- || GET_MODE_SIZE (mode) == 8))) \
- : GP_REG_P (regno))
-
-#define GP_REG_OR_PSEUDO_STRICT_P(regno, mode) \
- BASE_REG_P((regno < FIRST_PSEUDO_REGISTER) ? (int) regno : reg_renumber[regno], \
- (mode))
-
-#define GP_REG_OR_PSEUDO_NONSTRICT_P(regno, mode) \
- (((regno) >= FIRST_PSEUDO_REGISTER) || (BASE_REG_P ((regno), (mode))))
-
-#define REGNO_OK_FOR_INDEX_P(regno) 0
-#define REGNO_MODE_OK_FOR_BASE_P(regno, mode) \
- GP_REG_OR_PSEUDO_STRICT_P ((regno), (mode))
+#define REGNO_OK_FOR_INDEX_P(REGNO) 0
+#define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
+ mips_regno_mode_ok_for_base_p (REGNO, MODE, 1)
/* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
and check its validity for a certain class.
#ifndef REG_OK_STRICT
#define REG_MODE_OK_FOR_BASE_P(X, MODE) \
- mips_reg_mode_ok_for_base_p (X, MODE, 0)
+ mips_regno_mode_ok_for_base_p (REGNO (X), MODE, 0)
#else
#define REG_MODE_OK_FOR_BASE_P(X, MODE) \
- mips_reg_mode_ok_for_base_p (X, MODE, 1)
+ mips_regno_mode_ok_for_base_p (REGNO (X), MODE, 1)
#endif
#define REG_OK_FOR_INDEX_P(X) 0
#define CONSTANT_ADDRESS_P(X) \
(CONSTANT_P (X) && mips_legitimate_address_p (SImode, X, 0))
-
-/* Nonzero if the constant value X is a legitimate general operand.
- It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
-
- At present, GAS doesn't understand li.[sd], so don't allow it
- to be generated at present. Also, the MIPS assembler does not
- grok li.d Infinity. */
-
-/* ??? SGI Irix 6 assembler fails for CONST address, so reject them.
- Note that the Irix 6 assembler problem may already be fixed.
- Note also that the GET_CODE (X) == CONST test catches the mips16
- gp pseudo reg (see mips16_gp_pseudo_reg) deciding it is not
- a LEGITIMATE_CONSTANT. If we ever want mips16 and ABI_N32 or
- ABI_64 to work together, we'll need to fix this. */
#define LEGITIMATE_CONSTANT_P(X) (mips_const_insns (X) > 0)
#define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
\f
/* Specify the machine mode that this machine uses
for the index in the tablejump instruction.
- ??? Using HImode in mips16 mode can cause overflow. However, the
- overflow is no more likely than the overflow in a branch
- instruction. Large functions can currently break in both ways. */
+ ??? Using HImode in mips16 mode can cause overflow. */
#define CASE_VECTOR_MODE \
(TARGET_MIPS16 ? HImode : ptr_mode)
that the constraints of the insn are met. Setting a cost of
other than 2 will allow reload to verify that the constraints are
met. You should do this if the `movM' pattern's constraints do
- not allow such copying. */
+ not allow such copying. */
#define REGISTER_MOVE_COST(MODE, FROM, TO) \
mips_register_move_cost (MODE, FROM, TO)
#define PREDICATE_CODES \
{"uns_arith_operand", { REG, CONST_INT, SUBREG, ADDRESSOF }}, \
{"symbolic_operand", { CONST, SYMBOL_REF, LABEL_REF }}, \
- {"const_arith_operand", { CONST, CONST_INT }}, \
+ {"global_got_operand", { CONST, SYMBOL_REF, LABEL_REF }}, \
+ {"local_got_operand", { CONST, SYMBOL_REF, LABEL_REF }}, \
+ {"const_arith_operand", { CONST_INT }}, \
+ {"small_data_pattern", { SET, PARALLEL, UNSPEC, \
+ UNSPEC_VOLATILE }}, \
{"arith_operand", { REG, CONST_INT, CONST, SUBREG, ADDRESSOF }}, \
{"reg_or_0_operand", { REG, CONST_INT, CONST_DOUBLE, SUBREG, ADDRESSOF }}, \
{"small_int", { CONST_INT }}, \
- {"mips_const_double_ok", { CONST_DOUBLE }}, \
{"const_float_1_operand", { CONST_DOUBLE }}, \
- {"simple_memory_operand", { MEM, SUBREG }}, \
+ {"reg_or_const_float_1_operand", { CONST_DOUBLE, REG}}, \
{"equality_op", { EQ, NE }}, \
{"cmp_op", { EQ, NE, GT, GE, GTU, GEU, LT, LE, \
LTU, LEU }}, \
{"move_operand", { CONST_INT, CONST_DOUBLE, CONST, \
SYMBOL_REF, LABEL_REF, SUBREG, \
REG, MEM}}, \
+ {"stack_operand", { MEM }}, \
{"consttable_operand", { LABEL_REF, SYMBOL_REF, CONST_INT, \
CONST_DOUBLE, CONST }}, \
{"fcc_register_operand", { REG, SUBREG }}, \
&mips_reg_names[175][0] \
}
-/* print-rtl.c can't use REGISTER_NAMES, since it depends on mips.c.
- So define this for it. */
-#define DEBUG_REGISTER_NAMES \
-{ \
- "$0", "at", "v0", "v1", "a0", "a1", "a2", "a3", \
- "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", \
- "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", \
- "t8", "t9", "k0", "k1", "gp", "sp", "$fp", "ra", \
- "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", \
- "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", \
- "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", \
- "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", \
- "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", \
- "$fcc5","$fcc6","$fcc7","$rap", "", "", "", "", \
- "$c0r0", "$c0r1", "$c0r2", "$c0r3", "$c0r4", "$c0r5", "$c0r6", "$c0r7",\
- "$c0r8", "$c0r9", "$c0r10","$c0r11","$c0r12","$c0r13","$c0r14","$c0r15",\
- "$c0r16","$c0r17","$c0r18","$c0r19","$c0r20","$c0r21","$c0r22","$c0r23",\
- "$c0r24","$c0r25","$c0r26","$c0r27","$c0r28","$c0r29","$c0r30","$c0r31",\
- "$c2r0", "$c2r1", "$c2r2", "$c2r3", "$c2r4", "$c2r5", "$c2r6", "$c2r7",\
- "$c2r8", "$c2r9", "$c2r10","$c2r11","$c2r12","$c2r13","$c2r14","$c2r15",\
- "$c2r16","$c2r17","$c2r18","$c2r19","$c2r20","$c2r21","$c2r22","$c2r23",\
- "$c2r24","$c2r25","$c2r26","$c2r27","$c2r28","$c2r29","$c2r30","$c2r31",\
- "$c3r0", "$c3r1", "$c3r2", "$c3r3", "$c3r4", "$c3r5", "$c3r6", "$c3r7",\
- "$c3r8", "$c3r9", "$c3r10","$c3r11","$c3r12","$c3r13","$c3r14","$c3r15",\
- "$c3r16","$c3r17","$c3r18","$c3r19","$c3r20","$c3r21","$c3r22","$c3r23",\
- "$c3r24","$c3r25","$c3r26","$c3r27","$c3r28","$c3r29","$c3r30","$c3r31"\
-}
-
/* If defined, a C initializer for an array of structures
containing a name and a register number. This macro defines
additional names for hard registers, thus allowing the `asm'
#define ASM_OUTPUT_EXTERNAL(STREAM,DECL,NAME) \
mips_output_external(STREAM,DECL,NAME)
-
/* This is how to declare a function name. The actual work of
emitting the label is moved to function_prologue, so that we can
get the line number correctly emitted before the .ent directive,
#undef ASM_DECLARE_FUNCTION_NAME
#define ASM_DECLARE_FUNCTION_NAME(STREAM,NAME,DECL)
+#ifndef FUNCTION_NAME_ALREADY_DECLARED
+#define FUNCTION_NAME_ALREADY_DECLARED 0
+#endif
+
/* This is how to store into the string LABEL
the symbol_ref name of an internal numbered label where
PREFIX is the class of label and NUM is the number within the class.
do { \
if (TARGET_EMBEDDED_PIC || TARGET_MIPS16) \
function_section (current_function_decl); \
- (*targetm.asm_out.internal_label) (FILE, PREFIX, NUM); \
+ (*targetm.asm_out.internal_label) (FILE, PREFIX, NUM); \
} while (0)
/* This is how to output an assembler line
/* This is how to output a string. */
#undef ASM_OUTPUT_ASCII
#define ASM_OUTPUT_ASCII(STREAM, STRING, LEN) \
- mips_output_ascii (STREAM, STRING, LEN)
+ mips_output_ascii (STREAM, STRING, LEN, "\t.ascii\t")
/* Output #ident as a in the read-only data section. */
#undef ASM_OUTPUT_IDENT
&& mips_abi != ABI_32 \
&& mips_abi != ABI_O64)
\f
-/* We need to use a special set of functions to handle hard floating
- point code in mips16 mode. */
-
-#ifndef INIT_SUBTARGET_OPTABS
-#define INIT_SUBTARGET_OPTABS
-#endif
-
-#define INIT_TARGET_OPTABS \
-do \
- { \
- if (! TARGET_MIPS16 || ! mips16_hard_float) \
- INIT_SUBTARGET_OPTABS; \
- else \
- { \
- add_optab->handlers[(int) SFmode].libfunc = \
- init_one_libfunc ("__mips16_addsf3"); \
- sub_optab->handlers[(int) SFmode].libfunc = \
- init_one_libfunc ("__mips16_subsf3"); \
- smul_optab->handlers[(int) SFmode].libfunc = \
- init_one_libfunc ("__mips16_mulsf3"); \
- sdiv_optab->handlers[(int) SFmode].libfunc = \
- init_one_libfunc ("__mips16_divsf3"); \
- \
- eqsf2_libfunc = init_one_libfunc ("__mips16_eqsf2"); \
- nesf2_libfunc = init_one_libfunc ("__mips16_nesf2"); \
- gtsf2_libfunc = init_one_libfunc ("__mips16_gtsf2"); \
- gesf2_libfunc = init_one_libfunc ("__mips16_gesf2"); \
- ltsf2_libfunc = init_one_libfunc ("__mips16_ltsf2"); \
- lesf2_libfunc = init_one_libfunc ("__mips16_lesf2"); \
- \
- floatsisf_libfunc = \
- init_one_libfunc ("__mips16_floatsisf"); \
- fixsfsi_libfunc = \
- init_one_libfunc ("__mips16_fixsfsi"); \
- \
- if (TARGET_DOUBLE_FLOAT) \
- { \
- add_optab->handlers[(int) DFmode].libfunc = \
- init_one_libfunc ("__mips16_adddf3"); \
- sub_optab->handlers[(int) DFmode].libfunc = \
- init_one_libfunc ("__mips16_subdf3"); \
- smul_optab->handlers[(int) DFmode].libfunc = \
- init_one_libfunc ("__mips16_muldf3"); \
- sdiv_optab->handlers[(int) DFmode].libfunc = \
- init_one_libfunc ("__mips16_divdf3"); \
- \
- extendsfdf2_libfunc = \
- init_one_libfunc ("__mips16_extendsfdf2"); \
- truncdfsf2_libfunc = \
- init_one_libfunc ("__mips16_truncdfsf2"); \
- \
- eqdf2_libfunc = \
- init_one_libfunc ("__mips16_eqdf2"); \
- nedf2_libfunc = \
- init_one_libfunc ("__mips16_nedf2"); \
- gtdf2_libfunc = \
- init_one_libfunc ("__mips16_gtdf2"); \
- gedf2_libfunc = \
- init_one_libfunc ("__mips16_gedf2"); \
- ltdf2_libfunc = \
- init_one_libfunc ("__mips16_ltdf2"); \
- ledf2_libfunc = \
- init_one_libfunc ("__mips16_ledf2"); \
- \
- floatsidf_libfunc = \
- init_one_libfunc ("__mips16_floatsidf"); \
- fixdfsi_libfunc = \
- init_one_libfunc ("__mips16_fixdfsi"); \
- } \
- } \
- } \
-while (0)
#define DFMODE_NAN \
unsigned short DFbignan[4] = {0x7ff7, 0xffff, 0xffff, 0xffff}; \
we need to load our GP. We don't preserve $gp or $ra, since each
init/fini chunk is supposed to initialize $gp, and crti/crtn
already take care of preserving $ra and, when appropriate, $gp. */
-#if _MIPS_SIM == _MIPS_SIM_ABI32
+#if (defined _ABIO32 && _MIPS_SIM == _ABIO32)
#define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
asm (SECTION_OP "\n\
.set noreorder\n\
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