;;
;; You should have received a copy of the GNU General Public License
;; along with GCC; see the file COPYING. If not, write to
-;; the Free Software Foundation, 59 Temple Place - Suite 330,
-;; Boston, MA 02111-1307, USA.
+;; the Free Software Foundation, 51 Franklin Street, Fifth Floor,
+;; Boston, MA 02110-1301, USA.
(define_insn "*movcc_v2sf_<mode>"
[(set (match_operand:V2SF 0 "register_operand" "=f,f")
(set_attr "mode" "SF")])
;----------------------------------------------------------------------------
-; Floating Point Comparisions for Scalars
+; Floating Point Comparisons for Scalars
;----------------------------------------------------------------------------
(define_insn "mips_cabs_cond_<fmt>"
;----------------------------------------------------------------------------
-; Floating Point Comparisions for Four Singles
+; Floating Point Comparisons for Four Singles
;----------------------------------------------------------------------------
(define_insn_and_split "mips_c_cond_4s"
;----------------------------------------------------------------------------
-; Floating Point Comparisions for Paired Singles
+; Floating Point Comparisons for Paired Singles
;----------------------------------------------------------------------------
(define_insn "mips_c_cond_ps"
[(set_attr "type" "fcmp")
(set_attr "mode" "FPSW")])
+;; An expander for generating an scc operation.
+(define_expand "scc_ps"
+ [(set (match_operand:CCV2 0)
+ (unspec:CCV2 [(match_operand 1)] UNSPEC_SCC))])
+
+(define_insn "s<code>_ps"
+ [(set (match_operand:CCV2 0 "register_operand" "=z")
+ (unspec:CCV2
+ [(fcond (match_operand:V2SF 1 "register_operand" "f")
+ (match_operand:V2SF 2 "register_operand" "f"))]
+ UNSPEC_SCC))]
+ "TARGET_PAIRED_SINGLE_FLOAT"
+ "c.<fcond>.ps\t%0,%1,%2"
+ [(set_attr "type" "fcmp")
+ (set_attr "mode" "FPSW")])
+
+(define_insn "s<code>_ps"
+ [(set (match_operand:CCV2 0 "register_operand" "=z")
+ (unspec:CCV2
+ [(swapped_fcond (match_operand:V2SF 1 "register_operand" "f")
+ (match_operand:V2SF 2 "register_operand" "f"))]
+ UNSPEC_SCC))]
+ "TARGET_PAIRED_SINGLE_FLOAT"
+ "c.<swapped_fcond>.ps\t%0,%2,%1"
+ [(set_attr "type" "fcmp")
+ (set_attr "mode" "FPSW")])
;----------------------------------------------------------------------------
; Floating Point Branch Instructions.
; Branch on Any of Four Floating Point Condition Codes True
(define_insn "bc1any4t"
[(set (pc)
- (if_then_else (ne:CCV4 (match_operand:CCV4 0 "register_operand" "z")
- (const_int 0))
+ (if_then_else (ne (match_operand:CCV4 0 "register_operand" "z")
+ (const_int 0))
(label_ref (match_operand 1 "" ""))
(pc)))]
"TARGET_MIPS3D"
; Branch on Any of Four Floating Point Condition Codes False
(define_insn "bc1any4f"
[(set (pc)
- (if_then_else (ne:CCV4 (match_operand:CCV4 0 "register_operand" "z")
- (const_int -1))
+ (if_then_else (ne (match_operand:CCV4 0 "register_operand" "z")
+ (const_int -1))
(label_ref (match_operand 1 "" ""))
(pc)))]
"TARGET_MIPS3D"
; Branch on Any of Two Floating Point Condition Codes True
(define_insn "bc1any2t"
[(set (pc)
- (if_then_else (ne:CCV2 (match_operand:CCV2 0 "register_operand" "z")
- (const_int 0))
+ (if_then_else (ne (match_operand:CCV2 0 "register_operand" "z")
+ (const_int 0))
(label_ref (match_operand 1 "" ""))
(pc)))]
"TARGET_MIPS3D"
; Branch on Any of Two Floating Point Condition Codes False
(define_insn "bc1any2f"
[(set (pc)
- (if_then_else (ne:CCV2 (match_operand:CCV2 0 "register_operand" "z")
- (const_int -1))
+ (if_then_else (ne (match_operand:CCV2 0 "register_operand" "z")
+ (const_int -1))
(label_ref (match_operand 1 "" ""))
(pc)))]
"TARGET_MIPS3D"
[(set_attr "type" "branch")
(set_attr "mode" "none")])
+; Used to access one register in a CCV2 pair. Operand 0 is the register
+; pair and operand 1 is the index of the register we want (a CONST_INT).
+(define_expand "single_cc"
+ [(ne (unspec:CC [(match_operand 0) (match_operand 1)] UNSPEC_SINGLE_CC)
+ (const_int 0))])
+
+; This is a normal floating-point branch pattern, but rather than check
+; a single CCmode register, it checks one register in a CCV2 pair.
+; Operand 2 is the register pair and operand 3 is the index of the
+; register we want.
+(define_insn "*branch_upper_lower"
+ [(set (pc)
+ (if_then_else
+ (match_operator 0 "equality_operator"
+ [(unspec:CC [(match_operand:CCV2 2 "register_operand" "z")
+ (match_operand 3 "const_int_operand")]
+ UNSPEC_SINGLE_CC)
+ (const_int 0)])
+ (label_ref (match_operand 1 "" ""))
+ (pc)))]
+ "TARGET_HARD_FLOAT"
+{
+ operands[2]
+ = gen_rtx_REG (CCmode, REGNO (operands[2]) + INTVAL (operands[3]));
+ return mips_output_conditional_branch (insn, operands,
+ MIPS_BRANCH ("b%F0", "%2,%1"),
+ MIPS_BRANCH ("b%W0", "%2,%1"));
+}
+ [(set_attr "type" "branch")
+ (set_attr "mode" "none")])
+
+; As above, but with the sense of the condition reversed.
+(define_insn "*branch_upper_lower_inverted"
+ [(set (pc)
+ (if_then_else
+ (match_operator 0 "equality_operator"
+ [(unspec:CC [(match_operand:CCV2 2 "register_operand" "z")
+ (match_operand 3 "const_int_operand")]
+ UNSPEC_SINGLE_CC)
+ (const_int 0)])
+ (pc)
+ (label_ref (match_operand 1 "" ""))))]
+ "TARGET_HARD_FLOAT"
+{
+ operands[2]
+ = gen_rtx_REG (CCmode, REGNO (operands[2]) + INTVAL (operands[3]));
+ return mips_output_conditional_branch (insn, operands,
+ MIPS_BRANCH ("b%W0", "%2,%1"),
+ MIPS_BRANCH ("b%F0", "%2,%1"));
+}
+ [(set_attr "type" "branch")
+ (set_attr "mode" "none")])
+
;----------------------------------------------------------------------------
; Floating Point Reduced Precision Reciprocal Square Root Instructions.
;----------------------------------------------------------------------------
UNSPEC_RSQRT1))]
"TARGET_MIPS3D"
"rsqrt1.<fmt>\t%0,%1"
- [(set_attr "type" "frsqrt")
+ [(set_attr "type" "frsqrt1")
(set_attr "mode" "<UNITMODE>")])
(define_insn "mips_rsqrt2_<fmt>"
UNSPEC_RSQRT2))]
"TARGET_MIPS3D"
"rsqrt2.<fmt>\t%0,%1,%2"
- [(set_attr "type" "frsqrt")
+ [(set_attr "type" "frsqrt2")
(set_attr "mode" "<UNITMODE>")])
(define_insn "mips_recip1_<fmt>"
UNSPEC_RECIP1))]
"TARGET_MIPS3D"
"recip1.<fmt>\t%0,%1"
- [(set_attr "type" "frdiv")
+ [(set_attr "type" "frdiv1")
(set_attr "mode" "<UNITMODE>")])
(define_insn "mips_recip2_<fmt>"
UNSPEC_RECIP2))]
"TARGET_MIPS3D"
"recip2.<fmt>\t%0,%1,%2"
- [(set_attr "type" "frdiv")
+ [(set_attr "type" "frdiv2")
(set_attr "mode" "<UNITMODE>")])
+
+(define_expand "vcondv2sf"
+ [(set (match_operand:V2SF 0 "register_operand")
+ (if_then_else:V2SF
+ (match_operator 3 ""
+ [(match_operand:V2SF 4 "register_operand")
+ (match_operand:V2SF 5 "register_operand")])
+ (match_operand:V2SF 1 "register_operand")
+ (match_operand:V2SF 2 "register_operand")))]
+ "TARGET_PAIRED_SINGLE_FLOAT"
+{
+ mips_expand_vcondv2sf (operands[0], operands[1], operands[2],
+ GET_CODE (operands[3]), operands[4], operands[5]);
+ DONE;
+})
+
+(define_expand "sminv2sf3"
+ [(set (match_operand:V2SF 0 "register_operand")
+ (smin:V2SF (match_operand:V2SF 1 "register_operand")
+ (match_operand:V2SF 2 "register_operand")))]
+ "TARGET_PAIRED_SINGLE_FLOAT"
+{
+ mips_expand_vcondv2sf (operands[0], operands[1], operands[2],
+ LE, operands[1], operands[2]);
+ DONE;
+})
+
+(define_expand "smaxv2sf3"
+ [(set (match_operand:V2SF 0 "register_operand")
+ (smax:V2SF (match_operand:V2SF 1 "register_operand")
+ (match_operand:V2SF 2 "register_operand")))]
+ "TARGET_PAIRED_SINGLE_FLOAT"
+{
+ mips_expand_vcondv2sf (operands[0], operands[1], operands[2],
+ LE, operands[2], operands[1]);
+ DONE;
+})
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