(load_sda_base_32): New pattern. Loads sda base address on medium model.

[pf3gnuchains/gcc-fork.git] / gcc / config / m32r / m32r.md

diff --git a/gcc/config/m32r/m32r.md b/gcc/config/m32r/m32r.md
index 8cd2679..d65282d 100644 (file)
--- a/gcc/config/m32r/m32r.md
+++ b/gcc/config/m32r/m32r.md
@@ -31,7 +31,9 @@
   [(UNSPEC_LOAD_SDA_BASE       2)
    (UNSPEC_SET_CBIT            3)
    (UNSPEC_PIC_LOAD_ADDR       4)
-   (UNSPEC_GET_PC              5)])
+   (UNSPEC_GET_PC              5)
+   (UNSPEC_GOTOFF              6)
+   ])
 
 ;; Insn type.  Used to default other attribute values.
 (define_attr "type"
@@ -169,7 +171,7 @@
 
 ;; Load/store instructions do 6 stages: IF D E MEM1 MEM2 WB.
 ;; MEM1 may require more than one cycle depending on locality.  We
-;; optimistically assume all memory is nearby, ie. MEM1 takes only
+;; optimistically assume all memory is nearby, i.e. MEM1 takes only
 ;; one cycle.  Hence, ready latency is 3.
 
 ;; The M32Rx can do short load/store only on the left pipe.
@@ -501,6 +503,14 @@
     operands[2] = gen_reg_rtx (SImode);
 }")
 
+(define_insn "*load_sda_base_32"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+       (unspec:SI [(const_int 0)] UNSPEC_LOAD_SDA_BASE))]
+  "TARGET_ADDR32"
+  "seth %0,%#shigh(_SDA_BASE_)\;add3 %0,%0,%#low(_SDA_BASE_)"
+  [(set_attr "type" "multi")
+   (set_attr "length" "8")])
+
 (define_insn "*load_sda_base"
   [(set (match_operand:SI 0 "register_operand" "=r")
        (unspec:SI [(const_int 0)] UNSPEC_LOAD_SDA_BASE))]
@@ -2570,6 +2580,14 @@
   "ld24 %0,%#%1"
   [(set_attr "type" "int4")])
 
+(define_insn "gotoff_load_addr"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+        (unspec:SI [(match_operand 1 "" "")] UNSPEC_GOTOFF))]
+  "flag_pic"
+  "seth %0, %#shigh(%1@GOTOFF)\;add3 %0, %0, low(%1@GOTOFF)"
+  [(set_attr "type"    "int4")
+   (set_attr "length"  "8")])
+
 ;; Load program counter insns.
 
 (define_insn "get_pc"