-;; Machine description of the Mitsubishi M32R cpu for GNU C compiler
-;; Copyright (C) 1996, 1997 Free Software Foundation, Inc.
+;; Machine description of the Renesas M32R cpu for GNU C compiler
+;; Copyright (C) 1996, 1997, 1998, 1999, 2001, 2003, 2004
+; Free Software Foundation, Inc.
-;; This file is part of GNU CC.
+;; This file is part of GCC.
-;; GNU CC is free software; you can redistribute it and/or modify
-;; it under the terms of the GNU General Public License as published by
-;; the Free Software Foundation; either version 2, or (at your option)
-;; any later version.
+;; GCC is free software; you can redistribute it and/or modify it
+;; under the terms of the GNU General Public License as published
+;; by the Free Software Foundation; either version 2, or (at your
+;; option) any later version.
-;; GNU CC is distributed in the hope that it will be useful,
-;; but WITHOUT ANY WARRANTY; without even the implied warranty of
-;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-;; GNU General Public License for more details.
+;; GCC is distributed in the hope that it will be useful, but WITHOUT
+;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+;; License for more details.
;; You should have received a copy of the GNU General Public License
-;; along with GNU CC; see the file COPYING. If not, write to
+;; along with GCC; see the file COPYING. If not, write to
;; the Free Software Foundation, 59 Temple Place - Suite 330,
;; Boston, MA 02111-1307, USA.
;; See file "rtl.def" for documentation on define_insn, match_*, et. al.
-
-;; unspec usage
-;; 0 - blockage
-;; 1 - flush_icache
-;; 2 - load_sda_base
\f
+;; UNSPEC_VOLATILE usage
+(define_constants
+ [(UNSPECV_BLOCKAGE 0)
+ (UNSPECV_FLUSH_ICACHE 1)])
+
+;; UNSPEC usage
+(define_constants
+ [(UNSPEC_LOAD_SDA_BASE 2)
+ (UNSPEC_SET_CBIT 3)
+ (UNSPEC_PIC_LOAD_ADDR 4)
+ (UNSPEC_GET_PC 5)
+ (UNSPEC_GOTOFF 6)
+ ])
+
;; Insn type. Used to default other attribute values.
-;; move4 = 4 byte move
(define_attr "type"
- "move,move4,load,store,unary,binary,compare,shift,mul,div,uncond_branch,branch,call,multi,misc"
+ "int2,int4,load2,load4,load8,store2,store4,store8,shift2,shift4,mul2,div4,uncond_branch,branch,call,multi,misc"
(const_string "misc"))
;; Length in bytes.
(define_attr "length" ""
- (cond [(eq_attr "type" "move,unary,shift,mul,div")
+ (cond [(eq_attr "type" "int2,load2,store2,shift2,mul2")
(const_int 2)
- (eq_attr "type" "binary")
- (if_then_else (match_operand 2 "register_operand" "")
- (const_int 2) (const_int 4))
-
- (eq_attr "type" "compare")
- (if_then_else (match_operand 1 "register_operand" "")
- (const_int 2) (const_int 4))
-
- (eq_attr "type" "load")
- (if_then_else (match_operand 1 "memreg_operand" "")
- (const_int 2) (const_int 4))
-
- (eq_attr "type" "store")
- (if_then_else (match_operand 0 "memreg_operand" "")
- (const_int 2) (const_int 4))
+ (eq_attr "type" "int4,load4,store4,shift4,div4")
+ (const_int 4)
(eq_attr "type" "multi")
(const_int 8)
(define_asm_attributes
[(set_attr "length" "4")
(set_attr "type" "multi")])
+
+;; Whether an instruction is short (16-bit) or long (32-bit).
+(define_attr "insn_size" "short,long"
+ (if_then_else (eq_attr "type" "int2,load2,store2,shift2,mul2")
+ (const_string "short")
+ (const_string "long")))
+
+;; The target CPU we're compiling for.
+(define_attr "cpu" "m32r,m32r2,m32rx"
+ (cond [(ne (symbol_ref "TARGET_M32RX") (const_int 0))
+ (const_string "m32rx")
+ (ne (symbol_ref "TARGET_M32R2") (const_int 0))
+ (const_string "m32r2")]
+ (const_string "m32r")))
+
+;; Defines the pipeline where an instruction can be executed on.
+;; For the M32R, a short instruction can execute one of the two pipes.
+;; For the M32Rx, the restrictions are modelled in the second
+;; condition of this attribute definition.
+(define_attr "m32r_pipeline" "either,s,o,long"
+ (cond [(and (eq_attr "cpu" "m32r")
+ (eq_attr "insn_size" "short"))
+ (const_string "either")
+ (eq_attr "insn_size" "!short")
+ (const_string "long")]
+ (cond [(eq_attr "type" "int2")
+ (const_string "either")
+ (eq_attr "type" "load2,store2,shift2,uncond_branch,branch,call")
+ (const_string "o")
+ (eq_attr "type" "mul2")
+ (const_string "s")]
+ (const_string "long"))))
\f
-;; Function units of the M32R
-;; Units that take one cycle do not need to be specified.
-
-;; (define_function_unit {name} {num-units} {n-users} {test}
-;; {ready-delay} {issue-delay} [{conflict-list}])
-
-;; References to loaded registers should wait a cycle.
-;; Memory with load-delay of 1 (i.e. 2 cycle load).
-(define_function_unit "memory" 1 1 (eq_attr "type" "load") 2 0)
-
-;; Hack to get GCC to better pack the instructions.
-;; We pretend there is a separate long function unit that conflicts with
-;; both the left and right 16 bit insn slots.
-
-(define_function_unit "left" 1 1
- (eq_attr "length" "2")
- 1 0
- [(not (eq_attr "length" "2"))])
-
-(define_function_unit "right" 1 1
- (eq_attr "length" "2")
- 1 0
- [(not (eq_attr "length" "2"))])
-
-(define_function_unit "long" 1 1
- (not (eq_attr "length" "2"))
- 1 0
- [(eq_attr "length" "2")])
+;; ::::::::::::::::::::
+;; ::
+;; :: Pipeline description
+;; ::
+;; ::::::::::::::::::::
+
+;; This model is based on Chapter 2, Appendix 3 and Appendix 4 of the
+;; "M32R-FPU Software Manual", Revision 1.01, plus additional information
+;; obtained by our best friend and mine, Google.
+;;
+;; The pipeline is modelled as a fetch unit, and a core with a memory unit,
+;; two execution units, where "fetch" models IF and D, "memory" for MEM1
+;; and MEM2, and "EXEC" for E, E1, E2, EM, and EA. Writeback and
+;; bypasses are not modelled.
+(define_automaton "m32r")
+
+;; We pretend there are two short (16 bits) instruction fetchers. The
+;; "s" short fetcher cannot be reserved until the "o" short fetcher is
+;; reserved. Some instructions reserve both the left and right fetchers.
+;; These fetch units are a hack to get GCC to better pack the instructions
+;; for the M32Rx processor, which has two execution pipes.
+;;
+;; In reality there is only one decoder, which can decode either two 16 bits
+;; instructions, or a single 32 bits instruction.
+;;
+;; Note, "fetch" models both the IF and the D pipeline stages.
+;;
+;; The m32rx core has two execution pipes. We name them o_E and s_E.
+;; In addition, there's a memory unit.
+
+(define_cpu_unit "o_IF,s_IF,o_E,s_E,memory" "m32r")
+
+;; Prevent the s pipe from being reserved before the o pipe.
+(absence_set "s_IF" "o_IF")
+(absence_set "s_E" "o_E")
+
+;; On the M32Rx, long instructions execute on both pipes, so reserve
+;; both fetch slots and both pipes.
+(define_reservation "long_IF" "o_IF+s_IF")
+(define_reservation "long_E" "o_E+s_E")
+
+;; ::::::::::::::::::::
+
+;; Simple instructions do 4 stages: IF D E WB. WB is not modelled.
+;; Hence, ready latency is 1.
+(define_insn_reservation "short_left" 1
+ (and (eq_attr "m32r_pipeline" "o")
+ (and (eq_attr "insn_size" "short")
+ (eq_attr "type" "!load2")))
+ "o_IF,o_E")
+
+(define_insn_reservation "short_right" 1
+ (and (eq_attr "m32r_pipeline" "s")
+ (and (eq_attr "insn_size" "short")
+ (eq_attr "type" "!load2")))
+ "s_IF,s_E")
+
+(define_insn_reservation "short_either" 1
+ (and (eq_attr "m32r_pipeline" "either")
+ (and (eq_attr "insn_size" "short")
+ (eq_attr "type" "!load2")))
+ "o_IF|s_IF,o_E|s_E")
+
+(define_insn_reservation "long_m32r" 1
+ (and (eq_attr "cpu" "m32r")
+ (and (eq_attr "insn_size" "long")
+ (eq_attr "type" "!load4,load8")))
+ "long_IF,long_E")
+
+(define_insn_reservation "long_m32rx" 2
+ (and (eq_attr "m32r_pipeline" "long")
+ (and (eq_attr "insn_size" "long")
+ (eq_attr "type" "!load4,load8")))
+ "long_IF,long_E")
+
+;; Load/store instructions do 6 stages: IF D E MEM1 MEM2 WB.
+;; MEM1 may require more than one cycle depending on locality. We
+;; optimistically assume all memory is nearby, i.e. MEM1 takes only
+;; one cycle. Hence, ready latency is 3.
+
+;; The M32Rx can do short load/store only on the left pipe.
+(define_insn_reservation "short_load_left" 3
+ (and (eq_attr "m32r_pipeline" "o")
+ (and (eq_attr "insn_size" "short")
+ (eq_attr "type" "load2")))
+ "o_IF,o_E,memory*2")
+
+(define_insn_reservation "short_load" 3
+ (and (eq_attr "m32r_pipeline" "either")
+ (and (eq_attr "insn_size" "short")
+ (eq_attr "type" "load2")))
+ "s_IF|o_IF,s_E|o_E,memory*2")
+
+(define_insn_reservation "long_load" 3
+ (and (eq_attr "cpu" "m32r")
+ (and (eq_attr "insn_size" "long")
+ (eq_attr "type" "load4,load8")))
+ "long_IF,long_E,memory*2")
+
+(define_insn_reservation "long_load_m32rx" 3
+ (and (eq_attr "m32r_pipeline" "long")
+ (eq_attr "type" "load4,load8"))
+ "long_IF,long_E,memory*2")
+
\f
;; Expand prologue as RTL
-;; ??? Unfinished.
-
-;(define_expand "prologue"
-; [(const_int 1)]
-; ""
-; "
-;{
-;}")
+(define_expand "prologue"
+ [(const_int 1)]
+ ""
+ "
+{
+ m32r_expand_prologue ();
+ DONE;
+}")
+
\f
;; Move instructions.
;;
""
"
{
+ /* Fixup PIC cases. */
+ if (flag_pic)
+ {
+ if (symbolic_operand (operands[1], QImode))
+ {
+ if (reload_in_progress || reload_completed)
+ operands[1] = m32r_legitimize_pic_address (operands[1], operands[0]);
+ else
+ operands[1] = m32r_legitimize_pic_address (operands[1], NULL_RTX);
+ }
+ }
+
/* Everything except mem = const or mem = mem can be done easily.
Objects in the small data area are handled too. */
}")
(define_insn "*movqi_insn"
- [(set (match_operand:QI 0 "move_dest_operand" "=r,r,r,r,m")
- (match_operand:QI 1 "move_src_operand" "r,I,JQR,m,r"))]
+ [(set (match_operand:QI 0 "move_dest_operand" "=r,r,r,r,r,T,m")
+ (match_operand:QI 1 "move_src_operand" "r,I,JQR,T,m,r,r"))]
"register_operand (operands[0], QImode) || register_operand (operands[1], QImode)"
"@
mv %0,%1
ldi %0,%#%1
ldi %0,%#%1
ldub %0,%1
+ ldub %0,%1
+ stb %1,%0
stb %1,%0"
- [(set_attr "type" "move,move,move4,load,store")])
+ [(set_attr "type" "int2,int2,int4,load2,load4,store2,store4")
+ (set_attr "length" "2,2,4,2,4,2,4")])
(define_expand "movhi"
[(set (match_operand:HI 0 "general_operand" "")
""
"
{
+ /* Fixup PIC cases. */
+ if (flag_pic)
+ {
+ if (symbolic_operand (operands[1], HImode))
+ {
+ if (reload_in_progress || reload_completed)
+ operands[1] = m32r_legitimize_pic_address (operands[1], operands[0]);
+ else
+ operands[1] = m32r_legitimize_pic_address (operands[1], NULL_RTX);
+ }
+ }
+
/* Everything except mem = const or mem = mem can be done easily. */
if (GET_CODE (operands[0]) == MEM)
}")
(define_insn "*movhi_insn"
- [(set (match_operand:HI 0 "move_dest_operand" "=r,r,r,r,r,m")
- (match_operand:HI 1 "move_src_operand" "r,I,JQR,K,m,r"))]
+ [(set (match_operand:HI 0 "move_dest_operand" "=r,r,r,r,r,r,T,m")
+ (match_operand:HI 1 "move_src_operand" "r,I,JQR,K,T,m,r,r"))]
"register_operand (operands[0], HImode) || register_operand (operands[1], HImode)"
"@
mv %0,%1
ldi %0,%#%1
ld24 %0,%#%1
lduh %0,%1
+ lduh %0,%1
+ sth %1,%0
sth %1,%0"
- [(set_attr "type" "move,move,move4,move4,load,store")])
+ [(set_attr "type" "int2,int2,int4,int4,load2,load4,store2,store4")
+ (set_attr "length" "2,2,4,4,2,4,2,4")])
+
+(define_expand "movsi_push"
+ [(set (mem:SI (pre_dec:SI (match_operand:SI 0 "register_operand" "")))
+ (match_operand:SI 1 "register_operand" ""))]
+ ""
+ "")
+
+(define_expand "movsi_pop"
+ [(set (match_operand:SI 0 "register_operand" "")
+ (mem:SI (post_inc:SI (match_operand:SI 1 "register_operand" ""))))]
+ ""
+ "")
(define_expand "movsi"
[(set (match_operand:SI 0 "general_operand" "")
""
"
{
+ /* Fixup PIC cases. */
+ if (flag_pic)
+ {
+ if (symbolic_operand (operands[1], SImode))
+ {
+ if (reload_in_progress || reload_completed)
+ operands[1] = m32r_legitimize_pic_address (operands[1], operands[0]);
+ else
+ operands[1] = m32r_legitimize_pic_address (operands[1], NULL_RTX);
+ }
+ }
+
/* Everything except mem = const or mem = mem can be done easily. */
if (GET_CODE (operands[0]) == MEM)
}
}")
-(define_insn "*movsi_insn"
- [(set (match_operand:SI 0 "move_dest_operand" "=r,r,r,r,r,r,r,m")
;; ??? Do we need a const_double constraint here for large unsigned values?
- (match_operand:SI 1 "move_src_operand" "r,I,J,MQ,L,N,m,r"))]
+(define_insn "*movsi_insn"
+ [(set (match_operand:SI 0 "move_dest_operand" "=r,r,r,r,r,r,r,r,r,T,S,m")
+ (match_operand:SI 1 "move_src_operand" "r,I,J,MQ,L,n,T,U,m,r,r,r"))]
"register_operand (operands[0], SImode) || register_operand (operands[1], SImode)"
- "@
- mv %0,%1
- ldi %0,%#%1 ; %X1
- ldi %0,%#%1 ; %X1
- ld24 %0,%#%1 ; %X1
- seth %0,%#%T1
- seth %0,%#%T1\;or3 %0,%0,%#%B1
- ld %0,%1
- st %1,%0"
- [(set_attr "type" "move,move,move4,move4,move4,multi,load,store")])
+ "*
+{
+ if (GET_CODE (operands[0]) == REG || GET_CODE (operands[1]) == SUBREG)
+ {
+ switch (GET_CODE (operands[1]))
+ {
+ HOST_WIDE_INT value;
+
+ default:
+ break;
+
+ case REG:
+ case SUBREG:
+ return \"mv %0,%1\";
+
+ case MEM:
+ if (GET_CODE (XEXP (operands[1], 0)) == POST_INC
+ && XEXP (XEXP (operands[1], 0), 0) == stack_pointer_rtx)
+ return \"pop %0\";
+
+ return \"ld %0,%1\";
+
+ case CONST_INT:
+ value = INTVAL (operands[1]);
+ if (INT16_P (value))
+ return \"ldi %0,%#%1\\t; %X1\";
+
+ if (UINT24_P (value))
+ return \"ld24 %0,%#%1\\t; %X1\";
+
+ if (UPPER16_P (value))
+ return \"seth %0,%#%T1\\t; %X1\";
+
+ return \"#\";
+
+ case CONST:
+ case SYMBOL_REF:
+ case LABEL_REF:
+ if (TARGET_ADDR24)
+ return \"ld24 %0,%#%1\";
+
+ return \"#\";
+ }
+ }
+
+ else if (GET_CODE (operands[0]) == MEM
+ && (GET_CODE (operands[1]) == REG || GET_CODE (operands[1]) == SUBREG))
+ {
+ if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC
+ && XEXP (XEXP (operands[0], 0), 0) == stack_pointer_rtx)
+ return \"push %1\";
+
+ return \"st %1,%0\";
+ }
+
+ abort ();
+}"
+ [(set_attr "type" "int2,int2,int4,int4,int4,multi,load2,load2,load4,store2,store2,store4")
+ (set_attr "length" "2,2,4,4,4,8,2,2,4,2,2,4")])
; Try to use a four byte / two byte pair for constants not loadable with
; ldi, ld24, seth.
}
}
- /* Can't use any two byte insn, fall back to seth/or3. */
- operands[2] = GEN_INT ((val) & 0xffff0000);
+ /* Can't use any two byte insn, fall back to seth/or3. Use ~0xffff instead
+ of 0xffff0000, since the later fails on a 64-bit host. */
+ operands[2] = GEN_INT ((val) & ~0xffff);
operands[3] = GEN_INT ((val) & 0xffff);
}")
+(define_split
+ [(set (match_operand:SI 0 "register_operand" "")
+ (match_operand:SI 1 "seth_add3_operand" ""))]
+ "TARGET_ADDR32"
+ [(set (match_dup 0)
+ (high:SI (match_dup 1)))
+ (set (match_dup 0)
+ (lo_sum:SI (match_dup 0)
+ (match_dup 1)))]
+ "")
+
;; Small data area support.
;; The address of _SDA_BASE_ is loaded into a register and all objects in
;; the small data area are indexed off that. This is done for each reference
(define_expand "movsi_sda"
[(set (match_dup 2)
- (unspec [(const_int 0)] 2))
+ (unspec:SI [(const_int 0)] UNSPEC_LOAD_SDA_BASE))
(set (match_operand:SI 0 "register_operand" "")
(lo_sum:SI (match_dup 2)
(match_operand:SI 1 "small_data_operand" "")))]
operands[2] = gen_reg_rtx (SImode);
}")
+(define_insn "*load_sda_base_32"
+ [(set (match_operand:SI 0 "register_operand" "=r")
+ (unspec:SI [(const_int 0)] UNSPEC_LOAD_SDA_BASE))]
+ "TARGET_ADDR32"
+ "seth %0,%#shigh(_SDA_BASE_)\;add3 %0,%0,%#low(_SDA_BASE_)"
+ [(set_attr "type" "multi")
+ (set_attr "length" "8")])
+
(define_insn "*load_sda_base"
[(set (match_operand:SI 0 "register_operand" "=r")
- (unspec [(const_int 0)] 2))]
+ (unspec:SI [(const_int 0)] UNSPEC_LOAD_SDA_BASE))]
""
"ld24 %0,#_SDA_BASE_"
- [(set_attr "type" "move4")])
+ [(set_attr "type" "int4")
+ (set_attr "length" "4")])
;; 32 bit address support.
(high:SI (match_operand 1 "symbolic_operand" "")))]
""
"seth %0,%#shigh(%1)"
- [(set_attr "type" "move4")])
+ [(set_attr "type" "int4")
+ (set_attr "length" "4")])
(define_insn "lo_sum_si"
[(set (match_operand:SI 0 "register_operand" "=r")
(match_operand:SI 2 "immediate_operand" "in")))]
""
"add3 %0,%1,%#%B2"
- [(set_attr "length" "4")])
+ [(set_attr "type" "int4")
+ (set_attr "length" "4")])
(define_expand "movdi"
[(set (match_operand:DI 0 "general_operand" "")
""
"
{
+ /* Fixup PIC cases. */
+ if (flag_pic)
+ {
+ if (symbolic_operand (operands[1], DImode))
+ {
+ if (reload_in_progress || reload_completed)
+ operands[1] = m32r_legitimize_pic_address (operands[1], operands[0]);
+ else
+ operands[1] = m32r_legitimize_pic_address (operands[1], NULL_RTX);
+ }
+ }
+
/* Everything except mem = const or mem = mem can be done easily. */
if (GET_CODE (operands[0]) == MEM)
operands[1] = force_reg (DImode, operands[1]);
-
- if (CONSTANT_P (operands[1])
- && ! easy_di_const (operands[1]))
- {
- rtx mem = force_const_mem (DImode, operands[1]);
- rtx reg = ((reload_in_progress || reload_completed)
- ? copy_to_suggested_reg (XEXP (mem, 0),
- gen_rtx (REG, Pmode, REGNO (operands[0])),
- Pmode)
- : force_reg (Pmode, XEXP (mem, 0)));
- operands[1] = change_address (mem, DImode, reg);
- }
}")
(define_insn "*movdi_insn"
- [(set (match_operand:DI 0 "move_dest_operand" "=r,r,r,m")
- (match_operand:DI 1 "move_double_src_operand" "r,nG,m,r"))]
+ [(set (match_operand:DI 0 "move_dest_operand" "=r,r,r,r,m")
+ (match_operand:DI 1 "move_double_src_operand" "r,nG,F,m,r"))]
"register_operand (operands[0], DImode) || register_operand (operands[1], DImode)"
- "*
-{
- switch (which_alternative)
- {
- case 0 :
- /* We normally copy the low-numbered register first. However, if
- the first register operand 0 is the same as the second register of
- operand 1, we must copy in the opposite order. */
- if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
- return \"mv %R0,%R1\;mv %0,%1\";
- else
- return \"mv %0,%1\;mv %R0,%R1\";
- case 1 :
- return \"#\";
- case 2 :
- /* If the low-address word is used in the address, we must load it
- last. Otherwise, load it first. Note that we cannot have
- auto-increment in that case since the address register is known to be
- dead. */
- if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
- operands [1], 0))
- {
- return \"ld %R0,%R1\;ld %0,%1\";
- }
- else
- {
- /* Try to use auto-inc addressing if we can. */
- if (GET_CODE (XEXP (operands[1], 0)) == REG
- && dead_or_set_p (insn, XEXP (operands[1], 0)))
- {
- operands[1] = XEXP (operands[1], 0);
- return \"ld %0,@%1+\;ld %R0,@%1\";
- }
- return \"ld %0,%1\;ld %R0,%R1\";
- }
- case 3 :
- /* Try to use auto-inc addressing if we can. */
- if (GET_CODE (XEXP (operands[0], 0)) == REG
- && dead_or_set_p (insn, XEXP (operands[0], 0)))
- {
- operands[0] = XEXP (operands[0], 0);
- return \"st %1,@%0\;st %R1,@+%0\";
- }
- return \"st %1,%0\;st %R1,%R0\";
- }
-}"
- [(set_attr "type" "multi,multi,multi,multi")
- (set_attr "length" "4,4,6,6")])
+ "#"
+ [(set_attr "type" "multi,multi,multi,load8,store8")
+ (set_attr "length" "4,4,16,6,6")])
(define_split
- [(set (match_operand:DI 0 "register_operand" "")
- (match_operand:DI 1 "const_double_operand" ""))]
+ [(set (match_operand:DI 0 "move_dest_operand" "")
+ (match_operand:DI 1 "move_double_src_operand" ""))]
"reload_completed"
- [(set (match_dup 2) (match_dup 4))
- (set (match_dup 3) (match_dup 5))]
- "
-{
- operands[2] = gen_rtx (SUBREG, SImode, operands[0], WORDS_BIG_ENDIAN == 0);
- operands[3] = gen_rtx (SUBREG, SImode, operands[0], WORDS_BIG_ENDIAN != 0);
- split_double (operands[1], operands + 4, operands + 5);
-}")
+ [(match_dup 2)]
+ "operands[2] = gen_split_move_double (operands);")
\f
;; Floating point move insns.
""
"
{
+ /* Fixup PIC cases. */
+ if (flag_pic)
+ {
+ if (symbolic_operand (operands[1], SFmode))
+ {
+ if (reload_in_progress || reload_completed)
+ operands[1] = m32r_legitimize_pic_address (operands[1], operands[0]);
+ else
+ operands[1] = m32r_legitimize_pic_address (operands[1], NULL_RTX);
+ }
+ }
+
/* Everything except mem = const or mem = mem can be done easily. */
if (GET_CODE (operands[0]) == MEM)
}")
(define_insn "*movsf_insn"
- [(set (match_operand:SF 0 "move_dest_operand" "=r,r,r,m")
- (match_operand:SF 1 "move_src_operand" "r,F,m,r"))]
+ [(set (match_operand:SF 0 "move_dest_operand" "=r,r,r,r,r,T,S,m")
+ (match_operand:SF 1 "move_src_operand" "r,F,U,S,m,r,r,r"))]
"register_operand (operands[0], SFmode) || register_operand (operands[1], SFmode)"
- "*
-{
- switch (which_alternative)
- {
- case 0 :
- return \"mv %0,%1\";
- case 1 :
- {
- REAL_VALUE_TYPE r;
- long l;
- REAL_VALUE_FROM_CONST_DOUBLE (r, operands[1]);
- REAL_VALUE_TO_TARGET_SINGLE (r, l);
- operands[1] = GEN_INT (l);
- if (l == 0)
- return \"ldi %0,%#0\";
- if ((l & 0xffff) == 0)
- return \"seth %0,%#%T1\";
- else
- return \"seth %0,%#%T1\;or3 %0,%0,%#%B1\";
- }
- case 2 :
- return \"ld %0,%1\";
- case 3 :
- return \"st %1,%0\";
- }
-}"
+ "@
+ mv %0,%1
+ #
+ ld %0,%1
+ ld %0,%1
+ ld %0,%1
+ st %1,%0
+ st %1,%0
+ st %1,%0"
;; ??? Length of alternative 1 is either 2, 4 or 8.
- [(set_attr "type" "move,multi,load,store")])
+ [(set_attr "type" "int2,multi,load2,load2,load4,store2,store2,store4")
+ (set_attr "length" "2,8,2,2,4,2,2,4")])
+
+(define_split
+ [(set (match_operand:SF 0 "register_operand" "")
+ (match_operand:SF 1 "const_double_operand" ""))]
+ "reload_completed"
+ [(set (match_dup 2) (match_dup 3))]
+ "
+{
+ operands[2] = operand_subword (operands[0], 0, 0, SFmode);
+ operands[3] = operand_subword (operands[1], 0, 0, SFmode);
+}")
(define_expand "movdf"
[(set (match_operand:DF 0 "general_operand" "")
""
"
{
+ /* Fixup PIC cases. */
+ if (flag_pic)
+ {
+ if (symbolic_operand (operands[1], DFmode))
+ {
+ if (reload_in_progress || reload_completed)
+ operands[1] = m32r_legitimize_pic_address (operands[1], operands[0]);
+ else
+ operands[1] = m32r_legitimize_pic_address (operands[1], NULL_RTX);
+ }
+ }
+
/* Everything except mem = const or mem = mem can be done easily. */
if (GET_CODE (operands[0]) == MEM)
operands[1] = force_reg (DFmode, operands[1]);
-
- if (GET_CODE (operands[1]) == CONST_DOUBLE
- && ! easy_df_const (operands[1]))
- {
- rtx mem = force_const_mem (DFmode, operands[1]);
- rtx reg = ((reload_in_progress || reload_completed)
- ? copy_to_suggested_reg (XEXP (mem, 0),
- gen_rtx (REG, Pmode, REGNO (operands[0])),
- Pmode)
- : force_reg (Pmode, XEXP (mem, 0)));
- operands[1] = change_address (mem, DFmode, reg);
- }
}")
(define_insn "*movdf_insn"
[(set (match_operand:DF 0 "move_dest_operand" "=r,r,r,m")
- (match_operand:DF 1 "move_double_src_operand" "r,H,m,r"))]
+ (match_operand:DF 1 "move_double_src_operand" "r,F,m,r"))]
"register_operand (operands[0], DFmode) || register_operand (operands[1], DFmode)"
- "*
-{
- switch (which_alternative)
- {
- case 0 :
- /* We normally copy the low-numbered register first. However, if
- the first register operand 0 is the same as the second register of
- operand 1, we must copy in the opposite order. */
- if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
- return \"mv %R0,%R1\;mv %0,%1\";
- else
- return \"mv %0,%1\;mv %R0,%R1\";
- case 1 :
- {
- REAL_VALUE_TYPE r;
- long l[2];
- REAL_VALUE_FROM_CONST_DOUBLE (r, operands[1]);
- REAL_VALUE_TO_TARGET_DOUBLE (r, l);
- operands[1] = GEN_INT (l[0]);
- if (l[0] == 0 && l[1] == 0)
- return \"ldi %0,%#0\;ldi %R0,%#0\";
- else if (l[1] != 0)
- abort ();
- else if ((l[0] & 0xffff) == 0)
- return \"seth %0,%#%T1\;ldi %R0,%#0\";
- else
- abort ();
- }
- case 2 :
- /* If the low-address word is used in the address, we must load it
- last. Otherwise, load it first. Note that we cannot have
- auto-increment in that case since the address register is known to be
- dead. */
- if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
- operands [1], 0))
- {
- return \"ld %R0,%R1\;ld %0,%1\";
- }
- else
- {
- /* Try to use auto-inc addressing if we can. */
- if (GET_CODE (XEXP (operands[1], 0)) == REG
- && dead_or_set_p (insn, XEXP (operands[1], 0)))
- {
- operands[1] = XEXP (operands[1], 0);
- return \"ld %0,@%1+\;ld %R0,@%1\";
- }
- return \"ld %0,%1\;ld %R0,%R1\";
- }
- case 3 :
- /* Try to use auto-inc addressing if we can. */
- if (GET_CODE (XEXP (operands[0], 0)) == REG
- && dead_or_set_p (insn, XEXP (operands[0], 0)))
- {
- operands[0] = XEXP (operands[0], 0);
- return \"st %1,@%0\;st %R1,@+%0\";
- }
- return \"st %1,%0\;st %R1,%R0\";
- }
-}"
- [(set_attr "type" "multi,multi,multi,multi")
- (set_attr "length" "4,6,6,6")])
+ "#"
+ [(set_attr "type" "multi,multi,load8,store8")
+ (set_attr "length" "4,16,6,6")])
+
+(define_split
+ [(set (match_operand:DF 0 "move_dest_operand" "")
+ (match_operand:DF 1 "move_double_src_operand" ""))]
+ "reload_completed"
+ [(match_dup 2)]
+ "operands[2] = gen_split_move_double (operands);")
\f
;; Zero extension instructions.
(define_insn "zero_extendqihi2"
- [(set (match_operand:HI 0 "register_operand" "=r,r")
- (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
+ [(set (match_operand:HI 0 "register_operand" "=r,r,r")
+ (zero_extend:HI (match_operand:QI 1 "extend_operand" "r,T,m")))]
""
"@
and3 %0,%1,%#255
+ ldub %0,%1
ldub %0,%1"
- [(set_attr "type" "unary,load")
- (set_attr "length" "4,*")])
+ [(set_attr "type" "int4,load2,load4")
+ (set_attr "length" "4,2,4")])
(define_insn "zero_extendqisi2"
- [(set (match_operand:SI 0 "register_operand" "=r,r")
- (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
+ [(set (match_operand:SI 0 "register_operand" "=r,r,r")
+ (zero_extend:SI (match_operand:QI 1 "extend_operand" "r,T,m")))]
""
"@
and3 %0,%1,%#255
+ ldub %0,%1
ldub %0,%1"
- [(set_attr "type" "unary,load")
- (set_attr "length" "4,*")])
+ [(set_attr "type" "int4,load2,load4")
+ (set_attr "length" "4,2,4")])
(define_insn "zero_extendhisi2"
- [(set (match_operand:SI 0 "register_operand" "=r,r")
- (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "r,m")))]
+ [(set (match_operand:SI 0 "register_operand" "=r,r,r")
+ (zero_extend:SI (match_operand:HI 1 "extend_operand" "r,T,m")))]
""
"@
and3 %0,%1,%#65535
+ lduh %0,%1
lduh %0,%1"
- [(set_attr "type" "unary,load")
- (set_attr "length" "4,*")])
+ [(set_attr "type" "int4,load2,load4")
+ (set_attr "length" "4,2,4")])
\f
-;; Sign extension instructions.
-;; ??? See v850.md.
-
-;; These patterns originally accepted general_operands, however, slightly
-;; better code is generated by only accepting register_operands, and then
-;; letting combine generate the lds[hb] insns.
-;; [This comment copied from sparc.md, I think.]
+;; Signed conversions from a smaller integer to a larger integer
+(define_insn "extendqihi2"
+ [(set (match_operand:HI 0 "register_operand" "=r,r,r")
+ (sign_extend:HI (match_operand:QI 1 "extend_operand" "0,T,m")))]
+ ""
+ "@
+ #
+ ldb %0,%1
+ ldb %0,%1"
+ [(set_attr "type" "multi,load2,load4")
+ (set_attr "length" "2,2,4")])
-(define_expand "extendqihi2"
+(define_split
[(set (match_operand:HI 0 "register_operand" "")
(sign_extend:HI (match_operand:QI 1 "register_operand" "")))]
- ""
+ "reload_completed"
+ [(match_dup 2)
+ (match_dup 3)]
"
{
- rtx temp = gen_reg_rtx (SImode);
- rtx shift_24 = gen_rtx (CONST_INT, VOIDmode, 24);
- int op1_subword = 0;
- int op0_subword = 0;
+ rtx op0 = gen_lowpart (SImode, operands[0]);
+ rtx shift = GEN_INT (24);
- if (GET_CODE (operand1) == SUBREG)
- {
- op1_subword = SUBREG_WORD (operand1);
- operand1 = XEXP (operand1, 0);
- }
- if (GET_CODE (operand0) == SUBREG)
- {
- op0_subword = SUBREG_WORD (operand0);
- operand0 = XEXP (operand0, 0);
- }
- emit_insn (gen_ashlsi3 (temp, gen_rtx (SUBREG, SImode, operand1,
- op1_subword),
- shift_24));
- if (GET_MODE (operand0) != SImode)
- operand0 = gen_rtx (SUBREG, SImode, operand0, op0_subword);
- emit_insn (gen_ashrsi3 (operand0, temp, shift_24));
- DONE;
+ operands[2] = gen_ashlsi3 (op0, op0, shift);
+ operands[3] = gen_ashrsi3 (op0, op0, shift);
}")
-(define_insn "*sign_extendqihi2_insn"
- [(set (match_operand:HI 0 "register_operand" "=r")
- (sign_extend:HI (match_operand:QI 1 "memory_operand" "m")))]
+(define_insn "extendqisi2"
+ [(set (match_operand:SI 0 "register_operand" "=r,r,r")
+ (sign_extend:SI (match_operand:QI 1 "extend_operand" "0,T,m")))]
""
- "ldb %0,%1"
- [(set_attr "type" "load")])
+ "@
+ #
+ ldb %0,%1
+ ldb %0,%1"
+ [(set_attr "type" "multi,load2,load4")
+ (set_attr "length" "4,2,4")])
-(define_expand "extendqisi2"
+(define_split
[(set (match_operand:SI 0 "register_operand" "")
(sign_extend:SI (match_operand:QI 1 "register_operand" "")))]
- ""
+ "reload_completed"
+ [(match_dup 2)
+ (match_dup 3)]
"
{
- rtx temp = gen_reg_rtx (SImode);
- rtx shift_24 = gen_rtx (CONST_INT, VOIDmode, 24);
- int op1_subword = 0;
-
- if (GET_CODE (operand1) == SUBREG)
- {
- op1_subword = SUBREG_WORD (operand1);
- operand1 = XEXP (operand1, 0);
- }
+ rtx shift = GEN_INT (24);
- emit_insn (gen_ashlsi3 (temp, gen_rtx (SUBREG, SImode, operand1,
- op1_subword),
- shift_24));
- emit_insn (gen_ashrsi3 (operand0, temp, shift_24));
- DONE;
+ operands[2] = gen_ashlsi3 (operands[0], operands[0], shift);
+ operands[3] = gen_ashrsi3 (operands[0], operands[0], shift);
}")
-(define_insn "*sign_extendqisi2_insn"
- [(set (match_operand:SI 0 "register_operand" "=r")
- (sign_extend:SI (match_operand:QI 1 "memory_operand" "m")))]
+(define_insn "extendhisi2"
+ [(set (match_operand:SI 0 "register_operand" "=r,r,r")
+ (sign_extend:SI (match_operand:HI 1 "extend_operand" "0,T,m")))]
""
- "ldb %0,%1"
- [(set_attr "type" "load")])
+ "@
+ #
+ ldh %0,%1
+ ldh %0,%1"
+ [(set_attr "type" "multi,load2,load4")
+ (set_attr "length" "4,2,4")])
-(define_expand "extendhisi2"
+(define_split
[(set (match_operand:SI 0 "register_operand" "")
(sign_extend:SI (match_operand:HI 1 "register_operand" "")))]
- ""
+ "reload_completed"
+ [(match_dup 2)
+ (match_dup 3)]
"
{
- rtx temp = gen_reg_rtx (SImode);
- rtx shift_16 = gen_rtx (CONST_INT, VOIDmode, 16);
- int op1_subword = 0;
-
- if (GET_CODE (operand1) == SUBREG)
- {
- op1_subword = SUBREG_WORD (operand1);
- operand1 = XEXP (operand1, 0);
- }
+ rtx shift = GEN_INT (16);
- emit_insn (gen_ashlsi3 (temp, gen_rtx (SUBREG, SImode, operand1,
- op1_subword),
- shift_16));
- emit_insn (gen_ashrsi3 (operand0, temp, shift_16));
- DONE;
+ operands[2] = gen_ashlsi3 (operands[0], operands[0], shift);
+ operands[3] = gen_ashrsi3 (operands[0], operands[0], shift);
}")
-
-(define_insn "*sign_extendhisi2_insn"
- [(set (match_operand:SI 0 "register_operand" "=r")
- (sign_extend:SI (match_operand:HI 1 "memory_operand" "m")))]
- ""
- "ldh %0,%1"
- [(set_attr "type" "load")])
\f
;; Arithmetic instructions.
add %0,%2
addi %0,%#%2
add3 %0,%1,%#%2"
- [(set_attr "type" "binary")
+ [(set_attr "type" "int2,int2,int4")
(set_attr "length" "2,2,4")])
;(define_split
(match_operand:DI 2 "register_operand" "r")))
(clobber (reg:CC 17))]
""
- "*
-{
- /* ??? The cmp clears the condition bit. Can we speed up somehow? */
- return \"cmp %L0,%L0\;addx %L0,%L2\;addx %H0,%H2\";
-}"
- [(set_attr "type" "binary")
+ "#"
+ [(set_attr "type" "multi")
(set_attr "length" "6")])
+;; ??? The cmp clears the condition bit. Can we speed up somehow?
+(define_split
+ [(set (match_operand:DI 0 "register_operand" "")
+ (plus:DI (match_operand:DI 1 "register_operand" "")
+ (match_operand:DI 2 "register_operand" "")))
+ (clobber (reg:CC 17))]
+ "reload_completed"
+ [(parallel [(set (reg:CC 17)
+ (const_int 0))
+ (use (match_dup 4))])
+ (parallel [(set (match_dup 4)
+ (plus:SI (match_dup 4)
+ (plus:SI (match_dup 5)
+ (ne:SI (reg:CC 17) (const_int 0)))))
+ (set (reg:CC 17)
+ (unspec:CC [(const_int 0)] UNSPEC_SET_CBIT))])
+ (parallel [(set (match_dup 6)
+ (plus:SI (match_dup 6)
+ (plus:SI (match_dup 7)
+ (ne:SI (reg:CC 17) (const_int 0)))))
+ (set (reg:CC 17)
+ (unspec:CC [(const_int 0)] UNSPEC_SET_CBIT))])]
+ "
+{
+ operands[4] = operand_subword (operands[0], (WORDS_BIG_ENDIAN != 0), 0, DImode);
+ operands[5] = operand_subword (operands[2], (WORDS_BIG_ENDIAN != 0), 0, DImode);
+ operands[6] = operand_subword (operands[0], (WORDS_BIG_ENDIAN == 0), 0, DImode);
+ operands[7] = operand_subword (operands[2], (WORDS_BIG_ENDIAN == 0), 0, DImode);
+}")
+
+(define_insn "*clear_c"
+ [(set (reg:CC 17)
+ (const_int 0))
+ (use (match_operand:SI 0 "register_operand" "r"))]
+ ""
+ "cmp %0,%0"
+ [(set_attr "type" "int2")
+ (set_attr "length" "2")])
+
+(define_insn "*add_carry"
+ [(set (match_operand:SI 0 "register_operand" "=r")
+ (plus:SI (match_operand:SI 1 "register_operand" "%0")
+ (plus:SI (match_operand:SI 2 "register_operand" "r")
+ (ne:SI (reg:CC 17) (const_int 0)))))
+ (set (reg:CC 17)
+ (unspec:CC [(const_int 0)] UNSPEC_SET_CBIT))]
+ ""
+ "addx %0,%2"
+ [(set_attr "type" "int2")
+ (set_attr "length" "2")])
+
(define_insn "subsi3"
[(set (match_operand:SI 0 "register_operand" "=r")
(minus:SI (match_operand:SI 1 "register_operand" "0")
(match_operand:SI 2 "register_operand" "r")))]
""
"sub %0,%2"
- [(set_attr "type" "binary")])
+ [(set_attr "type" "int2")
+ (set_attr "length" "2")])
(define_insn "subdi3"
[(set (match_operand:DI 0 "register_operand" "=r")
(match_operand:DI 2 "register_operand" "r")))
(clobber (reg:CC 17))]
""
- "*
-{
- /* ??? The cmp clears the condition bit. Can we speed up somehow? */
- return \"cmp %L0,%L0\;subx %L0,%L2\;subx %H0,%H2\";
-}"
- [(set_attr "type" "binary")
+ "#"
+ [(set_attr "type" "multi")
(set_attr "length" "6")])
+
+;; ??? The cmp clears the condition bit. Can we speed up somehow?
+(define_split
+ [(set (match_operand:DI 0 "register_operand" "")
+ (minus:DI (match_operand:DI 1 "register_operand" "")
+ (match_operand:DI 2 "register_operand" "")))
+ (clobber (reg:CC 17))]
+ "reload_completed"
+ [(parallel [(set (reg:CC 17)
+ (const_int 0))
+ (use (match_dup 4))])
+ (parallel [(set (match_dup 4)
+ (minus:SI (match_dup 4)
+ (minus:SI (match_dup 5)
+ (ne:SI (reg:CC 17) (const_int 0)))))
+ (set (reg:CC 17)
+ (unspec:CC [(const_int 0)] UNSPEC_SET_CBIT))])
+ (parallel [(set (match_dup 6)
+ (minus:SI (match_dup 6)
+ (minus:SI (match_dup 7)
+ (ne:SI (reg:CC 17) (const_int 0)))))
+ (set (reg:CC 17)
+ (unspec:CC [(const_int 0)] UNSPEC_SET_CBIT))])]
+ "
+{
+ operands[4] = operand_subword (operands[0], (WORDS_BIG_ENDIAN != 0), 0, DImode);
+ operands[5] = operand_subword (operands[2], (WORDS_BIG_ENDIAN != 0), 0, DImode);
+ operands[6] = operand_subword (operands[0], (WORDS_BIG_ENDIAN == 0), 0, DImode);
+ operands[7] = operand_subword (operands[2], (WORDS_BIG_ENDIAN == 0), 0, DImode);
+}")
+
+(define_insn "*sub_carry"
+ [(set (match_operand:SI 0 "register_operand" "=r")
+ (minus:SI (match_operand:SI 1 "register_operand" "%0")
+ (minus:SI (match_operand:SI 2 "register_operand" "r")
+ (ne:SI (reg:CC 17) (const_int 0)))))
+ (set (reg:CC 17)
+ (unspec:CC [(const_int 0)] UNSPEC_SET_CBIT))]
+ ""
+ "subx %0,%2"
+ [(set_attr "type" "int2")
+ (set_attr "length" "2")])
\f
; Multiply/Divide instructions.
(sign_extend:SI (match_operand:HI 2 "register_operand" "r"))))]
""
"mullo %1,%2\;mvfacmi %0"
- [(set_attr "type" "mul")
+ [(set_attr "type" "multi")
(set_attr "length" "4")])
(define_insn "mulsi3"
(match_operand:SI 2 "register_operand" "r")))]
""
"mul %0,%2"
- [(set_attr "type" "mul")])
+ [(set_attr "type" "mul2")
+ (set_attr "length" "2")])
(define_insn "divsi3"
[(set (match_operand:SI 0 "register_operand" "=r")
(match_operand:SI 2 "register_operand" "r")))]
""
"div %0,%2"
- [(set_attr "type" "div")])
+ [(set_attr "type" "div4")
+ (set_attr "length" "4")])
(define_insn "udivsi3"
[(set (match_operand:SI 0 "register_operand" "=r")
(match_operand:SI 2 "register_operand" "r")))]
""
"divu %0,%2"
- [(set_attr "type" "div")])
+ [(set_attr "type" "div4")
+ (set_attr "length" "4")])
(define_insn "modsi3"
[(set (match_operand:SI 0 "register_operand" "=r")
(match_operand:SI 2 "register_operand" "r")))]
""
"rem %0,%2"
- [(set_attr "type" "div")])
+ [(set_attr "type" "div4")
+ (set_attr "length" "4")])
(define_insn "umodsi3"
[(set (match_operand:SI 0 "register_operand" "=r")
(match_operand:SI 2 "register_operand" "r")))]
""
"remu %0,%2"
- [(set_attr "type" "div")])
+ [(set_attr "type" "div4")
+ (set_attr "length" "4")])
\f
;; Boolean instructions.
;;
(define_insn "andsi3"
[(set (match_operand:SI 0 "register_operand" "=r,r")
(and:SI (match_operand:SI 1 "register_operand" "%0,r")
- (match_operand:SI 2 "nonmemory_operand" "r,K")))]
+ (match_operand:SI 2 "reg_or_uint16_operand" "r,K")))]
""
- "@
- and %0,%2
- and3 %0,%1,%#%2 ; %X2"
- [(set_attr "type" "binary")])
+ "*
+{
+ /* If we are worried about space, see if we can break this up into two
+ short instructions, which might eliminate a NOP being inserted. */
+ if (optimize_size
+ && m32r_not_same_reg (operands[0], operands[1])
+ && GET_CODE (operands[2]) == CONST_INT
+ && INT8_P (INTVAL (operands[2])))
+ return \"#\";
+
+ else if (GET_CODE (operands[2]) == CONST_INT)
+ return \"and3 %0,%1,%#%X2\";
+
+ return \"and %0,%2\";
+}"
+ [(set_attr "type" "int2,int4")
+ (set_attr "length" "2,4")])
+
+(define_split
+ [(set (match_operand:SI 0 "register_operand" "")
+ (and:SI (match_operand:SI 1 "register_operand" "")
+ (match_operand:SI 2 "int8_operand" "")))]
+ "optimize_size && m32r_not_same_reg (operands[0], operands[1])"
+ [(set (match_dup 0) (match_dup 2))
+ (set (match_dup 0) (and:SI (match_dup 0) (match_dup 1)))]
+ "")
(define_insn "iorsi3"
[(set (match_operand:SI 0 "register_operand" "=r,r")
(ior:SI (match_operand:SI 1 "register_operand" "%0,r")
- (match_operand:SI 2 "nonmemory_operand" "r,K")))]
+ (match_operand:SI 2 "reg_or_uint16_operand" "r,K")))]
""
- "@
- or %0,%2
- or3 %0,%1,%#%2 ; %X2"
- [(set_attr "type" "binary")])
+ "*
+{
+ /* If we are worried about space, see if we can break this up into two
+ short instructions, which might eliminate a NOP being inserted. */
+ if (optimize_size
+ && m32r_not_same_reg (operands[0], operands[1])
+ && GET_CODE (operands[2]) == CONST_INT
+ && INT8_P (INTVAL (operands[2])))
+ return \"#\";
+
+ else if (GET_CODE (operands[2]) == CONST_INT)
+ return \"or3 %0,%1,%#%X2\";
+
+ return \"or %0,%2\";
+}"
+ [(set_attr "type" "int2,int4")
+ (set_attr "length" "2,4")])
+
+(define_split
+ [(set (match_operand:SI 0 "register_operand" "")
+ (ior:SI (match_operand:SI 1 "register_operand" "")
+ (match_operand:SI 2 "int8_operand" "")))]
+ "optimize_size && m32r_not_same_reg (operands[0], operands[1])"
+ [(set (match_dup 0) (match_dup 2))
+ (set (match_dup 0) (ior:SI (match_dup 0) (match_dup 1)))]
+ "")
(define_insn "xorsi3"
[(set (match_operand:SI 0 "register_operand" "=r,r")
(xor:SI (match_operand:SI 1 "register_operand" "%0,r")
- (match_operand:SI 2 "nonmemory_operand" "r,K")))]
+ (match_operand:SI 2 "reg_or_uint16_operand" "r,K")))]
""
- "@
- xor %0,%2
- xor3 %0,%1,%#%2 ; %X2"
- [(set_attr "type" "binary")])
+ "*
+{
+ /* If we are worried about space, see if we can break this up into two
+ short instructions, which might eliminate a NOP being inserted. */
+ if (optimize_size
+ && m32r_not_same_reg (operands[0], operands[1])
+ && GET_CODE (operands[2]) == CONST_INT
+ && INT8_P (INTVAL (operands[2])))
+ return \"#\";
+
+ else if (GET_CODE (operands[2]) == CONST_INT)
+ return \"xor3 %0,%1,%#%X2\";
+
+ return \"xor %0,%2\";
+}"
+ [(set_attr "type" "int2,int4")
+ (set_attr "length" "2,4")])
+
+(define_split
+ [(set (match_operand:SI 0 "register_operand" "")
+ (xor:SI (match_operand:SI 1 "register_operand" "")
+ (match_operand:SI 2 "int8_operand" "")))]
+ "optimize_size && m32r_not_same_reg (operands[0], operands[1])"
+ [(set (match_dup 0) (match_dup 2))
+ (set (match_dup 0) (xor:SI (match_dup 0) (match_dup 1)))]
+ "")
(define_insn "negsi2"
[(set (match_operand:SI 0 "register_operand" "=r")
(neg:SI (match_operand:SI 1 "register_operand" "r")))]
""
"neg %0,%1"
- [(set_attr "type" "unary")])
+ [(set_attr "type" "int2")
+ (set_attr "length" "2")])
(define_insn "one_cmplsi2"
[(set (match_operand:SI 0 "register_operand" "=r")
(not:SI (match_operand:SI 1 "register_operand" "r")))]
""
"not %0,%1"
- [(set_attr "type" "unary")])
+ [(set_attr "type" "int2")
+ (set_attr "length" "2")])
\f
;; Shift instructions.
sll %0,%2
slli %0,%#%2
sll3 %0,%1,%#%2"
- [(set_attr "type" "shift")
+ [(set_attr "type" "shift2,shift2,shift4")
(set_attr "length" "2,2,4")])
(define_insn "ashrsi3"
sra %0,%2
srai %0,%#%2
sra3 %0,%1,%#%2"
- [(set_attr "type" "shift")
+ [(set_attr "type" "shift2,shift2,shift4")
(set_attr "length" "2,2,4")])
(define_insn "lshrsi3"
srl %0,%2
srli %0,%#%2
srl3 %0,%1,%#%2"
- [(set_attr "type" "shift")
+ [(set_attr "type" "shift2,shift2,shift4")
(set_attr "length" "2,2,4")])
\f
;; Compare instructions.
(define_expand "cmpsi"
[(set (reg:CC 17)
(compare:CC (match_operand:SI 0 "register_operand" "")
- (match_operand:SI 1 "nonmemory_operand" "")))]
+ (match_operand:SI 1 "reg_or_cmp_int16_operand" "")))]
""
"
{
DONE;
}")
+(define_insn "cmp_eqsi_zero_insn"
+ [(set (reg:CC 17)
+ (eq:CC (match_operand:SI 0 "register_operand" "r,r")
+ (match_operand:SI 1 "reg_or_zero_operand" "r,P")))]
+ "TARGET_M32RX || TARGET_M32R2"
+ "@
+ cmpeq %0, %1
+ cmpz %0"
+ [(set_attr "type" "int4")
+ (set_attr "length" "4")])
+
;; The cmp_xxx_insn patterns set the condition bit to the result of the
;; comparison. There isn't a "compare equal" instruction so cmp_eqsi_insn
;; is quite inefficient. However, it is rarely used.
(define_insn "cmp_eqsi_insn"
[(set (reg:CC 17)
- (eq:CC (match_operand:SI 0 "register_operand" "r,r")
- (match_operand:SI 1 "reg_or_cmp_int16_operand" "r,P")))
+ (eq:CC (match_operand:SI 0 "register_operand" "r,r")
+ (match_operand:SI 1 "reg_or_cmp_int16_operand" "r,P")))
(clobber (match_scratch:SI 2 "=&r,&r"))]
- "TARGET_OLD_COMPARE"
- "@
- mv %2,%0\;sub %2,%1\;cmpui %2,#1
- add3 %2,%0,%#%N1\;cmpui %2,#1"
- [(set_attr "type" "compare,compare")
- (set_attr "length" "8,8")])
-
-(define_insn "cmp_ltsi_insn"
- [(set (reg:CC 17)
- (lt:CC (match_operand:SI 0 "register_operand" "r,r")
- (match_operand:SI 1 "reg_or_int16_operand" "r,J")))]
+ ""
+ "*
+{
+ if (which_alternative == 0)
+ {
+ return \"mv %2,%0\;sub %2,%1\;cmpui %2,#1\";
+ }
+ else
+ {
+ if (INTVAL (operands [1]) == 0)
+ return \"cmpui %0, #1\";
+ else if (REGNO (operands [2]) == REGNO (operands [0]))
+ return \"addi %0,%#%N1\;cmpui %2,#1\";
+ else
+ return \"add3 %2,%0,%#%N1\;cmpui %2,#1\";
+ }
+}"
+ [(set_attr "type" "multi,multi")
+ (set_attr "length" "8,8")])
+
+(define_insn "cmp_ltsi_insn"
+ [(set (reg:CC 17)
+ (lt:CC (match_operand:SI 0 "register_operand" "r,r")
+ (match_operand:SI 1 "reg_or_int16_operand" "r,J")))]
""
"@
cmp %0,%1
cmpi %0,%#%1"
- [(set_attr "type" "compare")])
+ [(set_attr "type" "int2,int4")
+ (set_attr "length" "2,4")])
(define_insn "cmp_ltusi_insn"
[(set (reg:CC 17)
- (ltu:CC (match_operand:SI 0 "register_operand" "r,r")
- (match_operand:SI 1 "reg_or_uint16_operand" "r,K")))]
+ (ltu:CC (match_operand:SI 0 "register_operand" "r,r")
+ (match_operand:SI 1 "reg_or_int16_operand" "r,J")))]
""
"@
cmpu %0,%1
cmpui %0,%#%1"
- [(set_attr "type" "compare")])
-
-;; reg == small constant comparisons are best handled by putting the result
-;; of the comparison in a tmp reg and then using beqz/bnez.
-;; ??? The result register doesn't contain 0/STORE_FLAG_VALUE,
-;; it contains 0/non-zero.
-
-(define_insn "cmp_ne_small_const_insn"
- [(set (match_operand:SI 0 "register_operand" "=r")
- (ne:SI (match_operand:SI 1 "register_operand" "r")
- (match_operand:SI 2 "cmp_int16_operand" "P")))]
- ""
- "add3 %0,%1,%#%N2"
- [(set_attr "type" "compare")
- (set_attr "length" "4")])
+ [(set_attr "type" "int2,int4")
+ (set_attr "length" "2,4")])
\f
;; These control RTL generation for conditional jump insns.
""
"
{
- operands[1] = gen_compare (EQ, m32r_compare_op0, m32r_compare_op1);
+ operands[1] = gen_compare (EQ, m32r_compare_op0, m32r_compare_op1, FALSE);
}")
(define_expand "bne"
""
"
{
- operands[1] = gen_compare (NE, m32r_compare_op0, m32r_compare_op1);
+ operands[1] = gen_compare (NE, m32r_compare_op0, m32r_compare_op1, FALSE);
}")
(define_expand "bgt"
""
"
{
- operands[1] = gen_compare (GT, m32r_compare_op0, m32r_compare_op1);
+ operands[1] = gen_compare (GT, m32r_compare_op0, m32r_compare_op1, FALSE);
}")
(define_expand "ble"
""
"
{
- operands[1] = gen_compare (LE, m32r_compare_op0, m32r_compare_op1);
+ operands[1] = gen_compare (LE, m32r_compare_op0, m32r_compare_op1, FALSE);
}")
(define_expand "bge"
""
"
{
- operands[1] = gen_compare (GE, m32r_compare_op0, m32r_compare_op1);
+ operands[1] = gen_compare (GE, m32r_compare_op0, m32r_compare_op1, FALSE);
}")
(define_expand "blt"
""
"
{
- operands[1] = gen_compare (LT, m32r_compare_op0, m32r_compare_op1);
+ operands[1] = gen_compare (LT, m32r_compare_op0, m32r_compare_op1, FALSE);
}")
(define_expand "bgtu"
""
"
{
- operands[1] = gen_compare (GTU, m32r_compare_op0, m32r_compare_op1);
+ operands[1] = gen_compare (GTU, m32r_compare_op0, m32r_compare_op1, FALSE);
}")
(define_expand "bleu"
""
"
{
- operands[1] = gen_compare (LEU, m32r_compare_op0, m32r_compare_op1);
+ operands[1] = gen_compare (LEU, m32r_compare_op0, m32r_compare_op1, FALSE);
}")
(define_expand "bgeu"
""
"
{
- operands[1] = gen_compare (GEU, m32r_compare_op0, m32r_compare_op1);
+ operands[1] = gen_compare (GEU, m32r_compare_op0, m32r_compare_op1, FALSE);
}")
(define_expand "bltu"
""
"
{
- operands[1] = gen_compare (LTU, m32r_compare_op0, m32r_compare_op1);
+ operands[1] = gen_compare (LTU, m32r_compare_op0, m32r_compare_op1, FALSE);
}")
;; Now match both normal and inverted jump.
""
"*
{
- if (GET_CODE (operands[1]) == NE)
- return \"bc %l0\";
- else
- return \"bnc %l0\";
+ static char instruction[40];
+ sprintf (instruction, \"%s%s %%l0\",
+ (GET_CODE (operands[1]) == NE) ? \"bc\" : \"bnc\",
+ (get_attr_length (insn) == 2) ? \".s\" : \"\");
+ return instruction;
}"
[(set_attr "type" "branch")
; We use 400/800 instead of 512,1024 to account for inaccurate insn
""
"*
{
- if (GET_CODE (operands[1]) == EQ)
- return \"bc %l0\";
- else
- return \"bnc %l0\";
+ static char instruction[40];
+ sprintf (instruction, \"%s%s %%l0\",
+ (GET_CODE (operands[1]) == EQ) ? \"bc\" : \"bnc\",
+ (get_attr_length (insn) == 2) ? \".s\" : \"\");
+ return instruction;
}"
[(set_attr "type" "branch")
; We use 400/800 instead of 512,1024 to account for inaccurate insn
""
"*
{
- char *br,*invbr;
+ const char *br,*invbr;
char asmtext[40];
switch (GET_CODE (operands[1]))
case GT : br = \"gt\"; invbr = \"le\"; break;
case LT : br = \"lt\"; invbr = \"ge\"; break;
case GE : br = \"ge\"; invbr = \"lt\"; break;
+
+ default: abort();
}
/* Is branch target reachable with bxxz? */
""
"*
{
- char *br,*invbr;
+ const char *br,*invbr;
char asmtext[40];
switch (GET_CODE (operands[1]))
case GT : br = \"gt\"; invbr = \"le\"; break;
case LT : br = \"lt\"; invbr = \"ge\"; break;
case GE : br = \"ge\"; invbr = \"lt\"; break;
+
+ default: abort();
}
/* Is branch target reachable with bxxz? */
(const_int 4)
(const_int 8)))])
\f
+;; S<cc> operations to set a register to 1/0 based on a comparison
+
+(define_expand "seq"
+ [(match_operand:SI 0 "register_operand" "")]
+ ""
+ "
+{
+ rtx op0 = operands[0];
+ rtx op1 = m32r_compare_op0;
+ rtx op2 = m32r_compare_op1;
+ enum machine_mode mode = GET_MODE (op0);
+
+ if (mode != SImode)
+ FAIL;
+
+ if (! register_operand (op1, mode))
+ op1 = force_reg (mode, op1);
+
+ if (TARGET_M32RX || TARGET_M32R2)
+ {
+ if (! reg_or_zero_operand (op2, mode))
+ op2 = force_reg (mode, op2);
+
+ emit_insn (gen_seq_insn_m32rx (op0, op1, op2));
+ DONE;
+ }
+ if (GET_CODE (op2) == CONST_INT && INTVAL (op2) == 0)
+ {
+ emit_insn (gen_seq_zero_insn (op0, op1));
+ DONE;
+ }
+
+ if (! reg_or_eq_int16_operand (op2, mode))
+ op2 = force_reg (mode, op2);
+
+ emit_insn (gen_seq_insn (op0, op1, op2));
+ DONE;
+}")
+
+(define_insn "seq_insn_m32rx"
+ [(set (match_operand:SI 0 "register_operand" "=r")
+ (eq:SI (match_operand:SI 1 "register_operand" "%r")
+ (match_operand:SI 2 "reg_or_zero_operand" "rP")))
+ (clobber (reg:CC 17))]
+ "TARGET_M32RX || TARGET_M32R2"
+ "#"
+ [(set_attr "type" "multi")
+ (set_attr "length" "6")])
+
+(define_split
+ [(set (match_operand:SI 0 "register_operand" "")
+ (eq:SI (match_operand:SI 1 "register_operand" "")
+ (match_operand:SI 2 "reg_or_zero_operand" "")))
+ (clobber (reg:CC 17))]
+ "TARGET_M32RX || TARGET_M32R2"
+ [(set (reg:CC 17)
+ (eq:CC (match_dup 1)
+ (match_dup 2)))
+ (set (match_dup 0)
+ (ne:SI (reg:CC 17) (const_int 0)))]
+ "")
+
+(define_insn "seq_zero_insn"
+ [(set (match_operand:SI 0 "register_operand" "=r")
+ (eq:SI (match_operand:SI 1 "register_operand" "r")
+ (const_int 0)))
+ (clobber (reg:CC 17))]
+ "TARGET_M32R"
+ "#"
+ [(set_attr "type" "multi")
+ (set_attr "length" "6")])
+
+(define_split
+ [(set (match_operand:SI 0 "register_operand" "")
+ (eq:SI (match_operand:SI 1 "register_operand" "")
+ (const_int 0)))
+ (clobber (reg:CC 17))]
+ "TARGET_M32R"
+ [(match_dup 3)]
+ "
+{
+ rtx op0 = operands[0];
+ rtx op1 = operands[1];
+
+ start_sequence ();
+ emit_insn (gen_cmp_ltusi_insn (op1, const1_rtx));
+ emit_insn (gen_movcc_insn (op0));
+ operands[3] = get_insns ();
+ end_sequence ();
+}")
+
+(define_insn "seq_insn"
+ [(set (match_operand:SI 0 "register_operand" "=r,r,??r,r")
+ (eq:SI (match_operand:SI 1 "register_operand" "r,r,r,r")
+ (match_operand:SI 2 "reg_or_eq_int16_operand" "r,r,r,PK")))
+ (clobber (reg:CC 17))
+ (clobber (match_scratch:SI 3 "=1,2,&r,r"))]
+ "TARGET_M32R"
+ "#"
+ [(set_attr "type" "multi")
+ (set_attr "length" "8,8,10,10")])
+
+(define_split
+ [(set (match_operand:SI 0 "register_operand" "")
+ (eq:SI (match_operand:SI 1 "register_operand" "")
+ (match_operand:SI 2 "reg_or_eq_int16_operand" "")))
+ (clobber (reg:CC 17))
+ (clobber (match_scratch:SI 3 ""))]
+ "TARGET_M32R && reload_completed"
+ [(match_dup 4)]
+ "
+{
+ rtx op0 = operands[0];
+ rtx op1 = operands[1];
+ rtx op2 = operands[2];
+ rtx op3 = operands[3];
+ HOST_WIDE_INT value;
+
+ if (GET_CODE (op2) == REG && GET_CODE (op3) == REG
+ && REGNO (op2) == REGNO (op3))
+ {
+ op1 = operands[2];
+ op2 = operands[1];
+ }
+
+ start_sequence ();
+ if (GET_CODE (op1) == REG && GET_CODE (op3) == REG
+ && REGNO (op1) != REGNO (op3))
+ {
+ emit_move_insn (op3, op1);
+ op1 = op3;
+ }
+
+ if (GET_CODE (op2) == CONST_INT && (value = INTVAL (op2)) != 0
+ && CMP_INT16_P (value))
+ emit_insn (gen_addsi3 (op3, op1, GEN_INT (-value)));
+ else
+ emit_insn (gen_xorsi3 (op3, op1, op2));
+
+ emit_insn (gen_cmp_ltusi_insn (op3, const1_rtx));
+ emit_insn (gen_movcc_insn (op0));
+ operands[4] = get_insns ();
+ end_sequence ();
+}")
+
+(define_expand "sne"
+ [(match_operand:SI 0 "register_operand" "")]
+ ""
+ "
+{
+ rtx op0 = operands[0];
+ rtx op1 = m32r_compare_op0;
+ rtx op2 = m32r_compare_op1;
+ enum machine_mode mode = GET_MODE (op0);
+
+ if (mode != SImode)
+ FAIL;
+
+ if (GET_CODE (op2) != CONST_INT
+ || (INTVAL (op2) != 0 && UINT16_P (INTVAL (op2))))
+ {
+ rtx reg;
+
+ if (reload_completed || reload_in_progress)
+ FAIL;
+
+ reg = gen_reg_rtx (SImode);
+ emit_insn (gen_xorsi3 (reg, op1, op2));
+ op1 = reg;
+
+ if (! register_operand (op1, mode))
+ op1 = force_reg (mode, op1);
+
+ emit_insn (gen_sne_zero_insn (op0, op1));
+ DONE;
+ }
+ else
+ FAIL;
+}")
+
+(define_insn "sne_zero_insn"
+ [(set (match_operand:SI 0 "register_operand" "=r")
+ (ne:SI (match_operand:SI 1 "register_operand" "r")
+ (const_int 0)))
+ (clobber (reg:CC 17))
+ (clobber (match_scratch:SI 2 "=&r"))]
+ ""
+ "#"
+ [(set_attr "type" "multi")
+ (set_attr "length" "6")])
+
+(define_split
+ [(set (match_operand:SI 0 "register_operand" "")
+ (ne:SI (match_operand:SI 1 "register_operand" "")
+ (const_int 0)))
+ (clobber (reg:CC 17))
+ (clobber (match_scratch:SI 2 ""))]
+ "reload_completed"
+ [(set (match_dup 2)
+ (const_int 0))
+ (set (reg:CC 17)
+ (ltu:CC (match_dup 2)
+ (match_dup 1)))
+ (set (match_dup 0)
+ (ne:SI (reg:CC 17) (const_int 0)))]
+ "")
+
+(define_expand "slt"
+ [(match_operand:SI 0 "register_operand" "")]
+ ""
+ "
+{
+ rtx op0 = operands[0];
+ rtx op1 = m32r_compare_op0;
+ rtx op2 = m32r_compare_op1;
+ enum machine_mode mode = GET_MODE (op0);
+
+ if (mode != SImode)
+ FAIL;
+
+ if (! register_operand (op1, mode))
+ op1 = force_reg (mode, op1);
+
+ if (! reg_or_int16_operand (op2, mode))
+ op2 = force_reg (mode, op2);
+
+ emit_insn (gen_slt_insn (op0, op1, op2));
+ DONE;
+}")
+
+(define_insn "slt_insn"
+ [(set (match_operand:SI 0 "register_operand" "=r,r")
+ (lt:SI (match_operand:SI 1 "register_operand" "r,r")
+ (match_operand:SI 2 "reg_or_int16_operand" "r,J")))
+ (clobber (reg:CC 17))]
+ ""
+ "#"
+ [(set_attr "type" "multi")
+ (set_attr "length" "4,6")])
+
+(define_split
+ [(set (match_operand:SI 0 "register_operand" "")
+ (lt:SI (match_operand:SI 1 "register_operand" "")
+ (match_operand:SI 2 "reg_or_int16_operand" "")))
+ (clobber (reg:CC 17))]
+ ""
+ [(set (reg:CC 17)
+ (lt:CC (match_dup 1)
+ (match_dup 2)))
+ (set (match_dup 0)
+ (ne:SI (reg:CC 17) (const_int 0)))]
+ "")
+
+(define_expand "sle"
+ [(match_operand:SI 0 "register_operand" "")]
+ ""
+ "
+{
+ rtx op0 = operands[0];
+ rtx op1 = m32r_compare_op0;
+ rtx op2 = m32r_compare_op1;
+ enum machine_mode mode = GET_MODE (op0);
+
+ if (mode != SImode)
+ FAIL;
+
+ if (! register_operand (op1, mode))
+ op1 = force_reg (mode, op1);
+
+ if (GET_CODE (op2) == CONST_INT)
+ {
+ HOST_WIDE_INT value = INTVAL (op2);
+ if (value >= 2147483647)
+ {
+ emit_move_insn (op0, const1_rtx);
+ DONE;
+ }
+
+ op2 = GEN_INT (value+1);
+ if (value < -32768 || value >= 32767)
+ op2 = force_reg (mode, op2);
+
+ emit_insn (gen_slt_insn (op0, op1, op2));
+ DONE;
+ }
+
+ if (! register_operand (op2, mode))
+ op2 = force_reg (mode, op2);
+
+ emit_insn (gen_sle_insn (op0, op1, op2));
+ DONE;
+}")
+
+(define_insn "sle_insn"
+ [(set (match_operand:SI 0 "register_operand" "=r")
+ (le:SI (match_operand:SI 1 "register_operand" "r")
+ (match_operand:SI 2 "register_operand" "r")))
+ (clobber (reg:CC 17))]
+ ""
+ "#"
+ [(set_attr "type" "multi")
+ (set_attr "length" "8")])
+
+(define_split
+ [(set (match_operand:SI 0 "register_operand" "")
+ (le:SI (match_operand:SI 1 "register_operand" "")
+ (match_operand:SI 2 "register_operand" "")))
+ (clobber (reg:CC 17))]
+ "!optimize_size"
+ [(set (reg:CC 17)
+ (lt:CC (match_dup 2)
+ (match_dup 1)))
+ (set (match_dup 0)
+ (ne:SI (reg:CC 17) (const_int 0)))
+ (set (match_dup 0)
+ (xor:SI (match_dup 0)
+ (const_int 1)))]
+ "")
+
+;; If optimizing for space, use -(reg - 1) to invert the comparison rather than
+;; xor reg,reg,1 which might eliminate a NOP being inserted.
+(define_split
+ [(set (match_operand:SI 0 "register_operand" "")
+ (le:SI (match_operand:SI 1 "register_operand" "")
+ (match_operand:SI 2 "register_operand" "")))
+ (clobber (reg:CC 17))]
+ "optimize_size"
+ [(set (reg:CC 17)
+ (lt:CC (match_dup 2)
+ (match_dup 1)))
+ (set (match_dup 0)
+ (ne:SI (reg:CC 17) (const_int 0)))
+ (set (match_dup 0)
+ (plus:SI (match_dup 0)
+ (const_int -1)))
+ (set (match_dup 0)
+ (neg:SI (match_dup 0)))]
+ "")
+
+(define_expand "sgt"
+ [(match_operand:SI 0 "register_operand" "")]
+ ""
+ "
+{
+ rtx op0 = operands[0];
+ rtx op1 = m32r_compare_op0;
+ rtx op2 = m32r_compare_op1;
+ enum machine_mode mode = GET_MODE (op0);
+
+ if (mode != SImode)
+ FAIL;
+
+ if (! register_operand (op1, mode))
+ op1 = force_reg (mode, op1);
+
+ if (! register_operand (op2, mode))
+ op2 = force_reg (mode, op2);
+
+ emit_insn (gen_slt_insn (op0, op2, op1));
+ DONE;
+}")
+
+(define_expand "sge"
+ [(match_operand:SI 0 "register_operand" "")]
+ ""
+ "
+{
+ rtx op0 = operands[0];
+ rtx op1 = m32r_compare_op0;
+ rtx op2 = m32r_compare_op1;
+ enum machine_mode mode = GET_MODE (op0);
+
+ if (mode != SImode)
+ FAIL;
+
+ if (! register_operand (op1, mode))
+ op1 = force_reg (mode, op1);
+
+ if (! reg_or_int16_operand (op2, mode))
+ op2 = force_reg (mode, op2);
+
+ emit_insn (gen_sge_insn (op0, op1, op2));
+ DONE;
+}")
+
+(define_insn "sge_insn"
+ [(set (match_operand:SI 0 "register_operand" "=r,r")
+ (ge:SI (match_operand:SI 1 "register_operand" "r,r")
+ (match_operand:SI 2 "reg_or_int16_operand" "r,J")))
+ (clobber (reg:CC 17))]
+ ""
+ "#"
+ [(set_attr "type" "multi")
+ (set_attr "length" "8,10")])
+
+(define_split
+ [(set (match_operand:SI 0 "register_operand" "")
+ (ge:SI (match_operand:SI 1 "register_operand" "")
+ (match_operand:SI 2 "reg_or_int16_operand" "")))
+ (clobber (reg:CC 17))]
+ "!optimize_size"
+ [(set (reg:CC 17)
+ (lt:CC (match_dup 1)
+ (match_dup 2)))
+ (set (match_dup 0)
+ (ne:SI (reg:CC 17) (const_int 0)))
+ (set (match_dup 0)
+ (xor:SI (match_dup 0)
+ (const_int 1)))]
+ "")
+
+;; If optimizing for space, use -(reg - 1) to invert the comparison rather than
+;; xor reg,reg,1 which might eliminate a NOP being inserted.
+(define_split
+ [(set (match_operand:SI 0 "register_operand" "")
+ (ge:SI (match_operand:SI 1 "register_operand" "")
+ (match_operand:SI 2 "reg_or_int16_operand" "")))
+ (clobber (reg:CC 17))]
+ "optimize_size"
+ [(set (reg:CC 17)
+ (lt:CC (match_dup 1)
+ (match_dup 2)))
+ (set (match_dup 0)
+ (ne:SI (reg:CC 17) (const_int 0)))
+ (set (match_dup 0)
+ (plus:SI (match_dup 0)
+ (const_int -1)))
+ (set (match_dup 0)
+ (neg:SI (match_dup 0)))]
+ "")
+
+(define_expand "sltu"
+ [(match_operand:SI 0 "register_operand" "")]
+ ""
+ "
+{
+ rtx op0 = operands[0];
+ rtx op1 = m32r_compare_op0;
+ rtx op2 = m32r_compare_op1;
+ enum machine_mode mode = GET_MODE (op0);
+
+ if (mode != SImode)
+ FAIL;
+
+ if (! register_operand (op1, mode))
+ op1 = force_reg (mode, op1);
+
+ if (! reg_or_int16_operand (op2, mode))
+ op2 = force_reg (mode, op2);
+
+ emit_insn (gen_sltu_insn (op0, op1, op2));
+ DONE;
+}")
+
+(define_insn "sltu_insn"
+ [(set (match_operand:SI 0 "register_operand" "=r,r")
+ (ltu:SI (match_operand:SI 1 "register_operand" "r,r")
+ (match_operand:SI 2 "reg_or_int16_operand" "r,J")))
+ (clobber (reg:CC 17))]
+ ""
+ "#"
+ [(set_attr "type" "multi")
+ (set_attr "length" "6,8")])
+
+(define_split
+ [(set (match_operand:SI 0 "register_operand" "")
+ (ltu:SI (match_operand:SI 1 "register_operand" "")
+ (match_operand:SI 2 "reg_or_int16_operand" "")))
+ (clobber (reg:CC 17))]
+ ""
+ [(set (reg:CC 17)
+ (ltu:CC (match_dup 1)
+ (match_dup 2)))
+ (set (match_dup 0)
+ (ne:SI (reg:CC 17) (const_int 0)))]
+ "")
+
+(define_expand "sleu"
+ [(match_operand:SI 0 "register_operand" "")]
+ ""
+ "
+{
+ rtx op0 = operands[0];
+ rtx op1 = m32r_compare_op0;
+ rtx op2 = m32r_compare_op1;
+ enum machine_mode mode = GET_MODE (op0);
+
+ if (mode != SImode)
+ FAIL;
+
+ if (GET_CODE (op2) == CONST_INT)
+ {
+ HOST_WIDE_INT value = INTVAL (op2);
+ if (value >= 2147483647)
+ {
+ emit_move_insn (op0, const1_rtx);
+ DONE;
+ }
+
+ op2 = GEN_INT (value+1);
+ if (value < 0 || value >= 32767)
+ op2 = force_reg (mode, op2);
+
+ emit_insn (gen_sltu_insn (op0, op1, op2));
+ DONE;
+ }
+
+ if (! register_operand (op2, mode))
+ op2 = force_reg (mode, op2);
+
+ emit_insn (gen_sleu_insn (op0, op1, op2));
+ DONE;
+}")
+
+(define_insn "sleu_insn"
+ [(set (match_operand:SI 0 "register_operand" "=r")
+ (leu:SI (match_operand:SI 1 "register_operand" "r")
+ (match_operand:SI 2 "register_operand" "r")))
+ (clobber (reg:CC 17))]
+ ""
+ "#"
+ [(set_attr "type" "multi")
+ (set_attr "length" "8")])
+
+(define_split
+ [(set (match_operand:SI 0 "register_operand" "")
+ (leu:SI (match_operand:SI 1 "register_operand" "")
+ (match_operand:SI 2 "register_operand" "")))
+ (clobber (reg:CC 17))]
+ "!optimize_size"
+ [(set (reg:CC 17)
+ (ltu:CC (match_dup 2)
+ (match_dup 1)))
+ (set (match_dup 0)
+ (ne:SI (reg:CC 17) (const_int 0)))
+ (set (match_dup 0)
+ (xor:SI (match_dup 0)
+ (const_int 1)))]
+ "")
+
+;; If optimizing for space, use -(reg - 1) to invert the comparison rather than
+;; xor reg,reg,1 which might eliminate a NOP being inserted.
+(define_split
+ [(set (match_operand:SI 0 "register_operand" "")
+ (leu:SI (match_operand:SI 1 "register_operand" "")
+ (match_operand:SI 2 "register_operand" "")))
+ (clobber (reg:CC 17))]
+ "optimize_size"
+ [(set (reg:CC 17)
+ (ltu:CC (match_dup 2)
+ (match_dup 1)))
+ (set (match_dup 0)
+ (ne:SI (reg:CC 17) (const_int 0)))
+ (set (match_dup 0)
+ (plus:SI (match_dup 0)
+ (const_int -1)))
+ (set (match_dup 0)
+ (neg:SI (match_dup 0)))]
+ "")
+
+(define_expand "sgtu"
+ [(match_operand:SI 0 "register_operand" "")]
+ ""
+ "
+{
+ rtx op0 = operands[0];
+ rtx op1 = m32r_compare_op0;
+ rtx op2 = m32r_compare_op1;
+ enum machine_mode mode = GET_MODE (op0);
+
+ if (mode != SImode)
+ FAIL;
+
+ if (! register_operand (op1, mode))
+ op1 = force_reg (mode, op1);
+
+ if (! register_operand (op2, mode))
+ op2 = force_reg (mode, op2);
+
+ emit_insn (gen_sltu_insn (op0, op2, op1));
+ DONE;
+}")
+
+(define_expand "sgeu"
+ [(match_operand:SI 0 "register_operand" "")]
+ ""
+ "
+{
+ rtx op0 = operands[0];
+ rtx op1 = m32r_compare_op0;
+ rtx op2 = m32r_compare_op1;
+ enum machine_mode mode = GET_MODE (op0);
+
+ if (mode != SImode)
+ FAIL;
+
+ if (! register_operand (op1, mode))
+ op1 = force_reg (mode, op1);
+
+ if (! reg_or_int16_operand (op2, mode))
+ op2 = force_reg (mode, op2);
+
+ emit_insn (gen_sgeu_insn (op0, op1, op2));
+ DONE;
+}")
+
+(define_insn "sgeu_insn"
+ [(set (match_operand:SI 0 "register_operand" "=r,r")
+ (geu:SI (match_operand:SI 1 "register_operand" "r,r")
+ (match_operand:SI 2 "reg_or_int16_operand" "r,J")))
+ (clobber (reg:CC 17))]
+ ""
+ "#"
+ [(set_attr "type" "multi")
+ (set_attr "length" "8,10")])
+
+(define_split
+ [(set (match_operand:SI 0 "register_operand" "")
+ (geu:SI (match_operand:SI 1 "register_operand" "")
+ (match_operand:SI 2 "reg_or_int16_operand" "")))
+ (clobber (reg:CC 17))]
+ "!optimize_size"
+ [(set (reg:CC 17)
+ (ltu:CC (match_dup 1)
+ (match_dup 2)))
+ (set (match_dup 0)
+ (ne:SI (reg:CC 17) (const_int 0)))
+ (set (match_dup 0)
+ (xor:SI (match_dup 0)
+ (const_int 1)))]
+ "")
+
+;; If optimizing for space, use -(reg - 1) to invert the comparison rather than
+;; xor reg,reg,1 which might eliminate a NOP being inserted.
+(define_split
+ [(set (match_operand:SI 0 "register_operand" "")
+ (geu:SI (match_operand:SI 1 "register_operand" "")
+ (match_operand:SI 2 "reg_or_int16_operand" "")))
+ (clobber (reg:CC 17))]
+ "optimize_size"
+ [(set (reg:CC 17)
+ (ltu:CC (match_dup 1)
+ (match_dup 2)))
+ (set (match_dup 0)
+ (ne:SI (reg:CC 17) (const_int 0)))
+ (set (match_dup 0)
+ (plus:SI (match_dup 0)
+ (const_int -1)))
+ (set (match_dup 0)
+ (neg:SI (match_dup 0)))]
+ "")
+
+(define_insn "movcc_insn"
+ [(set (match_operand:SI 0 "register_operand" "=r")
+ (ne:SI (reg:CC 17) (const_int 0)))]
+ ""
+ "mvfc %0, cbr"
+ [(set_attr "type" "misc")
+ (set_attr "length" "2")])
+
+\f
;; Unconditional and other jump instructions.
(define_insn "jump"
"jmp %a0"
[(set_attr "type" "uncond_branch")
(set_attr "length" "2")])
+
+(define_insn "return"
+ [(return)]
+ "direct_return ()"
+ "jmp lr"
+ [(set_attr "type" "uncond_branch")
+ (set_attr "length" "2")])
-(define_insn "tablejump"
+(define_expand "tablejump"
+ [(parallel [(set (pc) (match_operand 0 "register_operand" "r"))
+ (use (label_ref (match_operand 1 "" "")))])]
+ ""
+ "
+{
+ /* In pic mode, our address differences are against the base of the
+ table. Add that base value back in; CSE ought to be able to combine
+ the two address loads. */
+ if (flag_pic)
+ {
+ rtx tmp, tmp2;
+
+ tmp = gen_rtx_LABEL_REF (Pmode, operands[1]);
+ tmp2 = operands[0];
+ tmp = gen_rtx_PLUS (Pmode, tmp2, tmp);
+ operands[0] = memory_address (Pmode, tmp);
+ }
+}")
+
+(define_insn "*tablejump_insn"
[(set (pc) (match_operand:SI 0 "address_operand" "p"))
(use (label_ref (match_operand 1 "" "")))]
""
(match_operand 1 "" ""))
(clobber (reg:SI 14))])]
""
- "")
+ "
+{
+ if (flag_pic)
+ current_function_uses_pic_offset_table = 1;
+}")
(define_insn "*call_via_reg"
[(call (mem:SI (match_operand:SI 0 "register_operand" "r"))
(match_operand 2 "" "")))
(clobber (reg:SI 14))])]
""
- "")
+ "
+{
+ if (flag_pic)
+ current_function_uses_pic_offset_table = 1;
+}")
(define_insn "*call_value_via_reg"
[(set (match_operand 0 "register_operand" "=r")
{
int call26_p = call26_operand (operands[1], FUNCTION_MODE);
+ if (flag_pic)
+ current_function_uses_pic_offset_table = 1;
+
if (! call26_p)
{
/* We may not be able to reach with a `bl' insn so punt and leave it to
[(const_int 0)]
""
"nop"
- [(set_attr "type" "misc")
+ [(set_attr "type" "int2")
(set_attr "length" "2")])
;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
;; all of memory. This blocks insns from being moved across this point.
(define_insn "blockage"
- [(unspec_volatile [(const_int 0)] 0)]
+ [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)]
""
"")
;; Special pattern to flush the icache.
(define_insn "flush_icache"
- [(unspec_volatile [(match_operand 0 "memory_operand" "m")] 0)]
+ [(unspec_volatile [(match_operand 0 "memory_operand" "m")]
+ UNSPECV_FLUSH_ICACHE)
+ (match_operand 1 "" "")
+ (clobber (reg:SI 17))]
""
- "* return \"nop ; flush-icache\";"
- [(set_attr "type" "misc")])
+ "* return \"trap %#%1 ; flush-icache\";"
+ [(set_attr "type" "int4")
+ (set_attr "length" "4")])
\f
-;; Split up troublesome insns for better scheduling.
+;; Speed up fabs and provide correct sign handling for -0
+
+(define_insn "absdf2"
+ [(set (match_operand:DF 0 "register_operand" "=r")
+ (abs:DF (match_operand:DF 1 "register_operand" "0")))]
+ ""
+ "#"
+ [(set_attr "type" "multi")
+ (set_attr "length" "4")])
+
+(define_split
+ [(set (match_operand:DF 0 "register_operand" "")
+ (abs:DF (match_operand:DF 1 "register_operand" "")))]
+ "reload_completed"
+ [(set (match_dup 2)
+ (ashift:SI (match_dup 2)
+ (const_int 1)))
+ (set (match_dup 2)
+ (lshiftrt:SI (match_dup 2)
+ (const_int 1)))]
+ "operands[2] = gen_highpart (SImode, operands[0]);")
+
+(define_insn "abssf2"
+ [(set (match_operand:SF 0 "register_operand" "=r")
+ (abs:SF (match_operand:SF 1 "register_operand" "0")))]
+ ""
+ "#"
+ [(set_attr "type" "multi")
+ (set_attr "length" "4")])
+
+(define_split
+ [(set (match_operand:SF 0 "register_operand" "")
+ (abs:SF (match_operand:SF 1 "register_operand" "")))]
+ "reload_completed"
+ [(set (match_dup 2)
+ (ashift:SI (match_dup 2)
+ (const_int 1)))
+ (set (match_dup 2)
+ (lshiftrt:SI (match_dup 2)
+ (const_int 1)))]
+ "operands[2] = gen_highpart (SImode, operands[0]);")
\f
-;; Peepholes go at the end.
-
-;; ??? Setting the type attribute may not be useful, but for completeness
-;; we do it.
-
-(define_peephole
- [(set (mem:SI (plus:SI (match_operand:SI 0 "register_operand" "r")
- (const_int 4)))
- (match_operand:SI 1 "register_operand" "r"))]
- "dead_or_set_p (insn, operands[0])"
- "st %1,@+%0"
- [(set_attr "type" "store")
- (set_attr "length" "2")])
+;; Conditional move instructions
+;; Based on those done for the d10v
+
+(define_expand "movsicc"
+ [
+ (set (match_operand:SI 0 "register_operand" "r")
+ (if_then_else:SI (match_operand 1 "" "")
+ (match_operand:SI 2 "conditional_move_operand" "O")
+ (match_operand:SI 3 "conditional_move_operand" "O")
+ )
+ )
+ ]
+ ""
+ "
+{
+ if (! zero_and_one (operands [2], operands [3]))
+ FAIL;
+
+ /* Generate the comparison that will set the carry flag. */
+ operands[1] = gen_compare (GET_CODE (operands[1]), m32r_compare_op0,
+ m32r_compare_op1, TRUE);
+
+ /* See other movsicc pattern below for reason why. */
+ emit_insn (gen_blockage ());
+}")
+
+;; Generate the conditional instructions based on how the carry flag is examined.
+(define_insn "*movsicc_internal"
+ [(set (match_operand:SI 0 "register_operand" "=r")
+ (if_then_else:SI (match_operand 1 "carry_compare_operand" "")
+ (match_operand:SI 2 "conditional_move_operand" "O")
+ (match_operand:SI 3 "conditional_move_operand" "O")
+ )
+ )]
+ "zero_and_one (operands [2], operands[3])"
+ "* return emit_cond_move (operands, insn);"
+ [(set_attr "type" "multi")
+ (set_attr "length" "8")
+ ]
+)
+
+\f
+;; Block moves, see m32r.c for more details.
+;; Argument 0 is the destination
+;; Argument 1 is the source
+;; Argument 2 is the length
+;; Argument 3 is the alignment
+
+(define_expand "movmemsi"
+ [(parallel [(set (match_operand:BLK 0 "general_operand" "")
+ (match_operand:BLK 1 "general_operand" ""))
+ (use (match_operand:SI 2 "immediate_operand" ""))
+ (use (match_operand:SI 3 "immediate_operand" ""))])]
+ ""
+ "
+{
+ if (operands[0]) /* avoid unused code messages */
+ {
+ m32r_expand_block_move (operands);
+ DONE;
+ }
+}")
+
+;; Insn generated by block moves
+
+(define_insn "movmemsi_internal"
+ [(set (mem:BLK (match_operand:SI 0 "register_operand" "r")) ;; destination
+ (mem:BLK (match_operand:SI 1 "register_operand" "r"))) ;; source
+ (use (match_operand:SI 2 "m32r_block_immediate_operand" "J"));; # bytes to move
+ (set (match_operand:SI 3 "register_operand" "=0")
+ (plus:SI (match_dup 0)
+ (minus (match_dup 2) (const_int 4))))
+ (set (match_operand:SI 4 "register_operand" "=1")
+ (plus:SI (match_dup 1)
+ (match_dup 2)))
+ (clobber (match_scratch:SI 5 "=&r")) ;; temp1
+ (clobber (match_scratch:SI 6 "=&r"))] ;; temp2
+ ""
+ "* m32r_output_block_move (insn, operands); return \"\"; "
+ [(set_attr "type" "store8")
+ (set_attr "length" "72")]) ;; Maximum
+
+;; PIC
+
+/* When generating pic, we need to load the symbol offset into a register.
+ So that the optimizer does not confuse this with a normal symbol load
+ we use an unspec. The offset will be loaded from a constant pool entry,
+ since that is the only type of relocation we can use. */
+
+(define_insn "pic_load_addr"
+ [(set (match_operand:SI 0 "register_operand" "=r")
+ (unspec:SI [(match_operand 1 "" "")] UNSPEC_PIC_LOAD_ADDR))]
+ "flag_pic"
+ "ld24 %0,%#%1"
+ [(set_attr "type" "int4")])
+
+(define_insn "gotoff_load_addr"
+ [(set (match_operand:SI 0 "register_operand" "=r")
+ (unspec:SI [(match_operand 1 "" "")] UNSPEC_GOTOFF))]
+ "flag_pic"
+ "seth %0, %#shigh(%1@GOTOFF)\;add3 %0, %0, low(%1@GOTOFF)"
+ [(set_attr "type" "int4")
+ (set_attr "length" "8")])
+
+;; Load program counter insns.
+
+(define_insn "get_pc"
+ [(clobber (reg:SI 14))
+ (set (match_operand 0 "register_operand" "=r")
+ (unspec [(match_operand 1 "" "")] UNSPEC_GET_PC))
+ (use (match_operand:SI 2 "immediate_operand" ""))]
+ "flag_pic"
+ "*
+{
+ if (INTVAL(operands[2]))
+ return \"bl.s .+4\;ld24 %0,%#%1\;add %0,lr\";
+ else
+ return \"bl.s .+4\;seth %0,%#shigh(%1)\;add3 %0,%0,%#low(%1+4)\;add %0,lr\";}"
+ [(set (attr "length") (if_then_else (ne (match_dup 2) (const_int 0))
+ (const_int 8)
+ (const_int 12)))])
+
+(define_expand "builtin_setjmp_receiver"
+ [(label_ref (match_operand 0 "" ""))]
+ "flag_pic"
+ "
+{
+ m32r_load_pic_register ();
+ DONE;
+}")
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