OSDN Git Service

(root) / pf3gnuchains / gcc-fork.git / blobdiff
? search:
summary | shortlog | log | commit | commitdiff | tree
raw | inline | side by side
Only expand strlen to Pmode.
[pf3gnuchains/gcc-fork.git] / gcc / config / i386 / i386.md
diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index 204a1e6..fce4268 100644 (file)
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -369,7 +369,7 @@
 \f
 ;; Processor type.
 (define_attr "cpu" "none,pentium,pentiumpro,geode,k6,athlon,k8,core2,corei7,
-                   atom,generic64,amdfam10,bdver1,btver1"
+                   atom,generic64,amdfam10,bdver1,bdver2,btver1"
   (const (symbol_ref "ix86_schedule")))
 
 ;; A basic instruction type.  Refinements due to arguments to be
@@ -790,24 +790,27 @@
 (define_code_attr sgnprefix [(sign_extend "i") (zero_extend "")
                             (div "i") (udiv "")])
 
-;; 64bit single word integer modes.
+;; All integer modes.
 (define_mode_iterator SWI1248x [QI HI SI DI])
 
-;; 64bit single word integer modes without QImode and HImode.
-(define_mode_iterator SWI48x [SI DI])
+;; All integer modes without QImode.
+(define_mode_iterator SWI248x [HI SI DI])
 
-;; Single word integer modes.
-(define_mode_iterator SWI [QI HI SI (DI "TARGET_64BIT")])
+;; All integer modes without QImode and HImode.
+(define_mode_iterator SWI48x [SI DI])
 
-;; Single word integer modes without SImode and DImode.
+;; All integer modes without SImode and DImode.
 (define_mode_iterator SWI12 [QI HI])
 
-;; Single word integer modes without DImode.
+;; All integer modes without DImode.
 (define_mode_iterator SWI124 [QI HI SI])
 
-;; Single word integer modes without QImode and DImode.
+;; All integer modes without QImode and DImode.
 (define_mode_iterator SWI24 [HI SI])
 
+;; Single word integer modes.
+(define_mode_iterator SWI [QI HI SI (DI "TARGET_64BIT")])
+
 ;; Single word integer modes without QImode.
 (define_mode_iterator SWI248 [HI SI (DI "TARGET_64BIT")])
 
@@ -824,7 +827,7 @@
                            (HI "TARGET_HIMODE_MATH")
                            SI (DI "TARGET_64BIT")])
 
-;; Math-dependant single word integer modes without DImode.
+;; Math-dependant integer modes without DImode.
 (define_mode_iterator SWIM124 [(QI "TARGET_QIMODE_MATH")
                               (HI "TARGET_HIMODE_MATH")
                               SI])
@@ -858,13 +861,13 @@
 (define_mode_attr r [(QI "q") (HI "r") (SI "r") (DI "r")])
 
 ;; Immediate operand constraint for integer modes.
-(define_mode_attr i [(QI "n") (HI "n") (SI "i") (DI "e")])
+(define_mode_attr i [(QI "n") (HI "n") (SI "e") (DI "e")])
 
 ;; General operand constraint for word modes.
-(define_mode_attr g [(QI "qmn") (HI "rmn") (SI "g") (DI "rme")])
+(define_mode_attr g [(QI "qmn") (HI "rmn") (SI "rme") (DI "rme")])
 
 ;; Immediate operand constraint for double integer modes.
-(define_mode_attr di [(SI "iF") (DI "e")])
+(define_mode_attr di [(SI "nF") (DI "e")])
 
 ;; Immediate operand constraint for shifts.
 (define_mode_attr S [(QI "I") (HI "I") (SI "I") (DI "J") (TI "O")])
@@ -873,7 +876,7 @@
 (define_mode_attr general_operand
        [(QI "general_operand")
         (HI "general_operand")
-        (SI "general_operand")
+        (SI "x86_64_general_operand")
         (DI "x86_64_general_operand")
         (TI "x86_64_general_operand")])
 
@@ -881,21 +884,21 @@
 (define_mode_attr general_szext_operand
        [(QI "general_operand")
         (HI "general_operand")
-        (SI "general_operand")
+        (SI "x86_64_szext_general_operand")
         (DI "x86_64_szext_general_operand")])
 
 ;; Immediate operand predicate for integer modes.
 (define_mode_attr immediate_operand
        [(QI "immediate_operand")
         (HI "immediate_operand")
-        (SI "immediate_operand")
+        (SI "x86_64_immediate_operand")
         (DI "x86_64_immediate_operand")])
 
 ;; Nonmemory operand predicate for integer modes.
 (define_mode_attr nonmemory_operand
        [(QI "nonmemory_operand")
         (HI "nonmemory_operand")
-        (SI "nonmemory_operand")
+        (SI "x86_64_nonmemory_operand")
         (DI "x86_64_nonmemory_operand")])
 
 ;; Operand predicate for shifts.
@@ -927,15 +930,6 @@
 ;; All x87 floating point modes
 (define_mode_iterator X87MODEF [SF DF XF])
 
-;; All integer modes handled by x87 fisttp operator.
-(define_mode_iterator X87MODEI [HI SI DI])
-
-;; All integer modes handled by integer x87 operators.
-(define_mode_iterator X87MODEI12 [HI SI])
-
-;; All integer modes handled by SSE cvtts?2si* operators.
-(define_mode_iterator SSEMODEI24 [SI DI])
-
 ;; SSE instruction suffix for various modes
 (define_mode_attr ssemodesuffix
   [(SF "ss") (DF "sd")
@@ -1425,7 +1419,7 @@
          [(compare:CCFP
             (match_operand 1 "register_operand" "f")
             (match_operator 3 "float_operator"
-              [(match_operand:X87MODEI12 2 "memory_operand" "m")]))]
+              [(match_operand:SWI24 2 "memory_operand" "m")]))]
          UNSPEC_FNSTSW))]
   "X87_FLOAT_MODE_P (GET_MODE (operands[1]))
    && (TARGET_USE_<MODE>MODE_FIOP || optimize_function_for_size_p (cfun))
@@ -1441,7 +1435,7 @@
        (compare:CCFP
          (match_operand 1 "register_operand" "f")
          (match_operator 3 "float_operator"
-           [(match_operand:X87MODEI12 2 "memory_operand" "m")])))
+           [(match_operand:SWI24 2 "memory_operand" "m")])))
    (clobber (match_operand:HI 0 "register_operand" "=a"))]
   "X87_FLOAT_MODE_P (GET_MODE (operands[1]))
    && TARGET_SAHF && !TARGET_CMOVE
@@ -1981,9 +1975,9 @@
 
 (define_insn "*movdi_internal_rex64"
   [(set (match_operand:DI 0 "nonimmediate_operand"
-         "=r,r  ,r,m ,!m,*y,*y,?r ,m ,?*Ym,?*y,*x,*x,?r ,m,?*Yi,*x,?*x,?*Ym")
+         "=r,r  ,r,m ,!m,*y,m*y,?*y,?r ,?*Ym,*x,m ,*x,*x,?r ,?*Yi,?*x,?*Ym")
        (match_operand:DI 1 "general_operand"
-         "Z ,rem,i,re,n ,C ,*y,*Ym,*y,r   ,m  ,C ,*x,*Yi,*x,r  ,m ,*Ym,*x"))]
+         "Z ,rem,i,re,n ,C ,*y ,m  ,*Ym,r   ,C ,*x,*x,m ,*Yi,r   ,*Ym,*x"))]
   "TARGET_64BIT && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
 {
   switch (get_attr_type (insn))
@@ -2033,19 +2027,19 @@
     }
 }
   [(set (attr "type")
-     (cond [(eq_attr "alternative" "5")
+     (cond [(eq_attr "alternative" "4")
+             (const_string "multi")
+           (eq_attr "alternative" "5")
              (const_string "mmx")
-           (eq_attr "alternative" "6,7,8,9,10")
+           (eq_attr "alternative" "6,7,8,9")
              (const_string "mmxmov")
-           (eq_attr "alternative" "11")
+           (eq_attr "alternative" "10")
              (const_string "sselog1")
-           (eq_attr "alternative" "12,13,14,15,16")
+           (eq_attr "alternative" "11,12,13,14,15")
              (const_string "ssemov")
-           (eq_attr "alternative" "17,18")
+           (eq_attr "alternative" "16,17")
              (const_string "ssecvt")
-           (eq_attr "alternative" "4")
-             (const_string "multi")
-           (match_operand:DI 1 "pic_32bit_operand" "")
+           (match_operand 1 "pic_32bit_operand" "")
              (const_string "lea")
           ]
           (const_string "imov")))
@@ -2060,18 +2054,18 @@
         (const_string "8")
         (const_string "*")))
    (set (attr "prefix_rex")
-     (if_then_else (eq_attr "alternative" "7,9")
+     (if_then_else (eq_attr "alternative" "8,9")
        (const_string "1")
        (const_string "*")))
    (set (attr "prefix_data16")
-     (if_then_else (eq_attr "alternative" "15")
+     (if_then_else (eq_attr "alternative" "11")
        (const_string "1")
        (const_string "*")))
    (set (attr "prefix")
-     (if_then_else (eq_attr "alternative" "11,12,13,14,15,16")
+     (if_then_else (eq_attr "alternative" "10,11,12,13,14,15")
        (const_string "maybe_vex")
        (const_string "orig")))
-   (set_attr "mode" "SI,DI,DI,DI,SI,DI,DI,DI,DI,DI,DI,TI,TI,DI,DI,DI,DI,DI,DI")])
+   (set_attr "mode" "SI,DI,DI,DI,SI,DI,DI,DI,DI,DI,TI,DI,TI,DI,DI,DI,DI,DI")])
 
 ;; Convert impossible stores of immediate to existing instructions.
 ;; First try to get scratch register and go through it.  In case this
@@ -2157,7 +2151,7 @@
   [(set (attr "isa")
      (if_then_else (eq_attr "alternative" "9,10,11,12")
        (const_string "noavx")
-       (const_string "base")))
+       (const_string "*")))
    (set (attr "type")
      (cond [(eq_attr "alternative" "0,1")
              (const_string "multi")
@@ -2190,7 +2184,7 @@
   [(set (match_operand:SI 0 "nonimmediate_operand"
                        "=r,m ,*y,*y,?rm,?*y,*x,*x,?r ,m ,?*Yi,*x")
        (match_operand:SI 1 "general_operand"
-                       "g ,ri,C ,*y,*y ,rm ,C ,*x,*Yi,*x,r   ,m "))]
+                       "g ,re,C ,*y,*y ,rm ,C ,*x,*Yi,*x,r   ,m "))]
   "!(MEM_P (operands[0]) && MEM_P (operands[1]))"
 {
   switch (get_attr_type (insn))
@@ -2238,7 +2232,7 @@
              (const_string "sselog1")
            (eq_attr "alternative" "7,8,9,10,11")
              (const_string "ssemov")
-           (match_operand:DI 1 "pic_32bit_operand" "")
+           (match_operand 1 "pic_32bit_operand" "")
              (const_string "lea")
           ]
           (const_string "imov")))
@@ -2962,25 +2956,18 @@
     case 10:
       switch (get_attr_mode (insn))
        {
-       case MODE_V4SF:
-         return "%vmovaps\t{%1, %0|%0, %1}";
        case MODE_V2DF:
-         if (TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL)
-           return "%vmovaps\t{%1, %0|%0, %1}";
-         else
+         if (!TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL)
            return "%vmovapd\t{%1, %0|%0, %1}";
-       case MODE_TI:
-         if (TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL)
-           return "%vmovaps\t{%1, %0|%0, %1}";
-         else
-           return "%vmovdqa\t{%1, %0|%0, %1}";
+       case MODE_V4SF:
+         return "%vmovaps\t{%1, %0|%0, %1}";
+
        case MODE_DI:
          return "%vmovq\t{%1, %0|%0, %1}";
        case MODE_DF:
          if (TARGET_AVX && REG_P (operands[0]) && REG_P (operands[1]))
            return "vmovsd\t{%1, %0, %0|%0, %0, %1}";
-         else
-           return "%vmovsd\t{%1, %0|%0, %1}";
+         return "%vmovsd\t{%1, %0|%0, %1}";
        case MODE_V1DF:
          return "%vmovlpd\t{%1, %d0|%d0, %1}";
        case MODE_V2SF:
@@ -3023,13 +3010,6 @@
               (eq_attr "alternative" "3,4,5,6,11,12")
                 (const_string "DI")
 
-              /* For SSE1, we have many fewer alternatives.  */
-              (eq (symbol_ref "TARGET_SSE2") (const_int 0))
-                (cond [(eq_attr "alternative" "7,8")
-                         (const_string "V4SF")
-                      ]
-                  (const_string "V2SF"))
-
               /* xorps is one byte shorter.  */
               (eq_attr "alternative" "7")
                 (cond [(ne (symbol_ref "optimize_function_for_size_p (cfun)")
@@ -3108,35 +3088,22 @@
     case 8:
       switch (get_attr_mode (insn))
        {
-       case MODE_V4SF:
-         return "%vmovaps\t{%1, %0|%0, %1}";
        case MODE_V2DF:
-         if (TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL)
-           return "%vmovaps\t{%1, %0|%0, %1}";
-         else
+         if (!TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL)
            return "%vmovapd\t{%1, %0|%0, %1}";
-       case MODE_TI:
-         if (TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL)
-           return "%vmovaps\t{%1, %0|%0, %1}";
-         else
-           return "%vmovdqa\t{%1, %0|%0, %1}";
+       case MODE_V4SF:
+         return "%vmovaps\t{%1, %0|%0, %1}";
+
        case MODE_DI:
          return "%vmovq\t{%1, %0|%0, %1}";
        case MODE_DF:
          if (TARGET_AVX && REG_P (operands[0]) && REG_P (operands[1]))
            return "vmovsd\t{%1, %0, %0|%0, %0, %1}";
-         else
-           return "%vmovsd\t{%1, %0|%0, %1}";
+         return "%vmovsd\t{%1, %0|%0, %1}";
        case MODE_V1DF:
-         if (TARGET_AVX && REG_P (operands[0]))
-           return "vmovlpd\t{%1, %0, %0|%0, %0, %1}";
-         else
-           return "%vmovlpd\t{%1, %0|%0, %1}";
+         return "%vmovlpd\t{%1, %d0|%d0, %1}";
        case MODE_V2SF:
-         if (TARGET_AVX && REG_P (operands[0]))
-           return "vmovlps\t{%1, %0, %0|%0, %0, %1}";
-         else
-           return "%vmovlps\t{%1, %0|%0, %1}";
+         return "%vmovlps\t{%1, %d0|%d0, %1}";
        default:
          gcc_unreachable ();
        }
@@ -3162,9 +3129,9 @@
 
               /* For SSE1, we have many fewer alternatives.  */
               (eq (symbol_ref "TARGET_SSE2") (const_int 0))
-                (cond [(eq_attr "alternative" "5,6")
-                         (const_string "V4SF")
-                      ]
+                (if_then_else
+                  (eq_attr "alternative" "5,6")
+                  (const_string "V4SF")
                   (const_string "V2SF"))
 
               /* xorps is one byte shorter.  */
@@ -3207,9 +3174,9 @@
 
 (define_insn "*movsf_internal"
   [(set (match_operand:SF 0 "nonimmediate_operand"
-         "=f,m,f,?r ,?m,x,x,x ,m,!*y,!m,!*y,?Yi,?r,!*Ym,!r")
+         "=f,m,f,?r ,?m,x,x,x,m,!*y,!m,!*y,?Yi,?r,!*Ym,!r")
        (match_operand:SF 1 "general_operand"
-         "fm,f,G,rmF,Fr,C,x,xm,x,m  ,*y,*y ,r  ,Yi,r   ,*Ym"))]
+         "fm,f,G,rmF,Fr,C,x,m,x,m  ,*y,*y ,r  ,Yi,r   ,*Ym"))]
   "!(MEM_P (operands[0]) && MEM_P (operands[1]))
    && (!can_create_pseudo_p ()
        || (ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_LARGE)
@@ -3240,23 +3207,24 @@
     case 6:
       if (get_attr_mode (insn) == MODE_V4SF)
        return "%vmovaps\t{%1, %0|%0, %1}";
-      else
-       return "%vmovss\t{%1, %d0|%d0, %1}";
-    case 7:
-      if (TARGET_AVX && REG_P (operands[1]))
+      if (TARGET_AVX)
        return "vmovss\t{%1, %0, %0|%0, %0, %1}";
-      else
-       return "%vmovss\t{%1, %0|%0, %1}";
+
+    case 7:
     case 8:
       return "%vmovss\t{%1, %0|%0, %1}";
 
-    case 9: case 10: case 14: case 15:
+    case 9:
+    case 10:
+    case 14:
+    case 15:
       return "movd\t{%1, %0|%0, %1}";
 
     case 11:
       return "movq\t{%1, %0|%0, %1}";
 
-    case 12: case 13:
+    case 12:
+    case 13:
       return "%vmovd\t{%1, %0|%0, %1}";
 
     default:
@@ -4415,33 +4383,33 @@
 (define_peephole2
   [(set (match_operand:MODEF 0 "register_operand" "")
        (match_operand:MODEF 1 "memory_operand" ""))
-   (set (match_operand:SSEMODEI24 2 "register_operand" "")
-       (fix:SSEMODEI24 (match_dup 0)))]
+   (set (match_operand:SWI48x 2 "register_operand" "")
+       (fix:SWI48x (match_dup 0)))]
   "TARGET_SHORTEN_X87_SSE
    && !(TARGET_AVOID_VECTOR_DECODE && optimize_insn_for_speed_p ())
    && peep2_reg_dead_p (2, operands[0])"
-  [(set (match_dup 2) (fix:SSEMODEI24 (match_dup 1)))])
+  [(set (match_dup 2) (fix:SWI48x (match_dup 1)))])
 
 ;; Avoid vector decoded forms of the instruction.
 (define_peephole2
   [(match_scratch:DF 2 "Y2")
-   (set (match_operand:SSEMODEI24 0 "register_operand" "")
-       (fix:SSEMODEI24 (match_operand:DF 1 "memory_operand" "")))]
+   (set (match_operand:SWI48x 0 "register_operand" "")
+       (fix:SWI48x (match_operand:DF 1 "memory_operand" "")))]
   "TARGET_AVOID_VECTOR_DECODE && optimize_insn_for_speed_p ()"
   [(set (match_dup 2) (match_dup 1))
-   (set (match_dup 0) (fix:SSEMODEI24 (match_dup 2)))])
+   (set (match_dup 0) (fix:SWI48x (match_dup 2)))])
 
 (define_peephole2
   [(match_scratch:SF 2 "x")
-   (set (match_operand:SSEMODEI24 0 "register_operand" "")
-       (fix:SSEMODEI24 (match_operand:SF 1 "memory_operand" "")))]
+   (set (match_operand:SWI48x 0 "register_operand" "")
+       (fix:SWI48x (match_operand:SF 1 "memory_operand" "")))]
   "TARGET_AVOID_VECTOR_DECODE && optimize_insn_for_speed_p ()"
   [(set (match_dup 2) (match_dup 1))
-   (set (match_dup 0) (fix:SSEMODEI24 (match_dup 2)))])
+   (set (match_dup 0) (fix:SWI48x (match_dup 2)))])
 
 (define_insn_and_split "fix_trunc<mode>_fisttp_i387_1"
-  [(set (match_operand:X87MODEI 0 "nonimmediate_operand" "")
-       (fix:X87MODEI (match_operand 1 "register_operand" "")))]
+  [(set (match_operand:SWI248x 0 "nonimmediate_operand" "")
+       (fix:SWI248x (match_operand 1 "register_operand" "")))]
   "X87_FLOAT_MODE_P (GET_MODE (operands[1]))
    && TARGET_FISTTP
    && !((SSE_FLOAT_MODE_P (GET_MODE (operands[1]))
@@ -4467,8 +4435,8 @@
    (set_attr "mode" "<MODE>")])
 
 (define_insn "fix_trunc<mode>_i387_fisttp"
-  [(set (match_operand:X87MODEI 0 "memory_operand" "=m")
-       (fix:X87MODEI (match_operand 1 "register_operand" "f")))
+  [(set (match_operand:SWI248x 0 "memory_operand" "=m")
+       (fix:SWI248x (match_operand 1 "register_operand" "f")))
    (clobber (match_scratch:XF 2 "=&1f"))]
   "X87_FLOAT_MODE_P (GET_MODE (operands[1]))
    && TARGET_FISTTP
@@ -4480,9 +4448,9 @@
    (set_attr "mode" "<MODE>")])
 
 (define_insn "fix_trunc<mode>_i387_fisttp_with_temp"
-  [(set (match_operand:X87MODEI 0 "nonimmediate_operand" "=m,?r")
-       (fix:X87MODEI (match_operand 1 "register_operand" "f,f")))
-   (clobber (match_operand:X87MODEI 2 "memory_operand" "=X,m"))
+  [(set (match_operand:SWI248x 0 "nonimmediate_operand" "=m,?r")
+       (fix:SWI248x (match_operand 1 "register_operand" "f,f")))
+   (clobber (match_operand:SWI248x 2 "memory_operand" "=X,m"))
    (clobber (match_scratch:XF 3 "=&1f,&1f"))]
   "X87_FLOAT_MODE_P (GET_MODE (operands[1]))
    && TARGET_FISTTP
@@ -4494,22 +4462,22 @@
    (set_attr "mode" "<MODE>")])
 
 (define_split
-  [(set (match_operand:X87MODEI 0 "register_operand" "")
-       (fix:X87MODEI (match_operand 1 "register_operand" "")))
-   (clobber (match_operand:X87MODEI 2 "memory_operand" ""))
+  [(set (match_operand:SWI248x 0 "register_operand" "")
+       (fix:SWI248x (match_operand 1 "register_operand" "")))
+   (clobber (match_operand:SWI248x 2 "memory_operand" ""))
    (clobber (match_scratch 3 ""))]
   "reload_completed"
-  [(parallel [(set (match_dup 2) (fix:X87MODEI (match_dup 1)))
+  [(parallel [(set (match_dup 2) (fix:SWI248x (match_dup 1)))
              (clobber (match_dup 3))])
    (set (match_dup 0) (match_dup 2))])
 
 (define_split
-  [(set (match_operand:X87MODEI 0 "memory_operand" "")
-       (fix:X87MODEI (match_operand 1 "register_operand" "")))
-   (clobber (match_operand:X87MODEI 2 "memory_operand" ""))
+  [(set (match_operand:SWI248x 0 "memory_operand" "")
+       (fix:SWI248x (match_operand 1 "register_operand" "")))
+   (clobber (match_operand:SWI248x 2 "memory_operand" ""))
    (clobber (match_scratch 3 ""))]
   "reload_completed"
-  [(parallel [(set (match_dup 0) (fix:X87MODEI (match_dup 1)))
+  [(parallel [(set (match_dup 0) (fix:SWI248x (match_dup 1)))
              (clobber (match_dup 3))])])
 
 ;; See the comments in i386.h near OPTIMIZE_MODE_SWITCHING for the description
@@ -4518,8 +4486,8 @@
 ;; clobbering insns can be used. Look at emit_i387_cw_initialization ()
 ;; function in i386.c.
 (define_insn_and_split "*fix_trunc<mode>_i387_1"
-  [(set (match_operand:X87MODEI 0 "nonimmediate_operand" "")
-       (fix:X87MODEI (match_operand 1 "register_operand" "")))
+  [(set (match_operand:SWI248x 0 "nonimmediate_operand" "")
+       (fix:SWI248x (match_operand 1 "register_operand" "")))
    (clobber (reg:CC FLAGS_REG))]
   "X87_FLOAT_MODE_P (GET_MODE (operands[1]))
    && !TARGET_FISTTP
@@ -4607,8 +4575,8 @@
              (clobber (match_dup 5))])])
 
 (define_insn "fix_trunc<mode>_i387"
-  [(set (match_operand:X87MODEI12 0 "memory_operand" "=m")
-       (fix:X87MODEI12 (match_operand 1 "register_operand" "f")))
+  [(set (match_operand:SWI24 0 "memory_operand" "=m")
+       (fix:SWI24 (match_operand 1 "register_operand" "f")))
    (use (match_operand:HI 2 "memory_operand" "m"))
    (use (match_operand:HI 3 "memory_operand" "m"))]
   "X87_FLOAT_MODE_P (GET_MODE (operands[1]))
@@ -4620,11 +4588,11 @@
    (set_attr "mode" "<MODE>")])
 
 (define_insn "fix_trunc<mode>_i387_with_temp"
-  [(set (match_operand:X87MODEI12 0 "nonimmediate_operand" "=m,?r")
-       (fix:X87MODEI12 (match_operand 1 "register_operand" "f,f")))
+  [(set (match_operand:SWI24 0 "nonimmediate_operand" "=m,?r")
+       (fix:SWI24 (match_operand 1 "register_operand" "f,f")))
    (use (match_operand:HI 2 "memory_operand" "m,m"))
    (use (match_operand:HI 3 "memory_operand" "m,m"))
-   (clobber (match_operand:X87MODEI12 4 "memory_operand" "=X,m"))]
+   (clobber (match_operand:SWI24 4 "memory_operand" "=X,m"))]
   "X87_FLOAT_MODE_P (GET_MODE (operands[1]))
    && !TARGET_FISTTP
    && !SSE_FLOAT_MODE_P (GET_MODE (operands[1]))"
@@ -4634,25 +4602,25 @@
    (set_attr "mode" "<MODE>")])
 
 (define_split
-  [(set (match_operand:X87MODEI12 0 "register_operand" "")
-       (fix:X87MODEI12 (match_operand 1 "register_operand" "")))
+  [(set (match_operand:SWI24 0 "register_operand" "")
+       (fix:SWI24 (match_operand 1 "register_operand" "")))
    (use (match_operand:HI 2 "memory_operand" ""))
    (use (match_operand:HI 3 "memory_operand" ""))
-   (clobber (match_operand:X87MODEI12 4 "memory_operand" ""))]
+   (clobber (match_operand:SWI24 4 "memory_operand" ""))]
   "reload_completed"
-  [(parallel [(set (match_dup 4) (fix:X87MODEI12 (match_dup 1)))
+  [(parallel [(set (match_dup 4) (fix:SWI24 (match_dup 1)))
              (use (match_dup 2))
              (use (match_dup 3))])
    (set (match_dup 0) (match_dup 4))])
 
 (define_split
-  [(set (match_operand:X87MODEI12 0 "memory_operand" "")
-       (fix:X87MODEI12 (match_operand 1 "register_operand" "")))
+  [(set (match_operand:SWI24 0 "memory_operand" "")
+       (fix:SWI24 (match_operand 1 "register_operand" "")))
    (use (match_operand:HI 2 "memory_operand" ""))
    (use (match_operand:HI 3 "memory_operand" ""))
-   (clobber (match_operand:X87MODEI12 4 "memory_operand" ""))]
+   (clobber (match_operand:SWI24 4 "memory_operand" ""))]
   "reload_completed"
-  [(parallel [(set (match_dup 0) (fix:X87MODEI12 (match_dup 1)))
+  [(parallel [(set (match_dup 0) (fix:SWI24 (match_dup 1)))
              (use (match_dup 2))
              (use (match_dup 3))])])
 
@@ -4752,22 +4720,22 @@
     && reload_completed"
   [(set (match_dup 0) (float:X87MODEF (match_dup 1)))])
 
-(define_expand "float<SSEMODEI24:mode><X87MODEF:mode>2"
+(define_expand "float<SWI48x:mode><X87MODEF:mode>2"
   [(set (match_operand:X87MODEF 0 "register_operand" "")
        (float:X87MODEF
-         (match_operand:SSEMODEI24 1 "nonimmediate_operand" "")))]
+         (match_operand:SWI48x 1 "nonimmediate_operand" "")))]
   "TARGET_80387
-   || ((<SSEMODEI24:MODE>mode != DImode || TARGET_64BIT)
+   || ((<SWI48x:MODE>mode != DImode || TARGET_64BIT)
        && SSE_FLOAT_MODE_P (<X87MODEF:MODE>mode) && TARGET_SSE_MATH)"
 {
-  if (!((<SSEMODEI24:MODE>mode != DImode || TARGET_64BIT)
+  if (!((<SWI48x:MODE>mode != DImode || TARGET_64BIT)
        && SSE_FLOAT_MODE_P (<X87MODEF:MODE>mode) && TARGET_SSE_MATH)
-      && !X87_ENABLE_FLOAT (<X87MODEF:MODE>mode, <SSEMODEI24:MODE>mode))
+      && !X87_ENABLE_FLOAT (<X87MODEF:MODE>mode, <SWI48x:MODE>mode))
     {
       rtx reg = gen_reg_rtx (XFmode);
       rtx (*insn)(rtx, rtx);
 
-      emit_insn (gen_float<SSEMODEI24:mode>xf2 (reg, operands[1]));
+      emit_insn (gen_float<SWI48x:mode>xf2 (reg, operands[1]));
 
       if (<X87MODEF:MODE>mode == SFmode)
        insn = gen_truncxfsf2;
@@ -4782,17 +4750,17 @@
 })
 
 ;; Pre-reload splitter to add memory clobber to the pattern.
-(define_insn_and_split "*float<SSEMODEI24:mode><X87MODEF:mode>2_1"
+(define_insn_and_split "*float<SWI48x:mode><X87MODEF:mode>2_1"
   [(set (match_operand:X87MODEF 0 "register_operand" "")
-       (float:X87MODEF (match_operand:SSEMODEI24 1 "register_operand" "")))]
+       (float:X87MODEF (match_operand:SWI48x 1 "register_operand" "")))]
   "((TARGET_80387
-     && X87_ENABLE_FLOAT (<X87MODEF:MODE>mode, <SSEMODEI24:MODE>mode)
-     && (!((<SSEMODEI24:MODE>mode != DImode || TARGET_64BIT)
+     && X87_ENABLE_FLOAT (<X87MODEF:MODE>mode, <SWI48x:MODE>mode)
+     && (!((<SWI48x:MODE>mode != DImode || TARGET_64BIT)
           && SSE_FLOAT_MODE_P (<X87MODEF:MODE>mode) && TARGET_SSE_MATH)
         || TARGET_MIX_SSE_I387))
-    || ((<SSEMODEI24:MODE>mode != DImode || TARGET_64BIT)
+    || ((<SWI48x:MODE>mode != DImode || TARGET_64BIT)
        && SSE_FLOAT_MODE_P (<X87MODEF:MODE>mode) && TARGET_SSE_MATH
-       && ((<SSEMODEI24:MODE>mode == SImode
+       && ((<SWI48x:MODE>mode == SImode
             && TARGET_SSE2 && TARGET_USE_VECTOR_CONVERTS
             && optimize_function_for_speed_p (cfun)
             && flag_trapping_math)
@@ -4804,11 +4772,11 @@
   [(parallel [(set (match_dup 0) (float:X87MODEF (match_dup 1)))
              (clobber (match_dup 2))])]
 {
-  operands[2] = assign_386_stack_local (<SSEMODEI24:MODE>mode, SLOT_TEMP);
+  operands[2] = assign_386_stack_local (<SWI48x:MODE>mode, SLOT_TEMP);
 
   /* Avoid store forwarding (partial memory) stall penalty
      by passing DImode value through XMM registers.  */
-  if (<SSEMODEI24:MODE>mode == DImode && !TARGET_64BIT
+  if (<SWI48x:MODE>mode == DImode && !TARGET_64BIT
       && TARGET_80387 && TARGET_SSE2 && TARGET_INTER_UNIT_MOVES
       && optimize_function_for_speed_p (cfun))
     {
@@ -4851,12 +4819,12 @@
    (set_attr "bdver1_decode" "*,direct")
    (set_attr "fp_int_src" "true")])
 
-(define_insn "*float<SSEMODEI24:mode><MODEF:mode>2_mixed_with_temp"
+(define_insn "*float<SWI48x:mode><MODEF:mode>2_mixed_with_temp"
   [(set (match_operand:MODEF 0 "register_operand" "=f,f,x,x")
        (float:MODEF
-         (match_operand:SSEMODEI24 1 "nonimmediate_operand" "m,?r,r,m")))
-  (clobber (match_operand:SSEMODEI24 2 "memory_operand" "=X,m,m,X"))]
-  "(<SSEMODEI24:MODE>mode != DImode || TARGET_64BIT)
+         (match_operand:SWI48x 1 "nonimmediate_operand" "m,?r,r,m")))
+   (clobber (match_operand:SWI48x 2 "memory_operand" "=X,m,m,X"))]
+  "(<SWI48x:MODE>mode != DImode || TARGET_64BIT)
    && SSE_FLOAT_MODE_P (<MODEF:MODE>mode) && TARGET_MIX_SSE_I387"
   "#"
   [(set_attr "type" "fmov,multi,sseicvt,sseicvt")
@@ -4869,9 +4837,9 @@
 
 (define_split
   [(set (match_operand:MODEF 0 "register_operand" "")
-       (float:MODEF (match_operand:SSEMODEI24 1 "register_operand" "")))
-   (clobber (match_operand:SSEMODEI24 2 "memory_operand" ""))]
-  "(<SSEMODEI24:MODE>mode != DImode || TARGET_64BIT)
+       (float:MODEF (match_operand:SWI48x 1 "register_operand" "")))
+   (clobber (match_operand:SWI48x 2 "memory_operand" ""))]
+  "(<SWI48x:MODE>mode != DImode || TARGET_64BIT)
    && SSE_FLOAT_MODE_P (<MODEF:MODE>mode) && TARGET_MIX_SSE_I387
    && TARGET_INTER_UNIT_CONVERSIONS
    && reload_completed
@@ -4882,9 +4850,9 @@
 
 (define_split
   [(set (match_operand:MODEF 0 "register_operand" "")
-       (float:MODEF (match_operand:SSEMODEI24 1 "register_operand" "")))
-   (clobber (match_operand:SSEMODEI24 2 "memory_operand" ""))]
-  "(<SSEMODEI24:MODE>mode != DImode || TARGET_64BIT)
+       (float:MODEF (match_operand:SWI48x 1 "register_operand" "")))
+   (clobber (match_operand:SWI48x 2 "memory_operand" ""))]
+  "(<SWI48x:MODE>mode != DImode || TARGET_64BIT)
    && SSE_FLOAT_MODE_P (<MODEF:MODE>mode) && TARGET_MIX_SSE_I387
    && !(TARGET_INTER_UNIT_CONVERSIONS || optimize_function_for_size_p (cfun))
    && reload_completed
@@ -4894,24 +4862,24 @@
   [(set (match_dup 2) (match_dup 1))
    (set (match_dup 0) (float:MODEF (match_dup 2)))])
 
-(define_insn "*float<SSEMODEI24:mode><MODEF:mode>2_mixed_interunit"
+(define_insn "*float<SWI48x:mode><MODEF:mode>2_mixed_interunit"
   [(set (match_operand:MODEF 0 "register_operand" "=f,x,x")
        (float:MODEF
-         (match_operand:SSEMODEI24 1 "nonimmediate_operand" "m,r,m")))]
-  "(<SSEMODEI24:MODE>mode != DImode || TARGET_64BIT)
+         (match_operand:SWI48x 1 "nonimmediate_operand" "m,r,m")))]
+  "(<SWI48x:MODE>mode != DImode || TARGET_64BIT)
    && SSE_FLOAT_MODE_P (<MODEF:MODE>mode) && TARGET_MIX_SSE_I387
    && (TARGET_INTER_UNIT_CONVERSIONS || optimize_function_for_size_p (cfun))"
   "@
    fild%Z1\t%1
-   %vcvtsi2<MODEF:ssemodesuffix><SSEMODEI24:rex64suffix>\t{%1, %d0|%d0, %1}
-   %vcvtsi2<MODEF:ssemodesuffix><SSEMODEI24:rex64suffix>\t{%1, %d0|%d0, %1}"
+   %vcvtsi2<MODEF:ssemodesuffix><SWI48x:rex64suffix>\t{%1, %d0|%d0, %1}
+   %vcvtsi2<MODEF:ssemodesuffix><SWI48x:rex64suffix>\t{%1, %d0|%d0, %1}"
   [(set_attr "type" "fmov,sseicvt,sseicvt")
    (set_attr "prefix" "orig,maybe_vex,maybe_vex")
    (set_attr "mode" "<MODEF:MODE>")
    (set (attr "prefix_rex")
      (if_then_else
        (and (eq_attr "prefix" "maybe_vex")
-           (ne (symbol_ref "<SSEMODEI24:MODE>mode == DImode") (const_int 0)))
+           (ne (symbol_ref "<SWI48x:MODE>mode == DImode") (const_int 0)))
        (const_string "1")
        (const_string "*")))
    (set_attr "unit" "i387,*,*")
@@ -4920,23 +4888,23 @@
    (set_attr "bdver1_decode" "*,double,direct")
    (set_attr "fp_int_src" "true")])
 
-(define_insn "*float<SSEMODEI24:mode><MODEF:mode>2_mixed_nointerunit"
+(define_insn "*float<SWI48x:mode><MODEF:mode>2_mixed_nointerunit"
   [(set (match_operand:MODEF 0 "register_operand" "=f,x")
        (float:MODEF
-         (match_operand:SSEMODEI24 1 "memory_operand" "m,m")))]
-  "(<SSEMODEI24:MODE>mode != DImode || TARGET_64BIT)
+         (match_operand:SWI48x 1 "memory_operand" "m,m")))]
+  "(<SWI48x:MODE>mode != DImode || TARGET_64BIT)
    && SSE_FLOAT_MODE_P (<MODEF:MODE>mode) && TARGET_MIX_SSE_I387
    && !(TARGET_INTER_UNIT_CONVERSIONS || optimize_function_for_size_p (cfun))"
   "@
    fild%Z1\t%1
-   %vcvtsi2<MODEF:ssemodesuffix><SSEMODEI24:rex64suffix>\t{%1, %d0|%d0, %1}"
+   %vcvtsi2<MODEF:ssemodesuffix><SWI48x:rex64suffix>\t{%1, %d0|%d0, %1}"
   [(set_attr "type" "fmov,sseicvt")
    (set_attr "prefix" "orig,maybe_vex")
    (set_attr "mode" "<MODEF:MODE>")
    (set (attr "prefix_rex")
      (if_then_else
        (and (eq_attr "prefix" "maybe_vex")
-           (ne (symbol_ref "<SSEMODEI24:MODE>mode == DImode") (const_int 0)))
+           (ne (symbol_ref "<SWI48x:MODE>mode == DImode") (const_int 0)))
        (const_string "1")
        (const_string "*")))
    (set_attr "athlon_decode" "*,direct")
@@ -5054,11 +5022,20 @@
   if (GET_CODE (op1) == SUBREG)
     op1 = SUBREG_REG (op1);
 
-  if (GENERAL_REG_P (op1) && TARGET_INTER_UNIT_MOVES)
+  if (GENERAL_REG_P (op1))
     {
       operands[4] = simplify_gen_subreg (V4SImode, operands[0], <MODE>mode, 0);
-      emit_insn (gen_sse2_loadld (operands[4],
-                                 CONST0_RTX (V4SImode), operands[1]));
+      if (TARGET_INTER_UNIT_MOVES)
+       emit_insn (gen_sse2_loadld (operands[4],
+                                   CONST0_RTX (V4SImode), operands[1]));
+      else
+       {
+         operands[5] = ix86_force_to_memory (GET_MODE (operands[1]),
+                                             operands[1]);
+         emit_insn (gen_sse2_loadld (operands[4],
+                                     CONST0_RTX (V4SImode), operands[5]));
+         ix86_free_from_memory (GET_MODE (operands[1]));
+       }
     }
   /* We can ignore possible trapping value in the
      high part of SSE register for non-trapping math. */
@@ -5093,12 +5070,12 @@
   DONE;
 })
 
-(define_insn "*float<SSEMODEI24:mode><MODEF:mode>2_sse_with_temp"
+(define_insn "*float<SWI48x:mode><MODEF:mode>2_sse_with_temp"
   [(set (match_operand:MODEF 0 "register_operand" "=x,x")
        (float:MODEF
-         (match_operand:SSEMODEI24 1 "nonimmediate_operand" "r,m")))
-  (clobber (match_operand:SSEMODEI24 2 "memory_operand" "=m,X"))]
-  "(<SSEMODEI24:MODE>mode != DImode || TARGET_64BIT)
+         (match_operand:SWI48x 1 "nonimmediate_operand" "r,m")))
+  (clobber (match_operand:SWI48x 2 "memory_operand" "=m,X"))]
+  "(<SWI48x:MODE>mode != DImode || TARGET_64BIT)
    && SSE_FLOAT_MODE_P (<MODEF:MODE>mode) && TARGET_SSE_MATH"
   "#"
   [(set_attr "type" "sseicvt")
@@ -5108,21 +5085,21 @@
    (set_attr "bdver1_decode" "double,direct")
    (set_attr "fp_int_src" "true")])
 
-(define_insn "*float<SSEMODEI24:mode><MODEF:mode>2_sse_interunit"
+(define_insn "*float<SWI48x:mode><MODEF:mode>2_sse_interunit"
   [(set (match_operand:MODEF 0 "register_operand" "=x,x")
        (float:MODEF
-         (match_operand:SSEMODEI24 1 "nonimmediate_operand" "r,m")))]
-  "(<SSEMODEI24:MODE>mode != DImode || TARGET_64BIT)
+         (match_operand:SWI48x 1 "nonimmediate_operand" "r,m")))]
+  "(<SWI48x:MODE>mode != DImode || TARGET_64BIT)
    && SSE_FLOAT_MODE_P (<MODEF:MODE>mode) && TARGET_SSE_MATH
    && (TARGET_INTER_UNIT_CONVERSIONS || optimize_function_for_size_p (cfun))"
-  "%vcvtsi2<MODEF:ssemodesuffix><SSEMODEI24:rex64suffix>\t{%1, %d0|%d0, %1}"
+  "%vcvtsi2<MODEF:ssemodesuffix><SWI48x:rex64suffix>\t{%1, %d0|%d0, %1}"
   [(set_attr "type" "sseicvt")
    (set_attr "prefix" "maybe_vex")
    (set_attr "mode" "<MODEF:MODE>")
    (set (attr "prefix_rex")
      (if_then_else
        (and (eq_attr "prefix" "maybe_vex")
-           (ne (symbol_ref "<SSEMODEI24:MODE>mode == DImode") (const_int 0)))
+           (ne (symbol_ref "<SWI48x:MODE>mode == DImode") (const_int 0)))
        (const_string "1")
        (const_string "*")))
    (set_attr "athlon_decode" "double,direct")
@@ -5132,9 +5109,9 @@
 
 (define_split
   [(set (match_operand:MODEF 0 "register_operand" "")
-       (float:MODEF (match_operand:SSEMODEI24 1 "nonimmediate_operand" "")))
-   (clobber (match_operand:SSEMODEI24 2 "memory_operand" ""))]
-  "(<SSEMODEI24:MODE>mode != DImode || TARGET_64BIT)
+       (float:MODEF (match_operand:SWI48x 1 "nonimmediate_operand" "")))
+   (clobber (match_operand:SWI48x 2 "memory_operand" ""))]
+  "(<SWI48x:MODE>mode != DImode || TARGET_64BIT)
    && SSE_FLOAT_MODE_P (<MODEF:MODE>mode) && TARGET_SSE_MATH
    && (TARGET_INTER_UNIT_CONVERSIONS || optimize_function_for_size_p (cfun))
    && reload_completed
@@ -5143,21 +5120,21 @@
           && SSE_REG_P (operands[0])))"
   [(set (match_dup 0) (float:MODEF (match_dup 1)))])
 
-(define_insn "*float<SSEMODEI24:mode><MODEF:mode>2_sse_nointerunit"
+(define_insn "*float<SWI48x:mode><MODEF:mode>2_sse_nointerunit"
   [(set (match_operand:MODEF 0 "register_operand" "=x")
        (float:MODEF
-         (match_operand:SSEMODEI24 1 "memory_operand" "m")))]
-  "(<SSEMODEI24:MODE>mode != DImode || TARGET_64BIT)
+         (match_operand:SWI48x 1 "memory_operand" "m")))]
+  "(<SWI48x:MODE>mode != DImode || TARGET_64BIT)
    && SSE_FLOAT_MODE_P (<MODEF:MODE>mode) && TARGET_SSE_MATH
    && !(TARGET_INTER_UNIT_CONVERSIONS || optimize_function_for_size_p (cfun))"
-  "%vcvtsi2<MODEF:ssemodesuffix><SSEMODEI24:rex64suffix>\t{%1, %d0|%d0, %1}"
+  "%vcvtsi2<MODEF:ssemodesuffix><SWI48x:rex64suffix>\t{%1, %d0|%d0, %1}"
   [(set_attr "type" "sseicvt")
    (set_attr "prefix" "maybe_vex")
    (set_attr "mode" "<MODEF:MODE>")
    (set (attr "prefix_rex")
      (if_then_else
        (and (eq_attr "prefix" "maybe_vex")
-           (ne (symbol_ref "<SSEMODEI24:MODE>mode == DImode") (const_int 0)))
+           (ne (symbol_ref "<SWI48x:MODE>mode == DImode") (const_int 0)))
        (const_string "1")
        (const_string "*")))
    (set_attr "athlon_decode" "direct")
@@ -5167,9 +5144,9 @@
 
 (define_split
   [(set (match_operand:MODEF 0 "register_operand" "")
-       (float:MODEF (match_operand:SSEMODEI24 1 "register_operand" "")))
-   (clobber (match_operand:SSEMODEI24 2 "memory_operand" ""))]
-  "(<SSEMODEI24:MODE>mode != DImode || TARGET_64BIT)
+       (float:MODEF (match_operand:SWI48x 1 "register_operand" "")))
+   (clobber (match_operand:SWI48x 2 "memory_operand" ""))]
+  "(<SWI48x:MODE>mode != DImode || TARGET_64BIT)
    && SSE_FLOAT_MODE_P (<MODEF:MODE>mode) && TARGET_SSE_MATH
    && !(TARGET_INTER_UNIT_CONVERSIONS || optimize_function_for_size_p (cfun))
    && reload_completed
@@ -5181,9 +5158,9 @@
 
 (define_split
   [(set (match_operand:MODEF 0 "register_operand" "")
-       (float:MODEF (match_operand:SSEMODEI24 1 "memory_operand" "")))
-   (clobber (match_operand:SSEMODEI24 2 "memory_operand" ""))]
-  "(<SSEMODEI24:MODE>mode != DImode || TARGET_64BIT)
+       (float:MODEF (match_operand:SWI48x 1 "memory_operand" "")))
+   (clobber (match_operand:SWI48x 2 "memory_operand" ""))]
+  "(<SWI48x:MODE>mode != DImode || TARGET_64BIT)
    && SSE_FLOAT_MODE_P (<MODEF:MODE>mode) && TARGET_SSE_MATH
    && reload_completed
    && (SSE_REG_P (operands[0])
@@ -5191,13 +5168,13 @@
           && SSE_REG_P (operands[0])))"
   [(set (match_dup 0) (float:MODEF (match_dup 1)))])
 
-(define_insn "*float<SSEMODEI24:mode><X87MODEF:mode>2_i387_with_temp"
+(define_insn "*float<SWI48x:mode><X87MODEF:mode>2_i387_with_temp"
   [(set (match_operand:X87MODEF 0 "register_operand" "=f,f")
        (float:X87MODEF
-         (match_operand:SSEMODEI24 1 "nonimmediate_operand" "m,?r")))
-  (clobber (match_operand:SSEMODEI24 2 "memory_operand" "=X,m"))]
+         (match_operand:SWI48x 1 "nonimmediate_operand" "m,?r")))
+  (clobber (match_operand:SWI48x 2 "memory_operand" "=X,m"))]
   "TARGET_80387
-   && X87_ENABLE_FLOAT (<X87MODEF:MODE>mode, <SSEMODEI24:MODE>mode)"
+   && X87_ENABLE_FLOAT (<X87MODEF:MODE>mode, <SWI48x:MODE>mode)"
   "@
    fild%Z1\t%1
    #"
@@ -5206,12 +5183,12 @@
    (set_attr "unit" "*,i387")
    (set_attr "fp_int_src" "true")])
 
-(define_insn "*float<SSEMODEI24:mode><X87MODEF:mode>2_i387"
+(define_insn "*float<SWI48x:mode><X87MODEF:mode>2_i387"
   [(set (match_operand:X87MODEF 0 "register_operand" "=f")
        (float:X87MODEF
-         (match_operand:SSEMODEI24 1 "memory_operand" "m")))]
+         (match_operand:SWI48x 1 "memory_operand" "m")))]
   "TARGET_80387
-   && X87_ENABLE_FLOAT (<X87MODEF:MODE>mode, <SSEMODEI24:MODE>mode)"
+   && X87_ENABLE_FLOAT (<X87MODEF:MODE>mode, <SWI48x:MODE>mode)"
   "fild%Z1\t%1"
   [(set_attr "type" "fmov")
    (set_attr "mode" "<X87MODEF:MODE>")
@@ -5219,20 +5196,20 @@
 
 (define_split
   [(set (match_operand:X87MODEF 0 "fp_register_operand" "")
-       (float:X87MODEF (match_operand:SSEMODEI24 1 "register_operand" "")))
-   (clobber (match_operand:SSEMODEI24 2 "memory_operand" ""))]
+       (float:X87MODEF (match_operand:SWI48x 1 "register_operand" "")))
+   (clobber (match_operand:SWI48x 2 "memory_operand" ""))]
   "TARGET_80387
-   && X87_ENABLE_FLOAT (<X87MODEF:MODE>mode, <SSEMODEI24:MODE>mode)
+   && X87_ENABLE_FLOAT (<X87MODEF:MODE>mode, <SWI48x:MODE>mode)
    && reload_completed"
   [(set (match_dup 2) (match_dup 1))
    (set (match_dup 0) (float:X87MODEF (match_dup 2)))])
 
 (define_split
   [(set (match_operand:X87MODEF 0 "fp_register_operand" "")
-       (float:X87MODEF (match_operand:SSEMODEI24 1 "memory_operand" "")))
-   (clobber (match_operand:SSEMODEI24 2 "memory_operand" ""))]
+       (float:X87MODEF (match_operand:SWI48x 1 "memory_operand" "")))
+   (clobber (match_operand:SWI48x 2 "memory_operand" ""))]
   "TARGET_80387
-   && X87_ENABLE_FLOAT (<X87MODEF:MODE>mode, <SSEMODEI24:MODE>mode)
+   && X87_ENABLE_FLOAT (<X87MODEF:MODE>mode, <SWI48x:MODE>mode)
    && reload_completed"
   [(set (match_dup 0) (float:X87MODEF (match_dup 1)))])
 
@@ -5448,13 +5425,22 @@
    (set_attr "mode" "QI")])
 
 (define_insn "*lea_1"
-  [(set (match_operand:P 0 "register_operand" "=r")
-       (match_operand:P 1 "no_seg_address_operand" "p"))]
+  [(set (match_operand:SWI48 0 "register_operand" "=r")
+       (match_operand:SWI48 1 "no_seg_address_operand" "p"))]
   ""
   "lea{<imodesuffix>}\t{%a1, %0|%0, %a1}"
   [(set_attr "type" "lea")
    (set_attr "mode" "<MODE>")])
 
+(define_insn "*lea_1_zext"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+       (zero_extend:DI
+         (match_operand:SI 1 "no_seg_address_operand" "p")))]
+  "TARGET_64BIT"
+  "lea{l}\t{%a1, %k0|%k0, %a1}"
+  [(set_attr "type" "lea")
+   (set_attr "mode" "SI")])
+
 (define_insn "*lea_2"
   [(set (match_operand:SI 0 "register_operand" "=r")
        (subreg:SI (match_operand:DI 1 "no_seg_address_operand" "p") 0))]
@@ -5476,7 +5462,7 @@
   [(set (match_operand:SWI48 0 "nonimmediate_operand" "=r,rm,r,r")
        (plus:SWI48
          (match_operand:SWI48 1 "nonimmediate_operand" "%0,0,r,r")
-         (match_operand:SWI48 2 "<general_operand>" "<g>,r<i>,0,l<i>")))
+         (match_operand:SWI48 2 "x86_64_general_operand" "rme,re,0,le")))
    (clobber (reg:CC FLAGS_REG))]
   "ix86_binary_operator_ok (PLUS, <MODE>mode, operands)"
 {
@@ -5531,11 +5517,11 @@
 ;; operands so proper swapping will be done in reload.  This allow
 ;; patterns constructed from addsi_1 to match.
 
-(define_insn "*addsi_1_zext"
+(define_insn "addsi_1_zext"
   [(set (match_operand:DI 0 "register_operand" "=r,r,r")
        (zero_extend:DI
          (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,r,r")
-                  (match_operand:SI 2 "general_operand" "g,0,li"))))
+                  (match_operand:SI 2 "x86_64_general_operand" "rme,0,le"))))
    (clobber (reg:CC FLAGS_REG))]
   "TARGET_64BIT && ix86_binary_operator_ok (PLUS, SImode, operands)"
 {
@@ -5817,66 +5803,42 @@
         (const_string "none")))
    (set_attr "mode" "QI")])
 
-;; Convert lea to the lea pattern to avoid flags dependency.
+;; Convert add to the lea pattern to avoid flags dependency.
 (define_split
-  [(set (match_operand 0 "register_operand" "")
-       (plus (match_operand 1 "register_operand" "")
-              (match_operand 2 "nonmemory_operand" "")))
+  [(set (match_operand:SWI 0 "register_operand" "")
+       (plus:SWI (match_operand:SWI 1 "register_operand" "")
+                 (match_operand:SWI 2 "<nonmemory_operand>" "")))
    (clobber (reg:CC FLAGS_REG))]
   "reload_completed && ix86_lea_for_add_ok (insn, operands)" 
   [(const_int 0)]
 {
+  enum machine_mode mode = <MODE>mode;
   rtx pat;
-  enum machine_mode mode = GET_MODE (operands[0]);
-
-  /* In -fPIC mode the constructs like (const (unspec [symbol_ref]))
-     may confuse gen_lowpart.  */
-  if (mode != Pmode)
-    {
-      operands[1] = gen_lowpart (Pmode, operands[1]);
-      operands[2] = gen_lowpart (Pmode, operands[2]);
-    }
-
-  pat = gen_rtx_PLUS (Pmode, operands[1], operands[2]);
 
   if (GET_MODE_SIZE (mode) < GET_MODE_SIZE (SImode))
-    operands[0] = gen_lowpart (SImode, operands[0]);
+    { 
+      mode = SImode; 
+      operands[0] = gen_lowpart (mode, operands[0]);
+      operands[1] = gen_lowpart (mode, operands[1]);
+      operands[2] = gen_lowpart (mode, operands[2]);
+    }
 
-  if (TARGET_64BIT && mode != Pmode)
-    pat = gen_rtx_SUBREG (SImode, pat, 0);
+  pat = gen_rtx_PLUS (mode, operands[1], operands[2]);
 
   emit_insn (gen_rtx_SET (VOIDmode, operands[0], pat));
   DONE;
 })
 
-;; Convert lea to the lea pattern to avoid flags dependency.
-;; ??? This pattern handles immediate operands that do not satisfy immediate
-;; operand predicate (TARGET_LEGITIMATE_CONSTANT_P) in the previous pattern.
-(define_split
-  [(set (match_operand:DI 0 "register_operand" "")
-       (plus:DI (match_operand:DI 1 "register_operand" "")
-                (match_operand:DI 2 "x86_64_immediate_operand" "")))
-   (clobber (reg:CC FLAGS_REG))]
-  "TARGET_64BIT && reload_completed 
-   && true_regnum (operands[0]) != true_regnum (operands[1])"
-  [(set (match_dup 0)
-       (plus:DI (match_dup 1) (match_dup 2)))])
-
-;; Convert lea to the lea pattern to avoid flags dependency.
+;; Convert add to the lea pattern to avoid flags dependency.
 (define_split
   [(set (match_operand:DI 0 "register_operand" "")
        (zero_extend:DI
          (plus:SI (match_operand:SI 1 "register_operand" "")
-                  (match_operand:SI 2 "nonmemory_operand" ""))))
+                  (match_operand:SI 2 "x86_64_nonmemory_operand" ""))))
    (clobber (reg:CC FLAGS_REG))]
-  "TARGET_64BIT && reload_completed
-   && ix86_lea_for_add_ok (insn, operands)"
+  "TARGET_64BIT && reload_completed && ix86_lea_for_add_ok (insn, operands)"
   [(set (match_dup 0)
-       (zero_extend:DI (subreg:SI (plus:DI (match_dup 1) (match_dup 2)) 0)))]
-{
-  operands[1] = gen_lowpart (DImode, operands[1]);
-  operands[2] = gen_lowpart (DImode, operands[2]);
-})
+       (zero_extend:DI (plus:SI (match_dup 1) (match_dup 2))))])
 
 (define_insn "*add<mode>_2"
   [(set (reg FLAGS_REG)
@@ -5924,7 +5886,7 @@
   [(set (reg FLAGS_REG)
        (compare
          (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
-                  (match_operand:SI 2 "general_operand" "g"))
+                  (match_operand:SI 2 "x86_64_general_operand" "rme"))
          (const_int 0)))
    (set (match_operand:DI 0 "register_operand" "=r")
        (zero_extend:DI (plus:SI (match_dup 1) (match_dup 2))))]
@@ -6002,7 +5964,7 @@
 (define_insn "*addsi_3_zext"
   [(set (reg FLAGS_REG)
        (compare
-         (neg:SI (match_operand:SI 2 "general_operand" "g"))
+         (neg:SI (match_operand:SI 2 "x86_64_general_operand" "rme"))
          (match_operand:SI 1 "nonimmediate_operand" "%0")))
    (set (match_operand:DI 0 "register_operand" "=r")
        (zero_extend:DI (plus:SI (match_dup 1) (match_dup 2))))]
@@ -6256,7 +6218,7 @@
   [(set_attr "type" "alu")
    (set_attr "mode" "QI")])
 
-;; The lea patterns for non-Pmodes needs to be matched by
+;; The lea patterns for modes less than 32 bits need to be matched by
 ;; several insns converted to real lea by splitters.
 
 (define_insn_and_split "*lea_general_1"
@@ -6264,8 +6226,7 @@
        (plus (plus (match_operand 1 "index_register_operand" "l")
                    (match_operand 2 "register_operand" "r"))
              (match_operand 3 "immediate_operand" "i")))]
-  "(GET_MODE (operands[0]) == QImode || GET_MODE (operands[0]) == HImode
-    || (TARGET_64BIT && GET_MODE (operands[0]) == SImode))
+  "(GET_MODE (operands[0]) == QImode || GET_MODE (operands[0]) == HImode)
    && (!TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun))
    && GET_MODE (operands[0]) == GET_MODE (operands[1])
    && GET_MODE (operands[0]) == GET_MODE (operands[2])
@@ -6275,50 +6236,29 @@
   "&& reload_completed"
   [(const_int 0)]
 {
+  enum machine_mode mode = SImode;
   rtx pat;
-  operands[0] = gen_lowpart (SImode, operands[0]);
-  operands[1] = gen_lowpart (Pmode, operands[1]);
-  operands[2] = gen_lowpart (Pmode, operands[2]);
-  operands[3] = gen_lowpart (Pmode, operands[3]);
-  pat = gen_rtx_PLUS (Pmode, gen_rtx_PLUS (Pmode, operands[1], operands[2]),
+
+  operands[0] = gen_lowpart (mode, operands[0]);
+  operands[1] = gen_lowpart (mode, operands[1]);
+  operands[2] = gen_lowpart (mode, operands[2]);
+  operands[3] = gen_lowpart (mode, operands[3]);
+
+  pat = gen_rtx_PLUS (mode, gen_rtx_PLUS (mode, operands[1], operands[2]),
                      operands[3]);
-  if (Pmode != SImode)
-    pat = gen_rtx_SUBREG (SImode, pat, 0);
+
   emit_insn (gen_rtx_SET (VOIDmode, operands[0], pat));
   DONE;
 }
   [(set_attr "type" "lea")
    (set_attr "mode" "SI")])
 
-(define_insn_and_split "*lea_general_1_zext"
-  [(set (match_operand:DI 0 "register_operand" "=r")
-       (zero_extend:DI
-         (plus:SI (plus:SI
-                    (match_operand:SI 1 "index_register_operand" "l")
-                    (match_operand:SI 2 "register_operand" "r"))
-                  (match_operand:SI 3 "immediate_operand" "i"))))]
-  "TARGET_64BIT"
-  "#"
-  "&& reload_completed"
-  [(set (match_dup 0)
-       (zero_extend:DI (subreg:SI (plus:DI (plus:DI (match_dup 1)
-                                                    (match_dup 2))
-                                           (match_dup 3)) 0)))]
-{
-  operands[1] = gen_lowpart (Pmode, operands[1]);
-  operands[2] = gen_lowpart (Pmode, operands[2]);
-  operands[3] = gen_lowpart (Pmode, operands[3]);
-}
-  [(set_attr "type" "lea")
-   (set_attr "mode" "SI")])
-
 (define_insn_and_split "*lea_general_2"
   [(set (match_operand 0 "register_operand" "=r")
        (plus (mult (match_operand 1 "index_register_operand" "l")
-                   (match_operand 2 "const248_operand" "i"))
+                   (match_operand 2 "const248_operand" "n"))
              (match_operand 3 "nonmemory_operand" "ri")))]
-  "(GET_MODE (operands[0]) == QImode || GET_MODE (operands[0]) == HImode
-    || (TARGET_64BIT && GET_MODE (operands[0]) == SImode))
+  "(GET_MODE (operands[0]) == QImode || GET_MODE (operands[0]) == HImode)
    && (!TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun))
    && GET_MODE (operands[0]) == GET_MODE (operands[1])
    && (GET_MODE (operands[0]) == GET_MODE (operands[3])
@@ -6327,49 +6267,29 @@
   "&& reload_completed"
   [(const_int 0)]
 {
+  enum machine_mode mode = SImode;
   rtx pat;
-  operands[0] = gen_lowpart (SImode, operands[0]);
-  operands[1] = gen_lowpart (Pmode, operands[1]);
-  operands[3] = gen_lowpart (Pmode, operands[3]);
-  pat = gen_rtx_PLUS (Pmode, gen_rtx_MULT (Pmode, operands[1], operands[2]),
-                     operands[3]);
-  if (Pmode != SImode)
-    pat = gen_rtx_SUBREG (SImode, pat, 0);
+
+  operands[0] = gen_lowpart (mode, operands[0]);
+  operands[1] = gen_lowpart (mode, operands[1]);
+  operands[3] = gen_lowpart (mode, operands[3]);
+
+  pat = gen_rtx_PLUS (mode, gen_rtx_MULT (mode, operands[1], operands[2]),
+                     operands[3]);
+
   emit_insn (gen_rtx_SET (VOIDmode, operands[0], pat));
   DONE;
 }
   [(set_attr "type" "lea")
    (set_attr "mode" "SI")])
 
-(define_insn_and_split "*lea_general_2_zext"
-  [(set (match_operand:DI 0 "register_operand" "=r")
-       (zero_extend:DI
-         (plus:SI (mult:SI
-                    (match_operand:SI 1 "index_register_operand" "l")
-                    (match_operand:SI 2 "const248_operand" "n"))
-                  (match_operand:SI 3 "nonmemory_operand" "ri"))))]
-  "TARGET_64BIT"
-  "#"
-  "&& reload_completed"
-  [(set (match_dup 0)
-       (zero_extend:DI (subreg:SI (plus:DI (mult:DI (match_dup 1)
-                                                    (match_dup 2))
-                                           (match_dup 3)) 0)))]
-{
-  operands[1] = gen_lowpart (Pmode, operands[1]);
-  operands[3] = gen_lowpart (Pmode, operands[3]);
-}
-  [(set_attr "type" "lea")
-   (set_attr "mode" "SI")])
-
 (define_insn_and_split "*lea_general_3"
   [(set (match_operand 0 "register_operand" "=r")
        (plus (plus (mult (match_operand 1 "index_register_operand" "l")
-                         (match_operand 2 "const248_operand" "i"))
+                         (match_operand 2 "const248_operand" "n"))
                    (match_operand 3 "register_operand" "r"))
              (match_operand 4 "immediate_operand" "i")))]
-  "(GET_MODE (operands[0]) == QImode || GET_MODE (operands[0]) == HImode
-    || (TARGET_64BIT && GET_MODE (operands[0]) == SImode))
+  "(GET_MODE (operands[0]) == QImode || GET_MODE (operands[0]) == HImode)
    && (!TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun))
    && GET_MODE (operands[0]) == GET_MODE (operands[1])
    && GET_MODE (operands[0]) == GET_MODE (operands[3])"
@@ -6377,48 +6297,68 @@
   "&& reload_completed"
   [(const_int 0)]
 {
+  enum machine_mode mode = SImode;
   rtx pat;
-  operands[0] = gen_lowpart (SImode, operands[0]);
-  operands[1] = gen_lowpart (Pmode, operands[1]);
-  operands[3] = gen_lowpart (Pmode, operands[3]);
-  operands[4] = gen_lowpart (Pmode, operands[4]);
-  pat = gen_rtx_PLUS (Pmode,
-                     gen_rtx_PLUS (Pmode, gen_rtx_MULT (Pmode, operands[1],
-                                                        operands[2]),
+
+  operands[0] = gen_lowpart (mode, operands[0]);
+  operands[1] = gen_lowpart (mode, operands[1]);
+  operands[3] = gen_lowpart (mode, operands[3]);
+  operands[4] = gen_lowpart (mode, operands[4]);
+
+  pat = gen_rtx_PLUS (mode,
+                     gen_rtx_PLUS (mode,
+                                   gen_rtx_MULT (mode, operands[1],
+                                                       operands[2]),
                                    operands[3]),
                      operands[4]);
-  if (Pmode != SImode)
-    pat = gen_rtx_SUBREG (SImode, pat, 0);
+
   emit_insn (gen_rtx_SET (VOIDmode, operands[0], pat));
   DONE;
 }
   [(set_attr "type" "lea")
    (set_attr "mode" "SI")])
 
-(define_insn_and_split "*lea_general_3_zext"
-  [(set (match_operand:DI 0 "register_operand" "=r")
-       (zero_extend:DI
-         (plus:SI (plus:SI
-                    (mult:SI
-                      (match_operand:SI 1 "index_register_operand" "l")
-                      (match_operand:SI 2 "const248_operand" "n"))
-                    (match_operand:SI 3 "register_operand" "r"))
-                  (match_operand:SI 4 "immediate_operand" "i"))))]
-  "TARGET_64BIT"
+(define_insn_and_split "*lea_general_4"
+  [(set (match_operand 0 "register_operand" "=r")
+       (any_or (ashift
+                 (match_operand 1 "index_register_operand" "l")
+                 (match_operand 2 "const_int_operand" "n"))
+               (match_operand 3 "const_int_operand" "n")))]
+  "(((GET_MODE (operands[0]) == QImode || GET_MODE (operands[0]) == HImode)
+      && (!TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun)))
+    || GET_MODE (operands[0]) == SImode
+    || (TARGET_64BIT && GET_MODE (operands[0]) == DImode))
+   && GET_MODE (operands[0]) == GET_MODE (operands[1])
+   && ((unsigned HOST_WIDE_INT) INTVAL (operands[2])) - 1 < 3
+   && ((unsigned HOST_WIDE_INT) INTVAL (operands[3])
+       < ((unsigned HOST_WIDE_INT) 1 << INTVAL (operands[2])))"
   "#"
   "&& reload_completed"
-  [(set (match_dup 0)
-       (zero_extend:DI (subreg:SI (plus:DI (plus:DI (mult:DI (match_dup 1)
-                                                             (match_dup 2))
-                                                    (match_dup 3))
-                                           (match_dup 4)) 0)))]
-{
-  operands[1] = gen_lowpart (Pmode, operands[1]);
-  operands[3] = gen_lowpart (Pmode, operands[3]);
-  operands[4] = gen_lowpart (Pmode, operands[4]);
+  [(const_int 0)]
+{
+  enum machine_mode mode = GET_MODE (operands[0]);
+  rtx pat;
+
+  if (GET_MODE_SIZE (mode) < GET_MODE_SIZE (SImode))
+    { 
+      mode = SImode; 
+      operands[0] = gen_lowpart (mode, operands[0]);
+      operands[1] = gen_lowpart (mode, operands[1]);
+    }
+
+  operands[2] = GEN_INT (1 << INTVAL (operands[2]));
+
+  pat = plus_constant (gen_rtx_MULT (mode, operands[1], operands[2]),
+                      INTVAL (operands[3]));
+
+  emit_insn (gen_rtx_SET (VOIDmode, operands[0], pat));
+  DONE;
 }
   [(set_attr "type" "lea")
-   (set_attr "mode" "SI")])
+   (set (attr "mode")
+      (if_then_else (match_operand:DI 0 "" "")
+       (const_string "DI")
+       (const_string "SI")))])
 \f
 ;; Subtract instructions
 
@@ -6466,7 +6406,7 @@
   [(set (match_operand:DI 0 "register_operand" "=r")
        (zero_extend:DI
          (minus:SI (match_operand:SI 1 "register_operand" "0")
-                   (match_operand:SI 2 "general_operand" "g"))))
+                   (match_operand:SI 2 "x86_64_general_operand" "rme"))))
    (clobber (reg:CC FLAGS_REG))]
   "TARGET_64BIT && ix86_binary_operator_ok (MINUS, SImode, operands)"
   "sub{l}\t{%2, %k0|%k0, %2}"
@@ -6503,7 +6443,7 @@
   [(set (reg FLAGS_REG)
        (compare
          (minus:SI (match_operand:SI 1 "register_operand" "0")
-                   (match_operand:SI 2 "general_operand" "g"))
+                   (match_operand:SI 2 "x86_64_general_operand" "rme"))
          (const_int 0)))
    (set (match_operand:DI 0 "register_operand" "=r")
        (zero_extend:DI
@@ -6530,7 +6470,7 @@
 (define_insn "*subsi_3_zext"
   [(set (reg FLAGS_REG)
        (compare (match_operand:SI 1 "register_operand" "0")
-                (match_operand:SI 2 "general_operand" "g")))
+                (match_operand:SI 2 "x86_64_general_operand" "rme")))
    (set (match_operand:DI 0 "register_operand" "=r")
        (zero_extend:DI
          (minus:SI (match_dup 1)
@@ -6577,7 +6517,7 @@
          (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
                   (plus:SI (match_operator 3 "ix86_carry_flag_operator"
                             [(reg FLAGS_REG) (const_int 0)])
-                           (match_operand:SI 2 "general_operand" "g")))))
+                           (match_operand:SI 2 "x86_64_general_operand" "rme")))))
    (clobber (reg:CC FLAGS_REG))]
   "TARGET_64BIT && ix86_binary_operator_ok (PLUS, SImode, operands)"
   "adc{l}\t{%2, %k0|%k0, %2}"
@@ -6592,7 +6532,7 @@
          (minus:SI (match_operand:SI 1 "register_operand" "0")
                    (plus:SI (match_operator 3 "ix86_carry_flag_operator"
                              [(reg FLAGS_REG) (const_int 0)])
-                            (match_operand:SI 2 "general_operand" "g")))))
+                            (match_operand:SI 2 "x86_64_general_operand" "rme")))))
    (clobber (reg:CC FLAGS_REG))]
   "TARGET_64BIT && ix86_binary_operator_ok (MINUS, SImode, operands)"
   "sbb{l}\t{%2, %k0|%k0, %2}"
@@ -6646,7 +6586,7 @@
        (compare:CCC
          (plusminus:SI
            (match_operand:SI 1 "nonimmediate_operand" "<comm>0")
-           (match_operand:SI 2 "general_operand" "g"))
+           (match_operand:SI 2 "x86_64_general_operand" "rme"))
          (match_dup 1)))
    (set (match_operand:DI 0 "register_operand" "=r")
        (zero_extend:DI (plusminus:SI (match_dup 1) (match_dup 2))))]
@@ -6733,7 +6673,7 @@
   [(set (match_operand:DI 0 "register_operand" "=r,r,r")
        (zero_extend:DI
          (mult:SI (match_operand:SI 1 "nonimmediate_operand" "%rm,rm,0")
-                  (match_operand:SI 2 "general_operand" "K,i,mr"))))
+                  (match_operand:SI 2 "x86_64_general_operand" "K,e,mr"))))
    (clobber (reg:CC FLAGS_REG))]
   "TARGET_64BIT
    && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
@@ -7359,7 +7299,7 @@
   [(set (reg:CCNO FLAGS_REG)
        (compare:CCNO
          (and:SI (match_operand:SI 0 "nonimmediate_operand" "")
-                 (match_operand:SI 1 "nonmemory_operand" ""))
+                 (match_operand:SI 1 "x86_64_nonmemory_operand" ""))
          (const_int 0)))])
 
 (define_expand "testqi_ccz_1"
@@ -7425,7 +7365,7 @@
        (compare
         (and:SWI124
          (match_operand:SWI124 0 "nonimmediate_operand" "%!*a,<r>,<r>m")
-         (match_operand:SWI124 1 "general_operand" "<i>,<i>,<r><i>"))
+         (match_operand:SWI124 1 "<general_operand>" "<i>,<i>,<r><i>"))
         (const_int 0)))]
   "ix86_match_ccmode (insn, CCNOmode)
    && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
@@ -7715,7 +7655,7 @@
 (define_insn "*andsi_1"
   [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r,r")
        (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,qm")
-               (match_operand:SI 2 "general_operand" "ri,rm,L")))
+               (match_operand:SI 2 "x86_64_general_operand" "re,rm,L")))
    (clobber (reg:CC FLAGS_REG))]
   "ix86_binary_operator_ok (AND, SImode, operands)"
 {
@@ -7762,7 +7702,7 @@
   [(set (match_operand:DI 0 "register_operand" "=r")
        (zero_extend:DI
          (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
-                 (match_operand:SI 2 "general_operand" "g"))))
+                 (match_operand:SI 2 "x86_64_general_operand" "rme"))))
    (clobber (reg:CC FLAGS_REG))]
   "TARGET_64BIT && ix86_binary_operator_ok (AND, SImode, operands)"
   "and{l}\t{%2, %k0|%k0, %2}"
@@ -7910,7 +7850,7 @@
   [(set (reg FLAGS_REG)
        (compare (and:SWI124
                  (match_operand:SWI124 1 "nonimmediate_operand" "%0,0")
-                 (match_operand:SWI124 2 "general_operand" "<g>,<r><i>"))
+                 (match_operand:SWI124 2 "<general_operand>" "<g>,<r><i>"))
                 (const_int 0)))
    (set (match_operand:SWI124 0 "nonimmediate_operand" "=<r>,<r>m")
        (and:SWI124 (match_dup 1) (match_dup 2)))]
@@ -7925,7 +7865,7 @@
   [(set (reg FLAGS_REG)
        (compare (and:SI
                  (match_operand:SI 1 "nonimmediate_operand" "%0")
-                 (match_operand:SI 2 "general_operand" "g"))
+                 (match_operand:SI 2 "x86_64_general_operand" "rme"))
                 (const_int 0)))
    (set (match_operand:DI 0 "register_operand" "=r")
        (zero_extend:DI (and:SI (match_dup 1) (match_dup 2))))]
@@ -8142,7 +8082,7 @@
   [(set (match_operand:DI 0 "register_operand" "=r")
        (zero_extend:DI
         (any_or:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
-                   (match_operand:SI 2 "general_operand" "g"))))
+                   (match_operand:SI 2 "x86_64_general_operand" "rme"))))
    (clobber (reg:CC FLAGS_REG))]
   "TARGET_64BIT && ix86_binary_operator_ok (<CODE>, SImode, operands)"
   "<logic>{l}\t{%2, %k0|%k0, %2}"
@@ -8190,7 +8130,7 @@
 (define_insn "*<code>si_2_zext"
   [(set (reg FLAGS_REG)
        (compare (any_or:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
-                           (match_operand:SI 2 "general_operand" "g"))
+                           (match_operand:SI 2 "x86_64_general_operand" "rme"))
                 (const_int 0)))
    (set (match_operand:DI 0 "register_operand" "=r")
        (zero_extend:DI (any_or:SI (match_dup 1) (match_dup 2))))]
@@ -9380,36 +9320,36 @@
        (const_string "*")))
    (set_attr "mode" "QI")])
 
-;; Convert lea to the lea pattern to avoid flags dependency.
+;; Convert ashift to the lea pattern to avoid flags dependency.
 (define_split
   [(set (match_operand 0 "register_operand" "")
        (ashift (match_operand 1 "index_register_operand" "")
                 (match_operand:QI 2 "const_int_operand" "")))
    (clobber (reg:CC FLAGS_REG))]
-  "reload_completed
+  "GET_MODE (operands[0]) == GET_MODE (operands[1])
+   && reload_completed
    && true_regnum (operands[0]) != true_regnum (operands[1])"
   [(const_int 0)]
 {
-  rtx pat;
   enum machine_mode mode = GET_MODE (operands[0]);
-
-  if (mode != Pmode)
-    operands[1] = gen_lowpart (Pmode, operands[1]);
-  operands[2] = gen_int_mode (1 << INTVAL (operands[2]), Pmode);
-
-  pat = gen_rtx_MULT (Pmode, operands[1], operands[2]);
+  rtx pat;
 
   if (GET_MODE_SIZE (mode) < GET_MODE_SIZE (SImode))
-    operands[0] = gen_lowpart (SImode, operands[0]);
+    { 
+      mode = SImode; 
+      operands[0] = gen_lowpart (mode, operands[0]);
+      operands[1] = gen_lowpart (mode, operands[1]);
+    }
+
+  operands[2] = gen_int_mode (1 << INTVAL (operands[2]), mode);
 
-  if (TARGET_64BIT && mode != Pmode)
-    pat = gen_rtx_SUBREG (SImode, pat, 0);
+  pat = gen_rtx_MULT (mode, operands[1], operands[2]);
 
   emit_insn (gen_rtx_SET (VOIDmode, operands[0], pat));
   DONE;
 })
 
-;; Convert lea to the lea pattern to avoid flags dependency.
+;; Convert ashift to the lea pattern to avoid flags dependency.
 (define_split
   [(set (match_operand:DI 0 "register_operand" "")
        (zero_extend:DI
@@ -10349,7 +10289,7 @@
          (zero_extract:SWI48
            (match_operand:SWI48 0 "register_operand" "r")
            (const_int 1)
-           (match_operand:SWI48 1 "nonmemory_operand" "rN"))
+           (match_operand:SWI48 1 "x86_64_nonmemory_operand" "rN"))
          (const_int 0)))]
   "TARGET_USE_BT || optimize_function_for_size_p (cfun)"
   "bt{<imodesuffix>}\t{%1, %0|%0, %1}"
@@ -10868,7 +10808,7 @@
        (if_then_else
          (match_operator 0 "ix86_swapped_fp_comparison_operator"
            [(match_operator 1 "float_operator"
-             [(match_operand:X87MODEI12 2 "nonimmediate_operand" "m,?r")])
+             [(match_operand:SWI24 2 "nonimmediate_operand" "m,?r")])
             (match_operand 3 "register_operand" "f,f")])
          (label_ref (match_operand 4 "" ""))
          (pc)))
@@ -10887,7 +10827,7 @@
        (if_then_else
          (match_operator 0 "ix86_swapped_fp_comparison_operator"
            [(match_operator 1 "float_operator"
-             [(match_operand:X87MODEI12 2 "memory_operand" "")])
+             [(match_operand:SWI24 2 "memory_operand" "")])
             (match_operand 3 "register_operand" "")])
          (match_operand 4 "" "")
          (match_operand 5 "" "")))
@@ -10911,7 +10851,7 @@
        (if_then_else
          (match_operator 0 "ix86_swapped_fp_comparison_operator"
            [(match_operator 1 "float_operator"
-             [(match_operand:X87MODEI12 2 "register_operand" "")])
+             [(match_operand:SWI24 2 "register_operand" "")])
             (match_operand 3 "register_operand" "")])
          (match_operand 4 "" "")
          (match_operand 5 "" "")))
@@ -10948,19 +10888,17 @@
    (set_attr "modrm" "0")])
 
 (define_expand "indirect_jump"
-  [(set (pc) (match_operand 0 "nonimmediate_operand" ""))]
-  ""
-  "")
+  [(set (pc) (match_operand 0 "indirect_branch_operand" ""))])
 
 (define_insn "*indirect_jump"
-  [(set (pc) (match_operand:P 0 "nonimmediate_operand" "rm"))]
+  [(set (pc) (match_operand:P 0 "indirect_branch_operand" "rw"))]
   ""
   "jmp\t%A0"
   [(set_attr "type" "ibr")
    (set_attr "length_immediate" "0")])
 
 (define_expand "tablejump"
-  [(parallel [(set (pc) (match_operand 0 "nonimmediate_operand" ""))
+  [(parallel [(set (pc) (match_operand 0 "indirect_branch_operand" ""))
              (use (label_ref (match_operand 1 "" "")))])]
   ""
 {
@@ -10995,10 +10933,12 @@
       operands[0] = expand_simple_binop (Pmode, code, op0, op1, NULL_RTX, 0,
                                         OPTAB_DIRECT);
     }
+  else if (TARGET_X32)
+    operands[0] = convert_memory_address (Pmode, operands[0]);
 })
 
 (define_insn "*tablejump_1"
-  [(set (pc) (match_operand:P 0 "nonimmediate_operand" "rm"))
+  [(set (pc) (match_operand:P 0 "indirect_branch_operand" "rw"))
    (use (label_ref (match_operand 1 "" "")))]
   ""
   "jmp\t%A0"
@@ -11086,7 +11026,7 @@
 })
 
 (define_insn_and_split "*call_vzeroupper"
-  [(call (mem:QI (match_operand:P 0 "call_insn_operand" "<c>zm"))
+  [(call (mem:QI (match_operand:P 0 "call_insn_operand" "<c>zw"))
         (match_operand 1 "" ""))
    (unspec [(match_operand 2 "const_int_operand" "")]
           UNSPEC_CALL_NEEDS_VZEROUPPER)]
@@ -11098,7 +11038,7 @@
   [(set_attr "type" "call")])
 
 (define_insn "*call"
-  [(call (mem:QI (match_operand:P 0 "call_insn_operand" "<c>zm"))
+  [(call (mem:QI (match_operand:P 0 "call_insn_operand" "<c>zw"))
         (match_operand 1 "" ""))]
   "!SIBLING_CALL_P (insn)"
   "* return ix86_output_call_insn (insn, operands[0]);"
@@ -11106,7 +11046,7 @@
 
 (define_insn_and_split "*call_rex64_ms_sysv_vzeroupper"
   [(parallel
-    [(call (mem:QI (match_operand:DI 0 "call_insn_operand" "rzm"))
+    [(call (mem:QI (match_operand:DI 0 "call_insn_operand" "rzw"))
           (match_operand 1 "" ""))
      (unspec [(const_int 0)] UNSPEC_MS_TO_SYSV_CALL)
      (clobber (reg:TI XMM6_REG))
@@ -11131,7 +11071,7 @@
   [(set_attr "type" "call")])
 
 (define_insn "*call_rex64_ms_sysv"
-  [(call (mem:QI (match_operand:DI 0 "call_insn_operand" "rzm"))
+  [(call (mem:QI (match_operand:DI 0 "call_insn_operand" "rzw"))
         (match_operand 1 "" ""))
    (unspec [(const_int 0)] UNSPEC_MS_TO_SYSV_CALL)
    (clobber (reg:TI XMM6_REG))
@@ -11262,7 +11202,7 @@
 
 (define_insn_and_split "*call_value_vzeroupper"
   [(set (match_operand 0 "" "")
-       (call (mem:QI (match_operand:P 1 "call_insn_operand" "<c>zm"))
+       (call (mem:QI (match_operand:P 1 "call_insn_operand" "<c>zw"))
              (match_operand 2 "" "")))
    (unspec [(match_operand 3 "const_int_operand" "")]
           UNSPEC_CALL_NEEDS_VZEROUPPER)]
@@ -11275,7 +11215,7 @@
 
 (define_insn "*call_value"
   [(set (match_operand 0 "" "")
-       (call (mem:QI (match_operand:P 1 "call_insn_operand" "<c>zm"))
+       (call (mem:QI (match_operand:P 1 "call_insn_operand" "<c>zw"))
              (match_operand 2 "" "")))]
   "!SIBLING_CALL_P (insn)"
   "* return ix86_output_call_insn (insn, operands[1]);"
@@ -11305,7 +11245,7 @@
 (define_insn_and_split "*call_value_rex64_ms_sysv_vzeroupper"
   [(parallel
     [(set (match_operand 0 "" "")
-         (call (mem:QI (match_operand:DI 1 "call_insn_operand" "rzm"))
+         (call (mem:QI (match_operand:DI 1 "call_insn_operand" "rzw"))
                (match_operand 2 "" "")))
      (unspec [(const_int 0)] UNSPEC_MS_TO_SYSV_CALL)
      (clobber (reg:TI XMM6_REG))
@@ -11331,7 +11271,7 @@
 
 (define_insn "*call_value_rex64_ms_sysv"
   [(set (match_operand 0 "" "")
-       (call (mem:QI (match_operand:DI 1 "call_insn_operand" "rzm"))
+       (call (mem:QI (match_operand:DI 1 "call_insn_operand" "rzw"))
              (match_operand 2 "" "")))
    (unspec [(const_int 0)] UNSPEC_MS_TO_SYSV_CALL)
    (clobber (reg:TI XMM6_REG))
@@ -11653,7 +11593,7 @@
        (unspec:DI
          [(label_ref (match_operand 1 "" ""))]
          UNSPEC_SET_GOT_OFFSET))]
-  "TARGET_64BIT"
+  "TARGET_LP64"
   "movabs{q}\t{$_GLOBAL_OFFSET_TABLE_-%l1, %0|%0, OFFSET FLAT:_GLOBAL_OFFSET_TABLE_-%l1}"
   [(set_attr "type" "imov")
    (set_attr "length_immediate" "0")
@@ -12698,7 +12638,7 @@
           (if_then_else (match_operand:MODEF 3 "mult_operator" "")
              (const_string "fmul")
              (const_string "fop"))))
-   (set_attr "isa" "base,noavx,avx")
+   (set_attr "isa" "*,noavx,avx")
    (set_attr "prefix" "orig,orig,vex")
    (set_attr "mode" "<MODE>")])
 
@@ -12758,7 +12698,7 @@
                  (const_string "fdiv")
               ]
               (const_string "fop")))
-   (set_attr "isa" "base,base,noavx,avx")
+   (set_attr "isa" "*,*,noavx,avx")
    (set_attr "prefix" "orig,orig,orig,vex")
    (set_attr "mode" "<MODE>")])
 
@@ -12817,11 +12757,11 @@
   [(set (match_operand:MODEF 0 "register_operand" "=f,f")
        (match_operator:MODEF 3 "binary_fp_operator"
          [(float:MODEF
-            (match_operand:X87MODEI12 1 "nonimmediate_operand" "m,?r"))
+            (match_operand:SWI24 1 "nonimmediate_operand" "m,?r"))
           (match_operand:MODEF 2 "register_operand" "0,0")]))]
-  "TARGET_80387 && X87_ENABLE_FLOAT (<MODEF:MODE>mode, <X87MODEI12:MODE>mode)
+  "TARGET_80387 && X87_ENABLE_FLOAT (<MODEF:MODE>mode, <SWI24:MODE>mode)
    && !(SSE_FLOAT_MODE_P (<MODEF:MODE>mode) && TARGET_SSE_MATH)
-   && (TARGET_USE_<X87MODEI12:MODE>MODE_FIOP || optimize_function_for_size_p (cfun))"
+   && (TARGET_USE_<SWI24:MODE>MODE_FIOP || optimize_function_for_size_p (cfun))"
   "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
   [(set (attr "type")
         (cond [(match_operand:MODEF 3 "mult_operator" "")
@@ -12831,17 +12771,17 @@
               ]
               (const_string "fop")))
    (set_attr "fp_int_src" "true")
-   (set_attr "mode" "<X87MODEI12:MODE>")])
+   (set_attr "mode" "<SWI24:MODE>")])
 
 (define_insn "*fop_<MODEF:mode>_3_i387"
   [(set (match_operand:MODEF 0 "register_operand" "=f,f")
        (match_operator:MODEF 3 "binary_fp_operator"
          [(match_operand:MODEF 1 "register_operand" "0,0")
           (float:MODEF
-            (match_operand:X87MODEI12 2 "nonimmediate_operand" "m,?r"))]))]
-  "TARGET_80387 && X87_ENABLE_FLOAT (<MODEF:MODE>mode, <X87MODEI12:MODE>mode)
+            (match_operand:SWI24 2 "nonimmediate_operand" "m,?r"))]))]
+  "TARGET_80387 && X87_ENABLE_FLOAT (<MODEF:MODE>mode, <SWI24:MODE>mode)
    && !(SSE_FLOAT_MODE_P (<MODEF:MODE>mode) && TARGET_SSE_MATH)
-   && (TARGET_USE_<X87MODEI12:MODE>MODE_FIOP || optimize_function_for_size_p (cfun))"
+   && (TARGET_USE_<SWI24:MODE>MODE_FIOP || optimize_function_for_size_p (cfun))"
   "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
   [(set (attr "type")
         (cond [(match_operand:MODEF 3 "mult_operator" "")
@@ -12944,7 +12884,7 @@
   [(set (match_operand:XF 0 "register_operand" "=f,f")
        (match_operator:XF 3 "binary_fp_operator"
          [(float:XF
-            (match_operand:X87MODEI12 1 "nonimmediate_operand" "m,?r"))
+            (match_operand:SWI24 1 "nonimmediate_operand" "m,?r"))
           (match_operand:XF 2 "register_operand" "0,0")]))]
   "TARGET_80387 && (TARGET_USE_<MODE>MODE_FIOP || optimize_function_for_size_p (cfun))"
   "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
@@ -12963,7 +12903,7 @@
        (match_operator:XF 3 "binary_fp_operator"
          [(match_operand:XF 1 "register_operand" "0,0")
           (float:XF
-            (match_operand:X87MODEI12 2 "nonimmediate_operand" "m,?r"))]))]
+            (match_operand:SWI24 2 "nonimmediate_operand" "m,?r"))]))]
   "TARGET_80387 && (TARGET_USE_<MODE>MODE_FIOP || optimize_function_for_size_p (cfun))"
   "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
   [(set (attr "type")
@@ -13031,7 +12971,7 @@
 (define_split
   [(set (match_operand 0 "register_operand" "")
        (match_operator 3 "binary_fp_operator"
-          [(float (match_operand:X87MODEI12 1 "register_operand" ""))
+          [(float (match_operand:SWI24 1 "register_operand" ""))
            (match_operand 2 "register_operand" "")]))]
   "reload_completed
    && X87_FLOAT_MODE_P (GET_MODE (operands[0]))
@@ -13053,7 +12993,7 @@
   [(set (match_operand 0 "register_operand" "")
        (match_operator 3 "binary_fp_operator"
           [(match_operand 1 "register_operand" "")
-           (float (match_operand:X87MODEI12 2 "register_operand" ""))]))]
+           (float (match_operand:SWI24 2 "register_operand" ""))]))]
   "reload_completed
    && X87_FLOAT_MODE_P (GET_MODE (operands[0]))
    && X87_ENABLE_FLOAT (GET_MODE (operands[0]), GET_MODE (operands[2]))"
@@ -14439,9 +14379,9 @@
              (clobber (match_dup 3))])])
 
 (define_insn_and_split "*fist<mode>2_1"
-  [(set (match_operand:X87MODEI12 0 "register_operand" "")
-       (unspec:X87MODEI12 [(match_operand:XF 1 "register_operand" "")]
-                          UNSPEC_FIST))]
+  [(set (match_operand:SWI24 0 "register_operand" "")
+       (unspec:SWI24 [(match_operand:XF 1 "register_operand" "")]
+                     UNSPEC_FIST))]
   "TARGET_USE_FANCY_MATH_387
    && can_create_pseudo_p ()"
   "#"
@@ -14457,59 +14397,59 @@
    (set_attr "mode" "<MODE>")])
 
 (define_insn "fist<mode>2"
-  [(set (match_operand:X87MODEI12 0 "memory_operand" "=m")
-       (unspec:X87MODEI12 [(match_operand:XF 1 "register_operand" "f")]
-                          UNSPEC_FIST))]
+  [(set (match_operand:SWI24 0 "memory_operand" "=m")
+       (unspec:SWI24 [(match_operand:XF 1 "register_operand" "f")]
+                     UNSPEC_FIST))]
   "TARGET_USE_FANCY_MATH_387"
   "* return output_fix_trunc (insn, operands, false);"
   [(set_attr "type" "fpspc")
    (set_attr "mode" "<MODE>")])
 
 (define_insn "fist<mode>2_with_temp"
-  [(set (match_operand:X87MODEI12 0 "register_operand" "=r")
-       (unspec:X87MODEI12 [(match_operand:XF 1 "register_operand" "f")]
-                          UNSPEC_FIST))
-   (clobber (match_operand:X87MODEI12 2 "memory_operand" "=m"))]
+  [(set (match_operand:SWI24 0 "register_operand" "=r")
+       (unspec:SWI24 [(match_operand:XF 1 "register_operand" "f")]
+                     UNSPEC_FIST))
+   (clobber (match_operand:SWI24 2 "memory_operand" "=m"))]
   "TARGET_USE_FANCY_MATH_387"
   "#"
   [(set_attr "type" "fpspc")
    (set_attr "mode" "<MODE>")])
 
 (define_split
-  [(set (match_operand:X87MODEI12 0 "register_operand" "")
-       (unspec:X87MODEI12 [(match_operand:XF 1 "register_operand" "")]
-                          UNSPEC_FIST))
-   (clobber (match_operand:X87MODEI12 2 "memory_operand" ""))]
+  [(set (match_operand:SWI24 0 "register_operand" "")
+       (unspec:SWI24 [(match_operand:XF 1 "register_operand" "")]
+                     UNSPEC_FIST))
+   (clobber (match_operand:SWI24 2 "memory_operand" ""))]
   "reload_completed"
-  [(set (match_dup 2) (unspec:X87MODEI12 [(match_dup 1)] UNSPEC_FIST))
+  [(set (match_dup 2) (unspec:SWI24 [(match_dup 1)] UNSPEC_FIST))
    (set (match_dup 0) (match_dup 2))])
 
 (define_split
-  [(set (match_operand:X87MODEI12 0 "memory_operand" "")
-       (unspec:X87MODEI12 [(match_operand:XF 1 "register_operand" "")]
-                          UNSPEC_FIST))
-   (clobber (match_operand:X87MODEI12 2 "memory_operand" ""))]
+  [(set (match_operand:SWI24 0 "memory_operand" "")
+       (unspec:SWI24 [(match_operand:XF 1 "register_operand" "")]
+                     UNSPEC_FIST))
+   (clobber (match_operand:SWI24 2 "memory_operand" ""))]
   "reload_completed"
-  [(set (match_dup 0) (unspec:X87MODEI12 [(match_dup 1)] UNSPEC_FIST))])
+  [(set (match_dup 0) (unspec:SWI24 [(match_dup 1)] UNSPEC_FIST))])
 
 (define_expand "lrintxf<mode>2"
-  [(set (match_operand:X87MODEI 0 "nonimmediate_operand" "")
-     (unspec:X87MODEI [(match_operand:XF 1 "register_operand" "")]
-                     UNSPEC_FIST))]
+  [(set (match_operand:SWI248x 0 "nonimmediate_operand" "")
+     (unspec:SWI248x [(match_operand:XF 1 "register_operand" "")]
+                    UNSPEC_FIST))]
   "TARGET_USE_FANCY_MATH_387")
 
-(define_expand "lrint<MODEF:mode><SSEMODEI24:mode>2"
-  [(set (match_operand:SSEMODEI24 0 "nonimmediate_operand" "")
-     (unspec:SSEMODEI24 [(match_operand:MODEF 1 "register_operand" "")]
+(define_expand "lrint<MODEF:mode><SWI48x:mode>2"
+  [(set (match_operand:SWI48x 0 "nonimmediate_operand" "")
+     (unspec:SWI48x [(match_operand:MODEF 1 "register_operand" "")]
                        UNSPEC_FIX_NOTRUNC))]
   "SSE_FLOAT_MODE_P (<MODEF:MODE>mode) && TARGET_SSE_MATH
-   && ((<SSEMODEI24:MODE>mode != DImode) || TARGET_64BIT)")
+   && ((<SWI48x:MODE>mode != DImode) || TARGET_64BIT)")
 
-(define_expand "lround<MODEF:mode><SSEMODEI24:mode>2"
-  [(match_operand:SSEMODEI24 0 "nonimmediate_operand" "")
+(define_expand "lround<MODEF:mode><SWI48x:mode>2"
+  [(match_operand:SWI48x 0 "nonimmediate_operand" "")
    (match_operand:MODEF 1 "register_operand" "")]
   "SSE_FLOAT_MODE_P (<MODEF:MODE>mode) && TARGET_SSE_MATH
-   && ((<SSEMODEI24:MODE>mode != DImode) || TARGET_64BIT)
+   && ((<SWI48x:MODE>mode != DImode) || TARGET_64BIT)
    && !flag_trapping_math && !flag_rounding_math"
 {
   if (optimize_insn_for_size_p ())
@@ -14611,9 +14551,9 @@
 })
 
 (define_insn_and_split "*fist<mode>2_floor_1"
-  [(set (match_operand:X87MODEI 0 "nonimmediate_operand" "")
-       (unspec:X87MODEI [(match_operand:XF 1 "register_operand" "")]
-        UNSPEC_FIST_FLOOR))
+  [(set (match_operand:SWI248x 0 "nonimmediate_operand" "")
+       (unspec:SWI248x [(match_operand:XF 1 "register_operand" "")]
+                       UNSPEC_FIST_FLOOR))
    (clobber (reg:CC FLAGS_REG))]
   "TARGET_USE_FANCY_MATH_387
    && flag_unsafe_math_optimizations
@@ -14645,7 +14585,7 @@
 (define_insn "fistdi2_floor"
   [(set (match_operand:DI 0 "memory_operand" "=m")
        (unspec:DI [(match_operand:XF 1 "register_operand" "f")]
-        UNSPEC_FIST_FLOOR))
+                  UNSPEC_FIST_FLOOR))
    (use (match_operand:HI 2 "memory_operand" "m"))
    (use (match_operand:HI 3 "memory_operand" "m"))
    (clobber (match_scratch:XF 4 "=&1f"))]
@@ -14659,7 +14599,7 @@
 (define_insn "fistdi2_floor_with_temp"
   [(set (match_operand:DI 0 "nonimmediate_operand" "=m,?r")
        (unspec:DI [(match_operand:XF 1 "register_operand" "f,f")]
-        UNSPEC_FIST_FLOOR))
+                  UNSPEC_FIST_FLOOR))
    (use (match_operand:HI 2 "memory_operand" "m,m"))
    (use (match_operand:HI 3 "memory_operand" "m,m"))
    (clobber (match_operand:DI 4 "memory_operand" "=X,m"))
@@ -14674,13 +14614,14 @@
 (define_split
   [(set (match_operand:DI 0 "register_operand" "")
        (unspec:DI [(match_operand:XF 1 "register_operand" "")]
-        UNSPEC_FIST_FLOOR))
+                  UNSPEC_FIST_FLOOR))
    (use (match_operand:HI 2 "memory_operand" ""))
    (use (match_operand:HI 3 "memory_operand" ""))
    (clobber (match_operand:DI 4 "memory_operand" ""))
    (clobber (match_scratch 5 ""))]
   "reload_completed"
-  [(parallel [(set (match_dup 4) (unspec:DI [(match_dup 1)] UNSPEC_FIST_FLOOR))
+  [(parallel [(set (match_dup 4)
+                  (unspec:DI [(match_dup 1)] UNSPEC_FIST_FLOOR))
              (use (match_dup 2))
              (use (match_dup 3))
              (clobber (match_dup 5))])
@@ -14689,21 +14630,22 @@
 (define_split
   [(set (match_operand:DI 0 "memory_operand" "")
        (unspec:DI [(match_operand:XF 1 "register_operand" "")]
-        UNSPEC_FIST_FLOOR))
+                  UNSPEC_FIST_FLOOR))
    (use (match_operand:HI 2 "memory_operand" ""))
    (use (match_operand:HI 3 "memory_operand" ""))
    (clobber (match_operand:DI 4 "memory_operand" ""))
    (clobber (match_scratch 5 ""))]
   "reload_completed"
-  [(parallel [(set (match_dup 0) (unspec:DI [(match_dup 1)] UNSPEC_FIST_FLOOR))
+  [(parallel [(set (match_dup 0)
+                  (unspec:DI [(match_dup 1)] UNSPEC_FIST_FLOOR))
              (use (match_dup 2))
              (use (match_dup 3))
              (clobber (match_dup 5))])])
 
 (define_insn "fist<mode>2_floor"
-  [(set (match_operand:X87MODEI12 0 "memory_operand" "=m")
-       (unspec:X87MODEI12 [(match_operand:XF 1 "register_operand" "f")]
-        UNSPEC_FIST_FLOOR))
+  [(set (match_operand:SWI24 0 "memory_operand" "=m")
+       (unspec:SWI24 [(match_operand:XF 1 "register_operand" "f")]
+                     UNSPEC_FIST_FLOOR))
    (use (match_operand:HI 2 "memory_operand" "m"))
    (use (match_operand:HI 3 "memory_operand" "m"))]
   "TARGET_USE_FANCY_MATH_387
@@ -14714,12 +14656,12 @@
    (set_attr "mode" "<MODE>")])
 
 (define_insn "fist<mode>2_floor_with_temp"
-  [(set (match_operand:X87MODEI12 0 "nonimmediate_operand" "=m,?r")
-       (unspec:X87MODEI12 [(match_operand:XF 1 "register_operand" "f,f")]
-        UNSPEC_FIST_FLOOR))
+  [(set (match_operand:SWI24 0 "nonimmediate_operand" "=m,?r")
+       (unspec:SWI24 [(match_operand:XF 1 "register_operand" "f,f")]
+                     UNSPEC_FIST_FLOOR))
    (use (match_operand:HI 2 "memory_operand" "m,m"))
    (use (match_operand:HI 3 "memory_operand" "m,m"))
-   (clobber (match_operand:X87MODEI12 4 "memory_operand" "=X,m"))]
+   (clobber (match_operand:SWI24 4 "memory_operand" "=X,m"))]
   "TARGET_USE_FANCY_MATH_387
    && flag_unsafe_math_optimizations"
   "#"
@@ -14728,36 +14670,36 @@
    (set_attr "mode" "<MODE>")])
 
 (define_split
-  [(set (match_operand:X87MODEI12 0 "register_operand" "")
-       (unspec:X87MODEI12 [(match_operand:XF 1 "register_operand" "")]
-        UNSPEC_FIST_FLOOR))
+  [(set (match_operand:SWI24 0 "register_operand" "")
+       (unspec:SWI24 [(match_operand:XF 1 "register_operand" "")]
+                     UNSPEC_FIST_FLOOR))
    (use (match_operand:HI 2 "memory_operand" ""))
    (use (match_operand:HI 3 "memory_operand" ""))
-   (clobber (match_operand:X87MODEI12 4 "memory_operand" ""))]
+   (clobber (match_operand:SWI24 4 "memory_operand" ""))]
   "reload_completed"
-  [(parallel [(set (match_dup 4) (unspec:X87MODEI12 [(match_dup 1)]
-                                 UNSPEC_FIST_FLOOR))
+  [(parallel [(set (match_dup 4)
+                  (unspec:SWI24 [(match_dup 1)] UNSPEC_FIST_FLOOR))
              (use (match_dup 2))
              (use (match_dup 3))])
    (set (match_dup 0) (match_dup 4))])
 
 (define_split
-  [(set (match_operand:X87MODEI12 0 "memory_operand" "")
-       (unspec:X87MODEI12 [(match_operand:XF 1 "register_operand" "")]
-        UNSPEC_FIST_FLOOR))
+  [(set (match_operand:SWI24 0 "memory_operand" "")
+       (unspec:SWI24 [(match_operand:XF 1 "register_operand" "")]
+                     UNSPEC_FIST_FLOOR))
    (use (match_operand:HI 2 "memory_operand" ""))
    (use (match_operand:HI 3 "memory_operand" ""))
-   (clobber (match_operand:X87MODEI12 4 "memory_operand" ""))]
+   (clobber (match_operand:SWI24 4 "memory_operand" ""))]
   "reload_completed"
-  [(parallel [(set (match_dup 0) (unspec:X87MODEI12 [(match_dup 1)]
-                                 UNSPEC_FIST_FLOOR))
+  [(parallel [(set (match_dup 0)
+                  (unspec:SWI24 [(match_dup 1)] UNSPEC_FIST_FLOOR))
              (use (match_dup 2))
              (use (match_dup 3))])])
 
 (define_expand "lfloorxf<mode>2"
-  [(parallel [(set (match_operand:X87MODEI 0 "nonimmediate_operand" "")
-                  (unspec:X87MODEI [(match_operand:XF 1 "register_operand" "")]
-                   UNSPEC_FIST_FLOOR))
+  [(parallel [(set (match_operand:SWI248x 0 "nonimmediate_operand" "")
+                  (unspec:SWI248x [(match_operand:XF 1 "register_operand" "")]
+                                  UNSPEC_FIST_FLOOR))
              (clobber (reg:CC FLAGS_REG))])]
   "TARGET_USE_FANCY_MATH_387
    && (!TARGET_SSE_MATH || TARGET_MIX_SSE_I387)
@@ -14868,9 +14810,9 @@
 })
 
 (define_insn_and_split "*fist<mode>2_ceil_1"
-  [(set (match_operand:X87MODEI 0 "nonimmediate_operand" "")
-       (unspec:X87MODEI [(match_operand:XF 1 "register_operand" "")]
-        UNSPEC_FIST_CEIL))
+  [(set (match_operand:SWI248x 0 "nonimmediate_operand" "")
+       (unspec:SWI248x [(match_operand:XF 1 "register_operand" "")]
+                       UNSPEC_FIST_CEIL))
    (clobber (reg:CC FLAGS_REG))]
   "TARGET_USE_FANCY_MATH_387
    && flag_unsafe_math_optimizations
@@ -14902,7 +14844,7 @@
 (define_insn "fistdi2_ceil"
   [(set (match_operand:DI 0 "memory_operand" "=m")
        (unspec:DI [(match_operand:XF 1 "register_operand" "f")]
-        UNSPEC_FIST_CEIL))
+                  UNSPEC_FIST_CEIL))
    (use (match_operand:HI 2 "memory_operand" "m"))
    (use (match_operand:HI 3 "memory_operand" "m"))
    (clobber (match_scratch:XF 4 "=&1f"))]
@@ -14916,7 +14858,7 @@
 (define_insn "fistdi2_ceil_with_temp"
   [(set (match_operand:DI 0 "nonimmediate_operand" "=m,?r")
        (unspec:DI [(match_operand:XF 1 "register_operand" "f,f")]
-        UNSPEC_FIST_CEIL))
+                  UNSPEC_FIST_CEIL))
    (use (match_operand:HI 2 "memory_operand" "m,m"))
    (use (match_operand:HI 3 "memory_operand" "m,m"))
    (clobber (match_operand:DI 4 "memory_operand" "=X,m"))
@@ -14931,13 +14873,14 @@
 (define_split
   [(set (match_operand:DI 0 "register_operand" "")
        (unspec:DI [(match_operand:XF 1 "register_operand" "")]
-        UNSPEC_FIST_CEIL))
+                  UNSPEC_FIST_CEIL))
    (use (match_operand:HI 2 "memory_operand" ""))
    (use (match_operand:HI 3 "memory_operand" ""))
    (clobber (match_operand:DI 4 "memory_operand" ""))
    (clobber (match_scratch 5 ""))]
   "reload_completed"
-  [(parallel [(set (match_dup 4) (unspec:DI [(match_dup 1)] UNSPEC_FIST_CEIL))
+  [(parallel [(set (match_dup 4)
+                  (unspec:DI [(match_dup 1)] UNSPEC_FIST_CEIL))
              (use (match_dup 2))
              (use (match_dup 3))
              (clobber (match_dup 5))])
@@ -14946,21 +14889,22 @@
 (define_split
   [(set (match_operand:DI 0 "memory_operand" "")
        (unspec:DI [(match_operand:XF 1 "register_operand" "")]
-        UNSPEC_FIST_CEIL))
+                  UNSPEC_FIST_CEIL))
    (use (match_operand:HI 2 "memory_operand" ""))
    (use (match_operand:HI 3 "memory_operand" ""))
    (clobber (match_operand:DI 4 "memory_operand" ""))
    (clobber (match_scratch 5 ""))]
   "reload_completed"
-  [(parallel [(set (match_dup 0) (unspec:DI [(match_dup 1)] UNSPEC_FIST_CEIL))
+  [(parallel [(set (match_dup 0)
+                  (unspec:DI [(match_dup 1)] UNSPEC_FIST_CEIL))
              (use (match_dup 2))
              (use (match_dup 3))
              (clobber (match_dup 5))])])
 
 (define_insn "fist<mode>2_ceil"
-  [(set (match_operand:X87MODEI12 0 "memory_operand" "=m")
-       (unspec:X87MODEI12 [(match_operand:XF 1 "register_operand" "f")]
-        UNSPEC_FIST_CEIL))
+  [(set (match_operand:SWI24 0 "memory_operand" "=m")
+       (unspec:SWI24 [(match_operand:XF 1 "register_operand" "f")]
+                     UNSPEC_FIST_CEIL))
    (use (match_operand:HI 2 "memory_operand" "m"))
    (use (match_operand:HI 3 "memory_operand" "m"))]
   "TARGET_USE_FANCY_MATH_387
@@ -14971,12 +14915,12 @@
    (set_attr "mode" "<MODE>")])
 
 (define_insn "fist<mode>2_ceil_with_temp"
-  [(set (match_operand:X87MODEI12 0 "nonimmediate_operand" "=m,?r")
-       (unspec:X87MODEI12 [(match_operand:XF 1 "register_operand" "f,f")]
-        UNSPEC_FIST_CEIL))
+  [(set (match_operand:SWI24 0 "nonimmediate_operand" "=m,?r")
+       (unspec:SWI24 [(match_operand:XF 1 "register_operand" "f,f")]
+                     UNSPEC_FIST_CEIL))
    (use (match_operand:HI 2 "memory_operand" "m,m"))
    (use (match_operand:HI 3 "memory_operand" "m,m"))
-   (clobber (match_operand:X87MODEI12 4 "memory_operand" "=X,m"))]
+   (clobber (match_operand:SWI24 4 "memory_operand" "=X,m"))]
   "TARGET_USE_FANCY_MATH_387
    && flag_unsafe_math_optimizations"
   "#"
@@ -14985,36 +14929,36 @@
    (set_attr "mode" "<MODE>")])
 
 (define_split
-  [(set (match_operand:X87MODEI12 0 "register_operand" "")
-       (unspec:X87MODEI12 [(match_operand:XF 1 "register_operand" "")]
-        UNSPEC_FIST_CEIL))
+  [(set (match_operand:SWI24 0 "register_operand" "")
+       (unspec:SWI24 [(match_operand:XF 1 "register_operand" "")]
+                     UNSPEC_FIST_CEIL))
    (use (match_operand:HI 2 "memory_operand" ""))
    (use (match_operand:HI 3 "memory_operand" ""))
-   (clobber (match_operand:X87MODEI12 4 "memory_operand" ""))]
+   (clobber (match_operand:SWI24 4 "memory_operand" ""))]
   "reload_completed"
-  [(parallel [(set (match_dup 4) (unspec:X87MODEI12 [(match_dup 1)]
-                                 UNSPEC_FIST_CEIL))
+  [(parallel [(set (match_dup 4)
+                  (unspec:SWI24 [(match_dup 1)] UNSPEC_FIST_CEIL))
              (use (match_dup 2))
              (use (match_dup 3))])
    (set (match_dup 0) (match_dup 4))])
 
 (define_split
-  [(set (match_operand:X87MODEI12 0 "memory_operand" "")
-       (unspec:X87MODEI12 [(match_operand:XF 1 "register_operand" "")]
-        UNSPEC_FIST_CEIL))
+  [(set (match_operand:SWI24 0 "memory_operand" "")
+       (unspec:SWI24 [(match_operand:XF 1 "register_operand" "")]
+                     UNSPEC_FIST_CEIL))
    (use (match_operand:HI 2 "memory_operand" ""))
    (use (match_operand:HI 3 "memory_operand" ""))
-   (clobber (match_operand:X87MODEI12 4 "memory_operand" ""))]
+   (clobber (match_operand:SWI24 4 "memory_operand" ""))]
   "reload_completed"
-  [(parallel [(set (match_dup 0) (unspec:X87MODEI12 [(match_dup 1)]
-                                 UNSPEC_FIST_CEIL))
+  [(parallel [(set (match_dup 0)
+                  (unspec:SWI24 [(match_dup 1)] UNSPEC_FIST_CEIL))
              (use (match_dup 2))
              (use (match_dup 3))])])
 
 (define_expand "lceilxf<mode>2"
-  [(parallel [(set (match_operand:X87MODEI 0 "nonimmediate_operand" "")
-                  (unspec:X87MODEI [(match_operand:XF 1 "register_operand" "")]
-                   UNSPEC_FIST_CEIL))
+  [(parallel [(set (match_operand:SWI248x 0 "nonimmediate_operand" "")
+                  (unspec:SWI248x [(match_operand:XF 1 "register_operand" "")]
+                                  UNSPEC_FIST_CEIL))
              (clobber (reg:CC FLAGS_REG))])]
   "TARGET_USE_FANCY_MATH_387
    && (!TARGET_SSE_MATH || TARGET_MIX_SSE_I387)
@@ -15880,11 +15824,11 @@
    (set_attr "prefix_rep" "1")])
 
 (define_expand "strlen<mode>"
-  [(set (match_operand:SWI48x 0 "register_operand" "")
-       (unspec:SWI48x [(match_operand:BLK 1 "general_operand" "")
-                       (match_operand:QI 2 "immediate_operand" "")
-                       (match_operand 3 "immediate_operand" "")]
-                      UNSPEC_SCAS))]
+  [(set (match_operand:P 0 "register_operand" "")
+       (unspec:P [(match_operand:BLK 1 "general_operand" "")
+                  (match_operand:QI 2 "immediate_operand" "")
+                  (match_operand 3 "immediate_operand" "")]
+                 UNSPEC_SCAS))]
   ""
 {
  if (ix86_expand_strlen (operands[0], operands[1], operands[2], operands[3]))
@@ -16002,8 +15946,8 @@
 (define_expand "mov<mode>cc"
   [(set (match_operand:SWIM 0 "register_operand" "")
        (if_then_else:SWIM (match_operand 1 "ordered_comparison_operator" "")
-                          (match_operand:SWIM 2 "general_operand" "")
-                          (match_operand:SWIM 3 "general_operand" "")))]
+                          (match_operand:SWIM 2 "<general_operand>" "")
+                          (match_operand:SWIM 3 "<general_operand>" "")))]
   ""
   "if (ix86_expand_int_movcc (operands)) DONE; else FAIL;")
 
@@ -17193,11 +17137,11 @@
   [(parallel
     [(set (match_operand:SWI48 0 "register_operand" "")
          (mult:SWI48 (match_operand:SWI48 1 "register_operand" "")
-                     (match_operand:SWI48 2 "const_int_operand" "")))
+                     (match_operand:SWI48 2 "const359_operand" "")))
      (clobber (reg:CC FLAGS_REG))])]
-  "INTVAL (operands[2]) == 3
-   || INTVAL (operands[2]) == 5
-   || INTVAL (operands[2]) == 9"
+  "!TARGET_PARTIAL_REG_STALL
+   || <MODE>mode == SImode
+   || optimize_function_for_size_p (cfun)"
   [(set (match_dup 0)
        (plus:SWI48 (mult:SWI48 (match_dup 1) (match_dup 2))
                    (match_dup 1)))]
@@ -17207,12 +17151,10 @@
   [(parallel
     [(set (match_operand:SWI48 0 "register_operand" "")
          (mult:SWI48 (match_operand:SWI48 1 "nonimmediate_operand" "")
-                     (match_operand:SWI48 2 "const_int_operand" "")))
+                     (match_operand:SWI48 2 "const359_operand" "")))
      (clobber (reg:CC FLAGS_REG))])]
   "optimize_insn_for_speed_p ()
-   && (INTVAL (operands[2]) == 3
-       || INTVAL (operands[2]) == 5
-       || INTVAL (operands[2]) == 9)"
+   && (!TARGET_PARTIAL_REG_STALL || <MODE>mode == SImode)"
   [(set (match_dup 0) (match_dup 1))
    (set (match_dup 0)
        (plus:SWI48 (mult:SWI48 (match_dup 0) (match_dup 2))
About OSDN
Find Software
Develop Software
Help