;; GCC machine description for IA-32 and x86-64.
;; Copyright (C) 1988, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
-;; 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008
+;; 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
;; Free Software Foundation, Inc.
;; Mostly by William Schelter.
;; x86_64 support added by Jan Hubicka
;; See file "rtl.def" for documentation on define_insn, match_*, et. al.
;;
;; The special asm out single letter directives following a '%' are:
-;; 'z' mov%z1 would be movl, movw, or movb depending on the mode of
-;; operands[1].
-;; 'L' Print the opcode suffix for a 32-bit integer opcode.
-;; 'W' Print the opcode suffix for a 16-bit integer opcode.
-;; 'B' Print the opcode suffix for an 8-bit integer opcode.
-;; 'Q' Print the opcode suffix for a 64-bit float opcode.
-;; 'S' Print the opcode suffix for a 32-bit float opcode.
-;; 'T' Print the opcode suffix for an 80-bit extended real XFmode float opcode.
-;; 'J' Print the appropriate jump operand.
-;;
-;; 'b' Print the QImode name of the register for the indicated operand.
-;; %b0 would print %al if operands[0] is reg 0.
-;; 'w' Likewise, print the HImode name of the register.
-;; 'k' Likewise, print the SImode name of the register.
-;; 'h' Print the QImode name for a "high" register, either ah, bh, ch or dh.
-;; 'y' Print "st(0)" instead of "st" as a register.
+;; L,W,B,Q,S,T -- print the opcode suffix for specified size of operand.
+;; C -- print opcode suffix for set/cmov insn.
+;; c -- like C, but print reversed condition
+;; E,e -- likewise, but for compare-and-branch fused insn.
+;; F,f -- likewise, but for floating-point.
+;; O -- if HAVE_AS_IX86_CMOV_SUN_SYNTAX, expand to "w.", "l." or "q.",
+;; otherwise nothing
+;; R -- print the prefix for register names.
+;; z -- print the opcode suffix for the size of the current operand.
+;; Z -- likewise, with special suffixes for x87 instructions.
+;; * -- print a star (in certain assembler syntax)
+;; A -- print an absolute memory reference.
+;; w -- print the operand as if it's a "word" (HImode) even if it isn't.
+;; s -- print a shift double count, followed by the assemblers argument
+;; delimiter.
+;; b -- print the QImode name of the register for the indicated operand.
+;; %b0 would print %al if operands[0] is reg 0.
+;; w -- likewise, print the HImode name of the register.
+;; k -- likewise, print the SImode name of the register.
+;; q -- likewise, print the DImode name of the register.
+;; x -- likewise, print the V4SFmode name of the register.
+;; t -- likewise, print the V8SFmode name of the register.
+;; h -- print the QImode name for a "high" register, either ah, bh, ch or dh.
+;; y -- print "st(0)" instead of "st" as a register.
+;; d -- print duplicated register operand for AVX instruction.
+;; D -- print condition for SSE cmp instruction.
+;; P -- if PIC, print an @PLT suffix.
+;; X -- don't print any sort of PIC '@' suffix for a symbol.
+;; & -- print some in-use local-dynamic symbol name.
+;; H -- print a memory address offset by 8; used for sse high-parts
+;; Y -- print condition for SSE5 com* instruction.
+;; + -- print a branch hint as 'cs' or 'ds' prefix
+;; ; -- print a semicolon (after prefixes due to bug in older gas).
;; UNSPEC usage:
(UNSPEC_DEF_CFA 15)
(UNSPEC_SET_RIP 16)
(UNSPEC_SET_GOT_OFFSET 17)
+ (UNSPEC_MEMORY_BLOCKAGE 18)
; TLS support
- (UNSPEC_TP 18)
- (UNSPEC_TLS_GD 19)
- (UNSPEC_TLS_LD_BASE 20)
- (UNSPEC_TLSDESC 21)
+ (UNSPEC_TP 20)
+ (UNSPEC_TLS_GD 21)
+ (UNSPEC_TLS_LD_BASE 22)
+ (UNSPEC_TLSDESC 23)
; Other random patterns
(UNSPEC_SCAS 30)
(UNSPEC_LFENCE 45)
(UNSPEC_PSADBW 46)
(UNSPEC_LDDQU 47)
+ (UNSPEC_MS_TO_SYSV_CALL 48)
; Generic math support
(UNSPEC_COPYSIGN 50)
(UNSPEC_FPREM1_U 91)
(UNSPEC_C2_FLAG 95)
+ (UNSPEC_FXAM_MEM 96)
; SSP patterns
(UNSPEC_SP_SET 100)
; For AVX support
(UNSPEC_PCMP 166)
(UNSPEC_VPERMIL 167)
- (UNSPEC_VPERMIL2 168)
- (UNSPEC_VPERMIL2F128 169)
- (UNSPEC_MASKLOAD 170)
- (UNSPEC_MASKSTORE 171)
- (UNSPEC_CAST 172)
- (UNSPEC_VTESTP 173)
+ (UNSPEC_VPERMIL2F128 168)
+ (UNSPEC_MASKLOAD 169)
+ (UNSPEC_MASKSTORE 170)
+ (UNSPEC_CAST 171)
+ (UNSPEC_VTESTP 172)
])
(define_constants
(UNSPECV_ALIGN 7)
(UNSPECV_MONITOR 8)
(UNSPECV_MWAIT 9)
- (UNSPECV_CMPXCHG_1 10)
- (UNSPECV_CMPXCHG_2 11)
+ (UNSPECV_CMPXCHG 10)
(UNSPECV_XCHG 12)
(UNSPECV_LOCK 13)
(UNSPECV_PROLOGUE_USE 14)
(DI_REG 5)
(BP_REG 6)
(SP_REG 7)
+ (ST0_REG 8)
+ (ST1_REG 9)
+ (ST2_REG 10)
+ (ST3_REG 11)
+ (ST4_REG 12)
+ (ST5_REG 13)
+ (ST6_REG 14)
+ (ST7_REG 15)
(FLAGS_REG 17)
(FPSR_REG 18)
(FPCR_REG 19)
(XMM5_REG 26)
(XMM6_REG 27)
(XMM7_REG 28)
+ (MM0_REG 29)
+ (MM1_REG 30)
+ (MM2_REG 31)
+ (MM3_REG 32)
+ (MM4_REG 33)
+ (MM5_REG 34)
+ (MM6_REG 35)
+ (MM7_REG 36)
+ (R8_REG 37)
+ (R9_REG 38)
(R10_REG 39)
(R11_REG 40)
(R13_REG 42)
\f
;; Processor type.
-(define_attr "cpu" "none,pentium,pentiumpro,geode,k6,athlon,k8,core2,
+(define_attr "cpu" "none,pentium,pentiumpro,geode,k6,athlon,k8,core2,atom,
generic64,amdfam10"
(const (symbol_ref "ix86_schedule")))
(define_attr "i387_cw" "trunc,floor,ceil,mask_pm,uninitialized,any"
(const_string "any"))
+;; Define attribute to classify add/sub insns that consumes carry flag (CF)
+(define_attr "use_carry" "0,1" (const_string "0"))
+
+;; Define attribute to indicate unaligned ssemov insns
+(define_attr "movu" "0,1" (const_string "0"))
+
;; Describe a user's asm statement.
(define_asm_attributes
[(set_attr "length" "128")
;; All single word integer modes.
(define_mode_iterator SWI [QI HI SI (DI "TARGET_64BIT")])
-;; Single word integer modes up to SImode.
-(define_mode_iterator SWI32 [QI HI SI])
+;; Single word integer modes without QImode.
+(define_mode_iterator SWI248 [HI SI (DI "TARGET_64BIT")])
;; Instruction suffix for integer modes.
(define_mode_attr imodesuffix [(QI "b") (HI "w") (SI "l") (DI "q")])
(include "k6.md")
(include "athlon.md")
(include "geode.md")
+(include "atom.md")
\f
;; Operand and operator predicates and constraints
(include "constraints.md")
\f
-;; Compare instructions.
+;; Compare and branch/compare and store instructions.
+
+(define_expand "cbranchti4"
+ [(set (reg:CC FLAGS_REG)
+ (compare:CC (match_operand:TI 1 "nonimmediate_operand" "")
+ (match_operand:TI 2 "x86_64_general_operand" "")))
+ (set (pc) (if_then_else
+ (match_operator 0 "comparison_operator"
+ [(reg:CC FLAGS_REG)
+ (const_int 0)])
+ (label_ref (match_operand 3 "" ""))
+ (pc)))]
+ "TARGET_64BIT"
+{
+ if (MEM_P (operands[1]) && MEM_P (operands[2]))
+ operands[1] = force_reg (TImode, operands[1]);
+ ix86_compare_op0 = operands[1];
+ ix86_compare_op1 = operands[2];
+ ix86_expand_branch (GET_CODE (operands[0]), operands[3]);
+ DONE;
+})
-;; All compare insns have expanders that save the operands away without
-;; actually generating RTL. The bCOND or sCOND (emitted immediately
-;; after the cmp) will actually emit the cmpM.
+(define_expand "cbranchdi4"
+ [(set (reg:CC FLAGS_REG)
+ (compare:CC (match_operand:DI 1 "nonimmediate_operand" "")
+ (match_operand:DI 2 "x86_64_general_operand" "")))
+ (set (pc) (if_then_else
+ (match_operator 0 "comparison_operator"
+ [(reg:CC FLAGS_REG)
+ (const_int 0)])
+ (label_ref (match_operand 3 "" ""))
+ (pc)))]
+ ""
+{
+ if (MEM_P (operands[1]) && MEM_P (operands[2]))
+ operands[1] = force_reg (DImode, operands[1]);
+ ix86_compare_op0 = operands[1];
+ ix86_compare_op1 = operands[2];
+ ix86_expand_branch (GET_CODE (operands[0]), operands[3]);
+ DONE;
+})
-(define_expand "cmpti"
+(define_expand "cstoredi4"
[(set (reg:CC FLAGS_REG)
- (compare:CC (match_operand:TI 0 "nonimmediate_operand" "")
- (match_operand:TI 1 "x86_64_general_operand" "")))]
+ (compare:CC (match_operand:DI 2 "nonimmediate_operand" "")
+ (match_operand:DI 3 "x86_64_general_operand" "")))
+ (set (match_operand:QI 0 "register_operand" "")
+ (match_operator 1 "comparison_operator"
+ [(reg:CC FLAGS_REG)
+ (const_int 0)]))]
"TARGET_64BIT"
{
- if (MEM_P (operands[0]) && MEM_P (operands[1]))
- operands[0] = force_reg (TImode, operands[0]);
- ix86_compare_op0 = operands[0];
- ix86_compare_op1 = operands[1];
+ if (MEM_P (operands[2]) && MEM_P (operands[3]))
+ operands[2] = force_reg (DImode, operands[2]);
+ ix86_compare_op0 = operands[2];
+ ix86_compare_op1 = operands[3];
+ ix86_expand_setcc (GET_CODE (operands[1]), operands[0]);
DONE;
})
-(define_expand "cmpdi"
+(define_expand "cbranchsi4"
[(set (reg:CC FLAGS_REG)
- (compare:CC (match_operand:DI 0 "nonimmediate_operand" "")
- (match_operand:DI 1 "x86_64_general_operand" "")))]
+ (compare:CC (match_operand:SI 1 "cmpsi_operand" "")
+ (match_operand:SI 2 "general_operand" "")))
+ (set (pc) (if_then_else
+ (match_operator 0 "comparison_operator"
+ [(reg:CC FLAGS_REG)
+ (const_int 0)])
+ (label_ref (match_operand 3 "" ""))
+ (pc)))]
""
{
- if (MEM_P (operands[0]) && MEM_P (operands[1]))
- operands[0] = force_reg (DImode, operands[0]);
- ix86_compare_op0 = operands[0];
- ix86_compare_op1 = operands[1];
+ if (MEM_P (operands[1]) && MEM_P (operands[2]))
+ operands[1] = force_reg (SImode, operands[1]);
+ ix86_compare_op0 = operands[1];
+ ix86_compare_op1 = operands[2];
+ ix86_expand_branch (GET_CODE (operands[0]), operands[3]);
DONE;
})
-(define_expand "cmpsi"
+(define_expand "cstoresi4"
[(set (reg:CC FLAGS_REG)
- (compare:CC (match_operand:SI 0 "cmpsi_operand" "")
- (match_operand:SI 1 "general_operand" "")))]
+ (compare:CC (match_operand:SI 2 "cmpsi_operand" "")
+ (match_operand:SI 3 "general_operand" "")))
+ (set (match_operand:QI 0 "register_operand" "")
+ (match_operator 1 "comparison_operator"
+ [(reg:CC FLAGS_REG)
+ (const_int 0)]))]
""
{
- if (MEM_P (operands[0]) && MEM_P (operands[1]))
- operands[0] = force_reg (SImode, operands[0]);
- ix86_compare_op0 = operands[0];
- ix86_compare_op1 = operands[1];
+ if (MEM_P (operands[2]) && MEM_P (operands[3]))
+ operands[2] = force_reg (SImode, operands[2]);
+ ix86_compare_op0 = operands[2];
+ ix86_compare_op1 = operands[3];
+ ix86_expand_setcc (GET_CODE (operands[1]), operands[0]);
DONE;
})
-(define_expand "cmphi"
+(define_expand "cbranchhi4"
[(set (reg:CC FLAGS_REG)
- (compare:CC (match_operand:HI 0 "nonimmediate_operand" "")
- (match_operand:HI 1 "general_operand" "")))]
+ (compare:CC (match_operand:HI 1 "nonimmediate_operand" "")
+ (match_operand:HI 2 "general_operand" "")))
+ (set (pc) (if_then_else
+ (match_operator 0 "comparison_operator"
+ [(reg:CC FLAGS_REG)
+ (const_int 0)])
+ (label_ref (match_operand 3 "" ""))
+ (pc)))]
""
{
- if (MEM_P (operands[0]) && MEM_P (operands[1]))
- operands[0] = force_reg (HImode, operands[0]);
- ix86_compare_op0 = operands[0];
- ix86_compare_op1 = operands[1];
+ if (MEM_P (operands[1]) && MEM_P (operands[2]))
+ operands[1] = force_reg (HImode, operands[1]);
+ ix86_compare_op0 = operands[1];
+ ix86_compare_op1 = operands[2];
+ ix86_expand_branch (GET_CODE (operands[0]), operands[3]);
DONE;
})
-(define_expand "cmpqi"
+(define_expand "cstorehi4"
[(set (reg:CC FLAGS_REG)
- (compare:CC (match_operand:QI 0 "nonimmediate_operand" "")
- (match_operand:QI 1 "general_operand" "")))]
- "TARGET_QIMODE_MATH"
+ (compare:CC (match_operand:HI 2 "nonimmediate_operand" "")
+ (match_operand:HI 3 "general_operand" "")))
+ (set (match_operand:QI 0 "register_operand" "")
+ (match_operator 1 "comparison_operator"
+ [(reg:CC FLAGS_REG)
+ (const_int 0)]))]
+ ""
{
- if (MEM_P (operands[0]) && MEM_P (operands[1]))
- operands[0] = force_reg (QImode, operands[0]);
- ix86_compare_op0 = operands[0];
- ix86_compare_op1 = operands[1];
+ if (MEM_P (operands[2]) && MEM_P (operands[3]))
+ operands[2] = force_reg (HImode, operands[2]);
+ ix86_compare_op0 = operands[2];
+ ix86_compare_op1 = operands[3];
+ ix86_expand_setcc (GET_CODE (operands[1]), operands[0]);
+ DONE;
+})
+
+
+(define_expand "cbranchqi4"
+ [(set (reg:CC FLAGS_REG)
+ (compare:CC (match_operand:QI 1 "nonimmediate_operand" "")
+ (match_operand:QI 2 "general_operand" "")))
+ (set (pc) (if_then_else
+ (match_operator 0 "comparison_operator"
+ [(reg:CC FLAGS_REG)
+ (const_int 0)])
+ (label_ref (match_operand 3 "" ""))
+ (pc)))]
+ ""
+{
+ if (MEM_P (operands[1]) && MEM_P (operands[2]))
+ operands[1] = force_reg (QImode, operands[1]);
+ ix86_compare_op0 = operands[1];
+ ix86_compare_op1 = operands[2];
+ ix86_expand_branch (GET_CODE (operands[0]), operands[3]);
+ DONE;
+})
+
+
+(define_expand "cstoreqi4"
+ [(set (reg:CC FLAGS_REG)
+ (compare:CC (match_operand:QI 2 "nonimmediate_operand" "")
+ (match_operand:QI 3 "general_operand" "")))
+ (set (match_operand:QI 0 "register_operand" "")
+ (match_operator 1 "comparison_operator"
+ [(reg:CC FLAGS_REG)
+ (const_int 0)]))]
+ ""
+{
+ if (MEM_P (operands[2]) && MEM_P (operands[3]))
+ operands[2] = force_reg (QImode, operands[2]);
+ ix86_compare_op0 = operands[2];
+ ix86_compare_op1 = operands[3];
+ ix86_expand_setcc (GET_CODE (operands[1]), operands[0]);
DONE;
})
+
(define_insn "cmpdi_ccno_1_rex64"
[(set (reg FLAGS_REG)
(compare (match_operand:DI 0 "nonimmediate_operand" "r,?mr")
;; which would allow mix and match FP modes on the compares. Which is what
;; the old patterns did, but with many more of them.
-(define_expand "cmpxf"
+(define_expand "cbranchxf4"
+ [(set (reg:CC FLAGS_REG)
+ (compare:CC (match_operand:XF 1 "nonmemory_operand" "")
+ (match_operand:XF 2 "nonmemory_operand" "")))
+ (set (pc) (if_then_else
+ (match_operator 0 "comparison_operator"
+ [(reg:CC FLAGS_REG)
+ (const_int 0)])
+ (label_ref (match_operand 3 "" ""))
+ (pc)))]
+ "TARGET_80387"
+{
+ ix86_compare_op0 = operands[1];
+ ix86_compare_op1 = operands[2];
+ ix86_expand_branch (GET_CODE (operands[0]), operands[3]);
+ DONE;
+})
+
+(define_expand "cstorexf4"
[(set (reg:CC FLAGS_REG)
- (compare:CC (match_operand:XF 0 "nonmemory_operand" "")
- (match_operand:XF 1 "nonmemory_operand" "")))]
+ (compare:CC (match_operand:XF 2 "nonmemory_operand" "")
+ (match_operand:XF 3 "nonmemory_operand" "")))
+ (set (match_operand:QI 0 "register_operand" "")
+ (match_operator 1 "comparison_operator"
+ [(reg:CC FLAGS_REG)
+ (const_int 0)]))]
"TARGET_80387"
{
- ix86_compare_op0 = operands[0];
- ix86_compare_op1 = operands[1];
+ ix86_compare_op0 = operands[2];
+ ix86_compare_op1 = operands[3];
+ ix86_expand_setcc (GET_CODE (operands[1]), operands[0]);
DONE;
})
-(define_expand "cmp<mode>"
+(define_expand "cbranch<mode>4"
[(set (reg:CC FLAGS_REG)
- (compare:CC (match_operand:MODEF 0 "cmp_fp_expander_operand" "")
- (match_operand:MODEF 1 "cmp_fp_expander_operand" "")))]
+ (compare:CC (match_operand:MODEF 1 "cmp_fp_expander_operand" "")
+ (match_operand:MODEF 2 "cmp_fp_expander_operand" "")))
+ (set (pc) (if_then_else
+ (match_operator 0 "comparison_operator"
+ [(reg:CC FLAGS_REG)
+ (const_int 0)])
+ (label_ref (match_operand 3 "" ""))
+ (pc)))]
"TARGET_80387 || (SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)"
{
- ix86_compare_op0 = operands[0];
- ix86_compare_op1 = operands[1];
+ ix86_compare_op0 = operands[1];
+ ix86_compare_op1 = operands[2];
+ ix86_expand_branch (GET_CODE (operands[0]), operands[3]);
+ DONE;
+})
+
+(define_expand "cstore<mode>4"
+ [(set (reg:CC FLAGS_REG)
+ (compare:CC (match_operand:MODEF 2 "cmp_fp_expander_operand" "")
+ (match_operand:MODEF 3 "cmp_fp_expander_operand" "")))
+ (set (match_operand:QI 0 "register_operand" "")
+ (match_operator 1 "comparison_operator"
+ [(reg:CC FLAGS_REG)
+ (const_int 0)]))]
+ "TARGET_80387 || (SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)"
+{
+ ix86_compare_op0 = operands[2];
+ ix86_compare_op1 = operands[3];
+ ix86_expand_setcc (GET_CODE (operands[1]), operands[0]);
+ DONE;
+})
+
+(define_expand "cbranchcc4"
+ [(set (pc) (if_then_else
+ (match_operator 0 "comparison_operator"
+ [(match_operand 1 "flags_reg_operand" "")
+ (match_operand 2 "const0_operand" "")])
+ (label_ref (match_operand 3 "" ""))
+ (pc)))]
+ ""
+{
+ ix86_compare_op0 = operands[1];
+ ix86_compare_op1 = operands[2];
+ ix86_expand_branch (GET_CODE (operands[0]), operands[3]);
+ DONE;
+})
+
+(define_expand "cstorecc4"
+ [(set (match_operand:QI 0 "register_operand" "")
+ (match_operator 1 "comparison_operator"
+ [(match_operand 2 "flags_reg_operand" "")
+ (match_operand 3 "const0_operand" "")]))]
+ ""
+{
+ ix86_compare_op0 = operands[2];
+ ix86_compare_op1 = operands[3];
+ ix86_expand_setcc (GET_CODE (operands[1]), operands[0]);
DONE;
})
+
;; FP compares, step 1:
;; Set the FP condition codes.
;;
gcc_unreachable ();
}
- case TYPE_MMXADD:
+ case TYPE_MMX:
return "pxor\t%0, %0";
case TYPE_MMXMOV:
}
[(set (attr "type")
(cond [(eq_attr "alternative" "2")
- (const_string "mmxadd")
+ (const_string "mmx")
(eq_attr "alternative" "3,4,5")
(const_string "mmxmov")
(eq_attr "alternative" "6")
case TYPE_SSELOG1:
return "%vpxor\t%0, %d0";
- case TYPE_MMXADD:
+ case TYPE_MMX:
return "pxor\t%0, %0";
case TYPE_MULTI:
}
[(set (attr "type")
(cond [(eq_attr "alternative" "5")
- (const_string "mmxadd")
+ (const_string "mmx")
(eq_attr "alternative" "6,7,8,9,10")
(const_string "mmxmov")
(eq_attr "alternative" "11")
;
else
{
- int slot = virtuals_instantiated ? SLOT_TEMP : SLOT_VIRTUAL;
+ enum ix86_stack_slot slot = (virtuals_instantiated
+ ? SLOT_TEMP
+ : SLOT_VIRTUAL);
rtx temp = assign_386_stack_local (SFmode, slot);
emit_insn (gen_truncdfsf2_with_temp (operands[0], operands[1], temp));
DONE;
(set_attr "mode" "SF")])
(define_insn "*truncdfsf_mixed"
- [(set (match_operand:SF 0 "nonimmediate_operand" "=m,?fx*r,Y2")
+ [(set (match_operand:SF 0 "nonimmediate_operand" "=m,Y2 ,?f,?x,?*r")
(float_truncate:SF
- (match_operand:DF 1 "nonimmediate_operand" "f ,f ,Y2m")))
- (clobber (match_operand:SF 2 "memory_operand" "=X,m ,X"))]
+ (match_operand:DF 1 "nonimmediate_operand" "f ,Y2m,f ,f ,f")))
+ (clobber (match_operand:SF 2 "memory_operand" "=X,X ,m ,m ,m"))]
"TARGET_MIX_SSE_I387"
{
switch (which_alternative)
{
case 0:
return output_387_reg_move (insn, operands);
-
case 1:
- return "#";
- case 2:
return "%vcvtsd2ss\t{%1, %d0|%d0, %1}";
+
default:
- gcc_unreachable ();
+ return "#";
}
}
- [(set_attr "type" "fmov,multi,ssecvt")
- (set_attr "unit" "*,i387,*")
- (set_attr "prefix" "orig,orig,maybe_vex")
+ [(set_attr "type" "fmov,ssecvt,multi,multi,multi")
+ (set_attr "unit" "*,*,i387,i387,i387")
+ (set_attr "prefix" "orig,maybe_vex,orig,orig,orig")
(set_attr "mode" "SF")])
(define_insn "*truncdfsf_i387"
- [(set (match_operand:SF 0 "nonimmediate_operand" "=m,?fx*r")
+ [(set (match_operand:SF 0 "nonimmediate_operand" "=m,?f,?x,?*r")
(float_truncate:SF
- (match_operand:DF 1 "nonimmediate_operand" "f,f")))
- (clobber (match_operand:SF 2 "memory_operand" "=X,m"))]
+ (match_operand:DF 1 "nonimmediate_operand" "f ,f ,f ,f")))
+ (clobber (match_operand:SF 2 "memory_operand" "=X,m ,m ,m"))]
"TARGET_80387"
{
switch (which_alternative)
case 0:
return output_387_reg_move (insn, operands);
- case 1:
- return "#";
default:
- gcc_unreachable ();
+ return "#";
}
}
- [(set_attr "type" "fmov,multi")
- (set_attr "unit" "*,i387")
+ [(set_attr "type" "fmov,multi,multi,multi")
+ (set_attr "unit" "*,i387,i387,i387")
(set_attr "mode" "SF")])
(define_insn "*truncdfsf2_i387_1"
}
else
{
- int slot = virtuals_instantiated ? SLOT_TEMP : SLOT_VIRTUAL;
+ enum ix86_stack_slot slot = (virtuals_instantiated
+ ? SLOT_TEMP
+ : SLOT_VIRTUAL);
operands[2] = assign_386_stack_local (<MODE>mode, slot);
}
})
(define_insn "*truncxfsf2_mixed"
- [(set (match_operand:SF 0 "nonimmediate_operand" "=m,?fx*r")
+ [(set (match_operand:SF 0 "nonimmediate_operand" "=m,?f,?x,?*r")
(float_truncate:SF
- (match_operand:XF 1 "register_operand" "f,f")))
- (clobber (match_operand:SF 2 "memory_operand" "=X,m"))]
+ (match_operand:XF 1 "register_operand" "f ,f ,f ,f")))
+ (clobber (match_operand:SF 2 "memory_operand" "=X,m ,m ,m"))]
"TARGET_80387"
{
gcc_assert (!which_alternative);
return output_387_reg_move (insn, operands);
}
- [(set_attr "type" "fmov,multi")
- (set_attr "unit" "*,i387")
+ [(set_attr "type" "fmov,multi,multi,multi")
+ (set_attr "unit" "*,i387,i387,i387")
(set_attr "mode" "SF")])
(define_insn "*truncxfdf2_mixed"
- [(set (match_operand:DF 0 "nonimmediate_operand" "=m,?fY2*r")
+ [(set (match_operand:DF 0 "nonimmediate_operand" "=m,?f,?Y2,?*r")
(float_truncate:DF
- (match_operand:XF 1 "register_operand" "f,f")))
- (clobber (match_operand:DF 2 "memory_operand" "=X,m"))]
+ (match_operand:XF 1 "register_operand" "f ,f ,f ,f")))
+ (clobber (match_operand:DF 2 "memory_operand" "=X,m ,m ,m"))]
"TARGET_80387"
{
gcc_assert (!which_alternative);
return output_387_reg_move (insn, operands);
}
- [(set_attr "type" "fmov,multi")
- (set_attr "unit" "*,i387")
+ [(set_attr "type" "fmov,multi,multi,multi")
+ (set_attr "unit" "*,i387,i387,i387")
(set_attr "mode" "DF")])
(define_insn "truncxf<mode>2_i387_noop"
"TARGET_80387
&& (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
|| TARGET_MIX_SSE_I387)"
- "fild%z1\t%1"
+ "fild%Z1\t%1"
[(set_attr "type" "fmov")
(set_attr "mode" "<MODE>")
(set_attr "fp_int_src" "true")])
"TARGET_80387
|| ((<SSEMODEI24:MODE>mode != DImode || TARGET_64BIT)
&& SSE_FLOAT_MODE_P (<X87MODEF:MODE>mode) && TARGET_SSE_MATH)"
- "")
+ "
+{
+ if (!((<SSEMODEI24:MODE>mode != DImode || TARGET_64BIT)
+ && SSE_FLOAT_MODE_P (<X87MODEF:MODE>mode) && TARGET_SSE_MATH)
+ && !X87_ENABLE_FLOAT (<X87MODEF:MODE>mode, <SSEMODEI24:MODE>mode))
+ {
+ rtx reg = gen_reg_rtx (XFmode);
+ emit_insn (gen_float<SSEMODEI24:mode>xf2 (reg, operands[1]));
+/* Avoid references to nonexistent function in dead code in XFmode case. */
+#define gen_truncxfxf2 gen_truncxfdf2
+ emit_insn (gen_truncxf<X87MODEF:mode>2 (operands[0], reg));
+#undef gen_truncxfxf2
+ DONE;
+ }
+}")
;; Pre-reload splitter to add memory clobber to the pattern.
(define_insn_and_split "*float<SSEMODEI24:mode><X87MODEF:mode>2_1"
[(set (match_operand:X87MODEF 0 "register_operand" "")
(float:X87MODEF (match_operand:SSEMODEI24 1 "register_operand" "")))]
"((TARGET_80387
+ && X87_ENABLE_FLOAT (<X87MODEF:MODE>mode, <SSEMODEI24:MODE>mode)
&& (!((<SSEMODEI24:MODE>mode != DImode || TARGET_64BIT)
&& SSE_FLOAT_MODE_P (<X87MODEF:MODE>mode) && TARGET_SSE_MATH)
|| TARGET_MIX_SSE_I387))
"TARGET_SSE2 && TARGET_MIX_SSE_I387
&& TARGET_USE_VECTOR_CONVERTS && optimize_function_for_speed_p (cfun)"
"@
- fild%z1\t%1
+ fild%Z1\t%1
#"
[(set_attr "type" "fmov,sseicvt")
(set_attr "mode" "<MODE>,<ssevecmode>")
&& SSE_FLOAT_MODE_P (<MODEF:MODE>mode) && TARGET_MIX_SSE_I387
&& (TARGET_INTER_UNIT_CONVERSIONS || optimize_function_for_size_p (cfun))"
"@
- fild%z1\t%1
+ fild%Z1\t%1
%vcvtsi2s<MODEF:ssemodefsuffix><SSEMODEI24:rex64suffix>\t{%1, %d0|%d0, %1}
%vcvtsi2s<MODEF:ssemodefsuffix><SSEMODEI24:rex64suffix>\t{%1, %d0|%d0, %1}"
[(set_attr "type" "fmov,sseicvt,sseicvt")
&& SSE_FLOAT_MODE_P (<MODEF:MODE>mode) && TARGET_MIX_SSE_I387
&& !(TARGET_INTER_UNIT_CONVERSIONS || optimize_function_for_size_p (cfun))"
"@
- fild%z1\t%1
+ fild%Z1\t%1
%vcvtsi2s<MODEF:ssemodefsuffix><SSEMODEI24:rex64suffix>\t{%1, %d0|%d0, %1}"
[(set_attr "type" "fmov,sseicvt")
(set_attr "prefix" "orig,maybe_vex")
(float:X87MODEF
(match_operand:SSEMODEI24 1 "nonimmediate_operand" "m,?r")))
(clobber (match_operand:SSEMODEI24 2 "memory_operand" "=X,m"))]
- "TARGET_80387"
+ "TARGET_80387
+ && X87_ENABLE_FLOAT (<X87MODEF:MODE>mode, <SSEMODEI24:MODE>mode)"
"@
- fild%z1\t%1
+ fild%Z1\t%1
#"
[(set_attr "type" "fmov,multi")
(set_attr "mode" "<X87MODEF:MODE>")
[(set (match_operand:X87MODEF 0 "register_operand" "=f")
(float:X87MODEF
(match_operand:SSEMODEI24 1 "memory_operand" "m")))]
- "TARGET_80387"
- "fild%z1\t%1"
+ "TARGET_80387
+ && X87_ENABLE_FLOAT (<X87MODEF:MODE>mode, <SSEMODEI24:MODE>mode)"
+ "fild%Z1\t%1"
[(set_attr "type" "fmov")
(set_attr "mode" "<X87MODEF:MODE>")
(set_attr "fp_int_src" "true")])
(float:X87MODEF (match_operand:SSEMODEI24 1 "register_operand" "")))
(clobber (match_operand:SSEMODEI24 2 "memory_operand" ""))]
"TARGET_80387
+ && X87_ENABLE_FLOAT (<X87MODEF:MODE>mode, <SSEMODEI24:MODE>mode)
&& reload_completed
&& FP_REG_P (operands[0])"
[(set (match_dup 2) (match_dup 1))
(float:X87MODEF (match_operand:SSEMODEI24 1 "memory_operand" "")))
(clobber (match_operand:SSEMODEI24 2 "memory_operand" ""))]
"TARGET_80387
+ && X87_ENABLE_FLOAT (<X87MODEF:MODE>mode, <SSEMODEI24:MODE>mode)
&& reload_completed
&& FP_REG_P (operands[0])"
[(set (match_dup 0) (float:X87MODEF (match_dup 1)))]
(clobber (match_scratch:V4SI 3 "=X,x"))
(clobber (match_scratch:V4SI 4 "=X,x"))
(clobber (match_operand:DI 2 "memory_operand" "=X,m"))]
- "TARGET_80387 && TARGET_SSE2 && TARGET_INTER_UNIT_MOVES
+ "TARGET_80387 && X87_ENABLE_FLOAT (<X87MODEF:MODE>mode, DImode)
+ && TARGET_SSE2 && TARGET_INTER_UNIT_MOVES
&& !TARGET_64BIT && optimize_function_for_speed_p (cfun)"
"#"
[(set_attr "type" "multi")
(clobber (match_scratch:V4SI 3 ""))
(clobber (match_scratch:V4SI 4 ""))
(clobber (match_operand:DI 2 "memory_operand" ""))]
- "TARGET_80387 && TARGET_SSE2 && TARGET_INTER_UNIT_MOVES
+ "TARGET_80387 && X87_ENABLE_FLOAT (<X87MODEF:MODE>mode, DImode)
+ && TARGET_SSE2 && TARGET_INTER_UNIT_MOVES
&& !TARGET_64BIT && optimize_function_for_speed_p (cfun)
&& reload_completed
&& FP_REG_P (operands[0])"
(clobber (match_scratch:V4SI 3 ""))
(clobber (match_scratch:V4SI 4 ""))
(clobber (match_operand:DI 2 "memory_operand" ""))]
- "TARGET_80387 && TARGET_SSE2 && TARGET_INTER_UNIT_MOVES
+ "TARGET_80387 && X87_ENABLE_FLOAT (<X87MODEF:MODE>mode, DImode)
+ && TARGET_SSE2 && TARGET_INTER_UNIT_MOVES
&& !TARGET_64BIT && optimize_function_for_speed_p (cfun)
&& reload_completed
&& FP_REG_P (operands[0])"
(clobber (match_operand:DI 2 "memory_operand" "=m,m"))
(clobber (match_scratch:SI 3 "=X,x"))]
"!TARGET_64BIT
- && TARGET_80387 && TARGET_SSE"
+ && TARGET_80387 && X87_ENABLE_FLOAT (<X87MODEF:MODE>mode, DImode)
+ && TARGET_SSE"
"#"
[(set_attr "type" "multi")
(set_attr "mode" "<MODE>")])
(clobber (match_operand:DI 2 "memory_operand" ""))
(clobber (match_scratch:SI 3 ""))]
"!TARGET_64BIT
- && TARGET_80387 && TARGET_SSE
+ && TARGET_80387 && X87_ENABLE_FLOAT (<X87MODEF:MODE>mode, DImode)
+ && TARGET_SSE
&& reload_completed"
[(set (match_dup 2) (match_dup 1))
(set (match_dup 0)
(clobber (match_operand:DI 2 "memory_operand" ""))
(clobber (match_scratch:SI 3 ""))]
"!TARGET_64BIT
- && TARGET_80387 && TARGET_SSE
+ && TARGET_80387 && X87_ENABLE_FLOAT (<X87MODEF:MODE>mode, DImode)
+ && TARGET_SSE
&& reload_completed"
[(set (match_dup 2) (match_dup 3))
(set (match_dup 0)
(clobber (match_dup 2))
(clobber (match_scratch:SI 3 ""))])]
"!TARGET_64BIT
- && ((TARGET_80387 && TARGET_SSE)
+ && ((TARGET_80387 && X87_ENABLE_FLOAT (<X87MODEF:MODE>mode, DImode)
+ && TARGET_SSE)
|| (SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH))"
{
if (SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
}
else
{
- int slot = virtuals_instantiated ? SLOT_TEMP : SLOT_VIRTUAL;
+ enum ix86_stack_slot slot = (virtuals_instantiated
+ ? SLOT_TEMP
+ : SLOT_VIRTUAL);
operands[2] = assign_386_stack_local (DImode, slot);
}
})
"TARGET_64BIT && ix86_binary_operator_ok (PLUS, DImode, operands)"
"adc{q}\t{%2, %0|%0, %2}"
[(set_attr "type" "alu")
+ (set_attr "use_carry" "1")
(set_attr "pent_pair" "pu")
(set_attr "mode" "DI")])
"ix86_binary_operator_ok (PLUS, QImode, operands)"
"adc{b}\t{%2, %0|%0, %2}"
[(set_attr "type" "alu")
+ (set_attr "use_carry" "1")
(set_attr "pent_pair" "pu")
(set_attr "mode" "QI")])
"ix86_binary_operator_ok (PLUS, HImode, operands)"
"adc{w}\t{%2, %0|%0, %2}"
[(set_attr "type" "alu")
+ (set_attr "use_carry" "1")
(set_attr "pent_pair" "pu")
(set_attr "mode" "HI")])
"ix86_binary_operator_ok (PLUS, SImode, operands)"
"adc{l}\t{%2, %0|%0, %2}"
[(set_attr "type" "alu")
+ (set_attr "use_carry" "1")
(set_attr "pent_pair" "pu")
(set_attr "mode" "SI")])
"TARGET_64BIT && ix86_binary_operator_ok (PLUS, SImode, operands)"
"adc{l}\t{%2, %k0|%k0, %2}"
[(set_attr "type" "alu")
+ (set_attr "use_carry" "1")
(set_attr "pent_pair" "pu")
(set_attr "mode" "SI")])
(set_attr "mode" "SI")])
(define_insn "*adddi_1_rex64"
- [(set (match_operand:DI 0 "nonimmediate_operand" "=r,rm,r")
- (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,r")
- (match_operand:DI 2 "x86_64_general_operand" "rme,re,le")))
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=r,rm,r,r")
+ (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,r,r")
+ (match_operand:DI 2 "x86_64_general_operand" "rme,re,0,le")))
(clobber (reg:CC FLAGS_REG))]
"TARGET_64BIT && ix86_binary_operator_ok (PLUS, DImode, operands)"
{
}
default:
+ /* Use add as much as possible to replace lea for AGU optimization. */
+ if (which_alternative == 2 && TARGET_OPT_AGU)
+ return "add{q}\t{%1, %0|%0, %1}";
+
gcc_assert (rtx_equal_p (operands[0], operands[1]));
/* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
}
}
[(set (attr "type")
- (cond [(eq_attr "alternative" "2")
+ (cond [(and (eq_attr "alternative" "2")
+ (eq (symbol_ref "TARGET_OPT_AGU") (const_int 0)))
(const_string "lea")
+ (eq_attr "alternative" "3")
+ (const_string "lea")
; Current assemblers are broken and do not allow @GOTOFF in
; ought but a memory context.
(match_operand:DI 2 "pic_symbolic_operand" "")
(plus:DI (match_operand:DI 1 "register_operand" "")
(match_operand:DI 2 "x86_64_nonmemory_operand" "")))
(clobber (reg:CC FLAGS_REG))]
- "TARGET_64BIT && reload_completed
- && true_regnum (operands[0]) != true_regnum (operands[1])"
+ "TARGET_64BIT && reload_completed
+ && ix86_lea_for_add_ok (PLUS, insn, operands)"
[(set (match_dup 0)
(plus:DI (match_dup 1)
(match_dup 2)))]
(define_insn "*addsi_1"
- [(set (match_operand:SI 0 "nonimmediate_operand" "=r,rm,r")
- (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,r")
- (match_operand:SI 2 "general_operand" "g,ri,li")))
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=r,rm,r,r")
+ (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,r,r")
+ (match_operand:SI 2 "general_operand" "g,ri,0,li")))
(clobber (reg:CC FLAGS_REG))]
"ix86_binary_operator_ok (PLUS, SImode, operands)"
{
}
default:
+ /* Use add as much as possible to replace lea for AGU optimization. */
+ if (which_alternative == 2 && TARGET_OPT_AGU)
+ return "add{l}\t{%1, %0|%0, %1}";
+
gcc_assert (rtx_equal_p (operands[0], operands[1]));
/* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
}
}
[(set (attr "type")
- (cond [(eq_attr "alternative" "2")
+ (cond [(and (eq_attr "alternative" "2")
+ (eq (symbol_ref "TARGET_OPT_AGU") (const_int 0)))
+ (const_string "lea")
+ (eq_attr "alternative" "3")
(const_string "lea")
; Current assemblers are broken and do not allow @GOTOFF in
; ought but a memory context.
(plus (match_operand 1 "register_operand" "")
(match_operand 2 "nonmemory_operand" "")))
(clobber (reg:CC FLAGS_REG))]
- "reload_completed
- && true_regnum (operands[0]) != true_regnum (operands[1])"
+ "reload_completed && ix86_lea_for_add_ok (PLUS, insn, operands)"
[(const_int 0)]
{
rtx pat;
[(set (match_operand:MODEF 0 "register_operand" "")
(plus:MODEF (match_operand:MODEF 1 "register_operand" "")
(match_operand:MODEF 2 "nonimmediate_operand" "")))]
- "TARGET_80387 || (SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)"
+ "(TARGET_80387 && X87_ENABLE_ARITH (<MODE>mode))
+ || (SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)"
"")
\f
;; Subtract instructions
"TARGET_64BIT && ix86_binary_operator_ok (MINUS, DImode, operands)"
"sbb{q}\t{%2, %0|%0, %2}"
[(set_attr "type" "alu")
+ (set_attr "use_carry" "1")
(set_attr "pent_pair" "pu")
(set_attr "mode" "DI")])
"ix86_binary_operator_ok (MINUS, QImode, operands)"
"sbb{b}\t{%2, %0|%0, %2}"
[(set_attr "type" "alu")
+ (set_attr "use_carry" "1")
(set_attr "pent_pair" "pu")
(set_attr "mode" "QI")])
"ix86_binary_operator_ok (MINUS, HImode, operands)"
"sbb{w}\t{%2, %0|%0, %2}"
[(set_attr "type" "alu")
+ (set_attr "use_carry" "1")
(set_attr "pent_pair" "pu")
(set_attr "mode" "HI")])
"ix86_binary_operator_ok (MINUS, SImode, operands)"
"sbb{l}\t{%2, %0|%0, %2}"
[(set_attr "type" "alu")
+ (set_attr "use_carry" "1")
(set_attr "pent_pair" "pu")
(set_attr "mode" "SI")])
[(set (match_operand:MODEF 0 "register_operand" "")
(minus:MODEF (match_operand:MODEF 1 "register_operand" "")
(match_operand:MODEF 2 "nonimmediate_operand" "")))]
- "TARGET_80387 || (SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)"
+ "(TARGET_80387 && X87_ENABLE_ARITH (<MODE>mode))
+ || (SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)"
"")
\f
;; Multiply instructions
[(set (match_operand:MODEF 0 "register_operand" "")
(mult:MODEF (match_operand:MODEF 1 "register_operand" "")
(match_operand:MODEF 2 "nonimmediate_operand" "")))]
- "TARGET_80387 || (SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)"
+ "(TARGET_80387 && X87_ENABLE_ARITH (<MODE>mode))
+ || (SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)"
"")
;; SSE5 scalar multiply/add instructions are defined in sse.md.
[(set (match_operand:DF 0 "register_operand" "")
(div:DF (match_operand:DF 1 "register_operand" "")
(match_operand:DF 2 "nonimmediate_operand" "")))]
- "TARGET_80387 || (TARGET_SSE2 && TARGET_SSE_MATH)"
+ "(TARGET_80387 && X87_ENABLE_ARITH (DFmode))
+ || (TARGET_SSE2 && TARGET_SSE_MATH)"
"")
(define_expand "divsf3"
[(set (match_operand:SF 0 "register_operand" "")
(div:SF (match_operand:SF 1 "register_operand" "")
(match_operand:SF 2 "nonimmediate_operand" "")))]
- "TARGET_80387 || TARGET_SSE_MATH"
+ "(TARGET_80387 && X87_ENABLE_ARITH (SFmode))
+ || TARGET_SSE_MATH"
{
if (TARGET_SSE_MATH && TARGET_RECIP && optimize_insn_for_speed_p ()
&& flag_finite_math_only && !flag_trapping_math
;; to avoid partial register stalls. Otherwise do things the setcc+movzx
;; way, which can later delete the movzx if only QImode is needed.
-(define_expand "s<code>"
- [(set (match_operand:QI 0 "register_operand" "")
- (int_cond:QI (reg:CC FLAGS_REG) (const_int 0)))]
- ""
- "if (ix86_expand_setcc (<CODE>, operands[0])) DONE; else FAIL;")
-
-(define_expand "s<code>"
- [(set (match_operand:QI 0 "register_operand" "")
- (fp_cond:QI (reg:CC FLAGS_REG) (const_int 0)))]
- "TARGET_80387 || TARGET_SSE"
- "if (ix86_expand_setcc (<CODE>, operands[0])) DONE; else FAIL;")
-
(define_insn "*setcc_1"
[(set (match_operand:QI 0 "nonimmediate_operand" "=qm")
(match_operator:QI 1 "ix86_comparison_operator"
;; Basic conditional jump instructions.
;; We ignore the overflow flag for signed branch instructions.
-;; For all bCOND expanders, also expand the compare or test insn that
-;; generates reg FLAGS_REG. Generate an equality comparison if `beq' or `bne'.
-
-(define_expand "b<code>"
- [(set (pc)
- (if_then_else (int_cond:CC (reg:CC FLAGS_REG)
- (const_int 0))
- (label_ref (match_operand 0 ""))
- (pc)))]
- ""
- "ix86_expand_branch (<CODE>, operands[0]); DONE;")
-
-(define_expand "b<code>"
- [(set (pc)
- (if_then_else (fp_cond:CC (reg:CC FLAGS_REG)
- (const_int 0))
- (label_ref (match_operand 0 ""))
- (pc)))]
- "TARGET_80387 || TARGET_SSE_MATH"
- "ix86_expand_branch (<CODE>, operands[0]); DONE;")
-
(define_insn "*jcc_1"
[(set (pc)
(if_then_else (match_operator 1 "ix86_comparison_operator"
(match_operand:QI 2 "register_operand" "r")))
(const_int 0)])
(label_ref (match_operand 3 "" ""))
- (pc)))]
+ (pc)))
+ (clobber (reg:CC FLAGS_REG))]
"TARGET_64BIT && (TARGET_USE_BT || optimize_function_for_size_p (cfun))"
"#"
"&& 1"
(match_operand:SI 2 "register_operand" "r")
(match_operand:SI 3 "const_int_operand" "n")))])
(label_ref (match_operand 4 "" ""))
- (pc)))]
+ (pc)))
+ (clobber (reg:CC FLAGS_REG))]
"TARGET_64BIT && (TARGET_USE_BT || optimize_function_for_size_p (cfun))
&& (INTVAL (operands[3]) & 0x3f) == 0x3f"
"#"
(match_operand:QI 2 "register_operand" "r")))
(const_int 0)])
(label_ref (match_operand 3 "" ""))
- (pc)))]
+ (pc)))
+ (clobber (reg:CC FLAGS_REG))]
"TARGET_USE_BT || optimize_function_for_size_p (cfun)"
"#"
"&& 1"
(match_operand:SI 2 "register_operand" "r")
(match_operand:SI 3 "const_int_operand" "n")))])
(label_ref (match_operand 4 "" ""))
- (pc)))]
+ (pc)))
+ (clobber (reg:CC FLAGS_REG))]
"(TARGET_USE_BT || optimize_function_for_size_p (cfun))
&& (INTVAL (operands[3]) & 0x1f) == 0x1f"
"#"
(const_int 1))
(const_int 0)])
(label_ref (match_operand 3 "" ""))
- (pc)))]
+ (pc)))
+ (clobber (reg:CC FLAGS_REG))]
"TARGET_USE_BT || optimize_function_for_size_p (cfun)"
"#"
"&& 1"
(const_int 1))
(const_int 0)])
(label_ref (match_operand 4 "" ""))
- (pc)))]
+ (pc)))
+ (clobber (reg:CC FLAGS_REG))]
"(TARGET_USE_BT || optimize_function_for_size_p (cfun))
&& (INTVAL (operands[3]) & 0x1f) == 0x1f"
"#"
}
[(set_attr "type" "call")])
+(define_insn "*call_1_rex64_ms_sysv"
+ [(call (mem:QI (match_operand:DI 0 "call_insn_operand" "rsm"))
+ (match_operand 1 "" ""))
+ (unspec [(const_int 0)] UNSPEC_MS_TO_SYSV_CALL)
+ (clobber (reg:TI XMM6_REG))
+ (clobber (reg:TI XMM7_REG))
+ (clobber (reg:TI XMM8_REG))
+ (clobber (reg:TI XMM9_REG))
+ (clobber (reg:TI XMM10_REG))
+ (clobber (reg:TI XMM11_REG))
+ (clobber (reg:TI XMM12_REG))
+ (clobber (reg:TI XMM13_REG))
+ (clobber (reg:TI XMM14_REG))
+ (clobber (reg:TI XMM15_REG))
+ (clobber (reg:DI SI_REG))
+ (clobber (reg:DI DI_REG))]
+ "!SIBLING_CALL_P (insn) && TARGET_64BIT"
+{
+ if (constant_call_address_operand (operands[0], Pmode))
+ return "call\t%P0";
+ return "call\t%A0";
+}
+ [(set_attr "type" "call")])
+
(define_insn "*call_1_rex64_large"
[(call (mem:QI (match_operand:DI 0 "call_insn_operand" "rm"))
(match_operand 1 "" ""))]
/* In order to give reg-stack an easier job in validating two
coprocessor registers as containing a possible return value,
simply pretend the untyped call returns a complex long double
- value. */
+ value.
+
+ We can't use SSE_REGPARM_MAX here since callee is unprototyped
+ and should have the default ABI. */
ix86_expand_call ((TARGET_FLOAT_RETURNS_IN_80387
? gen_rtx_REG (XCmode, FIRST_FLOAT_REG) : NULL),
operands[0], const0_rtx,
- GEN_INT ((DEFAULT_ABI == SYSV_ABI ? X86_64_SSE_REGPARM_MAX
- : X64_SSE_REGPARM_MAX)
+ GEN_INT ((TARGET_64BIT
+ ? (ix86_abi == SYSV_ABI
+ ? X86_64_SSE_REGPARM_MAX
+ : X64_SSE_REGPARM_MAX)
+ : X86_32_SSE_REGPARM_MAX)
- 1),
NULL, 0);
""
[(set_attr "length" "0")])
+;; Do not schedule instructions accessing memory across this point.
+
+(define_expand "memory_blockage"
+ [(set (match_dup 0)
+ (unspec:BLK [(match_dup 0)] UNSPEC_MEMORY_BLOCKAGE))]
+ ""
+{
+ operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
+ MEM_VOLATILE_P (operands[0]) = 1;
+})
+
+(define_insn "*memory_blockage"
+ [(set (match_operand:BLK 0 "" "")
+ (unspec:BLK [(match_dup 0)] UNSPEC_MEMORY_BLOCKAGE))]
+ ""
+ ""
+ [(set_attr "length" "0")])
+
;; As USE insns aren't meaningful after reload, this is used instead
;; to prevent deleting instructions setting registers for PIC code
(define_insn "prologue_use"
"reload_completed"
"ret"
[(set_attr "length" "1")
+ (set_attr "atom_unit" "jeu")
(set_attr "length_immediate" "0")
(set_attr "modrm" "0")])
"reload_completed"
"rep\;ret"
[(set_attr "length" "1")
+ (set_attr "atom_unit" "jeu")
(set_attr "length_immediate" "0")
(set_attr "prefix_rep" "1")
(set_attr "modrm" "0")])
"reload_completed"
"ret\t%0"
[(set_attr "length" "3")
+ (set_attr "atom_unit" "jeu")
(set_attr "length_immediate" "2")
(set_attr "modrm" "0")])
(set_attr "length_immediate" "0")
(set_attr "modrm" "0")])
-;; Align to 16-byte boundary, max skip in op0. Used to avoid
+;; Pad to 16-byte boundary, max skip in op0. Used to avoid
;; branch prediction penalty for the third jump in a 16-byte
;; block on K8.
-(define_insn "align"
+(define_insn "pad"
[(unspec_volatile [(match_operand 0 "" "")] UNSPECV_ALIGN)]
""
{
-#ifdef ASM_OUTPUT_MAX_SKIP_ALIGN
- ASM_OUTPUT_MAX_SKIP_ALIGN (asm_out_file, 4, (int)INTVAL (operands[0]));
+#ifdef ASM_OUTPUT_MAX_SKIP_PAD
+ ASM_OUTPUT_MAX_SKIP_PAD (asm_out_file, 4, (int)INTVAL (operands[0]));
#else
/* It is tempting to use ASM_OUTPUT_ALIGN here, but we don't want to do that.
The align insn is used to avoid 3 jump instructions in the row to improve
(define_insn "set_rip_rex64"
[(set (match_operand:DI 0 "register_operand" "=r")
- (unspec:DI [(match_operand:DI 1 "" "")] UNSPEC_SET_RIP))]
+ (unspec:DI [(label_ref (match_operand 1 "" ""))] UNSPEC_SET_RIP))]
"TARGET_64BIT"
"lea{q}\t{%l1(%%rip), %0|%0, %l1[rip]}"
[(set_attr "type" "lea")
(define_insn "set_got_offset_rex64"
[(set (match_operand:DI 0 "register_operand" "=r")
- (unspec:DI [(match_operand:DI 1 "" "")] UNSPEC_SET_GOT_OFFSET))]
+ (unspec:DI
+ [(label_ref (match_operand 1 "" ""))]
+ UNSPEC_SET_GOT_OFFSET))]
"TARGET_64BIT"
"movabs{q}\t{$_GLOBAL_OFFSET_TABLE_-%l1, %0|%0, OFFSET FLAT:_GLOBAL_OFFSET_TABLE_-%l1}"
[(set_attr "type" "imov")
(define_expand "ffs_cmove"
[(set (match_dup 2) (const_int -1))
(parallel [(set (reg:CCZ FLAGS_REG)
- (compare:CCZ (match_operand:SI 1 "register_operand" "")
+ (compare:CCZ (match_operand:SI 1 "nonimmediate_operand" "")
(const_int 0)))
- (set (match_operand:SI 0 "nonimmediate_operand" "")
+ (set (match_operand:SI 0 "register_operand" "")
(ctz:SI (match_dup 1)))])
(set (match_dup 0) (if_then_else:SI
(eq (reg:CCZ FLAGS_REG) (const_int 0))
"operands[2] = gen_reg_rtx (SImode);")
(define_insn_and_split "*ffs_no_cmove"
- [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
+ [(set (match_operand:SI 0 "register_operand" "=r")
(ffs:SI (match_operand:SI 1 "nonimmediate_operand" "rm")))
(clobber (match_scratch:SI 2 "=&q"))
(clobber (reg:CC FLAGS_REG))]
(define_expand "ffsdi2"
[(set (match_dup 2) (const_int -1))
(parallel [(set (reg:CCZ FLAGS_REG)
- (compare:CCZ (match_operand:DI 1 "register_operand" "")
+ (compare:CCZ (match_operand:DI 1 "nonimmediate_operand" "")
(const_int 0)))
- (set (match_operand:DI 0 "nonimmediate_operand" "")
+ (set (match_operand:DI 0 "register_operand" "")
(ctz:DI (match_dup 1)))])
(set (match_dup 0) (if_then_else:DI
(eq (reg:CCZ FLAGS_REG) (const_int 0))
[(set_attr "prefix_0f" "1")
(set_attr "mode" "SI")])
-(define_insn "popcountsi2"
- [(set (match_operand:SI 0 "register_operand" "=r")
- (popcount:SI (match_operand:SI 1 "nonimmediate_operand" "rm")))
+(define_insn "popcount<mode>2"
+ [(set (match_operand:SWI248 0 "register_operand" "=r")
+ (popcount:SWI248
+ (match_operand:SWI248 1 "nonimmediate_operand" "rm")))
(clobber (reg:CC FLAGS_REG))]
"TARGET_POPCNT"
- "popcnt{l}\t{%1, %0|%0, %1}"
+{
+#if TARGET_MACHO
+ return "popcnt\t{%1, %0|%0, %1}";
+#else
+ return "popcnt{<imodesuffix>}\t{%1, %0|%0, %1}";
+#endif
+}
[(set_attr "prefix_rep" "1")
(set_attr "type" "bitmanip")
- (set_attr "mode" "SI")])
+ (set_attr "mode" "<MODE>")])
-(define_insn "*popcountsi2_cmp"
+(define_insn "*popcount<mode>2_cmp"
[(set (reg FLAGS_REG)
(compare
- (popcount:SI (match_operand:SI 1 "nonimmediate_operand" "rm"))
+ (popcount:SWI248
+ (match_operand:SWI248 1 "nonimmediate_operand" "rm"))
(const_int 0)))
- (set (match_operand:SI 0 "register_operand" "=r")
- (popcount:SI (match_dup 1)))]
+ (set (match_operand:SWI248 0 "register_operand" "=r")
+ (popcount:SWI248 (match_dup 1)))]
"TARGET_POPCNT && ix86_match_ccmode (insn, CCZmode)"
- "popcnt{l}\t{%1, %0|%0, %1}"
+{
+#if TARGET_MACHO
+ return "popcnt\t{%1, %0|%0, %1}";
+#else
+ return "popcnt{<imodesuffix>}\t{%1, %0|%0, %1}";
+#endif
+}
[(set_attr "prefix_rep" "1")
(set_attr "type" "bitmanip")
- (set_attr "mode" "SI")])
+ (set_attr "mode" "<MODE>")])
(define_insn "*popcountsi2_cmp_zext"
[(set (reg FLAGS_REG)
(set (match_operand:DI 0 "register_operand" "=r")
(zero_extend:DI(popcount:SI (match_dup 1))))]
"TARGET_64BIT && TARGET_POPCNT && ix86_match_ccmode (insn, CCZmode)"
- "popcnt{l}\t{%1, %0|%0, %1}"
+{
+#if TARGET_MACHO
+ return "popcnt\t{%1, %0|%0, %1}";
+#else
+ return "popcnt{<imodesuffix>}\t{%1, %0|%0, %1}";
+#endif
+}
[(set_attr "prefix_rep" "1")
(set_attr "type" "bitmanip")
(set_attr "mode" "SI")])
[(set_attr "prefix_0f" "1")
(set_attr "mode" "DI")])
-(define_insn "popcountdi2"
- [(set (match_operand:DI 0 "register_operand" "=r")
- (popcount:DI (match_operand:DI 1 "nonimmediate_operand" "rm")))
- (clobber (reg:CC FLAGS_REG))]
- "TARGET_64BIT && TARGET_POPCNT"
- "popcnt{q}\t{%1, %0|%0, %1}"
- [(set_attr "prefix_rep" "1")
- (set_attr "type" "bitmanip")
- (set_attr "mode" "DI")])
-
-(define_insn "*popcountdi2_cmp"
- [(set (reg FLAGS_REG)
- (compare
- (popcount:DI (match_operand:DI 1 "nonimmediate_operand" "rm"))
- (const_int 0)))
- (set (match_operand:DI 0 "register_operand" "=r")
- (popcount:DI (match_dup 1)))]
- "TARGET_64BIT && TARGET_POPCNT && ix86_match_ccmode (insn, CCZmode)"
- "popcnt{q}\t{%1, %0|%0, %1}"
- [(set_attr "prefix_rep" "1")
- (set_attr "type" "bitmanip")
- (set_attr "mode" "DI")])
-
(define_expand "clzhi2"
[(parallel
[(set (match_operand:HI 0 "register_operand" "")
[(set_attr "prefix_0f" "1")
(set_attr "mode" "HI")])
-(define_insn "popcounthi2"
- [(set (match_operand:HI 0 "register_operand" "=r")
- (popcount:HI (match_operand:HI 1 "nonimmediate_operand" "rm")))
- (clobber (reg:CC FLAGS_REG))]
- "TARGET_POPCNT"
- "popcnt{w}\t{%1, %0|%0, %1}"
- [(set_attr "prefix_rep" "1")
- (set_attr "type" "bitmanip")
- (set_attr "mode" "HI")])
-
-(define_insn "*popcounthi2_cmp"
- [(set (reg FLAGS_REG)
- (compare
- (popcount:HI (match_operand:HI 1 "nonimmediate_operand" "rm"))
- (const_int 0)))
- (set (match_operand:HI 0 "register_operand" "=r")
- (popcount:HI (match_dup 1)))]
- "TARGET_POPCNT && ix86_match_ccmode (insn, CCZmode)"
- "popcnt{w}\t{%1, %0|%0, %1}"
- [(set_attr "prefix_rep" "1")
- (set_attr "type" "bitmanip")
- (set_attr "mode" "HI")])
-
(define_expand "paritydi2"
[(set (match_operand:DI 0 "register_operand" "")
(parity:DI (match_operand:DI 1 "register_operand" "")))]
(match_operator:MODEF 3 "binary_fp_operator"
[(match_operand:MODEF 1 "nonimmediate_operand" "%0")
(match_operand:MODEF 2 "nonimmediate_operand" "fm")]))]
- "TARGET_80387
+ "TARGET_80387 && X87_ENABLE_ARITH (<MODE>mode)
&& COMMUTATIVE_ARITH_P (operands[3])
&& !(MEM_P (operands[1]) && MEM_P (operands[2]))"
"* return output_387_binary_op (insn, operands);"
"TARGET_SSE_MATH"
"%vrcpss\t{%1, %d0|%d0, %1}"
[(set_attr "type" "sse")
+ (set_attr "atom_sse_attr" "rcp")
(set_attr "prefix" "maybe_vex")
(set_attr "mode" "SF")])
(match_operator:MODEF 3 "binary_fp_operator"
[(match_operand:MODEF 1 "nonimmediate_operand" "0,fm")
(match_operand:MODEF 2 "nonimmediate_operand" "fm,0")]))]
- "TARGET_80387 && !(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
+ "TARGET_80387 && X87_ENABLE_ARITH (<MODE>mode)
+ && !(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
&& !COMMUTATIVE_ARITH_P (operands[3])
&& !(MEM_P (operands[1]) && MEM_P (operands[2]))"
"* return output_387_binary_op (insn, operands);"
[(float:MODEF
(match_operand:X87MODEI12 1 "nonimmediate_operand" "m,?r"))
(match_operand:MODEF 2 "register_operand" "0,0")]))]
- "TARGET_80387 && !(SSE_FLOAT_MODE_P (<MODEF:MODE>mode) && TARGET_SSE_MATH)
+ "TARGET_80387 && X87_ENABLE_FLOAT (<MODEF:MODE>mode, <X87MODEI12:MODE>mode)
+ && !(SSE_FLOAT_MODE_P (<MODEF:MODE>mode) && TARGET_SSE_MATH)
&& (TARGET_USE_<X87MODEI12:MODE>MODE_FIOP || optimize_function_for_size_p (cfun))"
"* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
[(set (attr "type")
[(match_operand:MODEF 1 "register_operand" "0,0")
(float:MODEF
(match_operand:X87MODEI12 2 "nonimmediate_operand" "m,?r"))]))]
- "TARGET_80387 && !(SSE_FLOAT_MODE_P (<MODEF:MODE>mode) && TARGET_SSE_MATH)
+ "TARGET_80387 && X87_ENABLE_FLOAT (<MODEF:MODE>mode, <X87MODEI12:MODE>mode)
+ && !(SSE_FLOAT_MODE_P (<MODEF:MODE>mode) && TARGET_SSE_MATH)
&& (TARGET_USE_<X87MODEI12:MODE>MODE_FIOP || optimize_function_for_size_p (cfun))"
"* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
[(set (attr "type")
[(float_extend:DF
(match_operand:SF 1 "nonimmediate_operand" "fm,0"))
(match_operand:DF 2 "register_operand" "0,f")]))]
- "TARGET_80387 && !(TARGET_SSE2 && TARGET_SSE_MATH)
+ "TARGET_80387 && X87_ENABLE_ARITH (DFmode)
+ && !(TARGET_SSE2 && TARGET_SSE_MATH)
&& !(MEM_P (operands[1]) && MEM_P (operands[2]))"
"* return output_387_binary_op (insn, operands);"
[(set (attr "type")
[(match_operand:DF 1 "register_operand" "0,f")
(float_extend:DF
(match_operand:SF 2 "nonimmediate_operand" "fm,0"))]))]
- "TARGET_80387 && !(TARGET_SSE2 && TARGET_SSE_MATH)"
+ "TARGET_80387 && X87_ENABLE_ARITH (DFmode)
+ && !(TARGET_SSE2 && TARGET_SSE_MATH)"
"* return output_387_binary_op (insn, operands);"
[(set (attr "type")
(cond [(match_operand:DF 3 "mult_operator" "")
(match_operand:SF 1 "register_operand" "0,f"))
(float_extend:DF
(match_operand:SF 2 "nonimmediate_operand" "fm,0"))]))]
- "TARGET_80387 && !(TARGET_SSE2 && TARGET_SSE_MATH)"
+ "TARGET_80387 && X87_ENABLE_ARITH (DFmode)
+ && !(TARGET_SSE2 && TARGET_SSE_MATH)"
"* return output_387_binary_op (insn, operands);"
[(set (attr "type")
(cond [(match_operand:DF 3 "mult_operator" "")
[(float (match_operand:X87MODEI12 1 "register_operand" ""))
(match_operand 2 "register_operand" "")]))]
"reload_completed
- && X87_FLOAT_MODE_P (GET_MODE (operands[0]))"
+ && X87_FLOAT_MODE_P (GET_MODE (operands[0]))
+ && X87_ENABLE_FLOAT (GET_MODE (operands[0]), GET_MODE (operands[1]))"
[(const_int 0)]
{
operands[4] = ix86_force_to_memory (GET_MODE (operands[1]), operands[1]);
[(match_operand 1 "register_operand" "")
(float (match_operand:X87MODEI12 2 "register_operand" ""))]))]
"reload_completed
- && X87_FLOAT_MODE_P (GET_MODE (operands[0]))"
+ && X87_FLOAT_MODE_P (GET_MODE (operands[0]))
+ && X87_ENABLE_FLOAT (GET_MODE (operands[0]), GET_MODE (operands[2]))"
[(const_int 0)]
{
operands[4] = ix86_force_to_memory (GET_MODE (operands[2]), operands[2]);
"TARGET_SSE_MATH"
"%vrsqrtss\t{%1, %d0|%d0, %1}"
[(set_attr "type" "sse")
+ (set_attr "atom_sse_attr" "rcp")
(set_attr "prefix" "maybe_vex")
(set_attr "mode" "SF")])
"SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH"
"%vsqrts<ssemodefsuffix>\t{%1, %d0|%d0, %1}"
[(set_attr "type" "sse")
+ (set_attr "atom_sse_attr" "sqrt")
(set_attr "prefix" "maybe_vex")
(set_attr "mode" "<MODE>")
(set_attr "athlon_decode" "*")
[(set (match_operand:MODEF 0 "register_operand" "")
(sqrt:MODEF
(match_operand:MODEF 1 "nonimmediate_operand" "")))]
- "TARGET_USE_FANCY_MATH_387
+ "(TARGET_USE_FANCY_MATH_387 && X87_ENABLE_ARITH (<MODE>mode))
|| (SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)"
{
if (<MODE>mode == SFmode
(set_attr "unit" "i387")
(set_attr "mode" "<MODE>")])
+(define_insn_and_split "fxam<mode>2_i387_with_temp"
+ [(set (match_operand:HI 0 "register_operand" "")
+ (unspec:HI
+ [(match_operand:MODEF 1 "memory_operand" "")]
+ UNSPEC_FXAM_MEM))]
+ "TARGET_USE_FANCY_MATH_387
+ && !(reload_completed || reload_in_progress)"
+ "#"
+ "&& 1"
+ [(set (match_dup 2)(match_dup 1))
+ (set (match_dup 0)
+ (unspec:HI [(match_dup 2)] UNSPEC_FXAM))]
+{
+ operands[2] = gen_reg_rtx (<MODE>mode);
+
+ MEM_VOLATILE_P (operands[1]) = 1;
+}
+ [(set_attr "type" "multi")
+ (set_attr "unit" "i387")
+ (set_attr "mode" "<MODE>")])
+
+(define_expand "isinfxf2"
+ [(use (match_operand:SI 0 "register_operand" ""))
+ (use (match_operand:XF 1 "register_operand" ""))]
+ "TARGET_USE_FANCY_MATH_387
+ && TARGET_C99_FUNCTIONS"
+{
+ rtx mask = GEN_INT (0x45);
+ rtx val = GEN_INT (0x05);
+
+ rtx cond;
+
+ rtx scratch = gen_reg_rtx (HImode);
+ rtx res = gen_reg_rtx (QImode);
+
+ emit_insn (gen_fxamxf2_i387 (scratch, operands[1]));
+
+ emit_insn (gen_andqi_ext_0 (scratch, scratch, mask));
+ emit_insn (gen_cmpqi_ext_3 (scratch, val));
+ cond = gen_rtx_fmt_ee (EQ, QImode,
+ gen_rtx_REG (CCmode, FLAGS_REG),
+ const0_rtx);
+ emit_insn (gen_rtx_SET (VOIDmode, res, cond));
+ emit_insn (gen_zero_extendqisi2 (operands[0], res));
+ DONE;
+})
+
(define_expand "isinf<mode>2"
[(use (match_operand:SI 0 "register_operand" ""))
- (use (match_operand:X87MODEF 1 "register_operand" ""))]
+ (use (match_operand:MODEF 1 "nonimmediate_operand" ""))]
"TARGET_USE_FANCY_MATH_387
&& TARGET_C99_FUNCTIONS
&& !(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)"
rtx scratch = gen_reg_rtx (HImode);
rtx res = gen_reg_rtx (QImode);
- emit_insn (gen_fxam<mode>2_i387 (scratch, operands[1]));
+ /* Remove excess precision by forcing value through memory. */
+ if (memory_operand (operands[1], VOIDmode))
+ emit_insn (gen_fxam<mode>2_i387_with_temp (scratch, operands[1]));
+ else
+ {
+ enum ix86_stack_slot slot = (virtuals_instantiated
+ ? SLOT_TEMP
+ : SLOT_VIRTUAL);
+ rtx temp = assign_386_stack_local (<MODE>mode, slot);
+
+ emit_move_insn (temp, operands[1]);
+ emit_insn (gen_fxam<mode>2_i387_with_temp (scratch, temp));
+ }
+
emit_insn (gen_andqi_ext_0 (scratch, scratch, mask));
emit_insn (gen_cmpqi_ext_3 (scratch, val));
cond = gen_rtx_fmt_ee (EQ, QImode,
; Since we don't have the proper number of operands for an alu insn,
; fill in all the blanks.
[(set_attr "type" "alu")
+ (set_attr "use_carry" "1")
(set_attr "pent_pair" "pu")
(set_attr "memory" "none")
(set_attr "imm_disp" "false")
""
"sbb{q}\t%0, %0"
[(set_attr "type" "alu")
+ (set_attr "use_carry" "1")
(set_attr "pent_pair" "pu")
(set_attr "memory" "none")
(set_attr "imm_disp" "false")
; Since we don't have the proper number of operands for an alu insn,
; fill in all the blanks.
[(set_attr "type" "alu")
+ (set_attr "use_carry" "1")
(set_attr "pent_pair" "pu")
(set_attr "memory" "none")
(set_attr "imm_disp" "false")
""
"sbb{l}\t%0, %0"
[(set_attr "type" "alu")
+ (set_attr "use_carry" "1")
(set_attr "pent_pair" "pu")
(set_attr "memory" "none")
(set_attr "imm_disp" "false")
}
}
[(set (attr "type")
- (cond [(eq_attr "alternative" "0")
+ (cond [(and (eq_attr "alternative" "0")
+ (eq (symbol_ref "TARGET_OPT_AGU") (const_int 0)))
(const_string "alu")
(match_operand:SI 2 "const0_operand" "")
(const_string "imov")
}
}
[(set (attr "type")
- (cond [(eq_attr "alternative" "0")
+ (cond [(and (eq_attr "alternative" "0")
+ (eq (symbol_ref "TARGET_OPT_AGU") (const_int 0)))
(const_string "alu")
(match_operand:DI 2 "const0_operand" "")
(const_string "imov")
(set_attr "mode" "DI")])
(define_insn "allocate_stack_worker_32"
- [(set (match_operand:SI 0 "register_operand" "+a")
- (unspec_volatile:SI [(match_dup 0)] UNSPECV_STACK_PROBE))
- (set (reg:SI SP_REG) (minus:SI (reg:SI SP_REG) (match_dup 0)))
+ [(set (match_operand:SI 0 "register_operand" "=a")
+ (unspec_volatile:SI [(match_operand:SI 1 "register_operand" "0")]
+ UNSPECV_STACK_PROBE))
+ (set (reg:SI SP_REG) (minus:SI (reg:SI SP_REG) (match_dup 1)))
(clobber (reg:CC FLAGS_REG))]
"!TARGET_64BIT && TARGET_STACK_PROBE"
"call\t___chkstk"
(set_attr "length" "5")])
(define_insn "allocate_stack_worker_64"
- [(set (match_operand:DI 0 "register_operand" "+a")
- (unspec_volatile:DI [(match_dup 0)] UNSPECV_STACK_PROBE))
- (set (reg:DI SP_REG) (minus:DI (reg:DI SP_REG) (match_dup 0)))
+ [(set (match_operand:DI 0 "register_operand" "=a")
+ (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "0")]
+ UNSPECV_STACK_PROBE))
+ (set (reg:DI SP_REG) (minus:DI (reg:DI SP_REG) (match_dup 1)))
(clobber (reg:DI R10_REG))
(clobber (reg:DI R11_REG))
(clobber (reg:CC FLAGS_REG))]
{
x = copy_to_mode_reg (Pmode, operands[1]);
if (TARGET_64BIT)
- x = gen_allocate_stack_worker_64 (x);
+ x = gen_allocate_stack_worker_64 (x, x);
else
- x = gen_allocate_stack_worker_32 (x);
+ x = gen_allocate_stack_worker_32 (x, x);
emit_insn (x);
}
[(match_dup 0)
(match_operand:SI 1 "memory_operand" "")]))
(clobber (reg:CC FLAGS_REG))])]
- "optimize_insn_for_speed_p ()"
+ "optimize_insn_for_speed_p () && ! TARGET_READ_MODIFY"
[(set (match_dup 2) (match_dup 1))
(parallel [(set (match_dup 0)
(match_op_dup 3 [(match_dup 0) (match_dup 2)]))
(clobber (reg:CC FLAGS_REG))])]
"")
+;; Prefer Load+RegOp to Mov+MemOp. Watch out for cases when the memory address
+;; refers to the destination of the load!
+
+(define_peephole2
+ [(set (match_operand:SI 0 "register_operand" "")
+ (match_operand:SI 1 "register_operand" ""))
+ (parallel [(set (match_dup 0)
+ (match_operator:SI 3 "commutative_operator"
+ [(match_dup 0)
+ (match_operand:SI 2 "memory_operand" "")]))
+ (clobber (reg:CC FLAGS_REG))])]
+ "REGNO (operands[0]) != REGNO (operands[1])
+ && GENERAL_REGNO_P (REGNO (operands[0]))
+ && GENERAL_REGNO_P (REGNO (operands[1]))"
+ [(set (match_dup 0) (match_dup 4))
+ (parallel [(set (match_dup 0)
+ (match_op_dup 3 [(match_dup 0) (match_dup 1)]))
+ (clobber (reg:CC FLAGS_REG))])]
+ "operands[4] = replace_rtx (operands[2], operands[0], operands[1]);")
+
+(define_peephole2
+ [(set (match_operand 0 "register_operand" "")
+ (match_operand 1 "register_operand" ""))
+ (set (match_dup 0)
+ (match_operator 3 "commutative_operator"
+ [(match_dup 0)
+ (match_operand 2 "memory_operand" "")]))]
+ "REGNO (operands[0]) != REGNO (operands[1])
+ && ((MMX_REG_P (operands[0]) && MMX_REG_P (operands[1]))
+ || (SSE_REG_P (operands[0]) && SSE_REG_P (operands[1])))"
+ [(set (match_dup 0) (match_dup 2))
+ (set (match_dup 0)
+ (match_op_dup 3 [(match_dup 0) (match_dup 1)]))]
+ "")
+
; Don't do logical operations with memory outputs
;
; These two don't make sense for PPro/PII -- we're expanding a 4-uop
(match_operator 1 "compare_operator"
[(match_operand 2 "register_operand" "")
(match_operand 3 "const_int_operand" "")]))]
- "(((!TARGET_FUSE_CMP_AND_BRANCH || optimize_size)
+ "(((!TARGET_FUSE_CMP_AND_BRANCH || optimize_insn_for_size_p ())
&& incdec_operand (operands[3], GET_MODE (operands[3])))
|| (!TARGET_FUSE_CMP_AND_BRANCH
&& INTVAL (operands[3]) == 128))
}
[(set_attr "type" "callv")])
+(define_insn "*call_value_0_rex64_ms_sysv"
+ [(set (match_operand 0 "" "")
+ (call (mem:QI (match_operand:DI 1 "constant_call_address_operand" ""))
+ (match_operand:DI 2 "const_int_operand" "")))
+ (unspec [(const_int 0)] UNSPEC_MS_TO_SYSV_CALL)
+ (clobber (reg:TI XMM6_REG))
+ (clobber (reg:TI XMM7_REG))
+ (clobber (reg:TI XMM8_REG))
+ (clobber (reg:TI XMM9_REG))
+ (clobber (reg:TI XMM10_REG))
+ (clobber (reg:TI XMM11_REG))
+ (clobber (reg:TI XMM12_REG))
+ (clobber (reg:TI XMM13_REG))
+ (clobber (reg:TI XMM14_REG))
+ (clobber (reg:TI XMM15_REG))
+ (clobber (reg:DI SI_REG))
+ (clobber (reg:DI DI_REG))]
+ "!SIBLING_CALL_P (insn) && TARGET_64BIT"
+{
+ if (SIBLING_CALL_P (insn))
+ return "jmp\t%P1";
+ else
+ return "call\t%P1";
+}
+ [(set_attr "type" "callv")])
+
(define_insn "*call_value_1"
[(set (match_operand 0 "" "")
(call (mem:QI (match_operand:SI 1 "call_insn_operand" "rsm"))
}
[(set_attr "type" "callv")])
+(define_insn "*call_value_1_rex64_ms_sysv"
+ [(set (match_operand 0 "" "")
+ (call (mem:QI (match_operand:DI 1 "call_insn_operand" "rsm"))
+ (match_operand:DI 2 "" "")))
+ (unspec [(const_int 0)] UNSPEC_MS_TO_SYSV_CALL)
+ (clobber (reg:TI 27))
+ (clobber (reg:TI 28))
+ (clobber (reg:TI 45))
+ (clobber (reg:TI 46))
+ (clobber (reg:TI 47))
+ (clobber (reg:TI 48))
+ (clobber (reg:TI 49))
+ (clobber (reg:TI 50))
+ (clobber (reg:TI 51))
+ (clobber (reg:TI 52))
+ (clobber (reg:DI SI_REG))
+ (clobber (reg:DI DI_REG))]
+ "!SIBLING_CALL_P (insn) && TARGET_64BIT"
+{
+ if (constant_call_address_operand (operands[1], Pmode))
+ return "call\t%P1";
+ return "call\t%A1";
+}
+ [(set_attr "type" "callv")])
+
(define_insn "*call_value_1_rex64_large"
[(set (match_operand 0 "" "")
(call (mem:QI (match_operand:DI 1 "call_insn_operand" "rm"))
return patterns[locality];
}
[(set_attr "type" "sse")
+ (set_attr "atom_sse_attr" "prefetch")
(set_attr "memory" "none")])
(define_insn "*prefetch_sse_rex"
return patterns[locality];
}
[(set_attr "type" "sse")
+ (set_attr "atom_sse_attr" "prefetch")
(set_attr "memory" "none")])
(define_insn "*prefetch_3dnow"
""
{
rtx flags = gen_rtx_REG (CCZmode, FLAGS_REG);
- ix86_compare_op0 = operands[0];
- ix86_compare_op1 = operands[1];
- ix86_compare_emitted = flags;
#ifdef TARGET_THREAD_SSP_OFFSET
if (TARGET_64BIT)
else
emit_insn (gen_stack_protect_test_si (flags, operands[0], operands[1]));
#endif
- emit_jump_insn (gen_beq (operands[2]));
+
+ emit_jump_insn (gen_cbranchcc4 (gen_rtx_EQ (VOIDmode, flags, const0_rtx),
+ flags, const0_rtx, operands[2]));
DONE;
})
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