/* Definitions of target machine for GNU compiler for IA-32.
- Copyright (C) 1988, 92, 94-98, 1999 Free Software Foundation, Inc.
+ Copyright (C) 1988, 1992, 1994, 1995, 1996, 1997, 1998, 1999, 2000
+ Free Software Foundation, Inc.
This file is part of GNU CC.
ADDR_BEG, ADDR_END, PRINT_IREG, PRINT_SCALE, PRINT_B_I_S, and many
that start with ASM_ or end in ASM_OP. */
-/* Names to predefine in the preprocessor for this target machine. */
-
-#define I386 1
-
/* Stubs for half-pic support if not OSF/1 reference platform. */
#ifndef HALF_PIC_P
int mult_bit; /* cost of multiply per each bit set */
int divide; /* cost of a divide/mod */
int large_insn; /* insns larger than this cost more */
+ int move_ratio; /* The threshold of number of scalar memory-to-memory
+ move insns. */
int movzbl_load; /* cost of loading using movzbl */
int int_load[3]; /* cost of loading integer registers
in QImode, HImode and SImode relative
#define MASK_NO_FANCY_MATH_387 0x00000040 /* Disable sin, cos, sqrt */
#define MASK_OMIT_LEAF_FRAME_POINTER 0x080 /* omit leaf frame pointers */
#define MASK_STACK_PROBE 0x00000100 /* Enable stack probing */
+#define MASK_NO_ALIGN_STROPS 0x00001000 /* Enable aligning of string ops. */
+#define MASK_INLINE_ALL_STROPS 0x00002000 /* Inline stringops in all cases */
+#define MASK_NO_PUSH_ARGS 0x00004000 /* Use push instructions */
+#define MASK_ACCUMULATE_OUTGOING_ARGS 0x00008000/* Accumulate outgoing args */
/* Temporary codegen switches */
#define MASK_INTEL_SYNTAX 0x00000200
faster code on the pentium. */
#define TARGET_ALIGN_DOUBLE (target_flags & MASK_ALIGN_DOUBLE)
+/* Use push instructions to save outgoing args. */
+#define TARGET_PUSH_ARGS (!(target_flags & MASK_NO_PUSH_ARGS))
+
+/* Accumulate stack adjustments to prologue/epilogue. */
+#define TARGET_ACCUMULATE_OUTGOING_ARGS \
+ (target_flags & MASK_ACCUMULATE_OUTGOING_ARGS)
+
/* Put uninitialized locals into bss, not data.
Meaningful only on svr3. */
#define TARGET_SVR3_SHLIB (target_flags & MASK_SVR3_SHLIB)
#define TARGET_PENTIUM (ix86_cpu == PROCESSOR_PENTIUM)
#define TARGET_PENTIUMPRO (ix86_cpu == PROCESSOR_PENTIUMPRO)
#define TARGET_K6 (ix86_cpu == PROCESSOR_K6)
+#define TARGET_ATHLON (ix86_cpu == PROCESSOR_ATHLON)
#define CPUMASK (1 << ix86_cpu)
extern const int x86_use_leave, x86_push_memory, x86_zero_extend_with_and;
extern const int x86_use_loop, x86_use_fiop, x86_use_mov0;
extern const int x86_use_cltd, x86_read_modify_write;
extern const int x86_read_modify, x86_split_long_moves;
+extern const int x86_promote_QImode, x86_single_stringop;
+extern const int x86_himode_math, x86_qimode_math, x86_promote_qi_regs;
+extern const int x86_promote_hi_regs;
#define TARGET_USE_LEAVE (x86_use_leave & CPUMASK)
#define TARGET_PUSH_MEMORY (x86_push_memory & CPUMASK)
#define TARGET_SPLIT_LONG_MOVES (x86_split_long_moves & CPUMASK)
#define TARGET_READ_MODIFY_WRITE (x86_read_modify_write & CPUMASK)
#define TARGET_READ_MODIFY (x86_read_modify & CPUMASK)
+#define TARGET_PROMOTE_QImode (x86_promote_QImode & CPUMASK)
+#define TARGET_SINGLE_STRINGOP (x86_single_stringop & CPUMASK)
+#define TARGET_QIMODE_MATH (x86_qimode_math & CPUMASK)
+#define TARGET_HIMODE_MATH (x86_himode_math & CPUMASK)
+#define TARGET_PROMOTE_QI_REGS (x86_promote_qi_regs & CPUMASK)
+#define TARGET_PROMOTE_HI_REGS (x86_promote_hi_regs & CPUMASK)
#define TARGET_STACK_PROBE (target_flags & MASK_STACK_PROBE)
+#define TARGET_ALIGN_STRINGOPS (!(target_flags & MASK_NO_ALIGN_STROPS))
+#define TARGET_INLINE_ALL_STRINGOPS (target_flags & MASK_INLINE_ALL_STROPS)
+
#define ASSEMBLER_DIALECT ((target_flags & MASK_INTEL_SYNTAX) != 0)
#define TARGET_SWITCHES \
{ "intel-syntax", MASK_INTEL_SYNTAX, \
"Emit Intel syntax assembler opcodes" }, \
{ "no-intel-syntax", -MASK_INTEL_SYNTAX, "" }, \
+ { "align-stringops", -MASK_NO_ALIGN_STROPS, \
+ "Align destination of the string operations" }, \
+ { "no-align-stringops", MASK_NO_ALIGN_STROPS, \
+ "Do not align destination of the string operations" }, \
+ { "inline-all-stringops", MASK_INLINE_ALL_STROPS, \
+ "Inline all known string operations" }, \
+ { "no-inline-all-stringops", -MASK_INLINE_ALL_STROPS, \
+ "Do not inline all known string operations" }, \
+ { "push-args", -MASK_NO_PUSH_ARGS, \
+ "Use push instructions to save outgoing arguments" }, \
+ { "no-push-args", MASK_NO_PUSH_ARGS, \
+ "Do not use push instructions to save outgoing arguments" }, \
+ { "accumulate-outgoing-args", MASK_ACCUMULATE_OUTGOING_ARGS, \
+ "Use push instructions to save outgoing arguments" }, \
+ { "no-accumulate-outgoing-args",-MASK_ACCUMULATE_OUTGOING_ARGS, \
+ "Do not use push instructions to save outgoing arguments" }, \
SUBTARGET_SWITCHES \
{ "", TARGET_DEFAULT, 0 }}
PROCESSOR_PENTIUM,
PROCESSOR_PENTIUMPRO,
PROCESSOR_K6,
+ PROCESSOR_ATHLON,
PROCESSOR_max
};
#if TARGET_CPU_DEFAULT == 4
#define CPP_CPU_DEFAULT_SPEC "-D__tune_k6__"
#endif
+#if TARGET_CPU_DEFAULT == 5
+#define CPP_CPU_DEFAULT_SPEC "-D__tune_athlon__"
+#endif
#ifndef CPP_CPU_DEFAULT_SPEC
#define CPP_CPU_DEFAULT_SPEC "-D__tune_i386__"
#endif
%{march=pentiumpro|march=i686:-D__pentiumpro -D__pentiumpro__ \
%{!mcpu*:-D__tune_pentiumpro__ }}\
%{march=k6:-D__k6 -D__k6__ %{!mcpu*:-D__tune_k6__ }}\
+%{march=athlon:-D__athlon -D__athlon__ %{!mcpu*:-D__tune_athlon__ }}\
%{m386|mcpu=i386:-D__tune_i386__ }\
%{m486|mcpu=i486:-D__tune_i486__ }\
%{mpentium|mcpu=pentium|mcpu=i586:-D__tune_pentium__ }\
%{mpentiumpro|mcpu=pentiumpro|mcpu=i686:-D__tune_pentiumpro__ }\
%{mcpu=k6:-D__tune_k6__ }\
+%{mcpu=athlon:-D__tune_athlon__ }\
%{!march*:%{!mcpu*:%{!m386:%{!m486:%{!mpentium*:%(cpp_cpu_default)}}}}}"
#endif
/* Minimum size in bits of the largest boundary to which any
and all fundamental data types supported by the hardware
might need to be aligned. No data type wants to be aligned
- rounder than this. The i386 supports 64-bit floating point
- quantities, but these can be aligned on any 32-bit boundary.
- The published ABIs say that doubles should be aligned on word
- boundaries, but the Pentium gets better performance with them
- aligned on 64 bit boundaries. */
-#define BIGGEST_ALIGNMENT (TARGET_ALIGN_DOUBLE ? 64 : 32)
+ rounder than this.
+
+ Pentium+ preferrs DFmode values to be alignmed to 64 bit boundary
+ and Pentium Pro XFmode values at 128 bit boundaries. */
+
+#define BIGGEST_ALIGNMENT 128
+
+/* The published ABIs say that doubles should be aligned on word
+ boundaries, so lower the aligment for structure fields unless
+ -malign-double is set. */
+/* BIGGEST_FIELD_ALIGNMENT is also used in libobjc, where it must be
+ constant. Use the smaller value in that context. */
+#ifndef IN_TARGET_LIBS
+#define BIGGEST_FIELD_ALIGNMENT (TARGET_ALIGN_DOUBLE ? 64 : 32)
+#else
+#define BIGGEST_FIELD_ALIGNMENT 32
+#endif
/* If defined, a C expression to compute the alignment given to a
constant that is being placed in memory. CONSTANT is the constant
eliminated during reloading in favor of either the stack or frame
pointer. */
-#define FIRST_PSEUDO_REGISTER 19
+#define FIRST_PSEUDO_REGISTER 21
+
+/* Number of hardware registers that go into the DWARF-2 unwind info.
+ If not defined, equals FIRST_PSEUDO_REGISTER. */
+
+#define DWARF_FRAME_REGISTERS 17
/* 1 for registers that have pervasive standard uses
and are not available for the register allocator.
On the 80386, the stack pointer is such, as is the arg pointer. */
#define FIXED_REGISTERS \
-/*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7,arg,flags,fpsr*/ \
-{ 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0 }
+/*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7,arg,flags,fpsr, dir*/ \
+{ 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, \
+/*frame */ \
+ 1}
/* 1 for registers not available across function calls.
These must include the FIXED_REGISTERS and also any
Aside from that, you can include as many other registers as you like. */
#define CALL_USED_REGISTERS \
-/*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7,arg,flags,fpsr*/ \
-{ 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 }
+/*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7,arg,flags,fpsr, dir*/ \
+{ 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
+/*frame */ \
+ 1}
/* Order in which to allocate registers. Each register must be
listed once, even those in FIXED_REGISTERS. List frame pointer
generated by allocating edx first, so restore the 'natural' order of things. */
#define REG_ALLOC_ORDER \
-/*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7,arg,cc,fpsr*/ \
-{ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16,17, 18 }
+/*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7,arg,cc,fpsr, dir*/ \
+{ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16,17, 18, 19, \
+/*frame */ \
+ 20}
/* A C statement (sans semicolon) to choose the order in which to
allocate hard registers for pseudo-registers local to a basic
#define STACK_POINTER_REGNUM 7
/* Base register for access to local variables of the function. */
-#define FRAME_POINTER_REGNUM 6
+#define HARD_FRAME_POINTER_REGNUM 6
+
+/* Base register for access to local variables of the function. */
+#define FRAME_POINTER_REGNUM 20
/* First floating point reg */
#define FIRST_FLOAT_REG 8
#define FLAGS_REG 17
#define FPSR_REG 18
+#define DIRFLAG_REG 19
/* Value should be nonzero if functions must have frame pointers.
Zero means the frame pointer need not be set up (and parms
AREG, DREG, CREG, BREG, SIREG, DIREG,
AD_REGS, /* %eax/%edx for DImode */
Q_REGS, /* %eax %ebx %ecx %edx */
- NON_Q_REGS, /* %esi %edi %ebp %esi */
+ NON_Q_REGS, /* %esi %edi %ebp %esp */
INDEX_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp */
GENERAL_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp */
FP_TOP_REG, FP_SECOND_REG, /* %st(0) %st(1) */
{0x10}, {0x20}, /* SIREG, DIREG */ \
{0x3}, /* AD_REGS */ \
{0xf}, /* Q_REGS */ \
- {0xf0}, /* NON_Q_REGS */ \
+{0x1100f0}, /* NON_Q_REGS */ \
{0x7f}, /* INDEX_REGS */ \
- {0x100ff}, /* GENERAL_REGS */ \
+{0x1100ff}, /* GENERAL_REGS */ \
{0x0100}, {0x0200}, /* FP_TOP_REG, FP_SECOND_REG */ \
{0xff00}, /* FLOAT_REGS */ \
- {0x1ffff}, /* FLOAT_INT_REGS */ \
- {0x7ffff} \
+{0x11ffff}, /* FLOAT_INT_REGS */ \
+{0x17ffff} \
}
/* The same information, inverted:
#define PREFERRED_RELOAD_CLASS(X,CLASS) \
(GET_CODE (X) == CONST_DOUBLE && GET_MODE (X) != VOIDmode \
? (standard_80387_constant_p (X) \
- ? reg_class_subset_p (CLASS, FLOAT_REGS) ? CLASS : FLOAT_REGS \
- : NO_REGS) \
+ ? CLASS \
+ : (reg_class_subset_p (CLASS, FLOAT_REGS) \
+ ? NO_REGS \
+ : reg_class_subset_p (CLASS, GENERAL_REGS) ? CLASS : GENERAL_REGS)) \
: GET_MODE (X) == QImode && ! reg_class_subset_p (CLASS, Q_REGS) ? Q_REGS \
- : ((CLASS) == ALL_REGS \
- && GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT) ? GENERAL_REGS \
: (CLASS))
/* If we are copying between general and FP registers, we need a memory
do { \
(CLOBBERS) = tree_cons (NULL_TREE, build_string (5, "flags"), (CLOBBERS));\
(CLOBBERS) = tree_cons (NULL_TREE, build_string (4, "fpsr"), (CLOBBERS)); \
+ (CLOBBERS) = tree_cons (NULL_TREE, build_string (7, "dirflag"), (CLOBBERS)); \
} while (0)
\f
/* Stack layout; function entry, exit and calling. */
#define PUSH_ROUNDING(BYTES) (((BYTES) + 1) & (-2))
+/* If defined, the maximum amount of space required for outgoing arguments will
+ be computed and placed into the variable
+ `current_function_outgoing_args_size'. No space will be pushed onto the
+ stack for each call; instead, the function prologue should increase the stack
+ frame size by this amount. */
+
+#define ACCUMULATE_OUTGOING_ARGS TARGET_ACCUMULATE_OUTGOING_ARGS
+
+/* If defined, a C expression whose value is nonzero when we want to use PUSH
+ instructions to pass outgoing arguments. */
+
+#define PUSH_ARGS (TARGET_PUSH_ARGS && !ACCUMULATE_OUTGOING_ARGS)
+
/* Offset of first parameter from the argument pointer register value. */
#define FIRST_PARM_OFFSET(FNDECL) 0
#define APPLY_RESULT_SIZE (8+108)
/* 1 if N is a possible register number for function argument passing. */
-#define FUNCTION_ARG_REGNO_P(N) ((N) >= 0 && (N) < REGPARM_MAX)
+#define FUNCTION_ARG_REGNO_P(N) ((N) < REGPARM_MAX)
/* Define a data type for recording info about an argument list
during the scan of that argument list. This data type should
#define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) 0
+/* If PIC, we cannot optimize sibling calls to global functions
+ because the PLT requires %ebx live. */
+#define FUNCTION_OK_FOR_SIBCALL(DECL) \
+ (DECL && (! flag_pic || ! TREE_PUBLIC (DECL)))
+
/* This macro is invoked just before the start of a function.
It is used here to output code for -fpic that will load the
return address into %ebx. */
Note that function `__bb_trace_ret' must not change the
machine state, especially the flag register. To grant
this, you must output code to save and restore registers
- either in this macro or in the macros MACHINE_STATE_SAVE_RET
- and MACHINE_STATE_RESTORE_RET. The last two macros will be
+ either in this macro or in the macros MACHINE_STATE_SAVE
+ and MACHINE_STATE_RESTORE. The last two macros will be
used in the function `__bb_trace_ret', so you must make
sure that the function prologue does not change any
- register prior to saving it with MACHINE_STATE_SAVE_RET.
+ register prior to saving it with MACHINE_STATE_SAVE.
else if profiling_block_flag != 0:
On the i386 the initialization code at the begin of
function `__bb_trace_func' contains a `sub' instruction
therefore we handle save and restore of the flag register
- in the BLOCK_PROFILER macro. */
+ in the BLOCK_PROFILER macro.
+
+ Note that ebx, esi, and edi are callee-save, so we don't have to
+ preserve them explicitly. */
#define MACHINE_STATE_SAVE(ID) \
do { \
register int eax_ __asm__("eax"); \
register int ecx_ __asm__("ecx"); \
register int edx_ __asm__("edx"); \
- register int esi_ __asm__("esi"); \
- __asm__ __volatile__ ( \
- "push{l} %0\n\t" \
- "push{l} %1\n\t" \
- "push{l} %2\n\t" \
- "push{l} %3" \
- : : "r"(eax_), "r"(ecx_), "r"(edx_), "r"(esi_)); \
+ __asm__ __volatile__ ("\
+push{l} %0\n\t\
+push{l} %1\n\t\
+push{l} %2" \
+ : : "r"(eax_), "r"(ecx_), "r"(edx_)); \
} while (0);
#define MACHINE_STATE_RESTORE(ID) \
register int eax_ __asm__("eax"); \
register int ecx_ __asm__("ecx"); \
register int edx_ __asm__("edx"); \
- register int esi_ __asm__("esi"); \
- __asm__ __volatile__ ( \
- "pop{l} %3\n\t" \
- "pop{l} %2\n\t" \
- "pop{l} %1\n\t" \
- "pop{l} %0" \
- : "=r"(eax_), "=r"(ecx_), "=r"(edx_), "=r"(esi_)); \
+ __asm__ __volatile__ ("\
+pop{l} %2\n\t\
+pop{l} %1\n\t\
+pop{l} %0" \
+ : "=r"(eax_), "=r"(ecx_), "=r"(edx_)); \
} while (0);
/* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
followed by "to". Eliminations of the same "from" register are listed
in order of preference.
- We have two registers that can be eliminated on the i386. First, the
- frame pointer register can often be eliminated in favor of the stack
- pointer register. Secondly, the argument pointer register can always be
- eliminated; it is replaced with either the stack or frame pointer. */
-
-#define ELIMINABLE_REGS \
-{{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
- { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \
- { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}}
+ We have three registers that can be eliminated on the i386. First, the
+ hard frame pointer register can often be eliminated in favor of the stack
+ pointer register. Secondly, the argument and frame pointer register can
+ always be eliminated; They are replaced with either the stack or frame pointer. */
-/* Given FROM and TO register numbers, say whether this elimination is allowed.
- Frame pointer elimination is automatically handled.
+#define ELIMINABLE_REGS \
+{{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
+ { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
+ { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
+ { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}} \
- For the i386, if frame pointer elimination is being done, we would like to
- convert ap into sp, not fp.
+/* Given FROM and TO register numbers, say whether this elimination is
+ allowed. Frame pointer elimination is automatically handled.
All other eliminations are valid. */
-#define CAN_ELIMINATE(FROM, TO) \
- ((FROM) == ARG_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM \
- ? ! frame_pointer_needed \
- : 1)
+#define CAN_ELIMINATE(FROM, TO) \
+ ((TO) == STACK_POINTER_REGNUM ? ! frame_pointer_needed : 1)
/* Define the offset between two registers, one to be eliminated, and the other
its replacement, at the start of a routine. */
#define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
-{ \
- if ((FROM) == ARG_POINTER_REGNUM && (TO) == FRAME_POINTER_REGNUM) \
- (OFFSET) = 8; /* Skip saved PC and previous frame pointer */ \
- else \
- { \
- int nregs; \
- int offset; \
- int preferred_alignment = PREFERRED_STACK_BOUNDARY / BITS_PER_UNIT; \
- HOST_WIDE_INT tsize = ix86_compute_frame_size (get_frame_size (), \
- &nregs); \
- \
- (OFFSET) = (tsize + nregs * UNITS_PER_WORD); \
- \
- offset = 4; \
- if (frame_pointer_needed) \
- offset += UNITS_PER_WORD; \
- \
- if ((FROM) == ARG_POINTER_REGNUM) \
- (OFFSET) += offset; \
- else \
- (OFFSET) -= ((offset + preferred_alignment - 1) \
- & -preferred_alignment) - offset; \
- } \
-}
+ (OFFSET) = ix86_initial_elimination_offset (FROM, TO)
\f
/* Addressing modes, and classification of registers for them. */
#define REGNO_OK_FOR_BASE_P(REGNO) \
((REGNO) <= STACK_POINTER_REGNUM \
|| (REGNO) == ARG_POINTER_REGNUM \
+ || (REGNO) == FRAME_POINTER_REGNUM \
|| (unsigned) reg_renumber[REGNO] <= STACK_POINTER_REGNUM)
#define REGNO_OK_FOR_SIREG_P(REGNO) ((REGNO) == 4 || reg_renumber[REGNO] == 4)
#define REG_OK_FOR_BASE_NONSTRICT_P(X) \
(REGNO (X) <= STACK_POINTER_REGNUM \
|| REGNO (X) == ARG_POINTER_REGNUM \
+ || REGNO (X) == FRAME_POINTER_REGNUM \
|| REGNO (X) >= FIRST_PSEUDO_REGISTER)
#define REG_OK_FOR_STRREG_NONSTRICT_P(X) \
/* Nonzero if the constant value X is a legitimate general operand.
It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
-#define LEGITIMATE_CONSTANT_P(X) \
- (GET_CODE (X) == CONST_DOUBLE ? standard_80387_constant_p (X) : 1)
+#define LEGITIMATE_CONSTANT_P(X) 1
#ifdef REG_OK_STRICT
#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
Increasing the value will always make code faster, but eventually
incurs high cost in increased code size.
- If you don't define this, a reasonable default is used.
-
- Make this large on i386, since the block move is very inefficient with small
- blocks, and the hard register needs of the block move require much reload
- work. */
+ If you don't define this, a reasonable default is used. */
-#define MOVE_RATIO 5
+#define MOVE_RATIO (optimize_size ? 3 : ix86_cost->move_ratio)
/* Define if shifts truncate the shift count
which implies one can omit a sign-extension or zero-extension
#define PROMOTE_PROTOTYPES 1
+/* A macro to update M and UNSIGNEDP when an object whose type is
+ TYPE and which has the specified mode and signedness is to be
+ stored in a register. This macro is only called when TYPE is a
+ scalar type.
+
+ On i386 it is sometimes usefull to promote HImode and QImode
+ quantities to SImode. The choice depends on target type. */
+
+#define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
+ if (((MODE) == HImode && TARGET_PROMOTE_HI_REGS) \
+ || ((MODE) == QImode && TARGET_PROMOTE_QI_REGS)) \
+ (MODE) = SImode;
+
/* Specify the machine mode that pointers have.
After generation of rtl, the compiler makes no further distinction
between pointers and any other objects of this machine mode. */
If the value of this macro is always zero, it need not be defined. */
-/* #define SLOW_UNALIGNED_ACCESS 0 */
+/* #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) 0 */
/* Define this macro to inhibit strength reduction of memory
addresses. (On some machines, such strength reduction seems to do
Add CCNO to indicate No Overflow, which is often also includes
No Carry. This is typically used on the output of logicals,
- and is only valid in comparisons against zero. */
+ and is only valid in comparisons against zero.
+
+ Add CCZ to indicate that only the Zero flag is valid. */
#define EXTRA_CC_MODES \
CC(CCNOmode, "CCNO") \
+ CC(CCZmode, "CCZ") \
CC(CCFPmode, "CCFP") \
CC(CCFPUmode, "CCFPU")
For floating-point equality comparisons, CCFPEQmode should be used.
VOIDmode should be used in all other cases.
- For integer comparisons against zero, reduce to CCNOmode if
+ For integer comparisons against zero, reduce to CCNOmode or CCZmode if
possible, to allow for more combinations. */
#define SELECT_CC_MODE(OP,X,Y) \
? (OP) == EQ || (OP) == NE ? CCFPUmode : CCFPmode \
: (OP) == LE || (OP) == GT ? CCmode \
: (Y) != const0_rtx ? CCmode \
- : CCNOmode)
+ : (OP) == EQ || (OP) == NE ? CCZmode : CCNOmode)
\f
/* Control the assembler format that we output, to the extent
this does not vary between assemblers. */
#define HI_REGISTER_NAMES \
{"ax","dx","cx","bx","si","di","bp","sp", \
"st","st(1)","st(2)","st(3)","st(4)","st(5)","st(6)","st(7)","", \
- "flags","fpsr" }
+ "flags","fpsr", "dirflag", "frame" }
#define REGISTER_NAMES HI_REGISTER_NAMES
/* How to renumber registers for dbx and gdb. */
-/* {0,2,1,3,6,7,4,5,12,13,14,15,16,17} */
-#define DBX_REGISTER_NUMBER(n) \
-((n) == 0 ? 0 : \
- (n) == 1 ? 2 : \
- (n) == 2 ? 1 : \
- (n) == 3 ? 3 : \
- (n) == 4 ? 6 : \
- (n) == 5 ? 7 : \
- (n) == 6 ? 4 : \
- (n) == 7 ? 5 : \
- (n) + 4)
+#define DBX_REGISTER_NUMBER(n) dbx_register_map[n]
+
+extern int const dbx_register_map[FIRST_PSEUDO_REGISTER];
+extern int const svr4_dbx_register_map[FIRST_PSEUDO_REGISTER];
/* Before the prologue, RA is at 0(%esp). */
#define INCOMING_RETURN_ADDR_RTX \
#define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
fprintf (FILE, "\t%s\t%s%d-%s%d\n",ASM_LONG, LPREFIX, VALUE, LPREFIX, REL)
+/* A C statement that outputs an address constant appropriate to
+ for DWARF debugging. */
+
+#define ASM_OUTPUT_DWARF_ADDR_CONST(FILE,X) \
+ i386_dwarf_output_addr_const((FILE),(X))
+
+/* Either simplify a location expression, or return the original. */
+
+#define ASM_SIMPLIFY_DWARF_ADDR(X) \
+ i386_simplify_dwarf_addr(X)
+
/* Define the parentheses used to group arithmetic operations
in assembler code. */
programs that are not linked with aux-output.o. */
#define DEBUG_PRINT_REG(X, CODE, FILE) \
- do { static char *hi_name[] = HI_REGISTER_NAMES; \
- static char *qi_name[] = QI_REGISTER_NAMES; \
+ do { static const char * const hi_name[] = HI_REGISTER_NAMES; \
+ static const char * const qi_name[] = QI_REGISTER_NAMES; \
fprintf (FILE, "%d ", REGNO (X)); \
if (REGNO (X) == FLAGS_REG) \
{ fputs ("flags", FILE); break; } \
+ if (REGNO (X) == DIRFLAG_REG) \
+ { fputs ("dirflag", FILE); break; } \
if (REGNO (X) == FPSR_REG) \
{ fputs ("fpsr", FILE); break; } \
if (REGNO (X) == ARG_POINTER_REGNUM) \
{ fputs ("argp", FILE); break; } \
+ if (REGNO (X) == FRAME_POINTER_REGNUM) \
+ { fputs ("frame", FILE); break; } \
if (STACK_TOP_P (X)) \
{ fputs ("st(0)", FILE); break; } \
if (FP_REG_P (X)) \
#define PREDICATE_CODES \
{"symbolic_operand", {SYMBOL_REF, LABEL_REF, CONST}}, \
+ {"aligned_operand", {CONST_INT, CONST_DOUBLE, CONST, SYMBOL_REF, \
+ LABEL_REF, SUBREG, REG, MEM}}, \
{"pic_symbolic_operand", {CONST}}, \
{"call_insn_operand", {MEM}}, \
- {"expander_call_insn_operand", {MEM}}, \
{"constant_call_address_operand", {MEM}}, \
{"const0_operand", {CONST_INT, CONST_DOUBLE}}, \
{"const1_operand", {CONST_INT}}, \
{"const248_operand", {CONST_INT}}, \
{"incdec_operand", {CONST_INT}}, \
{"reg_no_sp_operand", {SUBREG, REG}}, \
+ {"general_no_elim_operand", {CONST_INT, CONST_DOUBLE, CONST, \
+ SYMBOL_REF, LABEL_REF, SUBREG, REG, MEM}}, \
+ {"nonmemory_no_elim_operand", {CONST_INT, REG, SUBREG}}, \
{"q_regs_operand", {SUBREG, REG}}, \
{"non_q_regs_operand", {SUBREG, REG}}, \
{"no_comparison_operator", {EQ, NE, LT, GE, LTU, GTU, LEU, GEU}}, \
{"fcmov_comparison_operator", {EQ, NE, LTU, GTU, LEU, GEU}}, \
+ {"uno_comparison_operator", {EQ, NE, LE, LT, GE, GT, LEU, LTU, GEU, \
+ GTU, UNORDERED, ORDERED}}, \
{"cmp_fp_expander_operand", {CONST_DOUBLE, SUBREG, REG, MEM}}, \
{"ext_register_operand", {SUBREG, REG}}, \
{"binary_fp_operator", {PLUS, MINUS, MULT, DIV}}, \
UMIN, UMAX, COMPARE, MINUS, DIV, MOD, \
UDIV, UMOD, ASHIFT, ROTATE, ASHIFTRT, \
LSHIFTRT, ROTATERT}}, \
+ {"promotable_binary_operator", {PLUS, MULT, AND, IOR, XOR, ASHIFT}}, \
{"memory_displacement_operand", {MEM}}, \
{"cmpsi_operand", {CONST_INT, CONST_DOUBLE, CONST, SYMBOL_REF, \
LABEL_REF, SUBREG, REG, MEM, AND}}, \
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