(define_constants
- [(REG_X 26)
- (REG_Y 28)
- (REG_Z 30)
- (REG_W 24)
- (REG_SP 32)
- (LPM_REGNO 0) ; implicit target register of LPM
- (TMP_REGNO 0) ; temporary register r0
- (ZERO_REGNO 1) ; zero register r1
-
- ;; RAM addresses of some SFRs common to all Devices.
-
- (SREG_ADDR 0x5F) ; Status Register
- (SP_ADDR 0x5D) ; Stack Pointer
- (RAMPZ_ADDR 0x5B) ; Address' high part when loading via ELPM
+ [(REG_X 26)
+ (REG_Y 28)
+ (REG_Z 30)
+ (REG_W 24)
+ (REG_SP 32)
+ (LPM_REGNO 0) ; implicit target register of LPM
+ (TMP_REGNO 0) ; temporary register r0
+ (ZERO_REGNO 1) ; zero register r1
])
(define_c_enum "unspec"
[UNSPEC_STRLEN
UNSPEC_MOVMEM
UNSPEC_INDEX_JMP
+ UNSPEC_LPM
UNSPEC_FMUL
UNSPEC_FMULS
UNSPEC_FMULSU
UNSPEC_COPYSIGN
UNSPEC_IDENTITY
- UNSPEC_MAP_BITS
+ UNSPEC_INSERT_BITS
])
(define_c_enum "unspecv"
UNSPECV_WRITE_SP
UNSPECV_GOTO_RECEIVER
UNSPECV_ENABLE_IRQS
+ UNSPECV_MEMORY_BARRIER
UNSPECV_NOP
UNSPECV_SLEEP
UNSPECV_WDR
(include "constraints.md")
;; Condition code settings.
-(define_attr "cc" "none,set_czn,set_zn,set_n,compare,clobber,
- out_plus, out_plus_noclobber"
+(define_attr "cc" "none,set_czn,set_vzn,set_zn,set_n,compare,clobber,
+ out_plus, out_plus_noclobber,ldi"
(const_string "none"))
(define_attr "type" "branch,branch1,arith,xcall"
(const_int 2043)))
(const_int 3)
(const_int 4)))
- (eq_attr "type" "xcall")
- (if_then_else (match_test "!AVR_HAVE_JMP_CALL")
- (const_int 1)
- (const_int 2))]
+ (eq_attr "type" "xcall")
+ (if_then_else (match_test "!AVR_HAVE_JMP_CALL")
+ (const_int 1)
+ (const_int 2))]
(const_int 2)))
;; Lengths of several insns are adjusted in avr.c:adjust_insn_length().
;; Otherwise do special processing depending on the attribute.
(define_attr "adjust_len"
- "out_bitop, out_plus, out_plus_noclobber, addto_sp,
- tsthi, tstpsi, tstsi, compare, call,
+ "out_bitop, out_plus, out_plus_noclobber, plus64, addto_sp,
+ tsthi, tstpsi, tstsi, compare, compare64, call,
mov8, mov16, mov24, mov32, reload_in16, reload_in24, reload_in32,
- xload, movmem,
+ xload, movmem, load_lpm,
ashlqi, ashrqi, lshrqi,
ashlhi, ashrhi, lshrhi,
ashlsi, ashrsi, lshrsi,
ashlpsi, ashrpsi, lshrpsi,
- map_bits,
+ insert_bits,
no"
(const_string "no"))
;; ijmp : ISA has no EICALL/EIJMP eijmp : ISA has EICALL/EIJMP
;; lpm : ISA has no LPMX lpmx : ISA has LPMX
;; elpm : ISA has ELPM but no ELPMX elpmx : ISA has ELPMX
+;; no_xmega: non-XMEGA core xmega : XMEGA core
(define_attr "isa"
- "mov,movw, rjmp,jmp, ijmp,eijmp, lpm,lpmx, elpm,elpmx,
+ "mov,movw, rjmp,jmp, ijmp,eijmp, lpm,lpmx, elpm,elpmx, no_xmega,xmega,
standard"
(const_string "standard"))
(and (eq_attr "isa" "elpmx")
(match_test "AVR_HAVE_ELPMX"))
(const_int 1)
+
+ (and (eq_attr "isa" "xmega")
+ (match_test "AVR_XMEGA"))
+ (const_int 1)
+
+ (and (eq_attr "isa" "no_xmega")
+ (match_test "!AVR_XMEGA"))
+ (const_int 1)
] (const_int 0)))
(define_mode_iterator QIHI2 [(QI "") (HI "")])
(define_mode_iterator QISI [(QI "") (HI "") (PSI "") (SI "")])
(define_mode_iterator QIDI [(QI "") (HI "") (PSI "") (SI "") (DI "")])
-(define_mode_iterator HIDI [(HI "") (PSI "") (SI "") (DI "")])
(define_mode_iterator HISI [(HI "") (PSI "") (SI "")])
;; All supported move-modes
(define_code_iterator any_extend [sign_extend zero_extend])
(define_code_iterator any_extend2 [sign_extend zero_extend])
+(define_code_iterator xior [xor ior])
+(define_code_iterator eqne [eq ne])
+
;; Define code attributes
(define_code_attr extend_su
[(sign_extend "s")
[(zero_extend "r")
(sign_extend "d")])
+;; Map RTX code to its standard insn name
+(define_code_attr code_stdname
+ [(ashift "ashl")
+ (ashiftrt "ashr")
+ (lshiftrt "lshr")
+ (ior "ior")
+ (xor "xor")
+ (rotate "rotl")])
;;========================================================================
;; The following is used by nonlocal_goto and setjmp.
(define_expand "nonlocal_goto_receiver"
[(set (reg:HI REG_Y)
- (unspec_volatile:HI [(const_int 0)] UNSPECV_GOTO_RECEIVER))]
+ (unspec_volatile:HI [(const_int 0)] UNSPECV_GOTO_RECEIVER))]
""
{
emit_move_insn (virtual_stack_vars_rtx,
- gen_rtx_PLUS (Pmode, hard_frame_pointer_rtx,
- gen_int_mode (STARTING_FRAME_OFFSET,
- Pmode)));
+ gen_rtx_PLUS (Pmode, hard_frame_pointer_rtx,
+ gen_int_mode (STARTING_FRAME_OFFSET,
+ Pmode)));
/* This might change the hard frame pointer in ways that aren't
apparent to early optimization passes, so force a clobber. */
emit_clobber (hard_frame_pointer_rtx);
{
rtx part = simplify_gen_subreg (QImode, operands[0], <MODE>mode, i);
if (part != const0_rtx)
- part = force_reg (QImode, part);
+ part = force_reg (QImode, part);
emit_insn (gen_pushqi1 (part));
}
DONE;
;;========================================================================
;; Move stuff around
-(define_expand "load<mode>_libgcc"
- [(set (match_dup 3)
- (match_dup 2))
- (set (reg:MOVMODE 22)
- (match_operand:MOVMODE 1 "memory_operand" ""))
- (set (match_operand:MOVMODE 0 "register_operand" "")
- (reg:MOVMODE 22))]
- "avr_load_libgcc_p (operands[1])"
- {
- operands[3] = gen_rtx_REG (HImode, REG_Z);
- operands[2] = force_operand (XEXP (operands[1], 0), NULL_RTX);
- operands[1] = replace_equiv_address (operands[1], operands[3]);
- set_mem_addr_space (operands[1], ADDR_SPACE_PGM);
- })
-
+;; Represent a load from __flash that needs libgcc support as UNSPEC.
+;; This is legal because we read from non-changing memory.
+;; For rationale see the FIXME below.
+
+;; "load_psi_libgcc"
+;; "load_si_libgcc"
+;; "load_sf_libgcc"
(define_insn "load_<mode>_libgcc"
[(set (reg:MOVMODE 22)
- (match_operand:MOVMODE 0 "memory_operand" "m,m"))]
- "avr_load_libgcc_p (operands[0])
- && REG_P (XEXP (operands[0], 0))
- && REG_Z == REGNO (XEXP (operands[0], 0))"
+ (unspec:MOVMODE [(reg:HI REG_Z)]
+ UNSPEC_LPM))]
+ ""
{
- operands[0] = GEN_INT (GET_MODE_SIZE (<MODE>mode));
- return "%~call __load_%0";
+ rtx n_bytes = GEN_INT (GET_MODE_SIZE (<MODE>mode));
+ output_asm_insn ("%~call __load_%0", &n_bytes);
+ return "";
}
- [(set_attr "length" "1,2")
- (set_attr "isa" "rjmp,jmp")
+ [(set_attr "type" "xcall")
+ (set_attr "cc" "clobber")])
+
+
+;; Similar for inline reads from flash. We use UNSPEC instead
+;; of MEM for the same reason as above: PR52543.
+;; $1 contains the memory segment.
+
+(define_insn "load_<mode>"
+ [(set (match_operand:MOVMODE 0 "register_operand" "=r")
+ (unspec:MOVMODE [(reg:HI REG_Z)
+ (match_operand:QI 1 "reg_or_0_operand" "rL")]
+ UNSPEC_LPM))]
+ "(CONST_INT_P (operands[1]) && AVR_HAVE_LPMX)
+ || (REG_P (operands[1]) && AVR_HAVE_ELPMX)"
+ {
+ return avr_load_lpm (insn, operands, NULL);
+ }
+ [(set_attr "adjust_len" "load_lpm")
+ (set_attr "cc" "clobber")])
+
+
+;; Similar to above for the complementary situation when there is no [E]LPMx.
+;; Clobber Z in that case.
+
+(define_insn "load_<mode>_clobber"
+ [(set (match_operand:MOVMODE 0 "register_operand" "=r")
+ (unspec:MOVMODE [(reg:HI REG_Z)
+ (match_operand:QI 1 "reg_or_0_operand" "rL")]
+ UNSPEC_LPM))
+ (clobber (reg:HI REG_Z))]
+ "!((CONST_INT_P (operands[1]) && AVR_HAVE_LPMX)
+ || (REG_P (operands[1]) && AVR_HAVE_ELPMX))"
+ {
+ return avr_load_lpm (insn, operands, NULL);
+ }
+ [(set_attr "adjust_len" "load_lpm")
(set_attr "cc" "clobber")])
(match_operand:QI 1 "memory_operand" "m"))
(clobber (reg:HI REG_Z))]
"can_create_pseudo_p()
- && avr_mem_pgmx_p (operands[1])
+ && !avr_xload_libgcc_p (QImode)
+ && avr_mem_memx_p (operands[1])
&& REG_P (XEXP (operands[1], 0))"
{ gcc_unreachable(); }
"&& 1"
DONE;
})
+;; "xloadqi_A"
+;; "xloadhi_A"
+;; "xloadpsi_A"
+;; "xloadsi_A"
+;; "xloadsf_A"
(define_insn_and_split "xload<mode>_A"
[(set (match_operand:MOVMODE 0 "register_operand" "=r")
(match_operand:MOVMODE 1 "memory_operand" "m"))
+ (clobber (reg:MOVMODE 22))
(clobber (reg:QI 21))
(clobber (reg:HI REG_Z))]
- "QImode != <MODE>mode
- && can_create_pseudo_p()
- && avr_mem_pgmx_p (operands[1])
+ "can_create_pseudo_p()
+ && avr_mem_memx_p (operands[1])
&& REG_P (XEXP (operands[1], 0))"
{ gcc_unreachable(); }
"&& 1"
rtx reg_z = gen_rtx_REG (HImode, REG_Z);
rtx addr_hi8 = simplify_gen_subreg (QImode, addr, PSImode, 2);
addr_space_t as = MEM_ADDR_SPACE (operands[1]);
- rtx hi8, insn;
+ rtx insn;
+ /* Split the address to R21:Z */
emit_move_insn (reg_z, simplify_gen_subreg (HImode, addr, PSImode, 0));
+ emit_move_insn (gen_rtx_REG (QImode, 21), addr_hi8);
- if (avr_xload_libgcc_p (<MODE>mode))
- {
- emit_move_insn (gen_rtx_REG (QImode, 21), addr_hi8);
- insn = emit_insn (gen_xload_<mode>_libgcc ());
- emit_move_insn (operands[0], gen_rtx_REG (<MODE>mode, 22));
- }
- else if (avr_current_arch->n_segments == 1
- && GET_MODE_SIZE (<MODE>mode) > 2
- && !AVR_HAVE_LPMX)
- {
- rtx src = gen_rtx_MEM (<MODE>mode, reg_z);
-
- as = ADDR_SPACE_PGM;
- insn = emit_insn (gen_load_<mode>_libgcc (src));
- emit_move_insn (operands[0], gen_rtx_REG (<MODE>mode, 22));
- }
- else
- {
- hi8 = gen_reg_rtx (QImode);
- emit_move_insn (hi8, addr_hi8);
- insn = emit_insn (gen_xload_<mode> (operands[0], hi8));
- }
-
+ /* Load with code from libgcc */
+ insn = emit_insn (gen_xload_<mode>_libgcc ());
set_mem_addr_space (SET_SRC (single_set (insn)), as);
+ /* Move to destination */
+ emit_move_insn (operands[0], gen_rtx_REG (<MODE>mode, 22));
+
DONE;
})
-;; Move value from address space pgmx to a register
+;; Move value from address space memx to a register
;; These insns must be prior to respective generic move insn.
(define_insn "xload_8"
- [(set (match_operand:QI 0 "register_operand" "=r")
- (mem:QI (lo_sum:PSI (match_operand:QI 1 "register_operand" "r")
+ [(set (match_operand:QI 0 "register_operand" "=&r,r")
+ (mem:QI (lo_sum:PSI (match_operand:QI 1 "register_operand" "r,r")
(reg:HI REG_Z))))]
- ""
+ "!avr_xload_libgcc_p (QImode)"
{
return avr_out_xload (insn, operands, NULL);
}
- [(set_attr "adjust_len" "xload")
- (set_attr "cc" "clobber")])
+ [(set_attr "length" "4,4")
+ (set_attr "adjust_len" "*,xload")
+ (set_attr "isa" "lpmx,lpm")
+ (set_attr "cc" "none")])
+
+;; R21:Z : 24-bit source address
+;; R22 : 1-4 byte output
+;; "xload_qi_libgcc"
;; "xload_hi_libgcc"
;; "xload_psi_libgcc"
;; "xload_si_libgcc"
(reg:HI REG_Z))))
(clobber (reg:QI 21))
(clobber (reg:HI REG_Z))]
- "<MODE>mode != QImode
- && avr_xload_libgcc_p (<MODE>mode)"
+ "avr_xload_libgcc_p (<MODE>mode)"
{
rtx x_bytes = GEN_INT (GET_MODE_SIZE (<MODE>mode));
- /* Devices with ELPM* also have CALL. */
-
- output_asm_insn ("call __xload_%0", &x_bytes);
+ output_asm_insn ("%~call __xload_%0", &x_bytes);
return "";
}
- [(set_attr "length" "2")
- (set_attr "cc" "clobber")])
-
-;; "xload_hi"
-;; "xload_psi"
-;; "xload_si"
-;; "xload_sf"
-(define_insn "xload_<mode>"
- [(set (match_operand:MOVMODE 0 "register_operand" "=r")
- (mem:MOVMODE (lo_sum:PSI (match_operand:QI 1 "register_operand" "r")
- (reg:HI REG_Z))))
- (clobber (scratch:HI))
- (clobber (reg:HI REG_Z))]
- "<MODE>mode != QImode
- && !avr_xload_libgcc_p (<MODE>mode)"
- {
- return avr_out_xload (insn, operands, NULL);
- }
- [(set_attr "adjust_len" "xload")
+ [(set_attr "type" "xcall")
(set_attr "cc" "clobber")])
;; "movsi"
;; "movsf"
;; "movpsi"
-
(define_expand "mov<mode>"
[(set (match_operand:MOVMODE 0 "nonimmediate_operand" "")
(match_operand:MOVMODE 1 "general_operand" ""))]
rtx dest = operands[0];
rtx src = operands[1];
- if (avr_mem_pgm_p (dest))
+ if (avr_mem_flash_p (dest))
DONE;
/* One of the operands has to be in a register. */
operands[1] = src = copy_to_mode_reg (<MODE>mode, src);
}
- if (avr_mem_pgmx_p (src))
+ if (avr_mem_memx_p (src))
{
rtx addr = XEXP (src, 0);
if (!REG_P (addr))
src = replace_equiv_address (src, copy_to_mode_reg (PSImode, addr));
- if (QImode == <MODE>mode)
+ if (!avr_xload_libgcc_p (<MODE>mode))
emit_insn (gen_xload8_A (dest, src));
else
emit_insn (gen_xload<mode>_A (dest, src));
DONE;
}
+ /* For old devices without LPMx, prefer __flash loads per libcall. */
+
if (avr_load_libgcc_p (src))
{
- /* For the small devices, do loads per libgcc call. */
- emit_insn (gen_load<mode>_libgcc (dest, src));
+ emit_move_insn (gen_rtx_REG (Pmode, REG_Z),
+ force_reg (Pmode, XEXP (src, 0)));
+
+ emit_insn (gen_load_<mode>_libgcc ());
+ emit_move_insn (dest, gen_rtx_REG (<MODE>mode, 22));
+ DONE;
+ }
+
+ /* ; FIXME: Hack around PR rtl-optimization/52543.
+ ; lower-subreg.c splits loads from the 16-bit address spaces which
+ ; causes code bloat because each load need his setting of RAMPZ.
+ ; Moreover, the split will happen in such a way that the loads don't
+ ; take advantage of POST_INC addressing. Thus, we use UNSPEC to
+ ; represent these loads instead. Notice that this is legitimate
+ ; because the memory content does not change: Loads from the same
+ ; address will yield the same value.
+ ; POST_INC addressing would make the addresses mode_dependent and could
+ ; work around that PR, too. However, notice that it is *not* legitimate
+ ; to expand to POST_INC at expand time: The following passes assert
+ ; that pre-/post-modify addressing is introduced by .auto_inc_dec and
+ ; does not exist before that pass. */
+
+ if (avr_mem_flash_p (src)
+ && (GET_MODE_SIZE (<MODE>mode) > 1
+ || MEM_ADDR_SPACE (src) != ADDR_SPACE_FLASH))
+ {
+ rtx xsegment = GEN_INT (avr_addrspace[MEM_ADDR_SPACE (src)].segment);
+ if (!AVR_HAVE_ELPM)
+ xsegment = const0_rtx;
+ if (xsegment != const0_rtx)
+ xsegment = force_reg (QImode, xsegment);
+
+ emit_move_insn (gen_rtx_REG (Pmode, REG_Z),
+ force_reg (Pmode, XEXP (src, 0)));
+
+ if ((CONST_INT_P (xsegment) && AVR_HAVE_LPMX)
+ || (REG_P (xsegment) && AVR_HAVE_ELPMX))
+ emit_insn (gen_load_<mode> (dest, xsegment));
+ else
+ emit_insn (gen_load_<mode>_clobber (dest, xsegment));
DONE;
}
+
+ /* ; The only address-space for which we use plain MEM and reload
+ ; machinery are 1-byte loads from __flash. */
})
;;========================================================================
}
[(set_attr "length" "1,1,5,5,1,1,4")
(set_attr "adjust_len" "mov8")
- (set_attr "cc" "none,none,clobber,clobber,none,none,clobber")])
+ (set_attr "cc" "ldi,none,clobber,clobber,none,none,clobber")])
;; This is used in peephole2 to optimize loading immediate constants
;; if a scratch register from LD_REGS happens to be available.
(define_insn "*reload_inqi"
[(set (match_operand:QI 0 "register_operand" "=l")
- (match_operand:QI 1 "immediate_operand" "i"))
+ (match_operand:QI 1 "immediate_operand" "i"))
(clobber (match_operand:QI 2 "register_operand" "=&d"))]
"reload_completed"
"ldi %2,lo8(%1)
(define_peephole2
[(match_scratch:QI 2 "d")
(set (match_operand:QI 0 "l_register_operand" "")
- (match_operand:QI 1 "immediate_operand" ""))]
+ (match_operand:QI 1 "immediate_operand" ""))]
"(operands[1] != const0_rtx
&& operands[1] != const1_rtx
&& operands[1] != constm1_rtx)"
[(parallel [(set (match_dup 0) (match_dup 1))
- (clobber (match_dup 2))])]
+ (clobber (match_dup 2))])]
"")
;;============================================================================
;; Move register $1 to the Stack Pointer register SP.
;; This insn is emit during function prologue/epilogue generation.
-;; $2 = 0: We know that IRQs are off
-;; $2 = 1: We know that IRQs are on
-;; Remaining cases when the state of the I-Flag is unknown are
-;; handled by generic movhi insn.
+;; $2 = 0: We know that IRQs are off
+;; $2 = 1: We know that IRQs are on
+;; $2 = 2: SP has 8 bits only, IRQ state does not matter
+;; $2 = -1: We don't know anything about IRQ on/off
+;; Always write SP via unspec, see PR50063
(define_insn "movhi_sp_r"
- [(set (match_operand:HI 0 "stack_register_operand" "=q,q")
- (unspec_volatile:HI [(match_operand:HI 1 "register_operand" "r,r")
- (match_operand:HI 2 "const_int_operand" "L,P")]
+ [(set (match_operand:HI 0 "stack_register_operand" "=q,q,q,q,q")
+ (unspec_volatile:HI [(match_operand:HI 1 "register_operand" "r,r,r,r,r")
+ (match_operand:HI 2 "const_int_operand" "L,P,N,K,LPN")]
UNSPECV_WRITE_SP))]
- "!AVR_HAVE_8BIT_SP"
+ ""
"@
- out __SP_H__,%B1\;out __SP_L__,%A1
- cli\;out __SP_H__,%B1\;sei\;out __SP_L__,%A1"
- [(set_attr "length" "2,4")
+ out %B0,%B1\;out %A0,%A1
+ cli\;out %B0,%B1\;sei\;out %A0,%A1
+ in __tmp_reg__,__SREG__\;cli\;out %B0,%B1\;out __SREG__,__tmp_reg__\;out %A0,%A1
+ out %A0,%A1
+ out %A0,%A1\;out %B0,%B1"
+ [(set_attr "length" "2,4,5,1,2")
+ (set_attr "isa" "no_xmega,no_xmega,no_xmega,*,xmega")
(set_attr "cc" "none")])
(define_peephole2
"(operands[1] != const0_rtx
&& operands[1] != constm1_rtx)"
[(parallel [(set (match_dup 0) (match_dup 1))
- (clobber (match_dup 2))])]
+ (clobber (match_dup 2))])]
"")
;; '*' because it is not used in rtl generation, only in above peephole
operands[5] = gen_rtx_REG (HImode, REGNO (operands[3]));
})
-;; For LPM loads from AS1 we split
-;; R = *Z
-;; to
-;; R = *Z++
-;; Z = Z - sizeof (R)
-;;
-;; so that the second instruction can be optimized out.
-
-(define_split ; "split-lpmx"
- [(set (match_operand:HISI 0 "register_operand" "")
- (match_operand:HISI 1 "memory_operand" ""))]
- "reload_completed
- && AVR_HAVE_LPMX"
- [(set (match_dup 0)
- (match_dup 2))
- (set (match_dup 3)
- (plus:HI (match_dup 3)
- (match_dup 4)))]
- {
- rtx addr = XEXP (operands[1], 0);
-
- if (!avr_mem_pgm_p (operands[1])
- || !REG_P (addr)
- || reg_overlap_mentioned_p (addr, operands[0]))
- {
- FAIL;
- }
-
- operands[2] = replace_equiv_address (operands[1],
- gen_rtx_POST_INC (Pmode, addr));
- operands[3] = addr;
- operands[4] = gen_int_mode (-GET_MODE_SIZE (<MODE>mode), HImode);
- })
-
;;==========================================================================
;; xpointer move (24 bit)
&& operands[1] != constm1_rtx"
[(parallel [(set (match_dup 0)
(match_dup 1))
- (clobber (match_dup 2))])]
+ (clobber (match_dup 2))])]
"")
;; '*' because it is not used in rtl generation.
"(operands[1] != const0_rtx
&& operands[1] != constm1_rtx)"
[(parallel [(set (match_dup 0) (match_dup 1))
- (clobber (match_dup 2))])]
+ (clobber (match_dup 2))])]
"")
;; '*' because it is not used in rtl generation.
})
(define_mode_attr MOVMEM_r_d [(QI "r")
- (HI "d")])
+ (HI "wd")])
-;; $0, $4 : & dest
-;; $1, $5 : & src
-;; $2 : Address Space
-;; $3, $7 : Loop register
-;; $6 : Scratch register
+;; $0 : Address Space
+;; $1, $2 : Loop register
+;; R30 : source address
+;; R26 : destination address
;; "movmem_qi"
;; "movmem_hi"
(define_insn "movmem_<mode>"
- [(set (mem:BLK (match_operand:HI 0 "register_operand" "x"))
- (mem:BLK (match_operand:HI 1 "register_operand" "z")))
- (unspec [(match_operand:QI 2 "const_int_operand" "LP")]
+ [(set (mem:BLK (reg:HI REG_X))
+ (mem:BLK (reg:HI REG_Z)))
+ (unspec [(match_operand:QI 0 "const_int_operand" "n")]
UNSPEC_MOVMEM)
- (use (match_operand:QIHI 3 "register_operand" "<MOVMEM_r_d>"))
- (clobber (match_operand:HI 4 "register_operand" "=0"))
- (clobber (match_operand:HI 5 "register_operand" "=1"))
- (clobber (match_operand:QI 6 "register_operand" "=&r"))
- (clobber (match_operand:QIHI 7 "register_operand" "=3"))]
+ (use (match_operand:QIHI 1 "register_operand" "<MOVMEM_r_d>"))
+ (clobber (reg:HI REG_X))
+ (clobber (reg:HI REG_Z))
+ (clobber (reg:QI LPM_REGNO))
+ (clobber (match_operand:QIHI 2 "register_operand" "=1"))]
""
{
return avr_out_movmem (insn, operands, NULL);
[(set_attr "adjust_len" "movmem")
(set_attr "cc" "clobber")])
-;; Ditto and
-;; $8, $9 : hh8 (& src)
-;; $10 : RAMPZ_ADDR
-
-;; "movmem_qi_elpm"
-;; "movmem_hi_elpm"
-(define_insn "movmem_<mode>_elpm"
- [(set (mem:BLK (match_operand:HI 0 "register_operand" "x"))
- (mem:BLK (lo_sum:PSI (match_operand:QI 8 "register_operand" "r")
- (match_operand:HI 1 "register_operand" "z"))))
- (unspec [(match_operand:QI 2 "const_int_operand" "n")]
+
+;; $0 : Address Space
+;; $1 : RAMPZ RAM address
+;; R24 : #bytes and loop register
+;; R23:Z : 24-bit source address
+;; R26 : 16-bit destination address
+
+;; "movmemx_qi"
+;; "movmemx_hi"
+(define_insn "movmemx_<mode>"
+ [(set (mem:BLK (reg:HI REG_X))
+ (mem:BLK (lo_sum:PSI (reg:QI 23)
+ (reg:HI REG_Z))))
+ (unspec [(match_operand:QI 0 "const_int_operand" "n")]
UNSPEC_MOVMEM)
- (use (match_operand:QIHI 3 "register_operand" "<MOVMEM_r_d>"))
- (clobber (match_operand:HI 4 "register_operand" "=0"))
- (clobber (match_operand:HI 5 "register_operand" "=1"))
- (clobber (match_operand:QI 6 "register_operand" "=&r"))
- (clobber (match_operand:QIHI 7 "register_operand" "=3"))
- (clobber (match_operand:QI 9 "register_operand" "=8"))
- (clobber (mem:QI (match_operand:QI 10 "io_address_operand" "n")))]
- ""
- {
- return avr_out_movmem (insn, operands, NULL);
- }
- [(set_attr "adjust_len" "movmem")
+ (use (reg:QIHI 24))
+ (clobber (reg:HI REG_X))
+ (clobber (reg:HI REG_Z))
+ (clobber (reg:QI LPM_REGNO))
+ (clobber (reg:HI 24))
+ (clobber (reg:QI 23))
+ (clobber (mem:QI (match_operand:QI 1 "io_address_operand" "n")))]
+ ""
+ "%~call __movmemx_<mode>"
+ [(set_attr "type" "xcall")
(set_attr "cc" "clobber")])
inc %0\;inc %0
dec %0\;dec %0"
[(set_attr "length" "1,1,1,1,2,2")
- (set_attr "cc" "set_czn,set_czn,set_zn,set_zn,set_zn,set_zn")])
+ (set_attr "cc" "set_czn,set_czn,set_vzn,set_vzn,set_vzn,set_vzn")])
(define_expand "addhi3"
[(set (match_operand:HI 0 "register_operand" "")
- (plus:HI (match_operand:HI 1 "register_operand" "")
- (match_operand:HI 2 "nonmemory_operand" "")))]
+ (plus:HI (match_operand:HI 1 "register_operand" "")
+ (match_operand:HI 2 "nonmemory_operand" "")))]
""
{
if (CONST_INT_P (operands[2]))
(set_attr "adjust_len" "addto_sp")])
(define_insn "*addhi3"
- [(set (match_operand:HI 0 "register_operand" "=r,d,d")
- (plus:HI (match_operand:HI 1 "register_operand" "%0,0,0")
- (match_operand:HI 2 "nonmemory_operand" "r,s,n")))]
+ [(set (match_operand:HI 0 "register_operand" "=r,d,!w,d")
+ (plus:HI (match_operand:HI 1 "register_operand" "%0,0,0 ,0")
+ (match_operand:HI 2 "nonmemory_operand" "r,s,IJ,n")))]
""
{
static const char * const asm_code[] =
{
"add %A0,%A2\;adc %B0,%B2",
"subi %A0,lo8(-(%2))\;sbci %B0,hi8(-(%2))",
+ "",
""
};
return avr_out_plus_noclobber (operands, NULL, NULL);
}
- [(set_attr "length" "2,2,2")
- (set_attr "adjust_len" "*,*,out_plus_noclobber")
- (set_attr "cc" "set_n,set_czn,out_plus_noclobber")])
+ [(set_attr "length" "2,2,2,2")
+ (set_attr "adjust_len" "*,*,out_plus_noclobber,out_plus_noclobber")
+ (set_attr "cc" "set_n,set_czn,out_plus_noclobber,out_plus_noclobber")])
;; Adding a constant to NO_LD_REGS might have lead to a reload of
;; that constant to LD_REGS. We don't add a scratch to *addhi3
(clobber (match_dup 2))])])
(define_insn "addhi3_clobber"
- [(set (match_operand:HI 0 "register_operand" "=d,l")
- (plus:HI (match_operand:HI 1 "register_operand" "%0,0")
- (match_operand:HI 2 "const_int_operand" "n,n")))
- (clobber (match_scratch:QI 3 "=X,&d"))]
+ [(set (match_operand:HI 0 "register_operand" "=!w,d,r")
+ (plus:HI (match_operand:HI 1 "register_operand" "%0,0,0")
+ (match_operand:HI 2 "const_int_operand" "IJ,n,n")))
+ (clobber (match_scratch:QI 3 "=X,X,&d"))]
""
{
gcc_assert (REGNO (operands[0]) == REGNO (operands[1]));
};
if (*asm_code[which_alternative])
- return asm_code [which_alternative];
+ return asm_code[which_alternative];
return avr_out_plus (operands, NULL, NULL);
}
};
if (*asm_code[which_alternative])
- return asm_code [which_alternative];
+ return asm_code[which_alternative];
return avr_out_plus (operands, NULL, NULL);
}
(define_insn "subhi3"
[(set (match_operand:HI 0 "register_operand" "=r,d")
(minus:HI (match_operand:HI 1 "register_operand" "0,0")
- (match_operand:HI 2 "nonmemory_operand" "r,i")))]
+ (match_operand:HI 2 "nonmemory_operand" "r,i")))]
""
"@
sub %A0,%A2\;sbc %B0,%B2
(define_expand "mulqi3"
[(set (match_operand:QI 0 "register_operand" "")
- (mult:QI (match_operand:QI 1 "register_operand" "")
- (match_operand:QI 2 "register_operand" "")))]
+ (mult:QI (match_operand:QI 1 "register_operand" "")
+ (match_operand:QI 2 "register_operand" "")))]
""
- "{
- if (!AVR_HAVE_MUL)
- {
- emit_insn (gen_mulqi3_call (operands[0], operands[1], operands[2]));
- DONE;
- }
-}")
+ {
+ if (!AVR_HAVE_MUL)
+ {
+ emit_insn (gen_mulqi3_call (operands[0], operands[1], operands[2]));
+ DONE;
+ }
+ })
(define_insn "*mulqi3_enh"
[(set (match_operand:QI 0 "register_operand" "=r")
- (mult:QI (match_operand:QI 1 "register_operand" "r")
- (match_operand:QI 2 "register_operand" "r")))]
+ (mult:QI (match_operand:QI 1 "register_operand" "r")
+ (match_operand:QI 2 "register_operand" "r")))]
"AVR_HAVE_MUL"
"mul %1,%2
mov %0,r0
[(set (reg:QI 24) (match_operand:QI 1 "register_operand" ""))
(set (reg:QI 22) (match_operand:QI 2 "register_operand" ""))
(parallel [(set (reg:QI 24) (mult:QI (reg:QI 24) (reg:QI 22)))
- (clobber (reg:QI 22))])
+ (clobber (reg:QI 22))])
(set (match_operand:QI 0 "register_operand" "") (reg:QI 24))]
""
"")
;; Handle small constants
+;; Special case of a += 2*b as frequently seen with accesses to int arrays.
+;; This is shorter, faster than MUL and has lower register pressure.
+
+(define_insn_and_split "*umaddqihi4.2"
+ [(set (match_operand:HI 0 "register_operand" "=r")
+ (plus:HI (mult:HI (zero_extend:HI (match_operand:QI 1 "register_operand" "r"))
+ (const_int 2))
+ (match_operand:HI 2 "register_operand" "r")))]
+ "!reload_completed
+ && !reg_overlap_mentioned_p (operands[0], operands[1])"
+ { gcc_unreachable(); }
+ "&& 1"
+ [(set (match_dup 0)
+ (match_dup 2))
+ ; *addhi3_zero_extend
+ (set (match_dup 0)
+ (plus:HI (zero_extend:HI (match_dup 1))
+ (match_dup 0)))
+ ; *addhi3_zero_extend
+ (set (match_dup 0)
+ (plus:HI (zero_extend:HI (match_dup 1))
+ (match_dup 0)))])
+
;; "umaddqihi4.uconst"
;; "maddqihi4.sconst"
(define_insn_and_split "*<extend_u>maddqihi4.<extend_su>const"
(define_insn "*mulhi3_enh"
[(set (match_operand:HI 0 "register_operand" "=&r")
- (mult:HI (match_operand:HI 1 "register_operand" "r")
- (match_operand:HI 2 "register_operand" "r")))]
+ (mult:HI (match_operand:HI 1 "register_operand" "r")
+ (match_operand:HI 2 "register_operand" "r")))]
"AVR_HAVE_MUL"
{
return REGNO (operands[1]) == REGNO (operands[2])
[(set (reg:HI 24) (match_operand:HI 1 "register_operand" ""))
(set (reg:HI 22) (match_operand:HI 2 "register_operand" ""))
(parallel [(set (reg:HI 24) (mult:HI (reg:HI 24) (reg:HI 22)))
- (clobber (reg:HI 22))
- (clobber (reg:QI 21))])
+ (clobber (reg:HI 22))
+ (clobber (reg:QI 21))])
(set (match_operand:HI 0 "register_operand" "") (reg:HI 24))]
""
"")
[(set_attr "type" "xcall")
(set_attr "cc" "clobber")])
-;; To support widening multiplicatioon with constant we postpone
+;; To support widening multiplication with constant we postpone
;; expanding to the implicit library call until post combine and
;; prior to register allocation. Clobber all hard registers that
;; might be used by the (widening) multiply until it is split and
[(set (reg:QI 24) (match_dup 1))
(set (reg:QI 22) (match_dup 2))
(parallel [(set (reg:QI 24) (div:QI (reg:QI 24) (reg:QI 22)))
- (set (reg:QI 25) (mod:QI (reg:QI 24) (reg:QI 22)))
- (clobber (reg:QI 22))
- (clobber (reg:QI 23))])
+ (set (reg:QI 25) (mod:QI (reg:QI 24) (reg:QI 22)))
+ (clobber (reg:QI 22))
+ (clobber (reg:QI 23))])
(set (match_dup 0) (reg:QI 24))
(set (match_dup 3) (reg:QI 25))]
"")
[(parallel [(set (match_operand:QI 0 "pseudo_register_operand" "")
(udiv:QI (match_operand:QI 1 "pseudo_register_operand" "")
(match_operand:QI 2 "pseudo_register_operand" "")))
- (set (match_operand:QI 3 "pseudo_register_operand" "")
+ (set (match_operand:QI 3 "pseudo_register_operand" "")
(umod:QI (match_dup 1) (match_dup 2)))
(clobber (reg:QI 22))
(clobber (reg:QI 23))
[(set (reg:QI 24) (match_dup 1))
(set (reg:QI 22) (match_dup 2))
(parallel [(set (reg:QI 24) (udiv:QI (reg:QI 24) (reg:QI 22)))
- (set (reg:QI 25) (umod:QI (reg:QI 24) (reg:QI 22)))
- (clobber (reg:QI 23))])
+ (set (reg:QI 25) (umod:QI (reg:QI 24) (reg:QI 22)))
+ (clobber (reg:QI 23))])
(set (match_dup 0) (reg:QI 24))
(set (match_dup 3) (reg:QI 25))]
"")
[(set (reg:HI 24) (match_dup 1))
(set (reg:HI 22) (match_dup 2))
(parallel [(set (reg:HI 22) (div:HI (reg:HI 24) (reg:HI 22)))
- (set (reg:HI 24) (mod:HI (reg:HI 24) (reg:HI 22)))
- (clobber (reg:HI 26))
- (clobber (reg:QI 21))])
+ (set (reg:HI 24) (mod:HI (reg:HI 24) (reg:HI 22)))
+ (clobber (reg:HI 26))
+ (clobber (reg:QI 21))])
(set (match_dup 0) (reg:HI 22))
(set (match_dup 3) (reg:HI 24))]
"")
[(parallel [(set (match_operand:HI 0 "pseudo_register_operand" "")
(udiv:HI (match_operand:HI 1 "pseudo_register_operand" "")
(match_operand:HI 2 "pseudo_register_operand" "")))
- (set (match_operand:HI 3 "pseudo_register_operand" "")
+ (set (match_operand:HI 3 "pseudo_register_operand" "")
(umod:HI (match_dup 1) (match_dup 2)))
(clobber (reg:QI 21))
(clobber (reg:HI 22))
[(set (reg:HI 24) (match_dup 1))
(set (reg:HI 22) (match_dup 2))
(parallel [(set (reg:HI 22) (udiv:HI (reg:HI 24) (reg:HI 22)))
- (set (reg:HI 24) (umod:HI (reg:HI 24) (reg:HI 22)))
- (clobber (reg:HI 26))
- (clobber (reg:QI 21))])
+ (set (reg:HI 24) (umod:HI (reg:HI 24) (reg:HI 22)))
+ (clobber (reg:HI 26))
+ (clobber (reg:QI 21))])
(set (match_dup 0) (reg:HI 22))
(set (match_dup 3) (reg:HI 24))]
"")
(set_attr "cc" "clobber")])
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;; 24-bit multiply
+
+;; To support widening multiplication with constant we postpone
+;; expanding to the implicit library call until post combine and
+;; prior to register allocation. Clobber all hard registers that
+;; might be used by the (widening) multiply until it is split and
+;; it's final register footprint is worked out.
+
+(define_expand "mulpsi3"
+ [(parallel [(set (match_operand:PSI 0 "register_operand" "")
+ (mult:PSI (match_operand:PSI 1 "register_operand" "")
+ (match_operand:PSI 2 "nonmemory_operand" "")))
+ (clobber (reg:HI 26))
+ (clobber (reg:DI 18))])]
+ "AVR_HAVE_MUL"
+ {
+ if (s8_operand (operands[2], PSImode))
+ {
+ rtx reg = force_reg (QImode, gen_int_mode (INTVAL (operands[2]), QImode));
+ emit_insn (gen_mulsqipsi3 (operands[0], reg, operands[1]));
+ DONE;
+ }
+ })
+
+(define_insn "*umulqihipsi3"
+ [(set (match_operand:PSI 0 "register_operand" "=&r")
+ (mult:PSI (zero_extend:PSI (match_operand:QI 1 "register_operand" "r"))
+ (zero_extend:PSI (match_operand:HI 2 "register_operand" "r"))))]
+ "AVR_HAVE_MUL"
+ "mul %1,%A2
+ movw %A0,r0
+ mul %1,%B2
+ clr %C0
+ add %B0,r0
+ adc %C0,r1
+ clr __zero_reg__"
+ [(set_attr "length" "7")
+ (set_attr "cc" "clobber")])
+
+(define_insn "*umulhiqipsi3"
+ [(set (match_operand:PSI 0 "register_operand" "=&r")
+ (mult:PSI (zero_extend:PSI (match_operand:HI 2 "register_operand" "r"))
+ (zero_extend:PSI (match_operand:QI 1 "register_operand" "r"))))]
+ "AVR_HAVE_MUL"
+ "mul %1,%A2
+ movw %A0,r0
+ mul %1,%B2
+ add %B0,r0
+ mov %C0,r1
+ clr __zero_reg__
+ adc %C0,__zero_reg__"
+ [(set_attr "length" "7")
+ (set_attr "cc" "clobber")])
+
+(define_insn_and_split "mulsqipsi3"
+ [(set (match_operand:PSI 0 "pseudo_register_operand" "=r")
+ (mult:PSI (sign_extend:PSI (match_operand:QI 1 "pseudo_register_operand" "r"))
+ (match_operand:PSI 2 "pseudo_register_or_const_int_operand" "rn")))
+ (clobber (reg:HI 26))
+ (clobber (reg:DI 18))]
+ "AVR_HAVE_MUL && !reload_completed"
+ { gcc_unreachable(); }
+ "&& 1"
+ [(set (reg:QI 25)
+ (match_dup 1))
+ (set (reg:PSI 22)
+ (match_dup 2))
+ (set (reg:PSI 18)
+ (mult:PSI (sign_extend:PSI (reg:QI 25))
+ (reg:PSI 22)))
+ (set (match_dup 0)
+ (reg:PSI 18))])
+
+(define_insn_and_split "*mulpsi3"
+ [(set (match_operand:PSI 0 "pseudo_register_operand" "=r")
+ (mult:PSI (match_operand:PSI 1 "pseudo_register_operand" "r")
+ (match_operand:PSI 2 "pseudo_register_or_const_int_operand" "rn")))
+ (clobber (reg:HI 26))
+ (clobber (reg:DI 18))]
+ "AVR_HAVE_MUL && !reload_completed"
+ { gcc_unreachable(); }
+ "&& 1"
+ [(set (reg:PSI 18)
+ (match_dup 1))
+ (set (reg:PSI 22)
+ (match_dup 2))
+ (parallel [(set (reg:PSI 22)
+ (mult:PSI (reg:PSI 22)
+ (reg:PSI 18)))
+ (clobber (reg:QI 21))
+ (clobber (reg:QI 25))
+ (clobber (reg:HI 26))])
+ (set (match_dup 0)
+ (reg:PSI 22))]
+ {
+ if (s8_operand (operands[2], PSImode))
+ {
+ rtx reg = force_reg (QImode, gen_int_mode (INTVAL (operands[2]), QImode));
+ emit_insn (gen_mulsqipsi3 (operands[0], reg, operands[1]));
+ DONE;
+ }
+ })
+
+(define_insn "*mulsqipsi3.libgcc"
+ [(set (reg:PSI 18)
+ (mult:PSI (sign_extend:PSI (reg:QI 25))
+ (reg:PSI 22)))]
+ "AVR_HAVE_MUL"
+ "%~call __mulsqipsi3"
+ [(set_attr "type" "xcall")
+ (set_attr "cc" "clobber")])
+
+(define_insn "*mulpsi3.libgcc"
+ [(set (reg:PSI 22)
+ (mult:PSI (reg:PSI 22)
+ (reg:PSI 18)))
+ (clobber (reg:QI 21))
+ (clobber (reg:QI 25))
+ (clobber (reg:HI 26))]
+ "AVR_HAVE_MUL"
+ "%~call __mulpsi3"
+ [(set_attr "type" "xcall")
+ (set_attr "cc" "clobber")])
+
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;; 24-bit signed/unsigned division and modulo.
;; Notice that the libgcc implementation return the quotient in R22
;; and the remainder in R18 whereas the 32-bit [u]divmodsi4
[(set (reg:SI 22) (match_dup 1))
(set (reg:SI 18) (match_dup 2))
(parallel [(set (reg:SI 18) (div:SI (reg:SI 22) (reg:SI 18)))
- (set (reg:SI 22) (mod:SI (reg:SI 22) (reg:SI 18)))
- (clobber (reg:HI 26))
- (clobber (reg:HI 30))])
+ (set (reg:SI 22) (mod:SI (reg:SI 22) (reg:SI 18)))
+ (clobber (reg:HI 26))
+ (clobber (reg:HI 30))])
(set (match_dup 0) (reg:SI 18))
(set (match_dup 3) (reg:SI 22))]
"")
[(set (reg:SI 22) (match_dup 1))
(set (reg:SI 18) (match_dup 2))
(parallel [(set (reg:SI 18) (udiv:SI (reg:SI 22) (reg:SI 18)))
- (set (reg:SI 22) (umod:SI (reg:SI 22) (reg:SI 18)))
- (clobber (reg:HI 26))
- (clobber (reg:HI 30))])
+ (set (reg:SI 22) (umod:SI (reg:SI 22) (reg:SI 18)))
+ (clobber (reg:HI 26))
+ (clobber (reg:HI 30))])
(set (match_dup 0) (reg:SI 18))
(set (match_dup 3) (reg:SI 22))]
"")
(define_peephole2 ; andi
[(set (match_operand:QI 0 "d_register_operand" "")
(and:QI (match_dup 0)
- (match_operand:QI 1 "const_int_operand" "")))
+ (match_operand:QI 1 "const_int_operand" "")))
(set (match_dup 0)
(and:QI (match_dup 0)
- (match_operand:QI 2 "const_int_operand" "")))]
+ (match_operand:QI 2 "const_int_operand" "")))]
""
[(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))]
{
[(set_attr "length" "2,4,4,1,3,5,3,0")
(set_attr "cc" "set_n,set_n,clobber,none,set_n,set_n,clobber,none")])
-;; Split all rotates of HI,SI and DImode registers where rotation is by
+;; Split all rotates of HI,SI and PSImode registers where rotation is by
;; a whole number of bytes. The split creates the appropriate moves and
-;; considers all overlap situations. DImode is split before reload.
+;; considers all overlap situations.
;; HImode does not need scratch. Use attribute for this constraint.
-;; Use QI scratch for DI mode as this is often split into byte sized operands.
-(define_mode_attr rotx [(DI "&r,&r,X") (SI "&r,&r,X") (PSI "&r,&r,X") (HI "X,X,X")])
-(define_mode_attr rotsmode [(DI "QI") (SI "HI") (PSI "QI") (HI "QI")])
+(define_mode_attr rotx [(SI "&r,&r,X") (PSI "&r,&r,X") (HI "X,X,X")])
+(define_mode_attr rotsmode [(SI "HI") (PSI "QI") (HI "QI")])
;; "rotlhi3"
;; "rotlpsi3"
;; "rotlsi3"
-;; "rotldi3"
(define_expand "rotl<mode>3"
- [(parallel [(set (match_operand:HIDI 0 "register_operand" "")
- (rotate:HIDI (match_operand:HIDI 1 "register_operand" "")
+ [(parallel [(set (match_operand:HISI 0 "register_operand" "")
+ (rotate:HISI (match_operand:HISI 1 "register_operand" "")
(match_operand:VOID 2 "const_int_operand" "")))
(clobber (match_dup 3))])]
""
else
operands[3] = gen_rtx_SCRATCH (QImode);
}
- else if (<MODE>mode != DImode
- && (offset == 1
- || offset == GET_MODE_BITSIZE (<MODE>mode) -1))
+ else if (offset == 1
+ || offset == GET_MODE_BITSIZE (<MODE>mode) -1)
{
/*; Support rotate left/right by 1 */
;; "*rotwhi"
;; "*rotwsi"
-;; "*rotwdi"
(define_insn_and_split "*rotw<mode>"
- [(set (match_operand:HIDI 0 "register_operand" "=r,r,#&r")
- (rotate:HIDI (match_operand:HIDI 1 "register_operand" "0,r,r")
- (match_operand 2 "const_int_operand" "n,n,n")))
+ [(set (match_operand:HISI 0 "register_operand" "=r,r,#&r")
+ (rotate:HISI (match_operand:HISI 1 "register_operand" "0,r,r")
+ (match_operand 2 "const_int_operand" "n,n,n")))
(clobber (match_scratch:<rotsmode> 3 "=<rotx>"))]
"AVR_HAVE_MOVW
&& CONST_INT_P (operands[2])
&& GET_MODE_SIZE (<MODE>mode) % 2 == 0
&& 0 == INTVAL (operands[2]) % 16"
"#"
- "&& (reload_completed || <MODE>mode == DImode)"
+ "&& reload_completed"
[(const_int 0)]
{
avr_rotate_bytes (operands);
;; "*rotbhi"
;; "*rotbpsi"
;; "*rotbsi"
-;; "*rotbdi"
(define_insn_and_split "*rotb<mode>"
- [(set (match_operand:HIDI 0 "register_operand" "=r,r,#&r")
- (rotate:HIDI (match_operand:HIDI 1 "register_operand" "0,r,r")
- (match_operand 2 "const_int_operand" "n,n,n")))
+ [(set (match_operand:HISI 0 "register_operand" "=r,r,#&r")
+ (rotate:HISI (match_operand:HISI 1 "register_operand" "0,r,r")
+ (match_operand 2 "const_int_operand" "n,n,n")))
(clobber (match_scratch:QI 3 "=<rotx>"))]
"CONST_INT_P (operands[2])
&& (8 == INTVAL (operands[2]) % 16
|| GET_MODE_SIZE (<MODE>mode) % 2 != 0)
&& 0 == INTVAL (operands[2]) % 16))"
"#"
- "&& (reload_completed || <MODE>mode == DImode)"
+ "&& reload_completed"
[(const_int 0)]
{
avr_rotate_bytes (operands);
(define_split ; ashlqi3_const4
[(set (match_operand:QI 0 "d_register_operand" "")
- (ashift:QI (match_dup 0)
- (const_int 4)))]
+ (ashift:QI (match_dup 0)
+ (const_int 4)))]
""
[(set (match_dup 0) (rotate:QI (match_dup 0) (const_int 4)))
(set (match_dup 0) (and:QI (match_dup 0) (const_int -16)))]
(define_split ; ashlqi3_const5
[(set (match_operand:QI 0 "d_register_operand" "")
- (ashift:QI (match_dup 0)
- (const_int 5)))]
+ (ashift:QI (match_dup 0)
+ (const_int 5)))]
""
[(set (match_dup 0) (rotate:QI (match_dup 0) (const_int 4)))
(set (match_dup 0) (ashift:QI (match_dup 0) (const_int 1)))
(define_split ; ashlqi3_const6
[(set (match_operand:QI 0 "d_register_operand" "")
- (ashift:QI (match_dup 0)
- (const_int 6)))]
+ (ashift:QI (match_dup 0)
+ (const_int 6)))]
""
[(set (match_dup 0) (rotate:QI (match_dup 0) (const_int 4)))
(set (match_dup 0) (ashift:QI (match_dup 0) (const_int 2)))
(define_peephole2 ; ashlqi3_l_const4
[(set (match_operand:QI 0 "l_register_operand" "")
- (ashift:QI (match_dup 0)
- (const_int 4)))
+ (ashift:QI (match_dup 0)
+ (const_int 4)))
(match_scratch:QI 1 "d")]
""
[(set (match_dup 0) (rotate:QI (match_dup 0) (const_int 4)))
(define_peephole2 ; ashlqi3_l_const5
[(set (match_operand:QI 0 "l_register_operand" "")
- (ashift:QI (match_dup 0)
- (const_int 5)))
+ (ashift:QI (match_dup 0)
+ (const_int 5)))
(match_scratch:QI 1 "d")]
""
[(set (match_dup 0) (rotate:QI (match_dup 0) (const_int 4)))
(define_peephole2 ; ashlqi3_l_const6
[(set (match_operand:QI 0 "l_register_operand" "")
- (ashift:QI (match_dup 0)
- (const_int 6)))
+ (ashift:QI (match_dup 0)
+ (const_int 6)))
(match_scratch:QI 1 "d")]
""
[(set (match_dup 0) (rotate:QI (match_dup 0) (const_int 4)))
(define_peephole2
[(match_scratch:QI 3 "d")
(set (match_operand:HI 0 "register_operand" "")
- (ashift:HI (match_operand:HI 1 "register_operand" "")
- (match_operand:QI 2 "const_int_operand" "")))]
+ (ashift:HI (match_operand:HI 1 "register_operand" "")
+ (match_operand:QI 2 "const_int_operand" "")))]
""
[(parallel [(set (match_dup 0) (ashift:HI (match_dup 1) (match_dup 2)))
- (clobber (match_dup 3))])]
+ (clobber (match_dup 3))])]
"")
(define_insn "*ashlhi3_const"
(define_peephole2
[(match_scratch:QI 3 "d")
(set (match_operand:SI 0 "register_operand" "")
- (ashift:SI (match_operand:SI 1 "register_operand" "")
- (match_operand:QI 2 "const_int_operand" "")))]
+ (ashift:SI (match_operand:SI 1 "register_operand" "")
+ (match_operand:QI 2 "const_int_operand" "")))]
""
[(parallel [(set (match_dup 0) (ashift:SI (match_dup 1) (match_dup 2)))
- (clobber (match_dup 3))])]
+ (clobber (match_dup 3))])]
"")
(define_insn "*ashlsi3_const"
(set_attr "adjust_len" "ashlsi")
(set_attr "cc" "none,set_n,clobber,clobber")])
-(define_insn "ashlpsi3"
+(define_expand "ashlpsi3"
+ [(parallel [(set (match_operand:PSI 0 "register_operand" "")
+ (ashift:PSI (match_operand:PSI 1 "register_operand" "")
+ (match_operand:QI 2 "nonmemory_operand" "")))
+ (clobber (scratch:QI))])]
+ ""
+ {
+ if (AVR_HAVE_MUL
+ && CONST_INT_P (operands[2]))
+ {
+ if (IN_RANGE (INTVAL (operands[2]), 3, 6))
+ {
+ rtx xoffset = force_reg (QImode, gen_int_mode (1 << INTVAL (operands[2]), QImode));
+ emit_insn (gen_mulsqipsi3 (operands[0], xoffset, operands[1]));
+ DONE;
+ }
+ else if (optimize_insn_for_speed_p ()
+ && INTVAL (operands[2]) != 16
+ && IN_RANGE (INTVAL (operands[2]), 9, 22))
+ {
+ rtx xoffset = force_reg (PSImode, gen_int_mode (1 << INTVAL (operands[2]), PSImode));
+ emit_insn (gen_mulpsi3 (operands[0], operands[1], xoffset));
+ DONE;
+ }
+ }
+ })
+
+(define_insn "*ashlpsi3"
[(set (match_operand:PSI 0 "register_operand" "=r,r,r,r")
(ashift:PSI (match_operand:PSI 1 "register_operand" "0,0,r,0")
(match_operand:QI 2 "nonmemory_operand" "r,P,O,n")))
(define_peephole2
[(match_scratch:QI 3 "d")
(set (match_operand:HI 0 "register_operand" "")
- (ashiftrt:HI (match_operand:HI 1 "register_operand" "")
- (match_operand:QI 2 "const_int_operand" "")))]
+ (ashiftrt:HI (match_operand:HI 1 "register_operand" "")
+ (match_operand:QI 2 "const_int_operand" "")))]
""
[(parallel [(set (match_dup 0) (ashiftrt:HI (match_dup 1) (match_dup 2)))
- (clobber (match_dup 3))])]
+ (clobber (match_dup 3))])]
"")
(define_insn "*ashrhi3_const"
(define_peephole2
[(match_scratch:QI 3 "d")
(set (match_operand:SI 0 "register_operand" "")
- (ashiftrt:SI (match_operand:SI 1 "register_operand" "")
- (match_operand:QI 2 "const_int_operand" "")))]
+ (ashiftrt:SI (match_operand:SI 1 "register_operand" "")
+ (match_operand:QI 2 "const_int_operand" "")))]
""
[(parallel [(set (match_dup 0) (ashiftrt:SI (match_dup 1) (match_dup 2)))
- (clobber (match_dup 3))])]
+ (clobber (match_dup 3))])]
"")
(define_insn "*ashrsi3_const"
(define_split ; lshrqi3_const4
[(set (match_operand:QI 0 "d_register_operand" "")
- (lshiftrt:QI (match_dup 0)
- (const_int 4)))]
+ (lshiftrt:QI (match_dup 0)
+ (const_int 4)))]
""
[(set (match_dup 0) (rotate:QI (match_dup 0) (const_int 4)))
(set (match_dup 0) (and:QI (match_dup 0) (const_int 15)))]
(define_split ; lshrqi3_const5
[(set (match_operand:QI 0 "d_register_operand" "")
- (lshiftrt:QI (match_dup 0)
- (const_int 5)))]
+ (lshiftrt:QI (match_dup 0)
+ (const_int 5)))]
""
[(set (match_dup 0) (rotate:QI (match_dup 0) (const_int 4)))
(set (match_dup 0) (lshiftrt:QI (match_dup 0) (const_int 1)))
(define_split ; lshrqi3_const6
[(set (match_operand:QI 0 "d_register_operand" "")
- (lshiftrt:QI (match_dup 0)
- (const_int 6)))]
+ (lshiftrt:QI (match_dup 0)
+ (const_int 6)))]
""
[(set (match_dup 0) (rotate:QI (match_dup 0) (const_int 4)))
(set (match_dup 0) (lshiftrt:QI (match_dup 0) (const_int 2)))
(define_peephole2 ; lshrqi3_l_const4
[(set (match_operand:QI 0 "l_register_operand" "")
- (lshiftrt:QI (match_dup 0)
- (const_int 4)))
+ (lshiftrt:QI (match_dup 0)
+ (const_int 4)))
(match_scratch:QI 1 "d")]
""
[(set (match_dup 0) (rotate:QI (match_dup 0) (const_int 4)))
(define_peephole2 ; lshrqi3_l_const5
[(set (match_operand:QI 0 "l_register_operand" "")
- (lshiftrt:QI (match_dup 0)
- (const_int 5)))
+ (lshiftrt:QI (match_dup 0)
+ (const_int 5)))
(match_scratch:QI 1 "d")]
""
[(set (match_dup 0) (rotate:QI (match_dup 0) (const_int 4)))
(define_peephole2 ; lshrqi3_l_const6
[(set (match_operand:QI 0 "l_register_operand" "")
- (lshiftrt:QI (match_dup 0)
- (const_int 6)))
+ (lshiftrt:QI (match_dup 0)
+ (const_int 6)))
(match_scratch:QI 1 "d")]
""
[(set (match_dup 0) (rotate:QI (match_dup 0) (const_int 4)))
(define_peephole2
[(match_scratch:QI 3 "d")
(set (match_operand:HI 0 "register_operand" "")
- (lshiftrt:HI (match_operand:HI 1 "register_operand" "")
- (match_operand:QI 2 "const_int_operand" "")))]
+ (lshiftrt:HI (match_operand:HI 1 "register_operand" "")
+ (match_operand:QI 2 "const_int_operand" "")))]
""
[(parallel [(set (match_dup 0) (lshiftrt:HI (match_dup 1) (match_dup 2)))
- (clobber (match_dup 3))])]
+ (clobber (match_dup 3))])]
"")
(define_insn "*lshrhi3_const"
(define_peephole2
[(match_scratch:QI 3 "d")
(set (match_operand:SI 0 "register_operand" "")
- (lshiftrt:SI (match_operand:SI 1 "register_operand" "")
- (match_operand:QI 2 "const_int_operand" "")))]
+ (lshiftrt:SI (match_operand:SI 1 "register_operand" "")
+ (match_operand:QI 2 "const_int_operand" "")))]
""
[(parallel [(set (match_dup 0) (lshiftrt:SI (match_dup 1) (match_dup 2)))
- (clobber (match_dup 3))])]
+ (clobber (match_dup 3))])]
"")
(define_insn "*lshrsi3_const"
""
"neg %0"
[(set_attr "length" "1")
- (set_attr "cc" "set_zn")])
+ (set_attr "cc" "set_vzn")])
(define_insn "*negqihi2"
[(set (match_operand:HI 0 "register_operand" "=r")
(set_attr "cc" "set_n")])
(define_insn "neghi2"
- [(set (match_operand:HI 0 "register_operand" "=!d,r,&r")
- (neg:HI (match_operand:HI 1 "register_operand" "0,0,r")))]
+ [(set (match_operand:HI 0 "register_operand" "=r,&r")
+ (neg:HI (match_operand:HI 1 "register_operand" "0,r")))]
""
"@
- com %B0\;neg %A0\;sbci %B0,lo8(-1)
- com %B0\;neg %A0\;sbc %B0,__zero_reg__\;inc %B0
+ neg %B0\;neg %A0\;sbc %B0,__zero_reg__
clr %A0\;clr %B0\;sub %A0,%A1\;sbc %B0,%B1"
- [(set_attr "length" "3,4,4")
- (set_attr "cc" "set_czn,set_n,set_czn")])
+ [(set_attr "length" "3,4")
+ (set_attr "cc" "set_czn")])
(define_insn "negpsi2"
[(set (match_operand:PSI 0 "register_operand" "=!d,r,&r")
(define_insn "*negated_tstqi"
[(set (cc0)
(compare (neg:QI (match_operand:QI 0 "register_operand" "r"))
- (const_int 0)))]
+ (const_int 0)))]
"(!flag_wrapv && !flag_trapv && flag_strict_overflow)"
"cp __zero_reg__,%0"
[(set_attr "cc" "compare")
(define_insn "*reversed_tstqi"
[(set (cc0)
(compare (const_int 0)
- (match_operand:QI 0 "register_operand" "r")))]
+ (match_operand:QI 0 "register_operand" "r")))]
""
"cp __zero_reg__,%0"
[(set_attr "cc" "compare")
(define_insn "*negated_tsthi"
[(set (cc0)
(compare (neg:HI (match_operand:HI 0 "register_operand" "r"))
- (const_int 0)))]
+ (const_int 0)))]
"(!flag_wrapv && !flag_trapv && flag_strict_overflow)"
"cp __zero_reg__,%A0
cpc __zero_reg__,%B0"
(define_insn "*reversed_tsthi"
[(set (cc0)
(compare (const_int 0)
- (match_operand:HI 0 "register_operand" "r")))
+ (match_operand:HI 0 "register_operand" "r")))
(clobber (match_scratch:QI 1 "=X"))]
""
"cp __zero_reg__,%A0
(define_insn "*negated_tstsi"
[(set (cc0)
(compare (neg:SI (match_operand:SI 0 "register_operand" "r"))
- (const_int 0)))]
+ (const_int 0)))]
"(!flag_wrapv && !flag_trapv && flag_strict_overflow)"
"cp __zero_reg__,%A0
cpc __zero_reg__,%B0
(define_insn "*reversed_tstsi"
[(set (cc0)
(compare (const_int 0)
- (match_operand:SI 0 "register_operand" "r")))
+ (match_operand:SI 0 "register_operand" "r")))
(clobber (match_scratch:QI 1 "=X"))]
""
"cp __zero_reg__,%A0
(define_insn "*cmpqi"
[(set (cc0)
(compare (match_operand:QI 0 "register_operand" "r,r,d")
- (match_operand:QI 1 "nonmemory_operand" "L,r,i")))]
+ (match_operand:QI 1 "nonmemory_operand" "L,r,i")))]
""
"@
tst %0
(define_expand "cbranchsi4"
[(parallel [(set (cc0)
- (compare (match_operand:SI 1 "register_operand" "")
- (match_operand:SI 2 "nonmemory_operand" "")))
- (clobber (match_scratch:QI 4 ""))])
+ (compare (match_operand:SI 1 "register_operand" "")
+ (match_operand:SI 2 "nonmemory_operand" "")))
+ (clobber (match_scratch:QI 4 ""))])
(set (pc)
(if_then_else
(match_operator 0 "ordered_comparison_operator" [(cc0)
(define_expand "cbranchhi4"
[(parallel [(set (cc0)
- (compare (match_operand:HI 1 "register_operand" "")
- (match_operand:HI 2 "nonmemory_operand" "")))
- (clobber (match_scratch:QI 4 ""))])
+ (compare (match_operand:HI 1 "register_operand" "")
+ (match_operand:HI 2 "nonmemory_operand" "")))
+ (clobber (match_scratch:QI 4 ""))])
(set (pc)
(if_then_else
(match_operator 0 "ordered_comparison_operator" [(cc0)
(define_insn "*sbrx_branch<mode>"
[(set (pc)
(if_then_else
- (match_operator 0 "eqne_operator"
- [(zero_extract:QIDI
- (match_operand:VOID 1 "register_operand" "r")
- (const_int 1)
- (match_operand 2 "const_int_operand" "n"))
- (const_int 0)])
- (label_ref (match_operand 3 "" ""))
- (pc)))]
- ""
- "* return avr_out_sbxx_branch (insn, operands);"
+ (match_operator 0 "eqne_operator"
+ [(zero_extract:QIDI
+ (match_operand:VOID 1 "register_operand" "r")
+ (const_int 1)
+ (match_operand 2 "const_int_operand" "n"))
+ (const_int 0)])
+ (label_ref (match_operand 3 "" ""))
+ (pc)))]
+ ""
+ {
+ return avr_out_sbxx_branch (insn, operands);
+ }
[(set (attr "length")
- (if_then_else (and (ge (minus (pc) (match_dup 3)) (const_int -2046))
- (le (minus (pc) (match_dup 3)) (const_int 2046)))
- (const_int 2)
- (if_then_else (match_test "!AVR_HAVE_JMP_CALL")
- (const_int 2)
- (const_int 4))))
+ (if_then_else (and (ge (minus (pc) (match_dup 3)) (const_int -2046))
+ (le (minus (pc) (match_dup 3)) (const_int 2046)))
+ (const_int 2)
+ (if_then_else (match_test "!AVR_HAVE_JMP_CALL")
+ (const_int 2)
+ (const_int 4))))
(set_attr "cc" "clobber")])
;; Same test based on Bitwise AND RTL. Keep this incase gcc changes patterns.
(define_insn "*sbrx_and_branch<mode>"
[(set (pc)
(if_then_else
- (match_operator 0 "eqne_operator"
- [(and:QISI
- (match_operand:QISI 1 "register_operand" "r")
- (match_operand:QISI 2 "single_one_operand" "n"))
- (const_int 0)])
- (label_ref (match_operand 3 "" ""))
- (pc)))]
+ (match_operator 0 "eqne_operator"
+ [(and:QISI
+ (match_operand:QISI 1 "register_operand" "r")
+ (match_operand:QISI 2 "single_one_operand" "n"))
+ (const_int 0)])
+ (label_ref (match_operand 3 "" ""))
+ (pc)))]
""
{
HOST_WIDE_INT bitnumber;
return avr_out_sbxx_branch (insn, operands);
}
[(set (attr "length")
- (if_then_else (and (ge (minus (pc) (match_dup 3)) (const_int -2046))
- (le (minus (pc) (match_dup 3)) (const_int 2046)))
- (const_int 2)
- (if_then_else (match_test "!AVR_HAVE_JMP_CALL")
- (const_int 2)
- (const_int 4))))
+ (if_then_else (and (ge (minus (pc) (match_dup 3)) (const_int -2046))
+ (le (minus (pc) (match_dup 3)) (const_int 2046)))
+ (const_int 2)
+ (if_then_else (match_test "!AVR_HAVE_JMP_CALL")
+ (const_int 2)
+ (const_int 4))))
(set_attr "cc" "clobber")])
;; Convert sign tests to bit 7/15/31 tests that match the above insns.
(define_peephole2
[(set (cc0) (compare (match_operand:QI 0 "register_operand" "")
- (const_int 0)))
+ (const_int 0)))
(set (pc) (if_then_else (ge (cc0) (const_int 0))
- (label_ref (match_operand 1 "" ""))
- (pc)))]
+ (label_ref (match_operand 1 "" ""))
+ (pc)))]
""
[(set (pc) (if_then_else (eq (zero_extract:HI (match_dup 0)
- (const_int 1)
- (const_int 7))
- (const_int 0))
- (label_ref (match_dup 1))
- (pc)))]
+ (const_int 1)
+ (const_int 7))
+ (const_int 0))
+ (label_ref (match_dup 1))
+ (pc)))]
"")
(define_peephole2
[(set (cc0) (compare (match_operand:QI 0 "register_operand" "")
- (const_int 0)))
+ (const_int 0)))
(set (pc) (if_then_else (lt (cc0) (const_int 0))
- (label_ref (match_operand 1 "" ""))
- (pc)))]
+ (label_ref (match_operand 1 "" ""))
+ (pc)))]
""
[(set (pc) (if_then_else (ne (zero_extract:HI (match_dup 0)
- (const_int 1)
- (const_int 7))
- (const_int 0))
- (label_ref (match_dup 1))
- (pc)))]
+ (const_int 1)
+ (const_int 7))
+ (const_int 0))
+ (label_ref (match_dup 1))
+ (pc)))]
"")
(define_peephole2
[(parallel [(set (cc0) (compare (match_operand:HI 0 "register_operand" "")
- (const_int 0)))
- (clobber (match_operand:HI 2 ""))])
+ (const_int 0)))
+ (clobber (match_operand:HI 2 ""))])
(set (pc) (if_then_else (ge (cc0) (const_int 0))
- (label_ref (match_operand 1 "" ""))
- (pc)))]
+ (label_ref (match_operand 1 "" ""))
+ (pc)))]
""
[(set (pc) (if_then_else (eq (and:HI (match_dup 0) (const_int -32768))
- (const_int 0))
- (label_ref (match_dup 1))
- (pc)))]
+ (const_int 0))
+ (label_ref (match_dup 1))
+ (pc)))]
"")
(define_peephole2
[(parallel [(set (cc0) (compare (match_operand:HI 0 "register_operand" "")
- (const_int 0)))
- (clobber (match_operand:HI 2 ""))])
+ (const_int 0)))
+ (clobber (match_operand:HI 2 ""))])
(set (pc) (if_then_else (lt (cc0) (const_int 0))
- (label_ref (match_operand 1 "" ""))
- (pc)))]
+ (label_ref (match_operand 1 "" ""))
+ (pc)))]
""
[(set (pc) (if_then_else (ne (and:HI (match_dup 0) (const_int -32768))
- (const_int 0))
- (label_ref (match_dup 1))
- (pc)))]
+ (const_int 0))
+ (label_ref (match_dup 1))
+ (pc)))]
"")
(define_peephole2
[(parallel [(set (cc0) (compare (match_operand:SI 0 "register_operand" "")
- (const_int 0)))
- (clobber (match_operand:SI 2 ""))])
+ (const_int 0)))
+ (clobber (match_operand:SI 2 ""))])
(set (pc) (if_then_else (ge (cc0) (const_int 0))
- (label_ref (match_operand 1 "" ""))
- (pc)))]
+ (label_ref (match_operand 1 "" ""))
+ (pc)))]
""
[(set (pc) (if_then_else (eq (and:SI (match_dup 0) (match_dup 2))
- (const_int 0))
- (label_ref (match_dup 1))
- (pc)))]
+ (const_int 0))
+ (label_ref (match_dup 1))
+ (pc)))]
"operands[2] = GEN_INT (-2147483647 - 1);")
(define_peephole2
[(parallel [(set (cc0) (compare (match_operand:SI 0 "register_operand" "")
- (const_int 0)))
- (clobber (match_operand:SI 2 ""))])
+ (const_int 0)))
+ (clobber (match_operand:SI 2 ""))])
(set (pc) (if_then_else (lt (cc0) (const_int 0))
- (label_ref (match_operand 1 "" ""))
- (pc)))]
+ (label_ref (match_operand 1 "" ""))
+ (pc)))]
""
[(set (pc) (if_then_else (ne (and:SI (match_dup 0) (match_dup 2))
- (const_int 0))
- (label_ref (match_dup 1))
- (pc)))]
+ (const_int 0))
+ (label_ref (match_dup 1))
+ (pc)))]
"operands[2] = GEN_INT (-2147483647 - 1);")
;; ************************************************************************
(label_ref (match_operand 0 "" ""))
(pc)))]
""
- "*
- return ret_cond_branch (operands[1], avr_jump_mode (operands[0],insn), 0);"
+ {
+ return ret_cond_branch (operands[1], avr_jump_mode (operands[0], insn), 0);
+ }
[(set_attr "type" "branch1")
(set_attr "cc" "clobber")])
(define_insn "rvbranch"
[(set (pc)
(if_then_else (match_operator 1 "simple_comparison_operator"
- [(cc0)
- (const_int 0)])
+ [(cc0)
+ (const_int 0)])
(pc)
(label_ref (match_operand 0 "" ""))))]
""
- "*
- return ret_cond_branch (operands[1], avr_jump_mode (operands[0], insn), 1);"
+ {
+ return ret_cond_branch (operands[1], avr_jump_mode (operands[0], insn), 1);
+ }
[(set_attr "type" "branch1")
(set_attr "cc" "clobber")])
(define_insn "difficult_rvbranch"
[(set (pc)
(if_then_else (match_operator 1 "difficult_comparison_operator"
- [(cc0)
- (const_int 0)])
+ [(cc0)
+ (const_int 0)])
(pc)
(label_ref (match_operand 0 "" ""))))]
""
- "*
- return ret_cond_branch (operands[1], avr_jump_mode (operands[0], insn), 1);"
+ {
+ return ret_cond_branch (operands[1], avr_jump_mode (operands[0], insn), 1);
+ }
[(set_attr "type" "branch")
(set_attr "cc" "clobber")])
: "rjmp %x0";
}
[(set (attr "length")
- (if_then_else (match_operand 0 "symbol_ref_operand" "")
+ (if_then_else (match_operand 0 "symbol_ref_operand" "")
(if_then_else (match_test "!AVR_HAVE_JMP_CALL")
(const_int 1)
(const_int 2))
(define_expand "casesi"
[(set (match_dup 6)
- (minus:HI (subreg:HI (match_operand:SI 0 "register_operand" "") 0)
- (match_operand:HI 1 "register_operand" "")))
+ (minus:HI (subreg:HI (match_operand:SI 0 "register_operand" "") 0)
+ (match_operand:HI 1 "register_operand" "")))
(parallel [(set (cc0)
- (compare (match_dup 6)
- (match_operand:HI 2 "register_operand" "")))
- (clobber (match_scratch:QI 9 ""))])
+ (compare (match_dup 6)
+ (match_operand:HI 2 "register_operand" "")))
+ (clobber (match_scratch:QI 9 ""))])
(set (pc)
- (if_then_else (gtu (cc0)
- (const_int 0))
- (label_ref (match_operand 4 "" ""))
- (pc)))
+ (if_then_else (gtu (cc0)
+ (const_int 0))
+ (label_ref (match_operand 4 "" ""))
+ (pc)))
(set (match_dup 6)
- (plus:HI (match_dup 6) (label_ref (match_operand:HI 3 "" ""))))
+ (plus:HI (match_dup 6) (label_ref (match_operand:HI 3 "" ""))))
(parallel [(set (pc) (unspec:HI [(match_dup 6)] UNSPEC_INDEX_JMP))
- (use (label_ref (match_dup 3)))
- (clobber (match_dup 6))])]
+ (use (label_ref (match_dup 3)))
+ (clobber (match_dup 6))])]
""
- "
-{
- operands[6] = gen_reg_rtx (HImode);
-}")
+ {
+ operands[6] = gen_reg_rtx (HImode);
+ })
;; ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
[(set (mem:QI (match_operand 0 "low_io_address_operand" "n"))
(and:QI (mem:QI (match_dup 0))
(match_operand:QI 1 "single_zero_operand" "n")))]
- "optimize > 0"
+ ""
{
operands[2] = GEN_INT (exact_log2 (~INTVAL (operands[1]) & 0xff));
return "cbi %i0,%2";
[(set (mem:QI (match_operand 0 "low_io_address_operand" "n"))
(ior:QI (mem:QI (match_dup 0))
(match_operand:QI 1 "single_one_operand" "n")))]
- "optimize > 0"
+ ""
{
operands[2] = GEN_INT (exact_log2 (INTVAL (operands[1]) & 0xff));
return "sbi %i0,%2";
;; Lower half of the I/O space - use sbic/sbis directly.
(define_insn "*sbix_branch"
[(set (pc)
- (if_then_else
- (match_operator 0 "eqne_operator"
- [(zero_extract:HI
- (mem:QI (match_operand 1 "low_io_address_operand" "n"))
- (const_int 1)
- (match_operand 2 "const_int_operand" "n"))
- (const_int 0)])
- (label_ref (match_operand 3 "" ""))
- (pc)))]
- "(optimize > 0)"
- "* return avr_out_sbxx_branch (insn, operands);"
+ (if_then_else
+ (match_operator 0 "eqne_operator"
+ [(zero_extract:QIHI
+ (mem:QI (match_operand 1 "low_io_address_operand" "n"))
+ (const_int 1)
+ (match_operand 2 "const_int_operand" "n"))
+ (const_int 0)])
+ (label_ref (match_operand 3 "" ""))
+ (pc)))]
+ ""
+ {
+ return avr_out_sbxx_branch (insn, operands);
+ }
[(set (attr "length")
- (if_then_else (and (ge (minus (pc) (match_dup 3)) (const_int -2046))
+ (if_then_else (and (ge (minus (pc) (match_dup 3)) (const_int -2046))
(le (minus (pc) (match_dup 3)) (const_int 2046)))
(const_int 2)
(if_then_else (match_test "!AVR_HAVE_JMP_CALL")
;; Tests of bit 7 are pessimized to sign tests, so we need this too...
(define_insn "*sbix_branch_bit7"
[(set (pc)
- (if_then_else
- (match_operator 0 "gelt_operator"
- [(mem:QI (match_operand 1 "low_io_address_operand" "n"))
- (const_int 0)])
- (label_ref (match_operand 2 "" ""))
- (pc)))]
- "(optimize > 0)"
+ (if_then_else
+ (match_operator 0 "gelt_operator"
+ [(mem:QI (match_operand 1 "low_io_address_operand" "n"))
+ (const_int 0)])
+ (label_ref (match_operand 2 "" ""))
+ (pc)))]
+ ""
{
operands[3] = operands[2];
operands[2] = GEN_INT (7);
return avr_out_sbxx_branch (insn, operands);
}
[(set (attr "length")
- (if_then_else (and (ge (minus (pc) (match_dup 2)) (const_int -2046))
+ (if_then_else (and (ge (minus (pc) (match_dup 2)) (const_int -2046))
(le (minus (pc) (match_dup 2)) (const_int 2046)))
(const_int 2)
(if_then_else (match_test "!AVR_HAVE_JMP_CALL")
;; Upper half of the I/O space - read port to __tmp_reg__ and use sbrc/sbrs.
(define_insn "*sbix_branch_tmp"
[(set (pc)
- (if_then_else
- (match_operator 0 "eqne_operator"
- [(zero_extract:HI
- (mem:QI (match_operand 1 "high_io_address_operand" "n"))
- (const_int 1)
- (match_operand 2 "const_int_operand" "n"))
- (const_int 0)])
- (label_ref (match_operand 3 "" ""))
- (pc)))]
- "(optimize > 0)"
- "* return avr_out_sbxx_branch (insn, operands);"
+ (if_then_else
+ (match_operator 0 "eqne_operator"
+ [(zero_extract:QIHI
+ (mem:QI (match_operand 1 "high_io_address_operand" "n"))
+ (const_int 1)
+ (match_operand 2 "const_int_operand" "n"))
+ (const_int 0)])
+ (label_ref (match_operand 3 "" ""))
+ (pc)))]
+ ""
+ {
+ return avr_out_sbxx_branch (insn, operands);
+ }
[(set (attr "length")
- (if_then_else (and (ge (minus (pc) (match_dup 3)) (const_int -2046))
+ (if_then_else (and (ge (minus (pc) (match_dup 3)) (const_int -2046))
(le (minus (pc) (match_dup 3)) (const_int 2045)))
(const_int 3)
(if_then_else (match_test "!AVR_HAVE_JMP_CALL")
(define_insn "*sbix_branch_tmp_bit7"
[(set (pc)
- (if_then_else
- (match_operator 0 "gelt_operator"
- [(mem:QI (match_operand 1 "high_io_address_operand" "n"))
- (const_int 0)])
- (label_ref (match_operand 2 "" ""))
- (pc)))]
- "(optimize > 0)"
+ (if_then_else
+ (match_operator 0 "gelt_operator"
+ [(mem:QI (match_operand 1 "high_io_address_operand" "n"))
+ (const_int 0)])
+ (label_ref (match_operand 2 "" ""))
+ (pc)))]
+ ""
{
operands[3] = operands[2];
operands[2] = GEN_INT (7);
return avr_out_sbxx_branch (insn, operands);
}
[(set (attr "length")
- (if_then_else (and (ge (minus (pc) (match_dup 2)) (const_int -2046))
- (le (minus (pc) (match_dup 2)) (const_int 2045)))
- (const_int 3)
+ (if_then_else (and (ge (minus (pc) (match_dup 2)) (const_int -2046))
+ (le (minus (pc) (match_dup 2)) (const_int 2045)))
+ (const_int 3)
(if_then_else (match_test "!AVR_HAVE_JMP_CALL")
- (const_int 3)
- (const_int 5))))
+ (const_int 3)
+ (const_int 5))))
(set_attr "cc" "clobber")])
;; ************************* Peepholes ********************************
-(define_peephole
+(define_peephole ; "*dec-and-branchsi!=-1.d.clobber"
[(parallel [(set (match_operand:SI 0 "d_register_operand" "")
(plus:SI (match_dup 0)
(const_int -1)))
(const_int -1)))
(clobber (match_operand:QI 1 "d_register_operand" ""))])
(set (pc)
- (if_then_else (ne (cc0)
- (const_int 0))
+ (if_then_else (eqne (cc0)
+ (const_int 0))
(label_ref (match_operand 2 "" ""))
(pc)))]
""
{
+ const char *op;
+ int jump_mode;
CC_STATUS_INIT;
if (test_hard_reg_class (ADDW_REGS, operands[0]))
- output_asm_insn (AS2 (sbiw,%0,1) CR_TAB
- AS2 (sbc,%C0,__zero_reg__) CR_TAB
- AS2 (sbc,%D0,__zero_reg__) "\n", operands);
+ output_asm_insn ("sbiw %0,1" CR_TAB
+ "sbc %C0,__zero_reg__" CR_TAB
+ "sbc %D0,__zero_reg__", operands);
else
- output_asm_insn (AS2 (subi,%A0,1) CR_TAB
- AS2 (sbc,%B0,__zero_reg__) CR_TAB
- AS2 (sbc,%C0,__zero_reg__) CR_TAB
- AS2 (sbc,%D0,__zero_reg__) "\n", operands);
+ output_asm_insn ("subi %A0,1" CR_TAB
+ "sbc %B0,__zero_reg__" CR_TAB
+ "sbc %C0,__zero_reg__" CR_TAB
+ "sbc %D0,__zero_reg__", operands);
+
+ jump_mode = avr_jump_mode (operands[2], insn);
+ op = ((EQ == <CODE>) ^ (jump_mode == 1)) ? "brcc" : "brcs";
+ operands[1] = gen_rtx_CONST_STRING (VOIDmode, op);
- switch (avr_jump_mode (operands[2], insn))
+ switch (jump_mode)
{
- case 1:
- return AS1 (brcc,%2);
- case 2:
- return (AS1 (brcs,.+2) CR_TAB
- AS1 (rjmp,%2));
+ case 1: return "%1 %2";
+ case 2: return "%1 .+2\;rjmp %2";
+ case 3: return "%1 .+4\;jmp %2";
}
- return (AS1 (brcs,.+4) CR_TAB
- AS1 (jmp,%2));
+ gcc_unreachable();
+ return "";
})
-(define_peephole
+(define_peephole ; "*dec-and-branchhi!=-1"
[(set (match_operand:HI 0 "d_register_operand" "")
(plus:HI (match_dup 0)
(const_int -1)))
- (parallel
- [(set (cc0)
- (compare (match_dup 0)
- (const_int -1)))
- (clobber (match_operand:QI 1 "d_register_operand" ""))])
+ (parallel [(set (cc0)
+ (compare (match_dup 0)
+ (const_int -1)))
+ (clobber (match_operand:QI 1 "d_register_operand" ""))])
(set (pc)
- (if_then_else (ne (cc0) (const_int 0))
- (label_ref (match_operand 2 "" ""))
- (pc)))]
+ (if_then_else (eqne (cc0)
+ (const_int 0))
+ (label_ref (match_operand 2 "" ""))
+ (pc)))]
""
- "*
-{
- CC_STATUS_INIT;
- if (test_hard_reg_class (ADDW_REGS, operands[0]))
- output_asm_insn (AS2 (sbiw,%0,1), operands);
- else
- output_asm_insn (AS2 (subi,%A0,1) CR_TAB
- AS2 (sbc,%B0,__zero_reg__) \"\\n\", operands);
- switch (avr_jump_mode (operands[2],insn))
- {
- case 1:
- return AS1 (brcc,%2);
- case 2:
- return (AS1 (brcs,.+2) CR_TAB
- AS1 (rjmp,%2));
- }
- return (AS1 (brcs,.+4) CR_TAB
- AS1 (jmp,%2));
-}")
+ {
+ const char *op;
+ int jump_mode;
+ CC_STATUS_INIT;
+ if (test_hard_reg_class (ADDW_REGS, operands[0]))
+ output_asm_insn ("sbiw %0,1", operands);
+ else
+ output_asm_insn ("subi %A0,1" CR_TAB
+ "sbc %B0,__zero_reg__", operands);
+
+ jump_mode = avr_jump_mode (operands[2], insn);
+ op = ((EQ == <CODE>) ^ (jump_mode == 1)) ? "brcc" : "brcs";
+ operands[1] = gen_rtx_CONST_STRING (VOIDmode, op);
+
+ switch (jump_mode)
+ {
+ case 1: return "%1 %2";
+ case 2: return "%1 .+2\;rjmp %2";
+ case 3: return "%1 .+4\;jmp %2";
+ }
+
+ gcc_unreachable();
+ return "";
+ })
+
+;; Same as above but with clobber flavour of addhi3
+(define_peephole ; "*dec-and-branchhi!=-1.d.clobber"
+ [(parallel [(set (match_operand:HI 0 "d_register_operand" "")
+ (plus:HI (match_dup 0)
+ (const_int -1)))
+ (clobber (scratch:QI))])
+ (parallel [(set (cc0)
+ (compare (match_dup 0)
+ (const_int -1)))
+ (clobber (match_operand:QI 1 "d_register_operand" ""))])
+ (set (pc)
+ (if_then_else (eqne (cc0)
+ (const_int 0))
+ (label_ref (match_operand 2 "" ""))
+ (pc)))]
+ ""
+ {
+ const char *op;
+ int jump_mode;
+ CC_STATUS_INIT;
+ if (test_hard_reg_class (ADDW_REGS, operands[0]))
+ output_asm_insn ("sbiw %0,1", operands);
+ else
+ output_asm_insn ("subi %A0,1" CR_TAB
+ "sbc %B0,__zero_reg__", operands);
+
+ jump_mode = avr_jump_mode (operands[2], insn);
+ op = ((EQ == <CODE>) ^ (jump_mode == 1)) ? "brcc" : "brcs";
+ operands[1] = gen_rtx_CONST_STRING (VOIDmode, op);
+
+ switch (jump_mode)
+ {
+ case 1: return "%1 %2";
+ case 2: return "%1 .+2\;rjmp %2";
+ case 3: return "%1 .+4\;jmp %2";
+ }
+
+ gcc_unreachable();
+ return "";
+ })
+
+;; Same as above but with clobber flavour of addhi3
+(define_peephole ; "*dec-and-branchhi!=-1.l.clobber"
+ [(parallel [(set (match_operand:HI 0 "l_register_operand" "")
+ (plus:HI (match_dup 0)
+ (const_int -1)))
+ (clobber (match_operand:QI 3 "d_register_operand" ""))])
+ (parallel [(set (cc0)
+ (compare (match_dup 0)
+ (const_int -1)))
+ (clobber (match_operand:QI 1 "d_register_operand" ""))])
+ (set (pc)
+ (if_then_else (eqne (cc0)
+ (const_int 0))
+ (label_ref (match_operand 2 "" ""))
+ (pc)))]
+ ""
+ {
+ const char *op;
+ int jump_mode;
+ CC_STATUS_INIT;
+ output_asm_insn ("ldi %3,1" CR_TAB
+ "sub %A0,%3" CR_TAB
+ "sbc %B0,__zero_reg__", operands);
+
+ jump_mode = avr_jump_mode (operands[2], insn);
+ op = ((EQ == <CODE>) ^ (jump_mode == 1)) ? "brcc" : "brcs";
+ operands[1] = gen_rtx_CONST_STRING (VOIDmode, op);
-(define_peephole
+ switch (jump_mode)
+ {
+ case 1: return "%1 %2";
+ case 2: return "%1 .+2\;rjmp %2";
+ case 3: return "%1 .+4\;jmp %2";
+ }
+
+ gcc_unreachable();
+ return "";
+ })
+
+(define_peephole ; "*dec-and-branchqi!=-1"
[(set (match_operand:QI 0 "d_register_operand" "")
(plus:QI (match_dup 0)
(const_int -1)))
(set (cc0)
- (compare (match_dup 0)
- (const_int -1)))
+ (compare (match_dup 0)
+ (const_int -1)))
(set (pc)
- (if_then_else (ne (cc0) (const_int 0))
- (label_ref (match_operand 1 "" ""))
- (pc)))]
+ (if_then_else (eqne (cc0)
+ (const_int 0))
+ (label_ref (match_operand 1 "" ""))
+ (pc)))]
""
- "*
-{
- CC_STATUS_INIT;
- cc_status.value1 = operands[0];
- cc_status.flags |= CC_OVERFLOW_UNUSABLE;
- output_asm_insn (AS2 (subi,%A0,1), operands);
- switch (avr_jump_mode (operands[1],insn))
- {
- case 1:
- return AS1 (brcc,%1);
- case 2:
- return (AS1 (brcs,.+2) CR_TAB
- AS1 (rjmp,%1));
- }
- return (AS1 (brcs,.+4) CR_TAB
- AS1 (jmp,%1));
-}")
+ {
+ const char *op;
+ int jump_mode;
+ CC_STATUS_INIT;
+ cc_status.value1 = operands[0];
+ cc_status.flags |= CC_OVERFLOW_UNUSABLE;
+
+ output_asm_insn ("subi %A0,1", operands);
+
+ jump_mode = avr_jump_mode (operands[1], insn);
+ op = ((EQ == <CODE>) ^ (jump_mode == 1)) ? "brcc" : "brcs";
+ operands[0] = gen_rtx_CONST_STRING (VOIDmode, op);
-(define_peephole
+ switch (jump_mode)
+ {
+ case 1: return "%0 %1";
+ case 2: return "%0 .+2\;rjmp %1";
+ case 3: return "%0 .+4\;jmp %1";
+ }
+
+ gcc_unreachable();
+ return "";
+ })
+
+
+(define_peephole ; "*cpse.eq"
[(set (cc0)
- (compare (match_operand:QI 0 "register_operand" "")
- (const_int 0)))
+ (compare (match_operand:QI 1 "register_operand" "r,r")
+ (match_operand:QI 2 "reg_or_0_operand" "r,L")))
(set (pc)
- (if_then_else (eq (cc0) (const_int 0))
- (label_ref (match_operand 1 "" ""))
- (pc)))]
- "jump_over_one_insn_p (insn, operands[1])"
- "cpse %0,__zero_reg__")
+ (if_then_else (eq (cc0)
+ (const_int 0))
+ (label_ref (match_operand 0 "" ""))
+ (pc)))]
+ "jump_over_one_insn_p (insn, operands[0])"
+ "@
+ cpse %1,%2
+ cpse %1,__zero_reg__")
+
+;; This peephole avoids code like
+;;
+;; TST Rn ; *cmpqi
+;; BREQ .+2 ; branch
+;; RJMP .Lm
+;;
+;; Notice that the peephole is always shorter than cmpqi + branch.
+;; The reason to write it as peephole is that sequences like
+;;
+;; AND Rm, Rn
+;; BRNE .La
+;;
+;; shall not be superseeded. With a respective combine pattern
+;; the latter sequence would be
+;;
+;; AND Rm, Rn
+;; CPSE Rm, __zero_reg__
+;; RJMP .La
+;;
+;; and thus longer and slower and not easy to be rolled back.
-(define_peephole
+(define_peephole ; "*cpse.ne"
[(set (cc0)
- (compare (match_operand:QI 0 "register_operand" "")
- (match_operand:QI 1 "register_operand" "")))
+ (compare (match_operand:QI 1 "register_operand" "")
+ (match_operand:QI 2 "reg_or_0_operand" "")))
(set (pc)
- (if_then_else (eq (cc0) (const_int 0))
- (label_ref (match_operand 2 "" ""))
- (pc)))]
- "jump_over_one_insn_p (insn, operands[2])"
- "cpse %0,%1")
+ (if_then_else (ne (cc0)
+ (const_int 0))
+ (label_ref (match_operand 0 "" ""))
+ (pc)))]
+ "!AVR_HAVE_JMP_CALL
+ || !avr_current_device->errata_skip"
+ {
+ if (operands[2] == const0_rtx)
+ operands[2] = zero_reg_rtx;
+
+ return 3 == avr_jump_mode (operands[0], insn)
+ ? "cpse %1,%2\;jmp %0"
+ : "cpse %1,%2\;rjmp %0";
+ })
;;pppppppppppppppppppppppppppppppppppppppppppppppppppp
;;prologue/epilogue support instructions
(set_attr "length" "1")])
;; Enable Interrupts
-(define_insn "enable_interrupt"
- [(unspec_volatile [(const_int 1)] UNSPECV_ENABLE_IRQS)]
+(define_expand "enable_interrupt"
+ [(clobber (const_int 0))]
""
- "sei"
- [(set_attr "length" "1")
- (set_attr "cc" "none")])
+ {
+ rtx mem = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
+ MEM_VOLATILE_P (mem) = 1;
+ emit_insn (gen_cli_sei (const1_rtx, mem));
+ DONE;
+ })
;; Disable Interrupts
-(define_insn "disable_interrupt"
- [(unspec_volatile [(const_int 0)] UNSPECV_ENABLE_IRQS)]
+(define_expand "disable_interrupt"
+ [(clobber (const_int 0))]
""
- "cli"
+ {
+ rtx mem = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
+ MEM_VOLATILE_P (mem) = 1;
+ emit_insn (gen_cli_sei (const0_rtx, mem));
+ DONE;
+ })
+
+(define_insn "cli_sei"
+ [(unspec_volatile [(match_operand:QI 0 "const_int_operand" "L,P")]
+ UNSPECV_ENABLE_IRQS)
+ (set (match_operand:BLK 1 "" "")
+ (unspec_volatile:BLK [(match_dup 1)] UNSPECV_MEMORY_BARRIER))]
+ ""
+ "@
+ cli
+ sei"
[(set_attr "length" "1")
(set_attr "cc" "none")])
[(unspec_volatile [(match_operand:QI 0 "const_int_operand" "n")
(const_int 1)]
UNSPECV_DELAY_CYCLES)
- (clobber (match_scratch:QI 1 "=&d"))]
+ (set (match_operand:BLK 1 "" "")
+ (unspec_volatile:BLK [(match_dup 1)] UNSPECV_MEMORY_BARRIER))
+ (clobber (match_scratch:QI 2 "=&d"))]
""
- "ldi %1,lo8(%0)
- 1: dec %1
+ "ldi %2,lo8(%0)
+ 1: dec %2
brne 1b"
[(set_attr "length" "3")
(set_attr "cc" "clobber")])
[(unspec_volatile [(match_operand:HI 0 "const_int_operand" "n")
(const_int 2)]
UNSPECV_DELAY_CYCLES)
- (clobber (match_scratch:HI 1 "=&w"))]
+ (set (match_operand:BLK 1 "" "")
+ (unspec_volatile:BLK [(match_dup 1)] UNSPECV_MEMORY_BARRIER))
+ (clobber (match_scratch:HI 2 "=&w"))]
""
- "ldi %A1,lo8(%0)
- ldi %B1,hi8(%0)
- 1: sbiw %A1,1
+ "ldi %A2,lo8(%0)
+ ldi %B2,hi8(%0)
+ 1: sbiw %A2,1
brne 1b"
[(set_attr "length" "4")
(set_attr "cc" "clobber")])
[(unspec_volatile [(match_operand:SI 0 "const_int_operand" "n")
(const_int 3)]
UNSPECV_DELAY_CYCLES)
- (clobber (match_scratch:QI 1 "=&d"))
+ (set (match_operand:BLK 1 "" "")
+ (unspec_volatile:BLK [(match_dup 1)] UNSPECV_MEMORY_BARRIER))
(clobber (match_scratch:QI 2 "=&d"))
- (clobber (match_scratch:QI 3 "=&d"))]
+ (clobber (match_scratch:QI 3 "=&d"))
+ (clobber (match_scratch:QI 4 "=&d"))]
""
- "ldi %1,lo8(%0)
- ldi %2,hi8(%0)
- ldi %3,hlo8(%0)
- 1: subi %1,1
- sbci %2,0
+ "ldi %2,lo8(%0)
+ ldi %3,hi8(%0)
+ ldi %4,hlo8(%0)
+ 1: subi %2,1
sbci %3,0
+ sbci %4,0
brne 1b"
[(set_attr "length" "7")
(set_attr "cc" "clobber")])
[(unspec_volatile [(match_operand:SI 0 "const_int_operand" "n")
(const_int 4)]
UNSPECV_DELAY_CYCLES)
- (clobber (match_scratch:QI 1 "=&d"))
+ (set (match_operand:BLK 1 "" "")
+ (unspec_volatile:BLK [(match_dup 1)] UNSPECV_MEMORY_BARRIER))
(clobber (match_scratch:QI 2 "=&d"))
(clobber (match_scratch:QI 3 "=&d"))
- (clobber (match_scratch:QI 4 "=&d"))]
- ""
- "ldi %1,lo8(%0)
- ldi %2,hi8(%0)
- ldi %3,hlo8(%0)
- ldi %4,hhi8(%0)
- 1: subi %1,1
- sbci %2,0
+ (clobber (match_scratch:QI 4 "=&d"))
+ (clobber (match_scratch:QI 5 "=&d"))]
+ ""
+ "ldi %2,lo8(%0)
+ ldi %3,hi8(%0)
+ ldi %4,hlo8(%0)
+ ldi %5,hhi8(%0)
+ 1: subi %2,1
sbci %3,0
sbci %4,0
+ sbci %5,0
brne 1b"
[(set_attr "length" "9")
(set_attr "cc" "clobber")])
-(define_insn "map_bitsqi"
- [(set (match_operand:QI 0 "register_operand" "=d")
- (unspec:QI [(match_operand:SI 1 "const_int_operand" "n")
- (match_operand:QI 2 "register_operand" "r")]
- UNSPEC_MAP_BITS))]
+
+;; __builtin_avr_insert_bits
+
+(define_insn "insert_bits"
+ [(set (match_operand:QI 0 "register_operand" "=r ,d ,r")
+ (unspec:QI [(match_operand:SI 1 "const_int_operand" "C0f,Cxf,C0f")
+ (match_operand:QI 2 "register_operand" "r ,r ,r")
+ (match_operand:QI 3 "nonmemory_operand" "n ,0 ,0")]
+ UNSPEC_INSERT_BITS))]
""
{
- return avr_out_map_bits (insn, operands, NULL);
+ return avr_out_insert_bits (operands, NULL);
}
- [(set_attr "adjust_len" "map_bits")
+ [(set_attr "adjust_len" "insert_bits")
(set_attr "cc" "clobber")])
-(define_insn "map_bitshi"
- [(set (match_operand:HI 0 "register_operand" "=&r")
- (unspec:HI [(match_operand:DI 1 "const_double_operand" "n")
- (match_operand:HI 2 "register_operand" "r")]
- UNSPEC_MAP_BITS))]
+
+;; __builtin_avr_flash_segment
+
+;; Just a helper for the next "official" expander.
+
+(define_expand "flash_segment1"
+ [(set (match_operand:QI 0 "register_operand" "")
+ (subreg:QI (match_operand:PSI 1 "register_operand" "")
+ 2))
+ (set (cc0)
+ (compare (match_dup 0)
+ (const_int 0)))
+ (set (pc)
+ (if_then_else (ge (cc0)
+ (const_int 0))
+ (label_ref (match_operand 2 "" ""))
+ (pc)))
+ (set (match_dup 0)
+ (const_int -1))])
+
+(define_expand "flash_segment"
+ [(parallel [(match_operand:QI 0 "register_operand" "")
+ (match_operand:PSI 1 "register_operand" "")])]
""
{
- return avr_out_map_bits (insn, operands, NULL);
- }
- [(set_attr "adjust_len" "map_bits")
- (set_attr "cc" "clobber")])
+ rtx label = gen_label_rtx ();
+ emit (gen_flash_segment1 (operands[0], operands[1], label));
+ emit_label (label);
+ DONE;
+ })
+
+;; Actually, it's too late now to work out address spaces known at compiletime.
+;; Best place would be to fold ADDR_SPACE_CONVERT_EXPR in avr_fold_builtin.
+;; However, avr_addr_space_convert can add some built-in knowledge for PSTR
+;; so that ADDR_SPACE_CONVERT_EXPR in the built-in must not be resolved.
+
+(define_insn_and_split "*split.flash_segment"
+ [(set (match_operand:QI 0 "register_operand" "=d")
+ (subreg:QI (lo_sum:PSI (match_operand:QI 1 "nonmemory_operand" "ri")
+ (match_operand:HI 2 "register_operand" "r"))
+ 2))]
+ ""
+ { gcc_unreachable(); }
+ ""
+ [(set (match_dup 0)
+ (match_dup 1))])
;; Parity
;; CPU instructions
;; NOP taking 1 or 2 Ticks
-(define_insn "nopv"
+(define_expand "nopv"
+ [(parallel [(unspec_volatile [(match_operand:SI 0 "const_int_operand" "")]
+ UNSPECV_NOP)
+ (set (match_dup 1)
+ (unspec_volatile:BLK [(match_dup 1)]
+ UNSPECV_MEMORY_BARRIER))])]
+ ""
+ {
+ operands[1] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
+ MEM_VOLATILE_P (operands[1]) = 1;
+ })
+
+(define_insn "*nopv"
[(unspec_volatile [(match_operand:SI 0 "const_int_operand" "P,K")]
- UNSPECV_NOP)]
+ UNSPECV_NOP)
+ (set (match_operand:BLK 1 "" "")
+ (unspec_volatile:BLK [(match_dup 1)] UNSPECV_MEMORY_BARRIER))]
""
"@
nop
(set_attr "cc" "none")])
;; SLEEP
-(define_insn "sleep"
- [(unspec_volatile [(const_int 0)] UNSPECV_SLEEP)]
+(define_expand "sleep"
+ [(parallel [(unspec_volatile [(const_int 0)] UNSPECV_SLEEP)
+ (set (match_dup 0)
+ (unspec_volatile:BLK [(match_dup 0)]
+ UNSPECV_MEMORY_BARRIER))])]
+ ""
+ {
+ operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
+ MEM_VOLATILE_P (operands[0]) = 1;
+ })
+
+(define_insn "*sleep"
+ [(unspec_volatile [(const_int 0)] UNSPECV_SLEEP)
+ (set (match_operand:BLK 0 "" "")
+ (unspec_volatile:BLK [(match_dup 0)] UNSPECV_MEMORY_BARRIER))]
""
"sleep"
[(set_attr "length" "1")
(set_attr "cc" "none")])
;; WDR
-(define_insn "wdr"
- [(unspec_volatile [(const_int 0)] UNSPECV_WDR)]
+(define_expand "wdr"
+ [(parallel [(unspec_volatile [(const_int 0)] UNSPECV_WDR)
+ (set (match_dup 0)
+ (unspec_volatile:BLK [(match_dup 0)]
+ UNSPECV_MEMORY_BARRIER))])]
+ ""
+ {
+ operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
+ MEM_VOLATILE_P (operands[0]) = 1;
+ })
+
+(define_insn "*wdr"
+ [(unspec_volatile [(const_int 0)] UNSPECV_WDR)
+ (set (match_operand:BLK 0 "" "")
+ (unspec_volatile:BLK [(match_dup 0)] UNSPECV_MEMORY_BARRIER))]
""
"wdr"
[(set_attr "length" "1")
;; in particular when subreg lowering (-fsplit-wide-types) is turned on.
;; That switch obfuscates things here and in many other places.
-(define_insn_and_split "*ior<mode>qi.byte0"
+;; "*iorhiqi.byte0" "*iorpsiqi.byte0" "*iorsiqi.byte0"
+;; "*xorhiqi.byte0" "*xorpsiqi.byte0" "*xorsiqi.byte0"
+(define_insn_and_split "*<code_stdname><mode>qi.byte0"
[(set (match_operand:HISI 0 "register_operand" "=r")
- (ior:HISI
+ (xior:HISI
(zero_extend:HISI (match_operand:QI 1 "register_operand" "r"))
(match_operand:HISI 2 "register_operand" "0")))]
""
"#"
"reload_completed"
[(set (match_dup 3)
- (ior:QI (match_dup 3)
- (match_dup 1)))]
+ (xior:QI (match_dup 3)
+ (match_dup 1)))]
{
operands[3] = simplify_gen_subreg (QImode, operands[0], <MODE>mode, 0);
})
-(define_insn_and_split "*ior<mode>qi.byte1-3"
+;; "*iorhiqi.byte1-3" "*iorpsiqi.byte1-3" "*iorsiqi.byte1-3"
+;; "*xorhiqi.byte1-3" "*xorpsiqi.byte1-3" "*xorsiqi.byte1-3"
+(define_insn_and_split "*<code_stdname><mode>qi.byte1-3"
[(set (match_operand:HISI 0 "register_operand" "=r")
- (ior:HISI
+ (xior:HISI
(ashift:HISI (zero_extend:HISI (match_operand:QI 1 "register_operand" "r"))
(match_operand:QI 2 "const_8_16_24_operand" "n"))
(match_operand:HISI 3 "register_operand" "0")))]
"#"
"&& reload_completed"
[(set (match_dup 4)
- (ior:QI (match_dup 4)
- (match_dup 1)))]
+ (xior:QI (match_dup 4)
+ (match_dup 1)))]
{
int byteno = INTVAL(operands[2]) / BITS_PER_UNIT;
operands[4] = simplify_gen_subreg (QImode, operands[0], <MODE>mode, byteno);
operands[3] = simplify_gen_subreg (QImode, operands[0], HImode, 0);
operands[4] = simplify_gen_subreg (QImode, operands[0], HImode, 1);
})
+
+\f
+(include "avr-dimode.md")
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