;; Machine description for DEC Alpha for GNU C compiler
;; Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
-;; 2000, 2001 Free Software Foundation, Inc.
+;; 2000, 2001, 2002 Free Software Foundation, Inc.
;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
;;
;; This file is part of GNU CC.
(UNSPEC_LDGP2 10)
(UNSPEC_LITERAL 11)
(UNSPEC_LITUSE 12)
+ (UNSPEC_SIBCALL 13)
+ (UNSPEC_SYMBOL 14)
+
+ ;; TLS Support
+ (UNSPEC_TLSGD_CALL 15)
+ (UNSPEC_TLSLDM_CALL 16)
+ (UNSPEC_TLSGD 17)
+ (UNSPEC_TLSLDM 18)
+ (UNSPEC_DTPREL 19)
+ (UNSPEC_TPREL 20)
+ (UNSPEC_TP 21)
+
+ ;; Builtins
+ (UNSPEC_CMPBGE 22)
+ (UNSPEC_ZAP 23)
+ (UNSPEC_AMASK 24)
+ (UNSPEC_IMPLVER 25)
+ (UNSPEC_PERR 26)
+ (UNSPEC_CTLZ 27)
+ (UNSPEC_CTPOP 28)
])
;; UNSPEC_VOLATILE:
(UNSPECV_FORCE_MOV 9)
(UNSPECV_LDGP1 10)
(UNSPECV_PLDGP2 11) ; prologue ldgp
+ (UNSPECV_SET_TP 12)
+ (UNSPECV_RPCC 13)
])
;; Where necessary, the suffixes _le and _be are used to distinguish between
(define_attr "type"
"ild,fld,ldsym,ist,fst,ibr,fbr,jsr,iadd,ilog,shift,icmov,fcmov,icmp,imul,\
-fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi"
+fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi,none"
(const_string "iadd"))
;; Describe a user's asm statement.
(define_attr "length" ""
(const_int 4))
\f
-;; On EV4 there are two classes of resources to consider: resources needed
-;; to issue, and resources needed to execute. IBUS[01] are in the first
-;; category. ABOX, BBOX, EBOX, FBOX, IMUL & FDIV make up the second.
-;; (There are a few other register-like resources, but ...)
-
-; First, describe all of the issue constraints with single cycle delays.
-; All insns need a bus, but all except loads require one or the other.
-(define_function_unit "ev4_ibus0" 1 0
- (and (eq_attr "cpu" "ev4")
- (eq_attr "type" "fst,fbr,iadd,imul,ilog,shift,icmov,icmp"))
- 1 1)
-
-(define_function_unit "ev4_ibus1" 1 0
- (and (eq_attr "cpu" "ev4")
- (eq_attr "type" "ist,ibr,jsr,fadd,fcmov,fcpys,fmul,fdiv,misc"))
- 1 1)
-
-; Memory delivers its result in three cycles. Actually return one and
-; take care of this in adjust_cost, since we want to handle user-defined
-; memory latencies.
-(define_function_unit "ev4_abox" 1 0
- (and (eq_attr "cpu" "ev4")
- (eq_attr "type" "ild,fld,ldsym,ist,fst"))
- 1 1)
-
-; Branches have no delay cost, but do tie up the unit for two cycles.
-(define_function_unit "ev4_bbox" 1 1
- (and (eq_attr "cpu" "ev4")
- (eq_attr "type" "ibr,fbr,jsr"))
- 2 2)
-
-; Arithmetic insns are normally have their results available after
-; two cycles. There are a number of exceptions. They are encoded in
-; ADJUST_COST. Some of the other insns have similar exceptions.
-(define_function_unit "ev4_ebox" 1 0
- (and (eq_attr "cpu" "ev4")
- (eq_attr "type" "iadd,ilog,shift,icmov,icmp,misc"))
- 2 1)
-
-(define_function_unit "imul" 1 0
- (and (eq_attr "cpu" "ev4")
- (and (eq_attr "type" "imul")
- (eq_attr "opsize" "si")))
- 21 19)
-
-(define_function_unit "imul" 1 0
- (and (eq_attr "cpu" "ev4")
- (and (eq_attr "type" "imul")
- (eq_attr "opsize" "!si")))
- 23 21)
-
-(define_function_unit "ev4_fbox" 1 0
- (and (eq_attr "cpu" "ev4")
- (eq_attr "type" "fadd,fmul,fcpys,fcmov"))
- 6 1)
-
-(define_function_unit "fdiv" 1 0
- (and (eq_attr "cpu" "ev4")
- (and (eq_attr "type" "fdiv")
- (eq_attr "opsize" "si")))
- 34 30)
-
-(define_function_unit "fdiv" 1 0
- (and (eq_attr "cpu" "ev4")
- (and (eq_attr "type" "fdiv")
- (eq_attr "opsize" "di")))
- 63 59)
-\f
-;; EV5 scheduling. EV5 can issue 4 insns per clock.
-;;
-;; EV5 has two asymetric integer units. Model this with E0 & E1 along
-;; with the combined resource EBOX.
-
-(define_function_unit "ev5_ebox" 2 0
- (and (eq_attr "cpu" "ev5")
- (eq_attr "type" "!fbr,fcmov,fadd,fmul,fcpys,fdiv"))
- 1 1)
-
-; Memory takes at least 2 clocks. Return one from here and fix up with
-; user-defined latencies in adjust_cost.
-(define_function_unit "ev5_ebox" 2 0
- (and (eq_attr "cpu" "ev5")
- (eq_attr "type" "ild,fld,ldsym"))
- 1 1)
-
-; Loads can dual issue with one another, but loads and stores do not mix.
-(define_function_unit "ev5_e0" 1 0
- (and (eq_attr "cpu" "ev5")
- (eq_attr "type" "ild,fld,ldsym"))
- 1 1
- [(eq_attr "type" "ist,fst")])
-
-; Stores, shifts, multiplies can only issue to E0
-(define_function_unit "ev5_e0" 1 0
- (and (eq_attr "cpu" "ev5")
- (eq_attr "type" "ist,fst,shift,imul"))
- 1 1)
-
-; Motion video insns also issue only to E0, and take two ticks.
-(define_function_unit "ev5_e0" 1 0
- (and (eq_attr "cpu" "ev5")
- (eq_attr "type" "mvi"))
- 2 1)
-
-; Conditional moves always take 2 ticks.
-(define_function_unit "ev5_ebox" 2 0
- (and (eq_attr "cpu" "ev5")
- (eq_attr "type" "icmov"))
- 2 1)
-
-; Branches can only issue to E1
-(define_function_unit "ev5_e1" 1 0
- (and (eq_attr "cpu" "ev5")
- (eq_attr "type" "ibr,jsr"))
- 1 1)
-
-; Multiplies also use the integer multiplier.
-; ??? How to: "No instruction can be issued to pipe E0 exactly two
-; cycles before an integer multiplication completes."
-(define_function_unit "imul" 1 0
- (and (eq_attr "cpu" "ev5")
- (and (eq_attr "type" "imul")
- (eq_attr "opsize" "si")))
- 8 4)
-
-(define_function_unit "imul" 1 0
- (and (eq_attr "cpu" "ev5")
- (and (eq_attr "type" "imul")
- (eq_attr "opsize" "di")))
- 12 8)
-
-(define_function_unit "imul" 1 0
- (and (eq_attr "cpu" "ev5")
- (and (eq_attr "type" "imul")
- (eq_attr "opsize" "udi")))
- 14 8)
-
-;; Similarly for the FPU we have two asymetric units. But fcpys can issue
-;; on either so we have to play the game again.
-
-(define_function_unit "ev5_fbox" 2 0
- (and (eq_attr "cpu" "ev5")
- (eq_attr "type" "fadd,fcmov,fmul,fcpys,fbr,fdiv"))
- 4 1)
-
-(define_function_unit "ev5_fm" 1 0
- (and (eq_attr "cpu" "ev5")
- (eq_attr "type" "fmul"))
- 4 1)
-
-; Add and cmov as you would expect; fbr never produces a result;
-; fdiv issues through fa to the divider,
-(define_function_unit "ev5_fa" 1 0
- (and (eq_attr "cpu" "ev5")
- (eq_attr "type" "fadd,fcmov,fbr,fdiv"))
- 4 1)
-
-; ??? How to: "No instruction can be issued to pipe FA exactly five
-; cycles before a floating point divide completes."
-(define_function_unit "fdiv" 1 0
- (and (eq_attr "cpu" "ev5")
- (and (eq_attr "type" "fdiv")
- (eq_attr "opsize" "si")))
- 15 15) ; 15 to 31 data dependent
-
-(define_function_unit "fdiv" 1 0
- (and (eq_attr "cpu" "ev5")
- (and (eq_attr "type" "fdiv")
- (eq_attr "opsize" "di")))
- 22 22) ; 22 to 60 data dependent
-\f
-;; EV6 scheduling. EV6 can issue 4 insns per clock.
-;;
-;; EV6 has two symmetric pairs ("clusters") of two asymetric integer units
-;; ("upper" and "lower"), yielding pipe names U0, U1, L0, L1.
-
-;; Conditional moves decompose into two independent primitives, each
-;; taking one cycle. Since ev6 is out-of-order, we can't see anything
-;; but two cycles.
-(define_function_unit "ev6_ebox" 4 0
- (and (eq_attr "cpu" "ev6")
- (eq_attr "type" "icmov"))
- 2 1)
-
-(define_function_unit "ev6_ebox" 4 0
- (and (eq_attr "cpu" "ev6")
- (eq_attr "type" "!fbr,fcmov,fadd,fmul,fcpys,fdiv,fsqrt"))
- 1 1)
-
-;; Integer loads take at least 3 clocks, and only issue to lower units.
-;; Return one from here and fix up with user-defined latencies in adjust_cost.
-(define_function_unit "ev6_l" 2 0
- (and (eq_attr "cpu" "ev6")
- (eq_attr "type" "ild,ldsym,ist,fst"))
- 1 1)
-
-;; FP loads take at least 4 clocks. Return two from here...
-(define_function_unit "ev6_l" 2 0
- (and (eq_attr "cpu" "ev6")
- (eq_attr "type" "fld"))
- 2 1)
-
-;; Motion video insns also issue only to U0, and take three ticks.
-(define_function_unit "ev6_u0" 1 0
- (and (eq_attr "cpu" "ev6")
- (eq_attr "type" "mvi"))
- 3 1)
-
-(define_function_unit "ev6_u" 2 0
- (and (eq_attr "cpu" "ev6")
- (eq_attr "type" "mvi"))
- 3 1)
-
-;; Shifts issue to either upper pipe.
-(define_function_unit "ev6_u" 2 0
- (and (eq_attr "cpu" "ev6")
- (eq_attr "type" "shift"))
- 1 1)
-
-;; Multiplies issue only to U1, and all take 7 ticks.
-;; Rather than create a new function unit just for U1, reuse IMUL
-(define_function_unit "imul" 1 0
- (and (eq_attr "cpu" "ev6")
- (eq_attr "type" "imul"))
- 7 1)
-
-(define_function_unit "ev6_u" 2 0
- (and (eq_attr "cpu" "ev6")
- (eq_attr "type" "imul"))
- 7 1)
-
-;; Branches issue to either upper pipe
-(define_function_unit "ev6_u" 2 0
- (and (eq_attr "cpu" "ev6")
- (eq_attr "type" "ibr"))
- 3 1)
-
-;; Calls only issue to L0.
-(define_function_unit "ev6_l0" 1 0
- (and (eq_attr "cpu" "ev6")
- (eq_attr "type" "jsr"))
- 1 1)
-
-(define_function_unit "ev6_l" 2 0
- (and (eq_attr "cpu" "ev6")
- (eq_attr "type" "jsr"))
- 1 1)
-
-;; Ftoi/itof only issue to lower pipes
-(define_function_unit "ev6_l" 2 0
- (and (eq_attr "cpu" "ev6")
- (eq_attr "type" "ftoi"))
- 3 1)
-
-(define_function_unit "ev6_l" 2 0
- (and (eq_attr "cpu" "ev6")
- (eq_attr "type" "itof"))
- 4 1)
-
-;; For the FPU we are very similar to EV5, except there's no insn that
-;; can issue to fm & fa, so we get to leave that out.
-
-(define_function_unit "ev6_fm" 1 0
- (and (eq_attr "cpu" "ev6")
- (eq_attr "type" "fmul"))
- 4 1)
-
-(define_function_unit "ev6_fa" 1 0
- (and (eq_attr "cpu" "ev6")
- (eq_attr "type" "fadd,fcpys,fbr,fdiv,fsqrt"))
- 4 1)
-
-(define_function_unit "ev6_fa" 1 0
- (and (eq_attr "cpu" "ev6")
- (eq_attr "type" "fcmov"))
- 8 1)
-
-(define_function_unit "fdiv" 1 0
- (and (eq_attr "cpu" "ev6")
- (and (eq_attr "type" "fdiv")
- (eq_attr "opsize" "si")))
- 12 10)
-
-(define_function_unit "fdiv" 1 0
- (and (eq_attr "cpu" "ev6")
- (and (eq_attr "type" "fdiv")
- (eq_attr "opsize" "di")))
- 15 13)
-
-(define_function_unit "fsqrt" 1 0
- (and (eq_attr "cpu" "ev6")
- (and (eq_attr "type" "fsqrt")
- (eq_attr "opsize" "si")))
- 16 14)
-
-(define_function_unit "fsqrt" 1 0
- (and (eq_attr "cpu" "ev6")
- (and (eq_attr "type" "fsqrt")
- (eq_attr "opsize" "di")))
- 32 30)
-
-; ??? The FPU communicates with memory and the integer register file
-; via two fp store units. We need a slot in the fst immediately, and
-; a slot in LOW after the operand data is ready. At which point the
-; data may be moved either to the store queue or the integer register
-; file and the insn retired.
-
+;; Include scheduling descriptions.
+
+(include "ev4.md")
+(include "ev5.md")
+(include "ev6.md")
\f
;; First define the arithmetic insns. Note that the 32-bit forms also
;; sign-extend.
(set_attr "length" "*,*,*,8")])
(define_insn "*extendsidi2_fix"
- [(set (match_operand:DI 0 "register_operand" "=r,r,r,*f,?*f")
+ [(set (match_operand:DI 0 "register_operand" "=r,r,r,?*f,?*f")
(sign_extend:DI
(match_operand:SI 1 "nonimmediate_operand" "r,m,*f,*f,m")))]
"TARGET_FIX"
(sign_extend:DI (match_dup 1)))]
"")
-;; Do addsi3 the way expand_binop would do if we didn't have one. This
-;; generates better code. We have the anonymous addsi3 pattern below in
-;; case combine wants to make it.
+;; Don't say we have addsi3 if optimizing. This generates better code. We
+;; have the anonymous addsi3 pattern below in case combine wants to make it.
(define_expand "addsi3"
[(set (match_operand:SI 0 "register_operand" "")
(plus:SI (match_operand:SI 1 "reg_or_0_operand" "")
(match_operand:SI 2 "add_operand" "")))]
- ""
-{
- if (optimize)
- {
- rtx op1 = gen_lowpart (DImode, operands[1]);
- rtx op2 = gen_lowpart (DImode, operands[2]);
-
- if (! cse_not_expected)
- {
- rtx tmp = gen_reg_rtx (DImode);
- emit_insn (gen_adddi3 (tmp, op1, op2));
- emit_move_insn (gen_lowpart (DImode, operands[0]), tmp);
- }
- else
- emit_insn (gen_adddi3 (gen_lowpart (DImode, operands[0]), op1, op2));
- DONE;
- }
-})
+ "! optimize"
+ "")
(define_insn "*addsi_internal"
[(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
addl %r1,%2,%0
subl %r1,%n2,%0")
+(define_insn "*addsi_se2"
+ [(set (match_operand:DI 0 "register_operand" "=r,r")
+ (sign_extend:DI
+ (subreg:SI (plus:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ")
+ (match_operand:DI 2 "sext_add_operand" "rI,O"))
+ 0)))]
+ ""
+ "@
+ addl %r1,%2,%0
+ subl %r1,%n2,%0")
+
(define_split
[(set (match_operand:DI 0 "register_operand" "")
(sign_extend:DI
""
"")
+(define_insn "*adddi_er_lo16_dtp"
+ [(set (match_operand:DI 0 "register_operand" "=r")
+ (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
+ (match_operand:DI 2 "dtp16_symbolic_operand" "")))]
+ "HAVE_AS_TLS"
+ "lda %0,%2(%1)\t\t!dtprel")
+
+(define_insn "*adddi_er_hi32_dtp"
+ [(set (match_operand:DI 0 "register_operand" "=r")
+ (plus:DI (match_operand:DI 1 "register_operand" "r")
+ (high:DI (match_operand:DI 2 "dtp32_symbolic_operand" ""))))]
+ "HAVE_AS_TLS"
+ "ldah %0,%2(%1)\t\t!dtprelhi")
+
+(define_insn "*adddi_er_lo32_dtp"
+ [(set (match_operand:DI 0 "register_operand" "=r")
+ (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
+ (match_operand:DI 2 "dtp32_symbolic_operand" "")))]
+ "HAVE_AS_TLS"
+ "lda %0,%2(%1)\t\t!dtprello")
+
+(define_insn "*adddi_er_lo16_tp"
+ [(set (match_operand:DI 0 "register_operand" "=r")
+ (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
+ (match_operand:DI 2 "tp16_symbolic_operand" "")))]
+ "HAVE_AS_TLS"
+ "lda %0,%2(%1)\t\t!tprel")
+
+(define_insn "*adddi_er_hi32_tp"
+ [(set (match_operand:DI 0 "register_operand" "=r")
+ (plus:DI (match_operand:DI 1 "register_operand" "r")
+ (high:DI (match_operand:DI 2 "tp32_symbolic_operand" ""))))]
+ "HAVE_AS_TLS"
+ "ldah %0,%2(%1)\t\t!tprelhi")
+
+(define_insn "*adddi_er_lo32_tp"
+ [(set (match_operand:DI 0 "register_operand" "=r")
+ (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
+ (match_operand:DI 2 "tp32_symbolic_operand" "")))]
+ "HAVE_AS_TLS"
+ "lda %0,%2(%1)\t\t!tprello")
+
(define_insn "*adddi_er_high_l"
[(set (match_operand:DI 0 "register_operand" "=r")
(plus:DI (match_operand:DI 1 "register_operand" "r")
"TARGET_EXPLICIT_RELOCS"
"ldah %0,%2(%1)\t\t!gprelhigh")
+(define_split
+ [(set (match_operand:DI 0 "register_operand" "")
+ (high:DI (match_operand:DI 1 "local_symbolic_operand" "")))]
+ "TARGET_EXPLICIT_RELOCS && reload_completed"
+ [(set (match_dup 0)
+ (plus:DI (match_dup 2) (high:DI (match_dup 1))))]
+ "operands[2] = pic_offset_table_rtx;")
+
;; We used to expend quite a lot of effort choosing addq/subq/lda.
;; With complications like
;;
[(set (match_operand:SI 0 "register_operand" "")
(minus:SI (match_operand:SI 1 "reg_or_0_operand" "")
(match_operand:SI 2 "reg_or_8bit_operand" "")))]
- ""
-{
- if (optimize)
- {
- rtx op1 = gen_lowpart (DImode, operands[1]);
- rtx op2 = gen_lowpart (DImode, operands[2]);
-
- if (! cse_not_expected)
- {
- rtx tmp = gen_reg_rtx (DImode);
- emit_insn (gen_subdi3 (tmp, op1, op2));
- emit_move_insn (gen_lowpart (DImode, operands[0]), tmp);
- }
- else
- emit_insn (gen_subdi3 (gen_lowpart (DImode, operands[0]), op1, op2));
- DONE;
- }
-})
+ "! optimize"
+ "")
(define_insn "*subsi_internal"
[(set (match_operand:SI 0 "register_operand" "=r")
""
"subl %r1,%2,%0")
+(define_insn "*subsi_se2"
+ [(set (match_operand:DI 0 "register_operand" "=r")
+ (sign_extend:DI
+ (subreg:SI (minus:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
+ (match_operand:DI 2 "reg_or_8bit_operand" "rI"))
+ 0)))]
+ ""
+ "subl %r1,%2,%0")
+
(define_insn "subvsi3"
[(set (match_operand:SI 0 "register_operand" "=r")
(minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ")
[(parallel [(set (match_dup 0)
(sign_extend:DI (match_dup 3)))
(use (match_dup 0))
+ (use (match_dup 4))
(clobber (reg:DI 23))
(clobber (reg:DI 28))])]
{
default:
abort ();
}
+ operands[4] = GEN_INT (alpha_next_sequence_number++);
emit_insn (gen_movdi_er_high_g (operands[0], pic_offset_table_rtx,
gen_rtx_SYMBOL_REF (DImode, str),
- const0_rtx));
+ operands[4]));
}
[(set_attr "type" "jsr")
(set_attr "length" "8")])
[(match_operand:DI 1 "register_operand" "a")
(match_operand:DI 2 "register_operand" "b")])))
(use (match_operand:DI 4 "register_operand" "c"))
+ (use (match_operand 5 "const_int_operand" ""))
(clobber (reg:DI 23))
(clobber (reg:DI 28))]
"TARGET_EXPLICIT_RELOCS && ! TARGET_ABI_OPEN_VMS"
- "jsr $23,($27),__%E3"
+ "jsr $23,($27),__%E3%J5"
[(set_attr "type" "jsr")
(set_attr "length" "4")])
"&& reload_completed"
[(parallel [(set (match_dup 0) (match_dup 3))
(use (match_dup 0))
+ (use (match_dup 4))
(clobber (reg:DI 23))
(clobber (reg:DI 28))])]
{
default:
abort ();
}
+ operands[4] = GEN_INT (alpha_next_sequence_number++);
emit_insn (gen_movdi_er_high_g (operands[0], pic_offset_table_rtx,
gen_rtx_SYMBOL_REF (DImode, str),
- const0_rtx));
+ operands[4]));
}
[(set_attr "type" "jsr")
(set_attr "length" "8")])
[(match_operand:DI 1 "register_operand" "a")
(match_operand:DI 2 "register_operand" "b")]))
(use (match_operand:DI 4 "register_operand" "c"))
+ (use (match_operand 5 "const_int_operand" ""))
(clobber (reg:DI 23))
(clobber (reg:DI 28))]
"TARGET_EXPLICIT_RELOCS && ! TARGET_ABI_OPEN_VMS"
- "jsr $23,($27),__%E3"
+ "jsr $23,($27),__%E3%J5"
[(set_attr "type" "jsr")
(set_attr "length" "4")])
}
[(set_attr "type" "iadd,shift")])
-;; ??? The following pattern is made by combine, but earlier phases
-;; (specifically flow) can't handle it. This occurs in jump.c. Deal
-;; with this in a better way at some point.
-;;(define_insn ""
-;; [(set (match_operand:DI 0 "register_operand" "=r")
-;; (sign_extend:DI
-;; (subreg:SI (ashift:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
-;; (match_operand:DI 2 "const_int_operand" "P"))
-;; 0)))]
-;; "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 3"
-;;{
-;; if (operands[2] == const1_rtx)
-;; return "addl %r1,%r1,%0";
-;; else
-;; return "s%P2addl %r1,0,%0";
-;;}
-;; [(set_attr "type" "iadd")])
+(define_insn "*ashldi_se"
+ [(set (match_operand:DI 0 "register_operand" "=r")
+ (sign_extend:DI
+ (subreg:SI (ashift:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
+ (match_operand:DI 2 "const_int_operand" "P"))
+ 0)))]
+ "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 3"
+{
+ if (operands[2] == const1_rtx)
+ return "addl %r1,%r1,%0";
+ else
+ return "s%P2addl %r1,0,%0";
+}
+ [(set_attr "type" "iadd")])
(define_insn "lshrdi3"
[(set (match_operand:DI 0 "register_operand" "=r")
(define_insn "abssf2"
[(set (match_operand:SF 0 "register_operand" "=f")
- (abs:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")))]
+ (abs:SF (match_operand:SF 1 "reg_or_0_operand" "fG")))]
"TARGET_FP"
"cpys $f31,%R1,%0"
[(set_attr "type" "fcpys")])
(define_insn "*nabssf2"
[(set (match_operand:SF 0 "register_operand" "=f")
- (neg:SF (abs:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG"))))]
+ (neg:SF (abs:SF (match_operand:SF 1 "reg_or_0_operand" "fG"))))]
"TARGET_FP"
"cpysn $f31,%R1,%0"
[(set_attr "type" "fadd")])
(define_insn "absdf2"
[(set (match_operand:DF 0 "register_operand" "=f")
- (abs:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
+ (abs:DF (match_operand:DF 1 "reg_or_0_operand" "fG")))]
"TARGET_FP"
"cpys $f31,%R1,%0"
[(set_attr "type" "fcpys")])
(define_insn "*nabsdf2"
[(set (match_operand:DF 0 "register_operand" "=f")
- (neg:DF (abs:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG"))))]
+ (neg:DF (abs:DF (match_operand:DF 1 "reg_or_0_operand" "fG"))))]
"TARGET_FP"
"cpysn $f31,%R1,%0"
[(set_attr "type" "fadd")])
(define_expand "abstf2"
[(parallel [(set (match_operand:TF 0 "register_operand" "")
- (neg:TF (match_operand:TF 1 "reg_or_fp0_operand" "")))
+ (neg:TF (match_operand:TF 1 "reg_or_0_operand" "")))
(use (match_dup 2))])]
"TARGET_HAS_XFLOATING_LIBS"
{
(define_insn_and_split "*abstf_internal"
[(set (match_operand:TF 0 "register_operand" "=r")
- (abs:TF (match_operand:TF 1 "reg_or_fp0_operand" "rG")))
+ (abs:TF (match_operand:TF 1 "reg_or_0_operand" "rG")))
(use (match_operand:DI 2 "register_operand" "r"))]
"TARGET_HAS_XFLOATING_LIBS"
"#"
(define_insn "negsf2"
[(set (match_operand:SF 0 "register_operand" "=f")
- (neg:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")))]
+ (neg:SF (match_operand:SF 1 "reg_or_0_operand" "fG")))]
"TARGET_FP"
"cpysn %R1,%R1,%0"
[(set_attr "type" "fadd")])
(define_insn "negdf2"
[(set (match_operand:DF 0 "register_operand" "=f")
- (neg:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
+ (neg:DF (match_operand:DF 1 "reg_or_0_operand" "fG")))]
"TARGET_FP"
"cpysn %R1,%R1,%0"
[(set_attr "type" "fadd")])
(define_expand "negtf2"
[(parallel [(set (match_operand:TF 0 "register_operand" "")
- (neg:TF (match_operand:TF 1 "reg_or_fp0_operand" "")))
+ (neg:TF (match_operand:TF 1 "reg_or_0_operand" "")))
(use (match_dup 2))])]
"TARGET_HAS_XFLOATING_LIBS"
{
(define_insn_and_split "*negtf_internal"
[(set (match_operand:TF 0 "register_operand" "=r")
- (neg:TF (match_operand:TF 1 "reg_or_fp0_operand" "rG")))
+ (neg:TF (match_operand:TF 1 "reg_or_0_operand" "rG")))
(use (match_operand:DI 2 "register_operand" "r"))]
"TARGET_HAS_XFLOATING_LIBS"
"#"
(define_insn "*addsf_ieee"
[(set (match_operand:SF 0 "register_operand" "=&f")
- (plus:SF (match_operand:SF 1 "reg_or_fp0_operand" "%fG")
- (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
+ (plus:SF (match_operand:SF 1 "reg_or_0_operand" "%fG")
+ (match_operand:SF 2 "reg_or_0_operand" "fG")))]
"TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
"add%,%/ %R1,%R2,%0"
[(set_attr "type" "fadd")
(define_insn "addsf3"
[(set (match_operand:SF 0 "register_operand" "=f")
- (plus:SF (match_operand:SF 1 "reg_or_fp0_operand" "%fG")
- (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
+ (plus:SF (match_operand:SF 1 "reg_or_0_operand" "%fG")
+ (match_operand:SF 2 "reg_or_0_operand" "fG")))]
"TARGET_FP"
"add%,%/ %R1,%R2,%0"
[(set_attr "type" "fadd")
(define_insn "*adddf_ieee"
[(set (match_operand:DF 0 "register_operand" "=&f")
- (plus:DF (match_operand:DF 1 "reg_or_fp0_operand" "%fG")
- (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
+ (plus:DF (match_operand:DF 1 "reg_or_0_operand" "%fG")
+ (match_operand:DF 2 "reg_or_0_operand" "fG")))]
"TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
"add%-%/ %R1,%R2,%0"
[(set_attr "type" "fadd")
(define_insn "adddf3"
[(set (match_operand:DF 0 "register_operand" "=f")
- (plus:DF (match_operand:DF 1 "reg_or_fp0_operand" "%fG")
- (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
+ (plus:DF (match_operand:DF 1 "reg_or_0_operand" "%fG")
+ (match_operand:DF 2 "reg_or_0_operand" "fG")))]
"TARGET_FP"
"add%-%/ %R1,%R2,%0"
[(set_attr "type" "fadd")
(define_insn "*adddf_ext1"
[(set (match_operand:DF 0 "register_operand" "=f")
(plus:DF (float_extend:DF
- (match_operand:SF 1 "reg_or_fp0_operand" "fG"))
- (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
+ (match_operand:SF 1 "reg_or_0_operand" "fG"))
+ (match_operand:DF 2 "reg_or_0_operand" "fG")))]
"TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
"add%-%/ %R1,%R2,%0"
[(set_attr "type" "fadd")
(define_insn "*adddf_ext2"
[(set (match_operand:DF 0 "register_operand" "=f")
(plus:DF (float_extend:DF
- (match_operand:SF 1 "reg_or_fp0_operand" "%fG"))
+ (match_operand:SF 1 "reg_or_0_operand" "%fG"))
(float_extend:DF
- (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))]
+ (match_operand:SF 2 "reg_or_0_operand" "fG"))))]
"TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
"add%-%/ %R1,%R2,%0"
[(set_attr "type" "fadd")
(define_insn "*cvtql"
[(set (match_operand:SI 0 "register_operand" "=f")
- (unspec:SI [(match_operand:DI 1 "reg_or_fp0_operand" "fG")]
+ (unspec:SI [(match_operand:DI 1 "reg_or_0_operand" "fG")]
UNSPEC_CVTQL))]
"TARGET_FP"
"cvtql%/ %R1,%0"
(define_insn_and_split "*fix_truncdfsi_ieee"
[(set (match_operand:SI 0 "memory_operand" "=m")
- (subreg:SI (fix:DI (match_operand:DF 1 "reg_or_fp0_operand" "fG")) 0))
+ (subreg:SI (fix:DI (match_operand:DF 1 "reg_or_0_operand" "fG")) 0))
(clobber (match_scratch:DI 2 "=&f"))
(clobber (match_scratch:SI 3 "=&f"))]
"TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
(define_insn_and_split "*fix_truncdfsi_internal"
[(set (match_operand:SI 0 "memory_operand" "=m")
- (subreg:SI (fix:DI (match_operand:DF 1 "reg_or_fp0_operand" "fG")) 0))
+ (subreg:SI (fix:DI (match_operand:DF 1 "reg_or_0_operand" "fG")) 0))
(clobber (match_scratch:DI 2 "=f"))]
"TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
"#"
(define_insn "*fix_truncdfdi_ieee"
[(set (match_operand:DI 0 "reg_no_subreg_operand" "=&f")
- (fix:DI (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
+ (fix:DI (match_operand:DF 1 "reg_or_0_operand" "fG")))]
"TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
"cvt%-q%/ %R1,%0"
[(set_attr "type" "fadd")
(define_insn "fix_truncdfdi2"
[(set (match_operand:DI 0 "reg_no_subreg_operand" "=f")
- (fix:DI (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
+ (fix:DI (match_operand:DF 1 "reg_or_0_operand" "fG")))]
"TARGET_FP"
"cvt%-q%/ %R1,%0"
[(set_attr "type" "fadd")
(define_insn_and_split "*fix_truncsfsi_ieee"
[(set (match_operand:SI 0 "memory_operand" "=m")
(subreg:SI (fix:DI (float_extend:DF
- (match_operand:SF 1 "reg_or_fp0_operand" "fG"))) 0))
+ (match_operand:SF 1 "reg_or_0_operand" "fG"))) 0))
(clobber (match_scratch:DI 2 "=&f"))
(clobber (match_scratch:SI 3 "=&f"))]
"TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
(define_insn_and_split "*fix_truncsfsi_internal"
[(set (match_operand:SI 0 "memory_operand" "=m")
(subreg:SI (fix:DI (float_extend:DF
- (match_operand:SF 1 "reg_or_fp0_operand" "fG"))) 0))
+ (match_operand:SF 1 "reg_or_0_operand" "fG"))) 0))
(clobber (match_scratch:DI 2 "=f"))]
"TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
"#"
(define_insn "*fix_truncsfdi_ieee"
[(set (match_operand:DI 0 "reg_no_subreg_operand" "=&f")
(fix:DI (float_extend:DF
- (match_operand:SF 1 "reg_or_fp0_operand" "fG"))))]
+ (match_operand:SF 1 "reg_or_0_operand" "fG"))))]
"TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
"cvt%-q%/ %R1,%0"
[(set_attr "type" "fadd")
(define_insn "fix_truncsfdi2"
[(set (match_operand:DI 0 "reg_no_subreg_operand" "=f")
(fix:DI (float_extend:DF
- (match_operand:SF 1 "reg_or_fp0_operand" "fG"))))]
+ (match_operand:SF 1 "reg_or_0_operand" "fG"))))]
"TARGET_FP"
"cvt%-q%/ %R1,%0"
[(set_attr "type" "fadd")
(define_insn "*truncdfsf2_ieee"
[(set (match_operand:SF 0 "register_operand" "=&f")
- (float_truncate:SF (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
+ (float_truncate:SF (match_operand:DF 1 "reg_or_0_operand" "fG")))]
"TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
"cvt%-%,%/ %R1,%0"
[(set_attr "type" "fadd")
(define_insn "truncdfsf2"
[(set (match_operand:SF 0 "register_operand" "=f")
- (float_truncate:SF (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
+ (float_truncate:SF (match_operand:DF 1 "reg_or_0_operand" "fG")))]
"TARGET_FP"
"cvt%-%,%/ %R1,%0"
[(set_attr "type" "fadd")
(define_insn "*divsf3_ieee"
[(set (match_operand:SF 0 "register_operand" "=&f")
- (div:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")
- (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
+ (div:SF (match_operand:SF 1 "reg_or_0_operand" "fG")
+ (match_operand:SF 2 "reg_or_0_operand" "fG")))]
"TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
"div%,%/ %R1,%R2,%0"
[(set_attr "type" "fdiv")
(define_insn "divsf3"
[(set (match_operand:SF 0 "register_operand" "=f")
- (div:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")
- (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
+ (div:SF (match_operand:SF 1 "reg_or_0_operand" "fG")
+ (match_operand:SF 2 "reg_or_0_operand" "fG")))]
"TARGET_FP"
"div%,%/ %R1,%R2,%0"
[(set_attr "type" "fdiv")
(define_insn "*divdf3_ieee"
[(set (match_operand:DF 0 "register_operand" "=&f")
- (div:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")
- (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
+ (div:DF (match_operand:DF 1 "reg_or_0_operand" "fG")
+ (match_operand:DF 2 "reg_or_0_operand" "fG")))]
"TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
"div%-%/ %R1,%R2,%0"
[(set_attr "type" "fdiv")
(define_insn "divdf3"
[(set (match_operand:DF 0 "register_operand" "=f")
- (div:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")
- (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
+ (div:DF (match_operand:DF 1 "reg_or_0_operand" "fG")
+ (match_operand:DF 2 "reg_or_0_operand" "fG")))]
"TARGET_FP"
"div%-%/ %R1,%R2,%0"
[(set_attr "type" "fdiv")
(define_insn "*divdf_ext1"
[(set (match_operand:DF 0 "register_operand" "=f")
- (div:DF (float_extend:DF (match_operand:SF 1 "reg_or_fp0_operand" "fG"))
- (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
+ (div:DF (float_extend:DF (match_operand:SF 1 "reg_or_0_operand" "fG"))
+ (match_operand:DF 2 "reg_or_0_operand" "fG")))]
"TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
"div%-%/ %R1,%R2,%0"
[(set_attr "type" "fdiv")
(define_insn "*divdf_ext2"
[(set (match_operand:DF 0 "register_operand" "=f")
- (div:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")
+ (div:DF (match_operand:DF 1 "reg_or_0_operand" "fG")
(float_extend:DF
- (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))]
+ (match_operand:SF 2 "reg_or_0_operand" "fG"))))]
"TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
"div%-%/ %R1,%R2,%0"
[(set_attr "type" "fdiv")
(define_insn "*divdf_ext3"
[(set (match_operand:DF 0 "register_operand" "=f")
- (div:DF (float_extend:DF (match_operand:SF 1 "reg_or_fp0_operand" "fG"))
- (float_extend:DF (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))]
+ (div:DF (float_extend:DF (match_operand:SF 1 "reg_or_0_operand" "fG"))
+ (float_extend:DF (match_operand:SF 2 "reg_or_0_operand" "fG"))))]
"TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
"div%-%/ %R1,%R2,%0"
[(set_attr "type" "fdiv")
(define_insn "*mulsf3_ieee"
[(set (match_operand:SF 0 "register_operand" "=&f")
- (mult:SF (match_operand:SF 1 "reg_or_fp0_operand" "%fG")
- (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
+ (mult:SF (match_operand:SF 1 "reg_or_0_operand" "%fG")
+ (match_operand:SF 2 "reg_or_0_operand" "fG")))]
"TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
"mul%,%/ %R1,%R2,%0"
[(set_attr "type" "fmul")
(define_insn "mulsf3"
[(set (match_operand:SF 0 "register_operand" "=f")
- (mult:SF (match_operand:SF 1 "reg_or_fp0_operand" "%fG")
- (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
+ (mult:SF (match_operand:SF 1 "reg_or_0_operand" "%fG")
+ (match_operand:SF 2 "reg_or_0_operand" "fG")))]
"TARGET_FP"
"mul%,%/ %R1,%R2,%0"
[(set_attr "type" "fmul")
(define_insn "*muldf3_ieee"
[(set (match_operand:DF 0 "register_operand" "=&f")
- (mult:DF (match_operand:DF 1 "reg_or_fp0_operand" "%fG")
- (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
+ (mult:DF (match_operand:DF 1 "reg_or_0_operand" "%fG")
+ (match_operand:DF 2 "reg_or_0_operand" "fG")))]
"TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
"mul%-%/ %R1,%R2,%0"
[(set_attr "type" "fmul")
(define_insn "muldf3"
[(set (match_operand:DF 0 "register_operand" "=f")
- (mult:DF (match_operand:DF 1 "reg_or_fp0_operand" "%fG")
- (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
+ (mult:DF (match_operand:DF 1 "reg_or_0_operand" "%fG")
+ (match_operand:DF 2 "reg_or_0_operand" "fG")))]
"TARGET_FP"
"mul%-%/ %R1,%R2,%0"
[(set_attr "type" "fmul")
(define_insn "*muldf_ext1"
[(set (match_operand:DF 0 "register_operand" "=f")
(mult:DF (float_extend:DF
- (match_operand:SF 1 "reg_or_fp0_operand" "fG"))
- (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
+ (match_operand:SF 1 "reg_or_0_operand" "fG"))
+ (match_operand:DF 2 "reg_or_0_operand" "fG")))]
"TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
"mul%-%/ %R1,%R2,%0"
[(set_attr "type" "fmul")
(define_insn "*muldf_ext2"
[(set (match_operand:DF 0 "register_operand" "=f")
(mult:DF (float_extend:DF
- (match_operand:SF 1 "reg_or_fp0_operand" "%fG"))
+ (match_operand:SF 1 "reg_or_0_operand" "%fG"))
(float_extend:DF
- (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))]
+ (match_operand:SF 2 "reg_or_0_operand" "fG"))))]
"TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
"mul%-%/ %R1,%R2,%0"
[(set_attr "type" "fmul")
(define_insn "*subsf3_ieee"
[(set (match_operand:SF 0 "register_operand" "=&f")
- (minus:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")
- (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
+ (minus:SF (match_operand:SF 1 "reg_or_0_operand" "fG")
+ (match_operand:SF 2 "reg_or_0_operand" "fG")))]
"TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
"sub%,%/ %R1,%R2,%0"
[(set_attr "type" "fadd")
(define_insn "subsf3"
[(set (match_operand:SF 0 "register_operand" "=f")
- (minus:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")
- (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
+ (minus:SF (match_operand:SF 1 "reg_or_0_operand" "fG")
+ (match_operand:SF 2 "reg_or_0_operand" "fG")))]
"TARGET_FP"
"sub%,%/ %R1,%R2,%0"
[(set_attr "type" "fadd")
(define_insn "*subdf3_ieee"
[(set (match_operand:DF 0 "register_operand" "=&f")
- (minus:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")
- (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
+ (minus:DF (match_operand:DF 1 "reg_or_0_operand" "fG")
+ (match_operand:DF 2 "reg_or_0_operand" "fG")))]
"TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
"sub%-%/ %R1,%R2,%0"
[(set_attr "type" "fadd")
(define_insn "subdf3"
[(set (match_operand:DF 0 "register_operand" "=f")
- (minus:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")
- (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
+ (minus:DF (match_operand:DF 1 "reg_or_0_operand" "fG")
+ (match_operand:DF 2 "reg_or_0_operand" "fG")))]
"TARGET_FP"
"sub%-%/ %R1,%R2,%0"
[(set_attr "type" "fadd")
(define_insn "*subdf_ext1"
[(set (match_operand:DF 0 "register_operand" "=f")
(minus:DF (float_extend:DF
- (match_operand:SF 1 "reg_or_fp0_operand" "fG"))
- (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
+ (match_operand:SF 1 "reg_or_0_operand" "fG"))
+ (match_operand:DF 2 "reg_or_0_operand" "fG")))]
"TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
"sub%-%/ %R1,%R2,%0"
[(set_attr "type" "fadd")
(define_insn "*subdf_ext2"
[(set (match_operand:DF 0 "register_operand" "=f")
- (minus:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")
+ (minus:DF (match_operand:DF 1 "reg_or_0_operand" "fG")
(float_extend:DF
- (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))]
+ (match_operand:SF 2 "reg_or_0_operand" "fG"))))]
"TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
"sub%-%/ %R1,%R2,%0"
[(set_attr "type" "fadd")
(define_insn "*subdf_ext3"
[(set (match_operand:DF 0 "register_operand" "=f")
(minus:DF (float_extend:DF
- (match_operand:SF 1 "reg_or_fp0_operand" "fG"))
+ (match_operand:SF 1 "reg_or_0_operand" "fG"))
(float_extend:DF
- (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))]
+ (match_operand:SF 2 "reg_or_0_operand" "fG"))))]
"TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
"sub%-%/ %R1,%R2,%0"
[(set_attr "type" "fadd")
(define_insn "*sqrtsf2_ieee"
[(set (match_operand:SF 0 "register_operand" "=&f")
- (sqrt:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")))]
+ (sqrt:SF (match_operand:SF 1 "reg_or_0_operand" "fG")))]
"TARGET_FP && TARGET_FIX && alpha_fptm >= ALPHA_FPTM_SU"
"sqrt%,%/ %R1,%0"
[(set_attr "type" "fsqrt")
(define_insn "sqrtsf2"
[(set (match_operand:SF 0 "register_operand" "=f")
- (sqrt:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")))]
+ (sqrt:SF (match_operand:SF 1 "reg_or_0_operand" "fG")))]
"TARGET_FP && TARGET_FIX"
"sqrt%,%/ %R1,%0"
[(set_attr "type" "fsqrt")
(define_insn "*sqrtdf2_ieee"
[(set (match_operand:DF 0 "register_operand" "=&f")
- (sqrt:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
+ (sqrt:DF (match_operand:DF 1 "reg_or_0_operand" "fG")))]
"TARGET_FP && TARGET_FIX && alpha_fptm >= ALPHA_FPTM_SU"
"sqrt%-%/ %R1,%0"
[(set_attr "type" "fsqrt")
(define_insn "sqrtdf2"
[(set (match_operand:DF 0 "register_operand" "=f")
- (sqrt:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
+ (sqrt:DF (match_operand:DF 1 "reg_or_0_operand" "fG")))]
"TARGET_FP && TARGET_FIX"
"sqrt%-%/ %1,%0"
[(set_attr "type" "fsqrt")
(define_insn "*cmpdf_ieee"
[(set (match_operand:DF 0 "register_operand" "=&f")
(match_operator:DF 1 "alpha_fp_comparison_operator"
- [(match_operand:DF 2 "reg_or_fp0_operand" "fG")
- (match_operand:DF 3 "reg_or_fp0_operand" "fG")]))]
+ [(match_operand:DF 2 "reg_or_0_operand" "fG")
+ (match_operand:DF 3 "reg_or_0_operand" "fG")]))]
"TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
"cmp%-%C1%/ %R2,%R3,%0"
[(set_attr "type" "fadd")
(define_insn "*cmpdf_internal"
[(set (match_operand:DF 0 "register_operand" "=f")
(match_operator:DF 1 "alpha_fp_comparison_operator"
- [(match_operand:DF 2 "reg_or_fp0_operand" "fG")
- (match_operand:DF 3 "reg_or_fp0_operand" "fG")]))]
+ [(match_operand:DF 2 "reg_or_0_operand" "fG")
+ (match_operand:DF 3 "reg_or_0_operand" "fG")]))]
"TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
"cmp%-%C1%/ %R2,%R3,%0"
[(set_attr "type" "fadd")
[(set (match_operand:DF 0 "register_operand" "=&f")
(match_operator:DF 1 "alpha_fp_comparison_operator"
[(float_extend:DF
- (match_operand:SF 2 "reg_or_fp0_operand" "fG"))
- (match_operand:DF 3 "reg_or_fp0_operand" "fG")]))]
+ (match_operand:SF 2 "reg_or_0_operand" "fG"))
+ (match_operand:DF 3 "reg_or_0_operand" "fG")]))]
"TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
"cmp%-%C1%/ %R2,%R3,%0"
[(set_attr "type" "fadd")
[(set (match_operand:DF 0 "register_operand" "=f")
(match_operator:DF 1 "alpha_fp_comparison_operator"
[(float_extend:DF
- (match_operand:SF 2 "reg_or_fp0_operand" "fG"))
- (match_operand:DF 3 "reg_or_fp0_operand" "fG")]))]
+ (match_operand:SF 2 "reg_or_0_operand" "fG"))
+ (match_operand:DF 3 "reg_or_0_operand" "fG")]))]
"TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
"cmp%-%C1%/ %R2,%R3,%0"
[(set_attr "type" "fadd")
(define_insn "*cmpdf_ieee_ext2"
[(set (match_operand:DF 0 "register_operand" "=&f")
(match_operator:DF 1 "alpha_fp_comparison_operator"
- [(match_operand:DF 2 "reg_or_fp0_operand" "fG")
+ [(match_operand:DF 2 "reg_or_0_operand" "fG")
(float_extend:DF
- (match_operand:SF 3 "reg_or_fp0_operand" "fG"))]))]
+ (match_operand:SF 3 "reg_or_0_operand" "fG"))]))]
"TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
"cmp%-%C1%/ %R2,%R3,%0"
[(set_attr "type" "fadd")
(define_insn "*cmpdf_ext2"
[(set (match_operand:DF 0 "register_operand" "=f")
(match_operator:DF 1 "alpha_fp_comparison_operator"
- [(match_operand:DF 2 "reg_or_fp0_operand" "fG")
+ [(match_operand:DF 2 "reg_or_0_operand" "fG")
(float_extend:DF
- (match_operand:SF 3 "reg_or_fp0_operand" "fG"))]))]
+ (match_operand:SF 3 "reg_or_0_operand" "fG"))]))]
"TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
"cmp%-%C1%/ %R2,%R3,%0"
[(set_attr "type" "fadd")
[(set (match_operand:DF 0 "register_operand" "=&f")
(match_operator:DF 1 "alpha_fp_comparison_operator"
[(float_extend:DF
- (match_operand:SF 2 "reg_or_fp0_operand" "fG"))
+ (match_operand:SF 2 "reg_or_0_operand" "fG"))
(float_extend:DF
- (match_operand:SF 3 "reg_or_fp0_operand" "fG"))]))]
+ (match_operand:SF 3 "reg_or_0_operand" "fG"))]))]
"TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
"cmp%-%C1%/ %R2,%R3,%0"
[(set_attr "type" "fadd")
[(set (match_operand:DF 0 "register_operand" "=f")
(match_operator:DF 1 "alpha_fp_comparison_operator"
[(float_extend:DF
- (match_operand:SF 2 "reg_or_fp0_operand" "fG"))
+ (match_operand:SF 2 "reg_or_0_operand" "fG"))
(float_extend:DF
- (match_operand:SF 3 "reg_or_fp0_operand" "fG"))]))]
+ (match_operand:SF 3 "reg_or_0_operand" "fG"))]))]
"TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
"cmp%-%C1%/ %R2,%R3,%0"
[(set_attr "type" "fadd")
[(set (match_operand:DF 0 "register_operand" "=f,f")
(if_then_else:DF
(match_operator 3 "signed_comparison_operator"
- [(match_operand:DF 4 "reg_or_fp0_operand" "fG,fG")
- (match_operand:DF 2 "fp0_operand" "G,G")])
- (match_operand:DF 1 "reg_or_fp0_operand" "fG,0")
- (match_operand:DF 5 "reg_or_fp0_operand" "0,fG")))]
+ [(match_operand:DF 4 "reg_or_0_operand" "fG,fG")
+ (match_operand:DF 2 "const0_operand" "G,G")])
+ (match_operand:DF 1 "reg_or_0_operand" "fG,0")
+ (match_operand:DF 5 "reg_or_0_operand" "0,fG")))]
"TARGET_FP"
"@
fcmov%C3 %R4,%R1,%0
[(set (match_operand:SF 0 "register_operand" "=f,f")
(if_then_else:SF
(match_operator 3 "signed_comparison_operator"
- [(match_operand:DF 4 "reg_or_fp0_operand" "fG,fG")
- (match_operand:DF 2 "fp0_operand" "G,G")])
- (match_operand:SF 1 "reg_or_fp0_operand" "fG,0")
- (match_operand:SF 5 "reg_or_fp0_operand" "0,fG")))]
+ [(match_operand:DF 4 "reg_or_0_operand" "fG,fG")
+ (match_operand:DF 2 "const0_operand" "G,G")])
+ (match_operand:SF 1 "reg_or_0_operand" "fG,0")
+ (match_operand:SF 5 "reg_or_0_operand" "0,fG")))]
"TARGET_FP"
"@
fcmov%C3 %R4,%R1,%0
[(set (match_operand:DF 0 "register_operand" "=f,f")
(if_then_else:DF
(match_operator 3 "signed_comparison_operator"
- [(match_operand:DF 4 "reg_or_fp0_operand" "fG,fG")
- (match_operand:DF 2 "fp0_operand" "G,G")])
- (float_extend:DF (match_operand:SF 1 "reg_or_fp0_operand" "fG,0"))
- (match_operand:DF 5 "reg_or_fp0_operand" "0,fG")))]
+ [(match_operand:DF 4 "reg_or_0_operand" "fG,fG")
+ (match_operand:DF 2 "const0_operand" "G,G")])
+ (float_extend:DF (match_operand:SF 1 "reg_or_0_operand" "fG,0"))
+ (match_operand:DF 5 "reg_or_0_operand" "0,fG")))]
"TARGET_FP"
"@
fcmov%C3 %R4,%R1,%0
(if_then_else:DF
(match_operator 3 "signed_comparison_operator"
[(float_extend:DF
- (match_operand:SF 4 "reg_or_fp0_operand" "fG,fG"))
- (match_operand:DF 2 "fp0_operand" "G,G")])
- (match_operand:DF 1 "reg_or_fp0_operand" "fG,0")
- (match_operand:DF 5 "reg_or_fp0_operand" "0,fG")))]
+ (match_operand:SF 4 "reg_or_0_operand" "fG,fG"))
+ (match_operand:DF 2 "const0_operand" "G,G")])
+ (match_operand:DF 1 "reg_or_0_operand" "fG,0")
+ (match_operand:DF 5 "reg_or_0_operand" "0,fG")))]
"TARGET_FP"
"@
fcmov%C3 %R4,%R1,%0
(if_then_else:SF
(match_operator 3 "signed_comparison_operator"
[(float_extend:DF
- (match_operand:SF 4 "reg_or_fp0_operand" "fG,fG"))
- (match_operand:DF 2 "fp0_operand" "G,G")])
- (match_operand:SF 1 "reg_or_fp0_operand" "fG,0")
- (match_operand:SF 5 "reg_or_fp0_operand" "0,fG")))]
+ (match_operand:SF 4 "reg_or_0_operand" "fG,fG"))
+ (match_operand:DF 2 "const0_operand" "G,G")])
+ (match_operand:SF 1 "reg_or_0_operand" "fG,0")
+ (match_operand:SF 5 "reg_or_0_operand" "0,fG")))]
"TARGET_FP"
"@
fcmov%C3 %R4,%R1,%0
(if_then_else:DF
(match_operator 3 "signed_comparison_operator"
[(float_extend:DF
- (match_operand:SF 4 "reg_or_fp0_operand" "fG,fG"))
- (match_operand:DF 2 "fp0_operand" "G,G")])
- (float_extend:DF (match_operand:SF 1 "reg_or_fp0_operand" "fG,0"))
- (match_operand:DF 5 "reg_or_fp0_operand" "0,fG")))]
+ (match_operand:SF 4 "reg_or_0_operand" "fG,fG"))
+ (match_operand:DF 2 "const0_operand" "G,G")])
+ (float_extend:DF (match_operand:SF 1 "reg_or_0_operand" "fG,0"))
+ (match_operand:DF 5 "reg_or_0_operand" "0,fG")))]
"TARGET_FP"
"@
fcmov%C3 %R4,%R1,%0
(define_expand "maxdf3"
[(set (match_dup 3)
- (le:DF (match_operand:DF 1 "reg_or_fp0_operand" "")
- (match_operand:DF 2 "reg_or_fp0_operand" "")))
+ (le:DF (match_operand:DF 1 "reg_or_0_operand" "")
+ (match_operand:DF 2 "reg_or_0_operand" "")))
(set (match_operand:DF 0 "register_operand" "")
(if_then_else:DF (eq (match_dup 3) (match_dup 4))
(match_dup 1) (match_dup 2)))]
(define_expand "mindf3"
[(set (match_dup 3)
- (lt:DF (match_operand:DF 1 "reg_or_fp0_operand" "")
- (match_operand:DF 2 "reg_or_fp0_operand" "")))
+ (lt:DF (match_operand:DF 1 "reg_or_0_operand" "")
+ (match_operand:DF 2 "reg_or_0_operand" "")))
(set (match_operand:DF 0 "register_operand" "")
(if_then_else:DF (ne (match_dup 3) (match_dup 4))
(match_dup 1) (match_dup 2)))]
(define_expand "maxsf3"
[(set (match_dup 3)
- (le:DF (float_extend:DF (match_operand:SF 1 "reg_or_fp0_operand" ""))
- (float_extend:DF (match_operand:SF 2 "reg_or_fp0_operand" ""))))
+ (le:DF (float_extend:DF (match_operand:SF 1 "reg_or_0_operand" ""))
+ (float_extend:DF (match_operand:SF 2 "reg_or_0_operand" ""))))
(set (match_operand:SF 0 "register_operand" "")
(if_then_else:SF (eq (match_dup 3) (match_dup 4))
(match_dup 1) (match_dup 2)))]
(define_expand "minsf3"
[(set (match_dup 3)
- (lt:DF (float_extend:DF (match_operand:SF 1 "reg_or_fp0_operand" ""))
- (float_extend:DF (match_operand:SF 2 "reg_or_fp0_operand" ""))))
+ (lt:DF (float_extend:DF (match_operand:SF 1 "reg_or_0_operand" ""))
+ (float_extend:DF (match_operand:SF 2 "reg_or_0_operand" ""))))
(set (match_operand:SF 0 "register_operand" "")
(if_then_else:SF (ne (match_dup 3) (match_dup 4))
(match_dup 1) (match_dup 2)))]
[(set (pc)
(if_then_else
(match_operator 1 "signed_comparison_operator"
- [(match_operand:DF 2 "reg_or_fp0_operand" "fG")
- (match_operand:DF 3 "fp0_operand" "G")])
+ [(match_operand:DF 2 "reg_or_0_operand" "fG")
+ (match_operand:DF 3 "const0_operand" "G")])
(label_ref (match_operand 0 "" ""))
(pc)))]
"TARGET_FP"
(if_then_else
(match_operator 1 "signed_comparison_operator"
[(float_extend:DF
- (match_operand:SF 2 "reg_or_fp0_operand" "fG"))
- (match_operand:DF 3 "fp0_operand" "G")])
+ (match_operand:SF 2 "reg_or_0_operand" "fG"))
+ (match_operand:DF 3 "const0_operand" "G")])
(label_ref (match_operand 0 "" ""))
(pc)))]
"TARGET_FP"
;; and compares.
(define_expand "cmpdf"
- [(set (cc0) (compare (match_operand:DF 0 "reg_or_fp0_operand" "")
- (match_operand:DF 1 "reg_or_fp0_operand" "")))]
+ [(set (cc0) (compare (match_operand:DF 0 "reg_or_0_operand" "")
+ (match_operand:DF 1 "reg_or_0_operand" "")))]
"TARGET_FP"
{
alpha_compare.op0 = operands[0];
(define_expand "sibcall"
[(parallel [(call (mem:DI (match_operand 0 "" ""))
(match_operand 1 "" ""))
- (use (reg:DI 29))])]
+ (unspec [(reg:DI 29)] UNSPEC_SIBCALL)])]
"TARGET_ABI_OSF"
{
if (GET_CODE (operands[0]) != MEM)
[(parallel [(set (match_operand 0 "" "")
(call (mem:DI (match_operand 1 "" ""))
(match_operand 2 "" "")))
- (use (reg:DI 29))])]
+ (unspec [(reg:DI 29)] UNSPEC_SIBCALL)])]
"TARGET_ABI_OSF"
{
if (GET_CODE (operands[1]) != MEM)
(match_dup 1))
(set (reg:DI 26) (plus:DI (pc) (const_int 4)))
(unspec_volatile [(reg:DI 29)] UNSPECV_BLOCKAGE)
- (use (match_dup 0))])]
+ (use (match_dup 0))
+ (use (match_dup 3))])]
{
if (CONSTANT_P (operands[0]))
{
operands[2] = gen_rtx_REG (Pmode, 27);
- emit_move_insn (operands[2], operands[0]);
+ operands[3] = GEN_INT (alpha_next_sequence_number++);
+ emit_insn (gen_movdi_er_high_g (operands[2], pic_offset_table_rtx,
+ operands[0], operands[3]));
}
else
{
operands[2] = operands[0];
operands[0] = const0_rtx;
+ operands[3] = const0_rtx;
}
})
(match_dup 1))
(set (reg:DI 26) (plus:DI (pc) (const_int 4)))
(unspec_volatile [(reg:DI 29)] UNSPECV_BLOCKAGE)
- (use (match_dup 0))])
+ (use (match_dup 0))
+ (use (match_dup 4))])
(set (reg:DI 29)
(unspec_volatile:DI [(reg:DI 26) (match_dup 3)] UNSPECV_LDGP1))
(set (reg:DI 29)
if (CONSTANT_P (operands[0]))
{
operands[2] = gen_rtx_REG (Pmode, 27);
- emit_move_insn (operands[2], operands[0]);
+ operands[4] = GEN_INT (alpha_next_sequence_number++);
+ emit_insn (gen_movdi_er_high_g (operands[2], pic_offset_table_rtx,
+ operands[0], operands[4]));
}
else
{
operands[2] = operands[0];
operands[0] = const0_rtx;
+ operands[4] = const0_rtx;
}
operands[3] = GEN_INT (alpha_next_sequence_number++);
})
(match_operand 1 "" ""))
(set (reg:DI 26) (plus:DI (pc) (const_int 4)))
(unspec_volatile [(reg:DI 29)] UNSPECV_BLOCKAGE)
- (use (match_operand 2 "" ""))]
+ (use (match_operand 2 "" ""))
+ (use (match_operand 3 "const_int_operand" ""))]
"TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
- "jsr $26,(%0),%2"
+ "jsr $26,(%0),%2%J3"
[(set_attr "type" "jsr")])
(define_insn "*call_osf_1_noreturn"
(define_insn "*sibcall_osf_1_er"
[(call (mem:DI (match_operand:DI 0 "symbolic_operand" "R,s"))
(match_operand 1 "" ""))
- (use (reg:DI 29))]
+ (unspec [(reg:DI 29)] UNSPEC_SIBCALL)]
"TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
"@
br $31,$%0..ng
(define_insn "*sibcall_osf_1"
[(call (mem:DI (match_operand:DI 0 "symbolic_operand" "R,s"))
(match_operand 1 "" ""))
- (use (reg:DI 29))]
+ (unspec [(reg:DI 29)] UNSPEC_SIBCALL)]
"! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
"@
br $31,$%0..ng
[(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)]
""
""
- [(set_attr "length" "0")])
+ [(set_attr "length" "0")
+ (set_attr "type" "none")])
(define_insn "jump"
[(set (pc)
""
"call_pal 0x86"
[(set_attr "type" "ibr")])
+
+;; BUGCHK is documented common to OSF/1 and VMS PALcode.
+;; NT does not document anything at 0x81 -- presumably it would generate
+;; the equivalent of SIGILL, but this isn't that important.
+;; ??? Presuming unicosmk uses either OSF/1 or VMS PALcode.
+(define_insn "trap"
+ [(trap_if (const_int 1) (const_int 0))]
+ "!TARGET_ABI_WINDOWS_NT"
+ "call_pal 0x81"
+ [(set_attr "type" "ibr")])
+
+;; For userland, we load the thread pointer from the TCB.
+;; For the kernel, we load the per-cpu private value.
+
+(define_insn "load_tp"
+ [(set (match_operand:DI 0 "register_operand" "=v")
+ (unspec:DI [(const_int 0)] UNSPEC_TP))]
+ "TARGET_ABI_OSF"
+{
+ if (TARGET_TLS_KERNEL)
+ return "call_pal 0x32";
+ else
+ return "call_pal 0x9e";
+}
+ [(set_attr "type" "ibr")])
+
+;; For completeness, and possibly a __builtin function, here's how to
+;; set the thread pointer. Since we don't describe enough of this
+;; quantity for CSE, we have to use a volatile unspec, and then there's
+;; not much point in creating an R16_REG register class.
+
+(define_expand "set_tp"
+ [(set (reg:DI 16) (match_operand:DI 0 "input_operand" ""))
+ (unspec_volatile [(reg:DI 16)] UNSPECV_SET_TP)]
+ "TARGET_ABI_OSF"
+ "")
+
+(define_insn "*set_tp"
+ [(unspec_volatile [(reg:DI 16)] UNSPECV_SET_TP)]
+ "TARGET_ABI_OSF"
+{
+ if (TARGET_TLS_KERNEL)
+ return "call_pal 0x31";
+ else
+ return "call_pal 0x9f";
+}
+ [(set_attr "type" "ibr")])
\f
;; Finally, we have the basic data motion insns. The byte and word insns
;; are done via define_expand. Start with the floating-point insns, since
(match_operand:SF 1 "input_operand" "fG,m,*rG,m,fG,*r"))]
"TARGET_FPREGS && ! TARGET_FIX
&& (register_operand (operands[0], SFmode)
- || reg_or_fp0_operand (operands[1], SFmode))"
+ || reg_or_0_operand (operands[1], SFmode))"
"@
cpys %R1,%R1,%0
ld%, %0,%1
(match_operand:SF 1 "input_operand" "fG,m,*rG,m,fG,*r,*r,f"))]
"TARGET_FPREGS && TARGET_FIX
&& (register_operand (operands[0], SFmode)
- || reg_or_fp0_operand (operands[1], SFmode))"
+ || reg_or_0_operand (operands[1], SFmode))"
"@
cpys %R1,%R1,%0
ld%, %0,%1
(match_operand:SF 1 "input_operand" "rG,m,r"))]
"! TARGET_FPREGS
&& (register_operand (operands[0], SFmode)
- || reg_or_fp0_operand (operands[1], SFmode))"
+ || reg_or_0_operand (operands[1], SFmode))"
"@
bis $31,%r1,%0
ldl %0,%1
(match_operand:DF 1 "input_operand" "fG,m,*rG,m,fG,*r"))]
"TARGET_FPREGS && ! TARGET_FIX
&& (register_operand (operands[0], DFmode)
- || reg_or_fp0_operand (operands[1], DFmode))"
+ || reg_or_0_operand (operands[1], DFmode))"
"@
cpys %R1,%R1,%0
ld%- %0,%1
(match_operand:DF 1 "input_operand" "fG,m,*rG,m,fG,*r,*r,f"))]
"TARGET_FPREGS && TARGET_FIX
&& (register_operand (operands[0], DFmode)
- || reg_or_fp0_operand (operands[1], DFmode))"
+ || reg_or_0_operand (operands[1], DFmode))"
"@
cpys %R1,%R1,%0
ld%- %0,%1
(match_operand:DF 1 "input_operand" "rG,m,r"))]
"! TARGET_FPREGS
&& (register_operand (operands[0], DFmode)
- || reg_or_fp0_operand (operands[1], DFmode))"
+ || reg_or_0_operand (operands[1], DFmode))"
"@
bis $31,%r1,%0
ldq %0,%1
[(set (match_operand:TF 0 "nonimmediate_operand" "=r,o")
(match_operand:TF 1 "input_operand" "roG,rG"))]
"register_operand (operands[0], TFmode)
- || reg_or_fp0_operand (operands[1], TFmode)"
+ || reg_or_0_operand (operands[1], TFmode)"
"#"
"reload_completed"
[(set (match_dup 0) (match_dup 2))
""
{
if (GET_CODE (operands[0]) == MEM
- && ! reg_or_fp0_operand (operands[1], SFmode))
+ && ! reg_or_0_operand (operands[1], SFmode))
operands[1] = force_reg (SFmode, operands[1]);
})
""
{
if (GET_CODE (operands[0]) == MEM
- && ! reg_or_fp0_operand (operands[1], DFmode))
+ && ! reg_or_0_operand (operands[1], DFmode))
operands[1] = force_reg (DFmode, operands[1]);
})
""
{
if (GET_CODE (operands[0]) == MEM
- && ! reg_or_fp0_operand (operands[1], TFmode))
+ && ! reg_or_0_operand (operands[1], TFmode))
operands[1] = force_reg (TFmode, operands[1]);
})
itofs %1,%0"
[(set_attr "type" "ilog,iadd,iadd,ild,ist,fcpys,fld,fst,ftoi,itof")])
-(define_insn "*movsi_nt_vms"
+(define_insn "*movsi_nt_vms_nofix"
[(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,r,m,*f,*f,m")
(match_operand:SI 1 "input_operand" "rJ,K,L,s,m,rJ,*fJ,m,*f"))]
"(TARGET_ABI_WINDOWS_NT || TARGET_ABI_OPEN_VMS)
+ && !TARGET_FIX
&& (register_operand (operands[0], SImode)
|| reg_or_0_operand (operands[1], SImode))"
"@
st%, %R1,%0"
[(set_attr "type" "ilog,iadd,iadd,ldsym,ild,ist,fcpys,fld,fst")])
+(define_insn "*movsi_nt_vms_fix"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,r,m,*f,*f,m,r,*f")
+ (match_operand:SI 1 "input_operand" "rJ,K,L,s,m,rJ,*fJ,m,*f,*f,r"))]
+ "(TARGET_ABI_WINDOWS_NT || TARGET_ABI_OPEN_VMS)
+ && TARGET_FIX
+ && (register_operand (operands[0], SImode)
+ || reg_or_0_operand (operands[1], SImode))"
+ "@
+ bis $31,%1,%0
+ lda %0,%1
+ ldah %0,%h1
+ lda %0,%1
+ ldl %0,%1
+ stl %r1,%0
+ cpys %R1,%R1,%0
+ ld%, %0,%1
+ st%, %R1,%0
+ ftois %1,%0
+ itofs %1,%0"
+ [(set_attr "type" "ilog,iadd,iadd,ldsym,ild,ist,fcpys,fld,fst,ftoi,itof")])
+
(define_insn "*movhi_nobwx"
[(set (match_operand:HI 0 "register_operand" "=r,r")
(match_operand:HI 1 "input_operand" "rJ,n"))]
return "lda %0,%2(%1)\t\t!gprellow";
})
+(define_split
+ [(set (match_operand:DI 0 "register_operand" "")
+ (match_operand:DI 1 "small_symbolic_operand" ""))]
+ "TARGET_EXPLICIT_RELOCS && reload_completed"
+ [(set (match_dup 0)
+ (lo_sum:DI (match_dup 2) (match_dup 1)))]
+ "operands[2] = pic_offset_table_rtx;")
+
+(define_split
+ [(set (match_operand:DI 0 "register_operand" "")
+ (match_operand:DI 1 "local_symbolic_operand" ""))]
+ "TARGET_EXPLICIT_RELOCS && reload_completed"
+ [(set (match_dup 0)
+ (plus:DI (match_dup 2) (high:DI (match_dup 1))))
+ (set (match_dup 0)
+ (lo_sum:DI (match_dup 0) (match_dup 1)))]
+ "operands[2] = pic_offset_table_rtx;")
+
+(define_split
+ [(match_operand 0 "some_small_symbolic_operand" "")]
+ "TARGET_EXPLICIT_RELOCS && reload_completed"
+ [(match_dup 0)]
+ "operands[0] = split_small_symbolic_operand (operands[0]);")
+
(define_insn "movdi_er_high_g"
[(set (match_operand:DI 0 "register_operand" "=r")
(unspec:DI [(match_operand:DI 1 "register_operand" "r")
(match_operand 3 "const_int_operand" "")]
UNSPEC_LITERAL))]
"TARGET_EXPLICIT_RELOCS"
- "ldq %0,%2(%1)\t\t!literal"
+{
+ if (INTVAL (operands[3]) == 0)
+ return "ldq %0,%2(%1)\t\t!literal";
+ else
+ return "ldq %0,%2(%1)\t\t!literal!%3";
+}
[(set_attr "type" "ldsym")])
+(define_split
+ [(set (match_operand:DI 0 "register_operand" "")
+ (match_operand:DI 1 "global_symbolic_operand" ""))]
+ "TARGET_EXPLICIT_RELOCS && reload_completed"
+ [(set (match_dup 0)
+ (unspec:DI [(match_dup 2)
+ (match_dup 1)
+ (const_int 0)] UNSPEC_LITERAL))]
+ "operands[2] = pic_offset_table_rtx;")
+
+;; With RTL inlining, at -O3, rtl is generated, stored, then actually
+;; compiled at the end of compilation. In the meantime, someone can
+;; re-encode-section-info on some symbol changing it e.g. from global
+;; to local-not-small. If this happens, we'd have emitted a plain
+;; load rather than a high+losum load and not recognize the insn.
+;;
+;; So if rtl inlining is in effect, we delay the global/not-global
+;; decision until rest_of_compilation by wrapping it in an UNSPEC_SYMBOL.
+
+(define_insn_and_split "movdi_er_maybe_g"
+ [(set (match_operand:DI 0 "register_operand" "=r")
+ (unspec:DI [(match_operand:DI 1 "symbolic_operand" "")]
+ UNSPEC_SYMBOL))]
+ "TARGET_EXPLICIT_RELOCS && flag_inline_functions"
+ "#"
+ ""
+ [(set (match_dup 0) (match_dup 1))]
+{
+ if (local_symbolic_operand (operands[1], Pmode)
+ && !small_symbolic_operand (operands[1], Pmode))
+ {
+ rtx subtarget = no_new_pseudos ? operands[0] : gen_reg_rtx (Pmode);
+ rtx tmp;
+
+ tmp = gen_rtx_HIGH (Pmode, operands[1]);
+ if (reload_completed)
+ tmp = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, tmp);
+ emit_insn (gen_rtx_SET (VOIDmode, subtarget, tmp));
+
+ tmp = gen_rtx_LO_SUM (Pmode, subtarget, operands[1]);
+ emit_insn (gen_rtx_SET (VOIDmode, operands[0], tmp));
+ DONE;
+ }
+})
+
+(define_insn "movdi_er_tlsgd"
+ [(set (match_operand:DI 0 "register_operand" "=r")
+ (unspec:DI [(match_operand:DI 1 "register_operand" "r")
+ (match_operand:DI 2 "symbolic_operand" "")
+ (match_operand 3 "const_int_operand" "")]
+ UNSPEC_TLSGD))]
+ "HAVE_AS_TLS"
+{
+ if (INTVAL (operands[3]) == 0)
+ return "lda %0,%2(%1)\t\t!tlsgd";
+ else
+ return "lda %0,%2(%1)\t\t!tlsgd!%3";
+})
+
+(define_insn "movdi_er_tlsldm"
+ [(set (match_operand:DI 0 "register_operand" "=r")
+ (unspec:DI [(match_operand:DI 1 "register_operand" "r")
+ (match_operand 2 "const_int_operand" "")]
+ UNSPEC_TLSLDM))]
+ "HAVE_AS_TLS"
+{
+ if (INTVAL (operands[2]) == 0)
+ return "lda %0,%&(%1)\t\t!tlsldm";
+ else
+ return "lda %0,%&(%1)\t\t!tlsldm!%2";
+})
+
+(define_insn "*movdi_er_gotdtp"
+ [(set (match_operand:DI 0 "register_operand" "=r")
+ (unspec:DI [(match_operand:DI 1 "register_operand" "r")
+ (match_operand:DI 2 "symbolic_operand" "")]
+ UNSPEC_DTPREL))]
+ "HAVE_AS_TLS"
+ "ldq %0,%2(%1)\t\t!gotdtprel"
+ [(set_attr "type" "ild")])
+
+(define_split
+ [(set (match_operand:DI 0 "register_operand" "")
+ (match_operand:DI 1 "gotdtp_symbolic_operand" ""))]
+ "HAVE_AS_TLS && reload_completed"
+ [(set (match_dup 0)
+ (unspec:DI [(match_dup 2)
+ (match_dup 1)] UNSPEC_DTPREL))]
+{
+ operands[1] = XVECEXP (XEXP (operands[1], 0), 0, 0);
+ operands[2] = pic_offset_table_rtx;
+})
+
+(define_insn "*movdi_er_gottp"
+ [(set (match_operand:DI 0 "register_operand" "=r")
+ (unspec:DI [(match_operand:DI 1 "register_operand" "r")
+ (match_operand:DI 2 "symbolic_operand" "")]
+ UNSPEC_TPREL))]
+ "HAVE_AS_TLS"
+ "ldq %0,%2(%1)\t\t!gottprel"
+ [(set_attr "type" "ild")])
+
+(define_split
+ [(set (match_operand:DI 0 "register_operand" "")
+ (match_operand:DI 1 "gottp_symbolic_operand" ""))]
+ "HAVE_AS_TLS && reload_completed"
+ [(set (match_dup 0)
+ (unspec:DI [(match_dup 2)
+ (match_dup 1)] UNSPEC_TPREL))]
+{
+ operands[1] = XVECEXP (XEXP (operands[1], 0), 0, 0);
+ operands[2] = pic_offset_table_rtx;
+})
+
(define_insn "*movdi_er_nofix"
- [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,r,r,m,*f,*f,Q")
- (match_operand:DI 1 "input_operand" "rJ,K,L,T,m,rJ,*fJ,Q,*f"))]
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,r,r,r,m,*f,*f,Q")
+ (match_operand:DI 1 "input_operand" "rJ,K,L,T,s,m,rJ,*fJ,Q,*f"))]
"TARGET_EXPLICIT_RELOCS && ! TARGET_FIX
&& (register_operand (operands[0], DImode)
|| reg_or_0_operand (operands[1], DImode))"
mov %r1,%0
lda %0,%1($31)
ldah %0,%h1($31)
- ldah %0,%H1
+ #
+ #
ldq%A1 %0,%1
stq%A0 %r1,%0
fmov %R1,%0
ldt %0,%1
stt %R1,%0"
- [(set_attr "type" "ilog,iadd,iadd,iadd,ild,ist,fcpys,fld,fst")])
+ [(set_attr "type" "ilog,iadd,iadd,iadd,ldsym,ild,ist,fcpys,fld,fst")])
;; The 'U' constraint matches symbolic operands on Unicos/Mk. Those should
;; have been split up by the rules above but we shouldn't reject the
(set_attr "length" "*,*,*,16,*,*,*,*,*,*")])
(define_insn "*movdi_er_fix"
- [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,r,r,m,*f,*f,Q,r,*f")
- (match_operand:DI 1 "input_operand" "rJ,K,L,T,m,rJ,*fJ,Q,*f,*f,r"))]
+ [(set (match_operand:DI 0 "nonimmediate_operand"
+ "=r,r,r,r,r,r, m, *f,*f, Q, r,*f")
+ (match_operand:DI 1 "input_operand"
+ "rJ,K,L,T,s,m,rJ,*fJ, Q,*f,*f, r"))]
"TARGET_EXPLICIT_RELOCS && TARGET_FIX
&& (register_operand (operands[0], DImode)
|| reg_or_0_operand (operands[1], DImode))"
mov %r1,%0
lda %0,%1($31)
ldah %0,%h1($31)
- ldah %0,%H1
+ #
+ #
ldq%A1 %0,%1
stq%A0 %r1,%0
fmov %R1,%0
stt %R1,%0
ftoit %1,%0
itoft %1,%0"
- [(set_attr "type" "ilog,iadd,iadd,iadd,ild,ist,fcpys,fld,fst,ftoi,itof")])
+ [(set_attr "type" "ilog,iadd,iadd,iadd,ldsym,ild,ist,fcpys,fld,fst,ftoi,itof")])
(define_insn "*movdi_fix"
[(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,r,r,m,*f,*f,Q,r,*f")
DONE;
})
\f
-;; Bit field extract patterns which use ext[wlq][lh]
+;; Vector operations
-(define_expand "extv"
- [(set (match_operand:DI 0 "register_operand" "")
- (sign_extract:DI (match_operand:QI 1 "memory_operand" "")
- (match_operand:DI 2 "immediate_operand" "")
- (match_operand:DI 3 "immediate_operand" "")))]
+(define_expand "movv8qi"
+ [(set (match_operand:V8QI 0 "nonimmediate_operand" "")
+ (match_operand:V8QI 1 "general_operand" ""))]
""
{
- int ofs;
+ if (alpha_expand_mov (V8QImode, operands))
+ DONE;
+})
- /* We can do 16, 32 and 64 bit fields, if aligned on byte boundaries. */
- if (INTVAL (operands[3]) % 8 != 0
- || (INTVAL (operands[2]) != 16
- && INTVAL (operands[2]) != 32
- && INTVAL (operands[2]) != 64))
- FAIL;
+(define_insn "*movv8qi_fix"
+ [(set (match_operand:V8QI 0 "nonimmediate_operand" "=r,r,m,*f,*f,m,r,*f")
+ (match_operand:V8QI 1 "input_operand" "rW,m,rW,*fW,m,*f,*f,r"))]
+ "TARGET_FIX
+ && (register_operand (operands[0], V8QImode)
+ || reg_or_0_operand (operands[1], V8QImode))"
+ "@
+ bis $31,%r1,%0
+ ldq %0,%1
+ stq %r1,%0
+ cpys %R1,%R1,%0
+ ldt %0,%1
+ stt %R1,%0
+ ftoit %1,%0
+ itoft %1,%0"
+ [(set_attr "type" "ilog,ild,ist,fcpys,fld,fst,ftoi,itof")])
- /* From mips.md: extract_bit_field doesn't verify that our source
- matches the predicate, so we force it to be a MEM here. */
- if (GET_CODE (operands[1]) != MEM)
- FAIL;
+(define_insn "*movv8qi_nofix"
+ [(set (match_operand:V8QI 0 "nonimmediate_operand" "=r,r,m,*f,*f,m")
+ (match_operand:V8QI 1 "input_operand" "rW,m,rW,*fW,m,*f"))]
+ "! TARGET_FIX
+ && (register_operand (operands[0], V8QImode)
+ || reg_or_0_operand (operands[1], V8QImode))"
+ "@
+ bis $31,%r1,%0
+ ldq %0,%1
+ stq %r1,%0
+ cpys %R1,%R1,%0
+ ldt %0,%1
+ stt %R1,%0"
+ [(set_attr "type" "ilog,ild,ist,fcpys,fld,fst")])
- /* The bit number is relative to the mode of operand 1 which is
- usually QImode (this might actually be a bug in expmed.c). Note
- that the bit number is negative in big-endian mode in this case.
- We have to convert that to the offset. */
- if (WORDS_BIG_ENDIAN)
- ofs = GET_MODE_BITSIZE (GET_MODE (operands[1]))
- - INTVAL (operands[2]) - INTVAL (operands[3]);
- else
- ofs = INTVAL (operands[3]);
+(define_expand "movv4hi"
+ [(set (match_operand:V4HI 0 "nonimmediate_operand" "")
+ (match_operand:V4HI 1 "general_operand" ""))]
+ ""
+{
+ if (alpha_expand_mov (V4HImode, operands))
+ DONE;
+})
- ofs = ofs / 8;
+(define_insn "*movv4hi_fix"
+ [(set (match_operand:V4HI 0 "nonimmediate_operand" "=r,r,m,*f,*f,m,r,*f")
+ (match_operand:V4HI 1 "input_operand" "rW,m,rW,*fW,m,*f,*f,r"))]
+ "TARGET_FIX
+ && (register_operand (operands[0], V4HImode)
+ || reg_or_0_operand (operands[1], V4HImode))"
+ "@
+ bis $31,%r1,%0
+ ldq %0,%1
+ stq %r1,%0
+ cpys %R1,%R1,%0
+ ldt %0,%1
+ stt %R1,%0
+ ftoit %1,%0
+ itoft %1,%0"
+ [(set_attr "type" "ilog,ild,ist,fcpys,fld,fst,ftoi,itof")])
- alpha_expand_unaligned_load (operands[0], operands[1],
- INTVAL (operands[2]) / 8,
- ofs, 1);
- DONE;
-})
+(define_insn "*movv4hi_nofix"
+ [(set (match_operand:V4HI 0 "nonimmediate_operand" "=r,r,m,*f,*f,m")
+ (match_operand:V4HI 1 "input_operand" "rW,m,rW,*fW,m,*f"))]
+ "! TARGET_FIX
+ && (register_operand (operands[0], V4HImode)
+ || reg_or_0_operand (operands[1], V4HImode))"
+ "@
+ bis $31,%r1,%0
+ ldq %0,%1
+ stq %r1,%0
+ cpys %R1,%R1,%0
+ ldt %0,%1
+ stt %R1,%0"
+ [(set_attr "type" "ilog,ild,ist,fcpys,fld,fst")])
-(define_expand "extzv"
- [(set (match_operand:DI 0 "register_operand" "")
- (zero_extract:DI (match_operand:DI 1 "nonimmediate_operand" "")
- (match_operand:DI 2 "immediate_operand" "")
- (match_operand:DI 3 "immediate_operand" "")))]
+(define_expand "movv2si"
+ [(set (match_operand:V2SI 0 "nonimmediate_operand" "")
+ (match_operand:V2SI 1 "general_operand" ""))]
""
{
- /* We can do 8, 16, 32 and 64 bit fields, if aligned on byte boundaries. */
- if (INTVAL (operands[3]) % 8 != 0
- || (INTVAL (operands[2]) != 8
- && INTVAL (operands[2]) != 16
- && INTVAL (operands[2]) != 32
+ if (alpha_expand_mov (V2SImode, operands))
+ DONE;
+})
+
+(define_insn "*movv2si_fix"
+ [(set (match_operand:V2SI 0 "nonimmediate_operand" "=r,r,m,*f,*f,m,r,*f")
+ (match_operand:V2SI 1 "input_operand" "rW,m,rW,*fW,m,*f,*f,r"))]
+ "TARGET_FIX
+ && (register_operand (operands[0], V2SImode)
+ || reg_or_0_operand (operands[1], V2SImode))"
+ "@
+ bis $31,%r1,%0
+ ldq %0,%1
+ stq %r1,%0
+ cpys %R1,%R1,%0
+ ldt %0,%1
+ stt %R1,%0
+ ftoit %1,%0
+ itoft %1,%0"
+ [(set_attr "type" "ilog,ild,ist,fcpys,fld,fst,ftoi,itof")])
+
+(define_insn "*movv2si_nofix"
+ [(set (match_operand:V2SI 0 "nonimmediate_operand" "=r,r,m,*f,*f,m")
+ (match_operand:V2SI 1 "input_operand" "rW,m,rW,*fW,m,*f"))]
+ "! TARGET_FIX
+ && (register_operand (operands[0], V2SImode)
+ || reg_or_0_operand (operands[1], V2SImode))"
+ "@
+ bis $31,%r1,%0
+ ldq %0,%1
+ stq %r1,%0
+ cpys %R1,%R1,%0
+ ldt %0,%1
+ stt %R1,%0"
+ [(set_attr "type" "ilog,ild,ist,fcpys,fld,fst")])
+
+(define_insn "uminv8qi3"
+ [(set (match_operand:V8QI 0 "register_operand" "=r")
+ (umin:V8QI (match_operand:V8QI 1 "reg_or_0_operand" "rW")
+ (match_operand:V8QI 2 "reg_or_0_operand" "rW")))]
+ "TARGET_MAX"
+ "minub8 %r1,%r2,%0"
+ [(set_attr "type" "mvi")])
+
+(define_insn "sminv8qi3"
+ [(set (match_operand:V8QI 0 "register_operand" "=r")
+ (smin:V8QI (match_operand:V8QI 1 "reg_or_0_operand" "rW")
+ (match_operand:V8QI 2 "reg_or_0_operand" "rW")))]
+ "TARGET_MAX"
+ "minsb8 %r1,%r2,%0"
+ [(set_attr "type" "mvi")])
+
+(define_insn "uminv4hi3"
+ [(set (match_operand:V4HI 0 "register_operand" "=r")
+ (umin:V4HI (match_operand:V4HI 1 "reg_or_0_operand" "rW")
+ (match_operand:V4HI 2 "reg_or_0_operand" "rW")))]
+ "TARGET_MAX"
+ "minuw4 %r1,%r2,%0"
+ [(set_attr "type" "mvi")])
+
+(define_insn "sminv4hi3"
+ [(set (match_operand:V4HI 0 "register_operand" "=r")
+ (smin:V4HI (match_operand:V4HI 1 "reg_or_0_operand" "rW")
+ (match_operand:V4HI 2 "reg_or_0_operand" "rW")))]
+ "TARGET_MAX"
+ "minsw4 %r1,%r2,%0"
+ [(set_attr "type" "mvi")])
+
+(define_insn "umaxv8qi3"
+ [(set (match_operand:V8QI 0 "register_operand" "=r")
+ (umax:V8QI (match_operand:V8QI 1 "reg_or_0_operand" "rW")
+ (match_operand:V8QI 2 "reg_or_0_operand" "rW")))]
+ "TARGET_MAX"
+ "maxub8 %r1,%r2,%0"
+ [(set_attr "type" "mvi")])
+
+(define_insn "smaxv8qi3"
+ [(set (match_operand:V8QI 0 "register_operand" "=r")
+ (smax:V8QI (match_operand:V8QI 1 "reg_or_0_operand" "rW")
+ (match_operand:V8QI 2 "reg_or_0_operand" "rW")))]
+ "TARGET_MAX"
+ "maxsb8 %r1,%r2,%0"
+ [(set_attr "type" "mvi")])
+
+(define_insn "umaxv4hi3"
+ [(set (match_operand:V4HI 0 "register_operand" "=r")
+ (umax:V4HI (match_operand:V4HI 1 "reg_or_0_operand" "rW")
+ (match_operand:V4HI 2 "reg_or_0_operand" "rW")))]
+ "TARGET_MAX"
+ "maxuw4 %r1,%r2,%0"
+ [(set_attr "type" "mvi")])
+
+(define_insn "smaxv4hi3"
+ [(set (match_operand:V4HI 0 "register_operand" "=r")
+ (smax:V4HI (match_operand:V4HI 1 "reg_or_0_operand" "rW")
+ (match_operand:V4HI 2 "reg_or_0_operand" "rW")))]
+ "TARGET_MAX"
+ "maxsw4 %r1,%r2,%0"
+ [(set_attr "type" "mvi")])
+\f
+;; Bit field extract patterns which use ext[wlq][lh]
+
+(define_expand "extv"
+ [(set (match_operand:DI 0 "register_operand" "")
+ (sign_extract:DI (match_operand:QI 1 "memory_operand" "")
+ (match_operand:DI 2 "immediate_operand" "")
+ (match_operand:DI 3 "immediate_operand" "")))]
+ ""
+{
+ int ofs;
+
+ /* We can do 16, 32 and 64 bit fields, if aligned on byte boundaries. */
+ if (INTVAL (operands[3]) % 8 != 0
+ || (INTVAL (operands[2]) != 16
+ && INTVAL (operands[2]) != 32
+ && INTVAL (operands[2]) != 64))
+ FAIL;
+
+ /* From mips.md: extract_bit_field doesn't verify that our source
+ matches the predicate, so we force it to be a MEM here. */
+ if (GET_CODE (operands[1]) != MEM)
+ FAIL;
+
+ /* The bit number is relative to the mode of operand 1 which is
+ usually QImode (this might actually be a bug in expmed.c). Note
+ that the bit number is negative in big-endian mode in this case.
+ We have to convert that to the offset. */
+ if (WORDS_BIG_ENDIAN)
+ ofs = GET_MODE_BITSIZE (GET_MODE (operands[1]))
+ - INTVAL (operands[2]) - INTVAL (operands[3]);
+ else
+ ofs = INTVAL (operands[3]);
+
+ ofs = ofs / 8;
+
+ alpha_expand_unaligned_load (operands[0], operands[1],
+ INTVAL (operands[2]) / 8,
+ ofs, 1);
+ DONE;
+})
+
+(define_expand "extzv"
+ [(set (match_operand:DI 0 "register_operand" "")
+ (zero_extract:DI (match_operand:DI 1 "nonimmediate_operand" "")
+ (match_operand:DI 2 "immediate_operand" "")
+ (match_operand:DI 3 "immediate_operand" "")))]
+ ""
+{
+ /* We can do 8, 16, 32 and 64 bit fields, if aligned on byte boundaries. */
+ if (INTVAL (operands[3]) % 8 != 0
+ || (INTVAL (operands[2]) != 8
+ && INTVAL (operands[2]) != 16
+ && INTVAL (operands[2]) != 32
&& INTVAL (operands[2]) != 64))
FAIL;
(define_insn "prologue_mcount"
[(unspec_volatile [(const_int 0)] UNSPECV_MCOUNT)]
""
- "lda $28,_mcount\;jsr $28,($28),_mcount"
+{
+ if (TARGET_EXPLICIT_RELOCS)
+ /* Note that we cannot use a lituse_jsr reloc, since _mcount
+ cannot be called via the PLT. */
+ return "ldq $28,_mcount($29)\t\t!literal\;jsr $28,($28),_mcount";
+ else
+ return "lda $28,_mcount\;jsr $28,($28),_mcount";
+}
[(set_attr "type" "multi")
(set_attr "length" "8")])
(set_attr "type" "multi")])
(define_insn "*exception_receiver_2"
- [(unspec_volatile [(match_operand:DI 0 "nonimmediate_operand" "r,m")]
- UNSPECV_EHR)]
+ [(unspec_volatile [(match_operand:DI 0 "memory_operand" "m")] UNSPECV_EHR)]
"TARGET_LD_BUGGY_LDGP"
- "@
- bis $31,%0,$29
- ldq $29,%0"
- [(set_attr "type" "ilog,ild")])
+ "ldq $29,%0"
+ [(set_attr "type" "ild")])
(define_expand "nonlocal_goto_receiver"
[(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)
else
return ".align %0 #realign";
})
+\f
+;; Instructions to be emitted from __builtins.
+
+(define_insn "builtin_cmpbge"
+ [(set (match_operand:DI 0 "register_operand" "=r")
+ (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "rJ")
+ (match_operand:DI 2 "reg_or_8bit_operand" "rI")]
+ UNSPEC_CMPBGE))]
+ ""
+ "cmpbge %r1,%2,%0"
+ ;; The EV6 data sheets list this as ILOG. OTOH, EV6 doesn't
+ ;; actually differentiate between ILOG and ICMP in the schedule.
+ [(set_attr "type" "icmp")])
+
+(define_expand "builtin_extbl"
+ [(match_operand:DI 0 "register_operand" "")
+ (match_operand:DI 1 "reg_or_0_operand" "")
+ (match_operand:DI 2 "reg_or_8bit_operand" "")]
+ ""
+{
+ rtx (*gen) PARAMS ((rtx, rtx, rtx, rtx));
+ if (WORDS_BIG_ENDIAN)
+ gen = gen_extxl_be;
+ else
+ gen = gen_extxl_le;
+ emit_insn ((*gen) (operands[0], operands[1], GEN_INT (8), operands[2]));
+ DONE;
+})
+
+(define_expand "builtin_extwl"
+ [(match_operand:DI 0 "register_operand" "")
+ (match_operand:DI 1 "reg_or_0_operand" "")
+ (match_operand:DI 2 "reg_or_8bit_operand" "")]
+ ""
+{
+ rtx (*gen) PARAMS ((rtx, rtx, rtx, rtx));
+ if (WORDS_BIG_ENDIAN)
+ gen = gen_extxl_be;
+ else
+ gen = gen_extxl_le;
+ emit_insn ((*gen) (operands[0], operands[1], GEN_INT (16), operands[2]));
+ DONE;
+})
+
+(define_expand "builtin_extll"
+ [(match_operand:DI 0 "register_operand" "")
+ (match_operand:DI 1 "reg_or_0_operand" "")
+ (match_operand:DI 2 "reg_or_8bit_operand" "")]
+ ""
+{
+ rtx (*gen) PARAMS ((rtx, rtx, rtx, rtx));
+ if (WORDS_BIG_ENDIAN)
+ gen = gen_extxl_be;
+ else
+ gen = gen_extxl_le;
+ emit_insn ((*gen) (operands[0], operands[1], GEN_INT (32), operands[2]));
+ DONE;
+})
+
+(define_expand "builtin_extql"
+ [(match_operand:DI 0 "register_operand" "")
+ (match_operand:DI 1 "reg_or_0_operand" "")
+ (match_operand:DI 2 "reg_or_8bit_operand" "")]
+ ""
+{
+ rtx (*gen) PARAMS ((rtx, rtx, rtx, rtx));
+ if (WORDS_BIG_ENDIAN)
+ gen = gen_extxl_be;
+ else
+ gen = gen_extxl_le;
+ emit_insn ((*gen) (operands[0], operands[1], GEN_INT (64), operands[2]));
+ DONE;
+})
+
+(define_expand "builtin_extwh"
+ [(match_operand:DI 0 "register_operand" "")
+ (match_operand:DI 1 "reg_or_0_operand" "")
+ (match_operand:DI 2 "reg_or_8bit_operand" "")]
+ ""
+{
+ rtx (*gen) PARAMS ((rtx, rtx, rtx));
+ if (WORDS_BIG_ENDIAN)
+ gen = gen_extwh_be;
+ else
+ gen = gen_extwh_le;
+ emit_insn ((*gen) (operands[0], operands[1], operands[2]));
+ DONE;
+})
+
+(define_expand "builtin_extlh"
+ [(match_operand:DI 0 "register_operand" "")
+ (match_operand:DI 1 "reg_or_0_operand" "")
+ (match_operand:DI 2 "reg_or_8bit_operand" "")]
+ ""
+{
+ rtx (*gen) PARAMS ((rtx, rtx, rtx));
+ if (WORDS_BIG_ENDIAN)
+ gen = gen_extlh_be;
+ else
+ gen = gen_extlh_le;
+ emit_insn ((*gen) (operands[0], operands[1], operands[2]));
+ DONE;
+})
+
+(define_expand "builtin_extqh"
+ [(match_operand:DI 0 "register_operand" "")
+ (match_operand:DI 1 "reg_or_0_operand" "")
+ (match_operand:DI 2 "reg_or_8bit_operand" "")]
+ ""
+{
+ rtx (*gen) PARAMS ((rtx, rtx, rtx));
+ if (WORDS_BIG_ENDIAN)
+ gen = gen_extqh_be;
+ else
+ gen = gen_extqh_le;
+ emit_insn ((*gen) (operands[0], operands[1], operands[2]));
+ DONE;
+})
+
+(define_expand "builtin_insbl"
+ [(match_operand:DI 0 "register_operand" "")
+ (match_operand:DI 1 "reg_or_0_operand" "")
+ (match_operand:DI 2 "reg_or_8bit_operand" "")]
+ ""
+{
+ rtx (*gen) PARAMS ((rtx, rtx, rtx));
+ if (WORDS_BIG_ENDIAN)
+ gen = gen_insbl_be;
+ else
+ gen = gen_insbl_le;
+ operands[1] = gen_lowpart (QImode, operands[1]);
+ emit_insn ((*gen) (operands[0], operands[1], operands[2]));
+ DONE;
+})
+
+(define_expand "builtin_inswl"
+ [(match_operand:DI 0 "register_operand" "")
+ (match_operand:DI 1 "reg_or_0_operand" "")
+ (match_operand:DI 2 "reg_or_8bit_operand" "")]
+ ""
+{
+ rtx (*gen) PARAMS ((rtx, rtx, rtx));
+ if (WORDS_BIG_ENDIAN)
+ gen = gen_inswl_be;
+ else
+ gen = gen_inswl_le;
+ operands[1] = gen_lowpart (HImode, operands[1]);
+ emit_insn ((*gen) (operands[0], operands[1], operands[2]));
+ DONE;
+})
+
+(define_expand "builtin_insll"
+ [(match_operand:DI 0 "register_operand" "")
+ (match_operand:DI 1 "reg_or_0_operand" "")
+ (match_operand:DI 2 "reg_or_8bit_operand" "")]
+ ""
+{
+ rtx (*gen) PARAMS ((rtx, rtx, rtx));
+ if (WORDS_BIG_ENDIAN)
+ gen = gen_insll_be;
+ else
+ gen = gen_insll_le;
+ operands[1] = gen_lowpart (SImode, operands[1]);
+ emit_insn ((*gen) (operands[0], operands[1], operands[2]));
+ emit_insn ((*gen) (operands[0], operands[1], operands[2]));
+ DONE;
+})
+
+(define_expand "builtin_insql"
+ [(match_operand:DI 0 "register_operand" "")
+ (match_operand:DI 1 "reg_or_0_operand" "")
+ (match_operand:DI 2 "reg_or_8bit_operand" "")]
+ ""
+{
+ rtx (*gen) PARAMS ((rtx, rtx, rtx));
+ if (WORDS_BIG_ENDIAN)
+ gen = gen_insql_be;
+ else
+ gen = gen_insql_le;
+ emit_insn ((*gen) (operands[0], operands[1], operands[2]));
+ DONE;
+})
+
+(define_expand "builtin_inswh"
+ [(match_operand:DI 0 "register_operand" "")
+ (match_operand:DI 1 "register_operand" "")
+ (match_operand:DI 2 "reg_or_8bit_operand" "")]
+ ""
+{
+ emit_insn (gen_insxh (operands[0], operands[1], GEN_INT (16), operands[2]));
+ DONE;
+})
+
+(define_expand "builtin_inslh"
+ [(match_operand:DI 0 "register_operand" "")
+ (match_operand:DI 1 "register_operand" "")
+ (match_operand:DI 2 "reg_or_8bit_operand" "")]
+ ""
+{
+ emit_insn (gen_insxh (operands[0], operands[1], GEN_INT (32), operands[2]));
+ DONE;
+})
+
+(define_expand "builtin_insqh"
+ [(match_operand:DI 0 "register_operand" "")
+ (match_operand:DI 1 "register_operand" "")
+ (match_operand:DI 2 "reg_or_8bit_operand" "")]
+ ""
+{
+ emit_insn (gen_insxh (operands[0], operands[1], GEN_INT (64), operands[2]));
+ DONE;
+})
+
+(define_expand "builtin_mskbl"
+ [(match_operand:DI 0 "register_operand" "")
+ (match_operand:DI 1 "reg_or_0_operand" "")
+ (match_operand:DI 2 "reg_or_8bit_operand" "")]
+ ""
+{
+ rtx (*gen) PARAMS ((rtx, rtx, rtx, rtx));
+ rtx mask;
+ if (WORDS_BIG_ENDIAN)
+ gen = gen_mskxl_be;
+ else
+ gen = gen_mskxl_le;
+ mask = GEN_INT (0xff);
+ emit_insn ((*gen) (operands[0], operands[1], mask, operands[2]));
+ DONE;
+})
+
+(define_expand "builtin_mskwl"
+ [(match_operand:DI 0 "register_operand" "")
+ (match_operand:DI 1 "reg_or_0_operand" "")
+ (match_operand:DI 2 "reg_or_8bit_operand" "")]
+ ""
+{
+ rtx (*gen) PARAMS ((rtx, rtx, rtx, rtx));
+ rtx mask;
+ if (WORDS_BIG_ENDIAN)
+ gen = gen_mskxl_be;
+ else
+ gen = gen_mskxl_le;
+ mask = GEN_INT (0xffff);
+ emit_insn ((*gen) (operands[0], operands[1], mask, operands[2]));
+ DONE;
+})
+
+(define_expand "builtin_mskll"
+ [(match_operand:DI 0 "register_operand" "")
+ (match_operand:DI 1 "reg_or_0_operand" "")
+ (match_operand:DI 2 "reg_or_8bit_operand" "")]
+ ""
+{
+ rtx (*gen) PARAMS ((rtx, rtx, rtx, rtx));
+ rtx mask;
+ if (WORDS_BIG_ENDIAN)
+ gen = gen_mskxl_be;
+ else
+ gen = gen_mskxl_le;
+ mask = immed_double_const (0xffffffff, 0, DImode);
+ emit_insn ((*gen) (operands[0], operands[1], mask, operands[2]));
+ DONE;
+})
+(define_expand "builtin_mskql"
+ [(match_operand:DI 0 "register_operand" "")
+ (match_operand:DI 1 "reg_or_0_operand" "")
+ (match_operand:DI 2 "reg_or_8bit_operand" "")]
+ ""
+{
+ rtx (*gen) PARAMS ((rtx, rtx, rtx, rtx));
+ rtx mask;
+ if (WORDS_BIG_ENDIAN)
+ gen = gen_mskxl_be;
+ else
+ gen = gen_mskxl_le;
+ mask = constm1_rtx;
+ emit_insn ((*gen) (operands[0], operands[1], mask, operands[2]));
+ DONE;
+})
+
+(define_expand "builtin_mskwh"
+ [(match_operand:DI 0 "register_operand" "")
+ (match_operand:DI 1 "register_operand" "")
+ (match_operand:DI 2 "reg_or_8bit_operand" "")]
+ ""
+{
+ emit_insn (gen_mskxh (operands[0], operands[1], GEN_INT (16), operands[2]));
+ DONE;
+})
+
+(define_expand "builtin_msklh"
+ [(match_operand:DI 0 "register_operand" "")
+ (match_operand:DI 1 "register_operand" "")
+ (match_operand:DI 2 "reg_or_8bit_operand" "")]
+ ""
+{
+ emit_insn (gen_mskxh (operands[0], operands[1], GEN_INT (32), operands[2]));
+ DONE;
+})
+
+(define_expand "builtin_mskqh"
+ [(match_operand:DI 0 "register_operand" "")
+ (match_operand:DI 1 "register_operand" "")
+ (match_operand:DI 2 "reg_or_8bit_operand" "")]
+ ""
+{
+ emit_insn (gen_mskxh (operands[0], operands[1], GEN_INT (64), operands[2]));
+ DONE;
+})
+
+(define_expand "builtin_zap"
+ [(set (match_operand:DI 0 "register_operand" "")
+ (and:DI (unspec:DI
+ [(match_operand:DI 2 "reg_or_const_int_operand" "")]
+ UNSPEC_ZAP)
+ (match_operand:DI 1 "reg_or_const_int_operand" "")))]
+ ""
+{
+ if (GET_CODE (operands[2]) == CONST_INT)
+ {
+ rtx mask = alpha_expand_zap_mask (INTVAL (operands[2]));
+
+ if (operands[1] == const0_rtx)
+ {
+ emit_move_insn (operands[0], const0_rtx);
+ DONE;
+ }
+ if (operands[1] == constm1_rtx)
+ {
+ emit_move_insn (operands[0], operands[1]);
+ DONE;
+ }
+
+ operands[1] = force_reg (DImode, operands[1]);
+ emit_insn (gen_anddi3 (operands[0], operands[1], mask));
+ DONE;
+ }
+
+ operands[1] = force_reg (DImode, operands[1]);
+ operands[2] = gen_lowpart (QImode, operands[2]);
+})
+
+(define_insn "*builtin_zap_1"
+ [(set (match_operand:DI 0 "register_operand" "=r,r,r,r")
+ (and:DI (unspec:DI
+ [(match_operand:QI 2 "reg_or_const_int_operand" "n,n,r,r")]
+ UNSPEC_ZAP)
+ (match_operand:DI 1 "reg_or_const_int_operand" "n,r,J,r")))]
+ ""
+ "@
+ #
+ #
+ bis $31,$31,%0
+ zap %r1,%2,%0"
+ [(set_attr "type" "shift,shift,ilog,shift")])
+
+(define_split
+ [(set (match_operand:DI 0 "register_operand" "")
+ (and:DI (unspec:DI
+ [(match_operand:QI 2 "const_int_operand" "")]
+ UNSPEC_ZAP)
+ (match_operand:DI 1 "const_int_operand" "")))]
+ ""
+ [(const_int 0)]
+{
+ rtx mask = alpha_expand_zap_mask (INTVAL (operands[2]));
+ if (HOST_BITS_PER_WIDE_INT >= 64 || GET_CODE (mask) == CONST_INT)
+ operands[1] = gen_int_mode (INTVAL (operands[1]) & INTVAL (mask), DImode);
+ else
+ {
+ HOST_WIDE_INT c_lo = INTVAL (operands[1]);
+ HOST_WIDE_INT c_hi = (c_lo < 0 ? -1 : 0);
+ operands[1] = immed_double_const (c_lo & CONST_DOUBLE_LOW (mask),
+ c_hi & CONST_DOUBLE_HIGH (mask),
+ DImode);
+ }
+ emit_move_insn (operands[0], operands[1]);
+ DONE;
+})
+
+(define_split
+ [(set (match_operand:DI 0 "register_operand" "")
+ (and:DI (unspec:DI
+ [(match_operand:QI 2 "const_int_operand" "")]
+ UNSPEC_ZAP)
+ (match_operand:DI 1 "register_operand" "")))]
+ ""
+ [(set (match_dup 0)
+ (and:DI (match_dup 1) (match_dup 2)))]
+{
+ operands[2] = alpha_expand_zap_mask (INTVAL (operands[2]));
+ if (operands[2] == const0_rtx)
+ {
+ emit_move_insn (operands[0], const0_rtx);
+ DONE;
+ }
+ if (operands[2] == constm1_rtx)
+ {
+ emit_move_insn (operands[0], operands[1]);
+ DONE;
+ }
+})
+
+(define_expand "builtin_zapnot"
+ [(set (match_operand:DI 0 "register_operand" "")
+ (and:DI (unspec:DI
+ [(not:QI (match_operand:QI 2 "reg_or_const_int_operand" ""))]
+ UNSPEC_ZAP)
+ (match_operand:DI 1 "reg_or_const_int_operand" "")))]
+ ""
+{
+ if (GET_CODE (operands[2]) == CONST_INT)
+ {
+ rtx mask = alpha_expand_zap_mask (~ INTVAL (operands[2]));
+
+ if (operands[1] == const0_rtx)
+ {
+ emit_move_insn (operands[0], const0_rtx);
+ DONE;
+ }
+ if (operands[1] == constm1_rtx)
+ {
+ emit_move_insn (operands[0], operands[1]);
+ DONE;
+ }
+
+ operands[1] = force_reg (DImode, operands[1]);
+ emit_insn (gen_anddi3 (operands[0], operands[1], mask));
+ DONE;
+ }
+
+ operands[1] = force_reg (DImode, operands[1]);
+ operands[2] = gen_lowpart (QImode, operands[2]);
+})
+
+(define_insn "*builtin_zapnot_1"
+ [(set (match_operand:DI 0 "register_operand" "=r")
+ (and:DI (unspec:DI
+ [(not:QI (match_operand:QI 2 "register_operand" "r"))]
+ UNSPEC_ZAP)
+ (match_operand:DI 1 "reg_or_0_operand" "rJ")))]
+ ""
+ "zapnot %r1,%2,%0"
+ [(set_attr "type" "shift")])
+
+(define_insn "builtin_amask"
+ [(set (match_operand:DI 0 "register_operand" "=r")
+ (unspec:DI [(match_operand:DI 1 "reg_or_8bit_operand" "rI")]
+ UNSPEC_AMASK))]
+ ""
+ "amask %1,%0"
+ [(set_attr "type" "ilog")])
+
+(define_insn "builtin_implver"
+ [(set (match_operand:DI 0 "register_operand" "=r")
+ (unspec:DI [(const_int 0)] UNSPEC_IMPLVER))]
+ ""
+ "implver %0"
+ [(set_attr "type" "ilog")])
+
+(define_insn "builtin_rpcc"
+ [(set (match_operand:DI 0 "register_operand" "=r")
+ (unspec_volatile:DI [(const_int 0)] UNSPECV_RPCC))]
+ ""
+ "rpcc %0"
+ [(set_attr "type" "ilog")])
+
+(define_expand "builtin_minub8"
+ [(match_operand:DI 0 "register_operand" "")
+ (match_operand:DI 1 "reg_or_0_operand" "")
+ (match_operand:DI 2 "reg_or_0_operand" "")]
+ "TARGET_MAX"
+{
+ alpha_expand_builtin_vector_binop (gen_uminv8qi3, V8QImode, operands[0],
+ operands[1], operands[2]);
+ DONE;
+})
+
+(define_expand "builtin_minsb8"
+ [(match_operand:DI 0 "register_operand" "")
+ (match_operand:DI 1 "reg_or_0_operand" "")
+ (match_operand:DI 2 "reg_or_0_operand" "")]
+ "TARGET_MAX"
+{
+ alpha_expand_builtin_vector_binop (gen_sminv8qi3, V8QImode, operands[0],
+ operands[1], operands[2]);
+ DONE;
+})
+
+(define_expand "builtin_minuw4"
+ [(match_operand:DI 0 "register_operand" "")
+ (match_operand:DI 1 "reg_or_0_operand" "")
+ (match_operand:DI 2 "reg_or_0_operand" "")]
+ "TARGET_MAX"
+{
+ alpha_expand_builtin_vector_binop (gen_uminv4hi3, V4HImode, operands[0],
+ operands[1], operands[2]);
+ DONE;
+})
+
+(define_expand "builtin_minsw4"
+ [(match_operand:DI 0 "register_operand" "")
+ (match_operand:DI 1 "reg_or_0_operand" "")
+ (match_operand:DI 2 "reg_or_0_operand" "")]
+ "TARGET_MAX"
+{
+ alpha_expand_builtin_vector_binop (gen_sminv4hi3, V4HImode, operands[0],
+ operands[1], operands[2]);
+ DONE;
+})
+
+(define_expand "builtin_maxub8"
+ [(match_operand:DI 0 "register_operand" "")
+ (match_operand:DI 1 "reg_or_0_operand" "")
+ (match_operand:DI 2 "reg_or_0_operand" "")]
+ "TARGET_MAX"
+{
+ alpha_expand_builtin_vector_binop (gen_umaxv8qi3, V8QImode, operands[0],
+ operands[1], operands[2]);
+ DONE;
+})
+
+(define_expand "builtin_maxsb8"
+ [(match_operand:DI 0 "register_operand" "")
+ (match_operand:DI 1 "reg_or_0_operand" "")
+ (match_operand:DI 2 "reg_or_0_operand" "")]
+ "TARGET_MAX"
+{
+ alpha_expand_builtin_vector_binop (gen_smaxv8qi3, V8QImode, operands[0],
+ operands[1], operands[2]);
+ DONE;
+})
+
+(define_expand "builtin_maxuw4"
+ [(match_operand:DI 0 "register_operand" "")
+ (match_operand:DI 1 "reg_or_0_operand" "")
+ (match_operand:DI 2 "reg_or_0_operand" "")]
+ "TARGET_MAX"
+{
+ alpha_expand_builtin_vector_binop (gen_umaxv4hi3, V4HImode, operands[0],
+ operands[1], operands[2]);
+ DONE;
+})
+
+(define_expand "builtin_maxsw4"
+ [(match_operand:DI 0 "register_operand" "")
+ (match_operand:DI 1 "reg_or_0_operand" "")
+ (match_operand:DI 2 "reg_or_0_operand" "")]
+ "TARGET_MAX"
+{
+ alpha_expand_builtin_vector_binop (gen_smaxv4hi3, V4HImode, operands[0],
+ operands[1], operands[2]);
+ DONE;
+})
+
+(define_insn "builtin_perr"
+ [(set (match_operand:DI 0 "register_operand" "=r")
+ (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "%rJ")
+ (match_operand:DI 2 "reg_or_8bit_operand" "rJ")]
+ UNSPEC_PERR))]
+ "TARGET_MAX"
+ "perr %r1,%r2,%0"
+ [(set_attr "type" "mvi")])
+
+(define_expand "builtin_pklb"
+ [(set (match_operand:DI 0 "register_operand" "")
+ (vec_concat:V8QI
+ (vec_concat:V4QI
+ (truncate:V2QI (match_operand:DI 1 "register_operand" ""))
+ (match_dup 2))
+ (match_dup 3)))]
+ "TARGET_MAX"
+{
+ operands[0] = gen_lowpart (V8QImode, operands[0]);
+ operands[1] = gen_lowpart (V2SImode, operands[1]);
+ operands[2] = CONST0_RTX (V2QImode);
+ operands[3] = CONST0_RTX (V4QImode);
+})
+
+(define_insn "*pklb"
+ [(set (match_operand:V8QI 0 "register_operand" "=r")
+ (vec_concat:V8QI
+ (vec_concat:V4QI
+ (truncate:V2QI (match_operand:V2SI 1 "register_operand" "r"))
+ (match_operand:V2QI 2 "const0_operand" ""))
+ (match_operand:V4QI 3 "const0_operand" "")))]
+ "TARGET_MAX"
+ "pklb %r1,%0"
+ [(set_attr "type" "mvi")])
+
+(define_expand "builtin_pkwb"
+ [(set (match_operand:DI 0 "register_operand" "")
+ (vec_concat:V8QI
+ (truncate:V4QI (match_operand:DI 1 "register_operand" ""))
+ (match_dup 2)))]
+ "TARGET_MAX"
+{
+ operands[0] = gen_lowpart (V8QImode, operands[0]);
+ operands[1] = gen_lowpart (V4HImode, operands[1]);
+ operands[2] = CONST0_RTX (V4QImode);
+})
+
+(define_insn "*pkwb"
+ [(set (match_operand:V8QI 0 "register_operand" "")
+ (vec_concat:V8QI
+ (truncate:V4QI (match_operand:V4HI 1 "register_operand" ""))
+ (match_operand:V4QI 2 "const0_operand" "")))]
+ "TARGET_MAX"
+ "pkwb %r1,%0"
+ [(set_attr "type" "mvi")])
+
+(define_expand "builtin_unpkbl"
+ [(set (match_operand:DI 0 "register_operand" "")
+ (zero_extend:V2SI
+ (vec_select:V2QI (match_operand:DI 1 "register_operand" "")
+ (parallel [(const_int 0) (const_int 1)]))))]
+ "TARGET_MAX"
+{
+ operands[0] = gen_lowpart (V2SImode, operands[0]);
+ operands[1] = gen_lowpart (V8QImode, operands[1]);
+})
+
+(define_insn "*unpkbl"
+ [(set (match_operand:V2SI 0 "register_operand" "=r")
+ (zero_extend:V2SI
+ (vec_select:V2QI (match_operand:V8QI 1 "reg_or_0_operand" "rW")
+ (parallel [(const_int 0) (const_int 1)]))))]
+ "TARGET_MAX"
+ "unpkbl %r1,%0"
+ [(set_attr "type" "mvi")])
+
+(define_expand "builtin_unpkbw"
+ [(set (match_operand:DI 0 "register_operand" "")
+ (zero_extend:V4HI
+ (vec_select:V4QI (match_operand:DI 1 "register_operand" "")
+ (parallel [(const_int 0)
+ (const_int 1)
+ (const_int 2)
+ (const_int 3)]))))]
+ "TARGET_MAX"
+{
+ operands[0] = gen_lowpart (V4HImode, operands[0]);
+ operands[1] = gen_lowpart (V8QImode, operands[1]);
+})
+
+(define_insn "*unpkbw"
+ [(set (match_operand:V4HI 0 "register_operand" "=r")
+ (zero_extend:V4HI
+ (vec_select:V4QI (match_operand:V8QI 1 "reg_or_0_operand" "rW")
+ (parallel [(const_int 0)
+ (const_int 1)
+ (const_int 2)
+ (const_int 3)]))))]
+ "TARGET_MAX"
+ "unpkbw %r1,%0"
+ [(set_attr "type" "mvi")])
+
+(define_expand "builtin_cttz"
+ [(set (match_operand:DI 0 "register_operand" "")
+ (unspec:DI [(match_operand:DI 1 "register_operand" "")]
+ UNSPEC_CTTZ))]
+ "TARGET_CIX"
+ "")
+
+(define_insn "builtin_ctlz"
+ [(set (match_operand:DI 0 "register_operand" "=r")
+ (unspec:DI [(match_operand:DI 1 "register_operand" "r")]
+ UNSPEC_CTLZ))]
+ "TARGET_CIX"
+ "ctlz %1,%0"
+ [(set_attr "type" "mvi")])
+
+(define_insn "builtin_ctpop"
+ [(set (match_operand:DI 0 "register_operand" "=r")
+ (unspec:DI [(match_operand:DI 1 "register_operand" "r")]
+ UNSPEC_CTPOP))]
+ "TARGET_CIX"
+ "ctpop %1,%0"
+ [(set_attr "type" "mvi")])
+\f
;; The call patterns are at the end of the file because their
;; wildcard operand0 interferes with nice recognition.
(match_operand 2 "" "")))
(use (reg:DI 29))
(clobber (reg:DI 26))])]
- "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF && reload_completed
- && ! current_file_function_operand (operands[0], Pmode)
+ "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF && reload_completed
+ && ! current_file_function_operand (operands[1], Pmode)
&& peep2_regno_dead_p (1, 29)"
[(parallel [(set (match_dup 0)
(call (mem:DI (match_dup 3))
(match_dup 2)))
(set (reg:DI 26) (plus:DI (pc) (const_int 4)))
(unspec_volatile [(reg:DI 29)] UNSPECV_BLOCKAGE)
- (use (match_dup 1))])]
+ (use (match_dup 1))
+ (use (match_dup 4))])]
{
if (CONSTANT_P (operands[1]))
{
operands[3] = gen_rtx_REG (Pmode, 27);
- emit_move_insn (operands[3], operands[1]);
+ operands[4] = GEN_INT (alpha_next_sequence_number++);
+ emit_insn (gen_movdi_er_high_g (operands[3], pic_offset_table_rtx,
+ operands[1], operands[4]));
}
else
{
operands[3] = operands[1];
operands[1] = const0_rtx;
+ operands[4] = const0_rtx;
}
})
(match_operand 2 "" "")))
(use (reg:DI 29))
(clobber (reg:DI 26))])]
- "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF && reload_completed
- && ! current_file_function_operand (operands[0], Pmode)
+ "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF && reload_completed
+ && ! current_file_function_operand (operands[1], Pmode)
&& ! peep2_regno_dead_p (1, 29)"
[(parallel [(set (match_dup 0)
(call (mem:DI (match_dup 3))
(match_dup 2)))
(set (reg:DI 26) (plus:DI (pc) (const_int 4)))
(unspec_volatile [(reg:DI 29)] UNSPECV_BLOCKAGE)
- (use (match_dup 1))])
+ (use (match_dup 1))
+ (use (match_dup 5))])
(set (reg:DI 29)
(unspec_volatile:DI [(reg:DI 26) (match_dup 4)] UNSPECV_LDGP1))
(set (reg:DI 29)
if (CONSTANT_P (operands[1]))
{
operands[3] = gen_rtx_REG (Pmode, 27);
- emit_move_insn (operands[3], operands[1]);
+ operands[5] = GEN_INT (alpha_next_sequence_number++);
+ emit_insn (gen_movdi_er_high_g (operands[3], pic_offset_table_rtx,
+ operands[1], operands[5]));
}
else
{
operands[3] = operands[1];
operands[1] = const0_rtx;
+ operands[5] = const0_rtx;
}
operands[4] = GEN_INT (alpha_next_sequence_number++);
})
(set (reg:DI 26)
(plus:DI (pc) (const_int 4)))
(unspec_volatile [(reg:DI 29)] UNSPECV_BLOCKAGE)
- (use (match_operand 3 "" ""))]
+ (use (match_operand 3 "" ""))
+ (use (match_operand 4 "" ""))]
"TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
- "jsr $26,(%1),%3"
+ "jsr $26,(%1),%3%J4"
[(set_attr "type" "jsr")])
(define_insn "*call_value_osf_1_noreturn"
[(set_attr "type" "jsr")
(set_attr "length" "*,*,8")])
+(define_insn_and_split "call_value_osf_tlsgd"
+ [(set (match_operand 0 "" "")
+ (call (mem:DI (match_operand:DI 1 "symbolic_operand" ""))
+ (const_int 0)))
+ (unspec [(match_operand:DI 2 "const_int_operand" "")] UNSPEC_TLSGD_CALL)
+ (use (reg:DI 29))
+ (clobber (reg:DI 26))]
+ "HAVE_AS_TLS"
+ "#"
+ "&& reload_completed"
+ [(set (match_dup 3)
+ (unspec:DI [(match_dup 5)
+ (match_dup 1)
+ (match_dup 2)] UNSPEC_LITERAL))
+ (parallel [(set (match_dup 0)
+ (call (mem:DI (match_dup 3))
+ (const_int 0)))
+ (set (reg:DI 26) (plus:DI (pc) (const_int 4)))
+ (unspec_volatile [(match_dup 5)] UNSPECV_BLOCKAGE)
+ (use (match_dup 1))
+ (use (unspec [(match_dup 2)] UNSPEC_TLSGD_CALL))])
+ (set (match_dup 5)
+ (unspec_volatile:DI [(reg:DI 26) (match_dup 4)] UNSPECV_LDGP1))
+ (set (match_dup 5)
+ (unspec:DI [(match_dup 5) (match_dup 4)] UNSPEC_LDGP2))]
+{
+ operands[3] = gen_rtx_REG (Pmode, 27);
+ operands[4] = GEN_INT (alpha_next_sequence_number++);
+ operands[5] = pic_offset_table_rtx;
+}
+ [(set_attr "type" "multi")])
+
+(define_insn_and_split "call_value_osf_tlsldm"
+ [(set (match_operand 0 "" "")
+ (call (mem:DI (match_operand:DI 1 "symbolic_operand" ""))
+ (const_int 0)))
+ (unspec [(match_operand:DI 2 "const_int_operand" "")] UNSPEC_TLSLDM_CALL)
+ (use (reg:DI 29))
+ (clobber (reg:DI 26))]
+ "HAVE_AS_TLS"
+ "#"
+ "&& reload_completed"
+ [(set (match_dup 3)
+ (unspec:DI [(match_dup 5)
+ (match_dup 1)
+ (match_dup 2)] UNSPEC_LITERAL))
+ (parallel [(set (match_dup 0)
+ (call (mem:DI (match_dup 3))
+ (const_int 0)))
+ (set (reg:DI 26) (plus:DI (pc) (const_int 4)))
+ (unspec_volatile [(match_dup 5)] UNSPECV_BLOCKAGE)
+ (use (match_dup 1))
+ (use (unspec [(match_dup 2)] UNSPEC_TLSLDM_CALL))])
+ (set (reg:DI 29)
+ (unspec_volatile:DI [(reg:DI 26) (match_dup 4)] UNSPECV_LDGP1))
+ (set (reg:DI 29)
+ (unspec:DI [(reg:DI 29) (match_dup 4)] UNSPEC_LDGP2))]
+{
+ operands[3] = gen_rtx_REG (Pmode, 27);
+ operands[4] = GEN_INT (alpha_next_sequence_number++);
+ operands[5] = pic_offset_table_rtx;
+}
+ [(set_attr "type" "multi")])
+
(define_insn "*call_value_osf_1"
[(set (match_operand 0 "" "")
(call (mem:DI (match_operand:DI 1 "call_operand" "c,R,s"))
[(set (match_operand 0 "" "")
(call (mem:DI (match_operand:DI 1 "symbolic_operand" "R,s"))
(match_operand 2 "" "")))
- (use (reg:DI 29))]
+ (unspec [(reg:DI 29)] UNSPEC_SIBCALL)]
"TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
"@
br $31,$%1..ng
[(set (match_operand 0 "" "")
(call (mem:DI (match_operand:DI 1 "symbolic_operand" "R,s"))
(match_operand 2 "" "")))
- (use (reg:DI 29))]
+ (unspec [(reg:DI 29)] UNSPEC_SIBCALL)]
"! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
"@
br $31,$%1..ng
"TARGET_ABI_UNICOSMK"
"jsr $26,(%1)"
[(set_attr "type" "jsr")])
-
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