/* Optimize by combining instructions for GNU compiler.
Copyright (C) 1987, 1988, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
- 1999, 2000, 2001 Free Software Foundation, Inc.
+ 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
-This file is part of GNU CC.
+This file is part of GCC.
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
+GCC is free software; you can redistribute it and/or modify it under
+the terms of the GNU General Public License as published by the Free
+Software Foundation; either version 2, or (at your option) any later
+version.
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-GNU General Public License for more details.
+GCC is distributed in the hope that it will be useful, but WITHOUT ANY
+WARRANTY; without even the implied warranty of MERCHANTABILITY or
+FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+for more details.
You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING. If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA. */
+along with GCC; see the file COPYING. If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
/* This module is essentially the "combiner" phase of the U. of Arizona
Portable Optimizer, but redone to work on our list-structured
#include "basic-block.h"
#include "insn-config.h"
#include "function.h"
-/* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
+/* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
#include "expr.h"
#include "insn-attr.h"
#include "recog.h"
BITS_PER_WORD would invoke undefined behavior. Work around it. */
#define UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD(val) \
- (((unsigned HOST_WIDE_INT)(val) << (BITS_PER_WORD - 1)) << 1)
+ (((unsigned HOST_WIDE_INT) (val) << (BITS_PER_WORD - 1)) << 1)
/* Maximum register number, which is the size of the tables below. */
if (oldval == newval)
return;
+ /* We'd like to catch as many invalid transformations here as
+ possible. Unfortunately, there are way too many mode changes
+ that are perfectly valid, so we'd waste too much effort for
+ little gain doing the checks here. Focus on catching invalid
+ transformations involving integer constants. */
+ if (GET_MODE_CLASS (GET_MODE (oldval)) == MODE_INT
+ && GET_CODE (newval) == CONST_INT)
+ {
+ /* Sanity check that we're replacing oldval with a CONST_INT
+ that is a valid sign-extension for the original mode. */
+ if (INTVAL (newval) != trunc_int_for_mode (INTVAL (newval),
+ GET_MODE (oldval)))
+ abort ();
+
+ /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
+ CONST_INT is not valid, because after the replacement, the
+ original mode would be gone. Unfortunately, we can't tell
+ when do_SUBST is called to replace the operand thereof, so we
+ perform this test on oldval instead, checking whether an
+ invalid replacement took place before we got here. */
+ if ((GET_CODE (oldval) == SUBREG
+ && GET_CODE (SUBREG_REG (oldval)) == CONST_INT)
+ || (GET_CODE (oldval) == ZERO_EXTEND
+ && GET_CODE (XEXP (oldval, 0)) == CONST_INT))
+ abort ();
+ }
+
if (undobuf.frees)
buf = undobuf.frees, undobuf.frees = buf->next;
else
rtx f;
unsigned int nregs;
{
- register rtx insn, next;
+ rtx insn, next;
#ifdef HAVE_cc0
- register rtx prev;
+ rtx prev;
#endif
- register int i;
- register rtx links, nextlinks;
+ int i;
+ rtx links, nextlinks;
int new_direct_jump_p = 0;
rtx link = XEXP (links, 0);
/* If the linked insn has been replaced by a note, then there
- is no point in persuing this chain any further. */
+ is no point in pursuing this chain any further. */
if (GET_CODE (link) == NOTE)
- break;
+ continue;
for (nextlinks = LOG_LINKS (link);
nextlinks;
nextlinks = XEXP (nextlinks, 1))
- if ((next = try_combine (insn, XEXP (links, 0),
+ if ((next = try_combine (insn, link,
XEXP (nextlinks, 0),
&new_direct_jump_p)) != 0)
goto retry;
;
}
}
+ clear_bb_flags ();
- if (need_refresh)
- {
- compute_bb_for_insn (get_max_uid ());
- update_life_info (refresh_blocks, UPDATE_LIFE_GLOBAL_RM_NOTES,
- PROP_DEATH_NOTES);
- }
+ EXECUTE_IF_SET_IN_SBITMAP (refresh_blocks, 0, this_basic_block,
+ BASIC_BLOCK (this_basic_block)->flags |= BB_DIRTY);
+ new_direct_jump_p |= purge_all_dead_edges (0);
+ delete_noop_moves (f);
+
+ update_life_info_in_dirty_blocks (UPDATE_LIFE_GLOBAL_RM_NOTES,
+ PROP_DEATH_NOTES | PROP_SCAN_DEAD_CODE
+ | PROP_KILL_DEAD_CODE);
/* Clean up. */
sbitmap_free (refresh_blocks);
for the SH4 port. */
case USE:
/* Combining an isolated USE doesn't make sense.
- We depend here on combinable_i3_pat to reject them. */
+ We depend here on combinable_i3pat to reject them. */
/* The code below this loop only verifies that the inputs of
the SET in INSN do not change. We call reg_set_between_p
- to verify that the REG in the USE does not change betweeen
+ to verify that the REG in the USE does not change between
I3 and INSN.
If the USE in INSN was for a pseudo register, the matching
insn pattern will likely match any register; combining this
with any other USE would only be safe if we knew that the
used registers have identical values, or if there was
something to tell them apart, e.g. different modes. For
- now, we forgo such compilcated tests and simply disallow
+ now, we forgo such complicated tests and simply disallow
combining of USES of pseudo registers with any other USE. */
if (GET_CODE (XEXP (elt, 0)) == REG
&& GET_CODE (PATTERN (i3)) == PARALLEL)
for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
if (INSN_P (p) && p != succ && volatile_refs_p (PATTERN (p)))
- return 0;
+ return 0;
}
/* If INSN is an asm, and DEST is a hard register, reject, since it has
This is NOT equivalent to:
(parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
- (set (reg:DI 101) (reg:DI 100))])
+ (set (reg:DI 101) (reg:DI 100))])
Not only does this modify 100 (in which case it might still be valid
if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
{
rtx set;
rtx src, dest;
-
+
/* If this isn't really an insn, we can't do anything.
This can occur when flow deletes an insn that it has merged into an
auto-increment address. */
static rtx
try_combine (i3, i2, i1, new_direct_jump_p)
- register rtx i3, i2, i1;
- register int *new_direct_jump_p;
+ rtx i3, i2, i1;
+ int *new_direct_jump_p;
{
/* New patterns for I3 and I2, respectively. */
rtx newpat, newi2pat = 0;
+ int substed_i2 = 0, substed_i1 = 0;
/* Indicates need to preserve SET in I1 or I2 in I3 if it is not dead. */
int added_sets_1, added_sets_2;
/* Total number of SETs to put into I3. */
int maxreg;
rtx temp;
- register rtx link;
+ rtx link;
int i;
/* Exit early if one of the insns involved can't be used for
abort ();
lo &= ~(UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1);
- lo |= INTVAL (SET_SRC (PATTERN (i3)));
+ lo |= (INTVAL (SET_SRC (PATTERN (i3)))
+ & (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1));
}
else if (HOST_BITS_PER_WIDE_INT == BITS_PER_WORD)
hi = INTVAL (SET_SRC (PATTERN (i3)));
/* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
We used to do this EXCEPT in one case: I3 has a post-inc in an
output operand. However, that exception can give rise to insns like
- mov r3,(r3)+
+ mov r3,(r3)+
which is a famous insn on the PDP-11 where the value of r3 used as the
source was model-dependent. Avoid this sort of thing. */
subst_low_cuid = INSN_CUID (i2);
newpat = subst (PATTERN (i3), i2dest, i2src, 0,
! i1_feeds_i3 && i1dest_in_i1src);
+ substed_i2 = 1;
/* Record whether i2's body now appears within i3's body. */
i2_is_used = n_occurrences;
isn't mentioned in any SETs in NEWPAT that are field assignments. */
if (! combinable_i3pat (NULL_RTX, &newpat, i1dest, NULL_RTX,
- 0, (rtx*)0))
+ 0, (rtx*) 0))
{
undo_all ();
return 0;
n_occurrences = 0;
subst_low_cuid = INSN_CUID (i1);
newpat = subst (newpat, i1dest, i1src, 0, 0);
+ substed_i1 = 1;
}
/* Fail if an autoincrement side-effect has been duplicated. Be careful
XVECEXP (newpat, 0, 0) = old;
}
- if (added_sets_1)
- XVECEXP (newpat, 0, --total_sets)
- = (GET_CODE (PATTERN (i1)) == PARALLEL
- ? gen_rtx_SET (VOIDmode, i1dest, i1src) : PATTERN (i1));
+ if (added_sets_1)
+ XVECEXP (newpat, 0, --total_sets)
+ = (GET_CODE (PATTERN (i1)) == PARALLEL
+ ? gen_rtx_SET (VOIDmode, i1dest, i1src) : PATTERN (i1));
- if (added_sets_2)
- {
- /* If there is no I1, use I2's body as is. We used to also not do
- the subst call below if I2 was substituted into I3,
- but that could lose a simplification. */
- if (i1 == 0)
- XVECEXP (newpat, 0, --total_sets) = i2pat;
- else
- /* See comment where i2pat is assigned. */
- XVECEXP (newpat, 0, --total_sets)
- = subst (i2pat, i1dest, i1src, 0, 0);
- }
+ if (added_sets_2)
+ {
+ /* If there is no I1, use I2's body as is. We used to also not do
+ the subst call below if I2 was substituted into I3,
+ but that could lose a simplification. */
+ if (i1 == 0)
+ XVECEXP (newpat, 0, --total_sets) = i2pat;
+ else
+ /* See comment where i2pat is assigned. */
+ XVECEXP (newpat, 0, --total_sets)
+ = subst (i2pat, i1dest, i1src, 0, 0);
+ }
}
/* We come here when we are replacing a destination in I2 with the
}
}
+ /* If we've split a jump pattern, we'll wind up with a sequence even
+ with one instruction. We can handle that below, so extract it. */
+ if (m_split && GET_CODE (m_split) == SEQUENCE
+ && XVECLEN (m_split, 0) == 1)
+ m_split = PATTERN (XVECEXP (m_split, 0, 0));
+
if (m_split && GET_CODE (m_split) != SEQUENCE)
{
insn_code_number = recog_for_combine (&m_split, i3, &new_i3_notes);
if (insn_code_number >= 0)
newpat = m_split;
- }
+ }
else if (m_split && GET_CODE (m_split) == SEQUENCE
&& XVECLEN (m_split, 0) == 2
&& (next_real_insn (i2) == i3
appeared to be a memory address. This is a kludge. */
if (split_code == MULT
&& GET_CODE (XEXP (*split, 1)) == CONST_INT
+ && INTVAL (XEXP (*split, 1)) > 0
&& (i = exact_log2 (INTVAL (XEXP (*split, 1)))) >= 0)
{
SUBST (*split, gen_rtx_ASHIFT (split_mode,
}
#ifdef HAVE_cc0
/* If I2 is the setter CC0 and I3 is the user CC0 then check whether
- they are adjacent to each other or not. */
+ they are adjacent to each other or not. */
{
rtx p = prev_nonnote_insn (i3);
if (p && p != i2 && GET_CODE (p) == INSN && newi2pat
INSN_CODE (i3) = insn_code_number;
PATTERN (i3) = newpat;
+
+ if (GET_CODE (i3) == CALL_INSN && CALL_INSN_FUNCTION_USAGE (i3))
+ {
+ rtx call_usage = CALL_INSN_FUNCTION_USAGE (i3);
+
+ reset_used_flags (call_usage);
+ call_usage = copy_rtx (call_usage);
+
+ if (substed_i2)
+ replace_rtx (call_usage, i2dest, i2src);
+
+ if (substed_i1)
+ replace_rtx (call_usage, i1dest, i1src);
+
+ CALL_INSN_FUNCTION_USAGE (i3) = call_usage;
+ }
+
if (undobuf.other_insn)
INSN_CODE (undobuf.other_insn) = other_code_number;
|| GET_CODE (temp) != BARRIER)
emit_barrier_after (i3);
}
+ /* An NOOP jump does not need barrier, but it does need cleaning up
+ of CFG. */
+ if (GET_CODE (newpat) == SET
+ && SET_SRC (newpat) == pc_rtx
+ && SET_DEST (newpat) == pc_rtx)
+ *new_direct_jump_p = 1;
}
combine_successes++;
&& GET_CODE (XEXP (SET_DEST (x), 2)) == CONST_INT
&& GET_CODE (SET_SRC (x)) == CONST_INT
&& ((INTVAL (XEXP (SET_DEST (x), 1))
- + INTVAL (XEXP (SET_DEST (x), 2)))
+ + INTVAL (XEXP (SET_DEST (x), 2)))
<= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0))))
&& ! side_effects_p (XEXP (SET_DEST (x), 0)))
{
&& GET_CODE (XEXP (SET_SRC (x), 0)) == REG
&& (pos = exact_log2 (INTVAL (XEXP (SET_SRC (x), 1)))) >= 7
&& GET_CODE (SET_DEST (x)) == REG
- && (split = find_single_use (SET_DEST (x), insn, (rtx*)0)) != 0
+ && (split = find_single_use (SET_DEST (x), insn, (rtx*) 0)) != 0
&& (GET_CODE (*split) == EQ || GET_CODE (*split) == NE)
&& XEXP (*split, 0) == SET_DEST (x)
&& XEXP (*split, 1) == const0_rtx)
case NE:
/* if STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
- is known to be on, this can be converted into a NEG of a shift. */
+ is known to be on, this can be converted into a NEG of a shift. */
if (STORE_FLAG_VALUE == -1 && XEXP (SET_SRC (x), 1) == const0_rtx
&& GET_MODE (SET_SRC (x)) == GET_MODE (XEXP (SET_SRC (x), 0))
&& 1 <= (pos = exact_log2
static rtx
subst (x, from, to, in_dest, unique_copy)
- register rtx x, from, to;
+ rtx x, from, to;
int in_dest;
int unique_copy;
{
- register enum rtx_code code = GET_CODE (x);
+ enum rtx_code code = GET_CODE (x);
enum machine_mode op0_mode = VOIDmode;
- register const char *fmt;
- register int len, i;
+ const char *fmt;
+ int len, i;
rtx new;
/* Two expressions are equal if they are identical copies of a shared
{
if (fmt[i] == 'E')
{
- register int j;
+ int j;
for (j = XVECLEN (x, i) - 1; j >= 0; j--)
{
if (COMBINE_RTX_EQUAL_P (XVECEXP (x, i, j), from))
if (GET_CODE (new) == CLOBBER && XEXP (new, 0) == const0_rtx)
return new;
- SUBST (XEXP (x, i), new);
+ if (GET_CODE (new) == CONST_INT && GET_CODE (x) == SUBREG)
+ {
+ x = simplify_subreg (GET_MODE (x), new,
+ GET_MODE (SUBREG_REG (x)),
+ SUBREG_BYTE (x));
+ if (! x)
+ abort ();
+ }
+ else if (GET_CODE (new) == CONST_INT
+ && GET_CODE (x) == ZERO_EXTEND)
+ {
+ x = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
+ new, GET_MODE (XEXP (x, 0)));
+ if (! x)
+ abort ();
+ }
+ else
+ SUBST (XEXP (x, i), new);
}
}
}
just make the comparison operation. */
if (true_rtx == const_true_rtx && false_rtx == const0_rtx)
x = gen_binary (cond_code, mode, cond, cop1);
- else if (true_rtx == const0_rtx && false_rtx == const_true_rtx)
+ else if (true_rtx == const0_rtx && false_rtx == const_true_rtx
+ && reverse_condition (cond_code) != UNKNOWN)
x = gen_binary (reverse_condition (cond_code),
mode, cond, cop1);
}
if (temp)
- x = temp, code = GET_CODE (temp), op0_mode = VOIDmode;
+ {
+ x = temp;
+ code = GET_CODE (temp);
+ op0_mode = VOIDmode;
+ mode = GET_MODE (temp);
+ }
/* First see if we can apply the inverse distributive law. */
if (code == PLUS || code == MINUS
/* If CODE is an associative operation not otherwise handled, see if we
can associate some operands. This can win if they are constants or
if they are logically related (i.e. (a & b) & a). */
- if ((code == PLUS || code == MINUS
- || code == MULT || code == AND || code == IOR || code == XOR
- || code == DIV || code == UDIV
+ if ((code == PLUS || code == MINUS || code == MULT || code == DIV
+ || code == AND || code == IOR || code == XOR
|| code == SMAX || code == SMIN || code == UMAX || code == UMIN)
- && INTEGRAL_MODE_P (mode))
+ && ((INTEGRAL_MODE_P (mode) && code != DIV)
+ || (flag_unsafe_math_optimizations && FLOAT_MODE_P (mode))))
{
if (GET_CODE (XEXP (x, 0)) == code)
{
}
inner = simplify_binary_operation (code == MINUS ? PLUS
: code == DIV ? MULT
- : code == UDIV ? MULT
: code,
mode, inner_op0, inner_op1);
&& subreg_lowpart_offset (mode, op0_mode) == SUBREG_BYTE (x))
return gen_lowpart_for_combine (mode, SUBREG_REG (x));
+ if (GET_MODE_CLASS (GET_MODE (SUBREG_REG (x))) == MODE_CC)
+ break;
{
rtx temp;
temp = simplify_subreg (mode, SUBREG_REG (x), op0_mode,
- SUBREG_BYTE (x));
+ SUBREG_BYTE (x));
if (temp)
return temp;
}
XEXP (XEXP (x, 0), 1))))
return reversed;
- /* (ashiftrt foo C) where C is the number of bits in FOO minus 1
- is (lt foo (const_int 0)) if STORE_FLAG_VALUE is -1, so we can
+ /* (not (ashiftrt foo C)) where C is the number of bits in FOO minus 1
+ is (ge foo (const_int 0)) if STORE_FLAG_VALUE is -1, so we can
perform the above simplification. */
if (STORE_FLAG_VALUE == -1
&& GET_CODE (XEXP (x, 0)) == ASHIFTRT
- && XEXP (x, 1) == const1_rtx
&& GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
&& INTVAL (XEXP (XEXP (x, 0), 1)) == GET_MODE_BITSIZE (mode) - 1)
return gen_rtx_GE (mode, XEXP (XEXP (x, 0), 0), const0_rtx);
/* Apply De Morgan's laws to reduce number of patterns for machines
- with negating logical insns (and-not, nand, etc.). If result has
- only one NOT, put it first, since that is how the patterns are
- coded. */
+ with negating logical insns (and-not, nand, etc.). If result has
+ only one NOT, put it first, since that is how the patterns are
+ coded. */
if (GET_CODE (XEXP (x, 0)) == IOR || GET_CODE (XEXP (x, 0)) == AND)
- {
+ {
rtx in1 = XEXP (XEXP (x, 0), 0), in2 = XEXP (XEXP (x, 0), 1);
enum machine_mode op_mode;
if (GET_CODE (XEXP (x, 0)) == NOT)
return plus_constant (XEXP (XEXP (x, 0), 0), 1);
- /* (neg (minus X Y)) can become (minus Y X). */
+ /* (neg (minus X Y)) can become (minus Y X). This transformation
+ isn't safe for modes with signed zeros, since if X and Y are
+ both +0, (minus Y X) is the same as (minus X Y). If the rounding
+ mode is towards +infinity (or -infinity) then the two expressions
+ will be rounded differently. */
if (GET_CODE (XEXP (x, 0)) == MINUS
- && (! FLOAT_MODE_P (mode)
- /* x-y != -(y-x) with IEEE floating point. */
- || TARGET_FLOAT_FORMAT != IEEE_FLOAT_FORMAT
- || flag_unsafe_math_optimizations))
+ && !HONOR_SIGNED_ZEROS (mode)
+ && !HONOR_SIGN_DEPENDENT_ROUNDING (mode))
return gen_binary (MINUS, mode, XEXP (XEXP (x, 0), 1),
XEXP (XEXP (x, 0), 0));
temp = simplify_unary_operation (NEG, mode,
XEXP (XEXP (x, 0), 0), mode);
if (temp)
- {
- SUBST (XEXP (XEXP (x, 0), 0), temp);
- return XEXP (x, 0);
- }
+ return gen_binary (ASHIFT, mode, temp, XEXP (XEXP (x, 0), 1));
}
temp = expand_compound_operation (XEXP (x, 0));
/* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
- replaced by (lshiftrt X C). This will convert
+ replaced by (lshiftrt X C). This will convert
(neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
if (GET_CODE (temp) == ASHIFTRT
&& num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
>= GET_MODE_BITSIZE (mode) + 1
&& ! (GET_CODE (XEXP (x, 0)) == LSHIFTRT
- && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT))
+ && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT))
return gen_lowpart_for_combine (mode, XEXP (x, 0));
/* A truncate of a comparison can be replaced with a subreg if
if (XEXP (x, 1) == const0_rtx)
return XEXP (x, 0);
- /* In IEEE floating point, x-0 is not the same as x. */
- if ((TARGET_FLOAT_FORMAT != IEEE_FLOAT_FORMAT
- || ! FLOAT_MODE_P (GET_MODE (XEXP (x, 0)))
- || flag_unsafe_math_optimizations)
+ /* x - 0 is the same as x unless x's mode has signed zeros and
+ allows rounding towards -infinity. Under those conditions,
+ 0 - 0 is -0. */
+ if (!(HONOR_SIGNED_ZEROS (GET_MODE (XEXP (x, 0)))
+ && HONOR_SIGN_DEPENDENT_ROUNDING (GET_MODE (XEXP (x, 0))))
&& XEXP (x, 1) == CONST0_RTX (GET_MODE (XEXP (x, 0))))
return XEXP (x, 0);
break;
if (GET_CODE (x) != MULT)
return x;
}
+ /* Try simplify a*(b/c) as (a*b)/c. */
+ if (FLOAT_MODE_P (mode) && flag_unsafe_math_optimizations
+ && GET_CODE (XEXP (x, 0)) == DIV)
+ {
+ rtx tem = simplify_binary_operation (MULT, mode,
+ XEXP (XEXP (x, 0), 0),
+ XEXP (x, 1));
+ if (tem)
+ return gen_binary (DIV, mode, tem, XEXP (XEXP (x, 0), 1));
+ }
break;
case UDIV:
case GT: case GTU: case GE: case GEU:
case LT: case LTU: case LE: case LEU:
case UNEQ: case LTGT:
- case UNGT: case UNGE:
- case UNLT: case UNLE:
+ case UNGT: case UNGE:
+ case UNLT: case UNLE:
case UNORDERED: case ORDERED:
/* If the first operand is a condition code, we can't do anything
with it. */
}
break;
-
+
default:
break;
}
simplify_gen_unary (NEG, mode,
simplify_gen_unary (ABS, mode, true_rtx, mode),
mode);
- default:
- break;
+ default:
+ break;
}
/* Look for MIN or MAX. */
&& GET_RTX_CLASS (GET_CODE (XEXP (XEXP (x, 0), 0))) == '<'
&& (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
<= HOST_BITS_PER_WIDE_INT)
- && ((HOST_WIDE_INT) STORE_FLAG_VALUE
+ && ((HOST_WIDE_INT) STORE_FLAG_VALUE
& ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
return XEXP (XEXP (x, 0), 0);
if (GET_CODE (SET_DEST (x)) == STRICT_LOW_PART
&& GET_CODE (XEXP (SET_DEST (x), 0)) == SUBREG)
{
- int byte_offset = SUBREG_BYTE (XEXP (SET_DEST (x), 0));
-
inner = SUBREG_REG (XEXP (SET_DEST (x), 0));
len = GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)));
- pos = GEN_INT (BITS_PER_WORD * (byte_offset / UNITS_PER_WORD));
+ pos = GEN_INT (subreg_lsb (XEXP (SET_DEST (x), 0)));
}
else if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
&& GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT)
&& GET_CODE (inner) != MEM
&& (! in_dest
|| (GET_CODE (inner) == REG
- && (movstrict_optab->handlers[(int) tmode].insn_code
- != CODE_FOR_nothing))))
+ && have_insn_for (STRICT_LOW_PART, tmode))))
|| (GET_CODE (inner) == MEM && pos_rtx == 0
&& (pos
% (STRICT_ALIGNMENT ? GET_MODE_ALIGNMENT (tmode)
if (GET_CODE (inner) == MEM)
{
- int offset;
+ HOST_WIDE_INT offset;
+
/* POS counts from lsb, but make OFFSET count in memory order. */
if (BYTES_BIG_ENDIAN)
offset = (GET_MODE_BITSIZE (is_mode) - len - pos) / BITS_PER_UNIT;
else
offset = pos / BITS_PER_UNIT;
- new = gen_rtx_MEM (tmode, plus_constant (XEXP (inner, 0), offset));
- MEM_COPY_ATTRIBUTES (new, inner);
+ new = adjust_address_nv (inner, tmode, offset);
}
else if (GET_CODE (inner) == REG)
{
a SUBREG and it would sometimes return a new hard register. */
if (tmode != inner_mode)
{
- int final_word = pos / BITS_PER_WORD;
+ HOST_WIDE_INT final_word = pos / BITS_PER_WORD;
if (WORDS_BIG_ENDIAN
&& GET_MODE_SIZE (inner_mode) > UNITS_PER_WORD)
new = gen_rtx_SUBREG (tmode, inner, final_word);
}
- else
- new = inner;
- }
+ else
+ new = inner;
+ }
else
new = force_to_mode (inner, tmode,
len >= HOST_BITS_PER_WIDE_INT
if (mode == tmode)
return new;
+ if (GET_CODE (new) == CONST_INT)
+ return gen_int_mode (INTVAL (new), mode);
+
/* If we know that no extraneous bits are set, and that the high
bit is not set, convert the extraction to the cheaper of
sign and zero extension, that are equivalent in these cases. */
/* Get the mode to use should INNER not be a MEM, the mode for the position,
and the mode for the result. */
-#ifdef HAVE_insv
- if (in_dest)
+ if (in_dest && mode_for_extraction (EP_insv, -1) != MAX_MACHINE_MODE)
{
- wanted_inner_reg_mode
- = insn_data[(int) CODE_FOR_insv].operand[0].mode;
- if (wanted_inner_reg_mode == VOIDmode)
- wanted_inner_reg_mode = word_mode;
-
- pos_mode = insn_data[(int) CODE_FOR_insv].operand[2].mode;
- if (pos_mode == VOIDmode)
- pos_mode = word_mode;
-
- extraction_mode = insn_data[(int) CODE_FOR_insv].operand[3].mode;
- if (extraction_mode == VOIDmode)
- extraction_mode = word_mode;
+ wanted_inner_reg_mode = mode_for_extraction (EP_insv, 0);
+ pos_mode = mode_for_extraction (EP_insv, 2);
+ extraction_mode = mode_for_extraction (EP_insv, 3);
}
-#endif
-#ifdef HAVE_extzv
- if (! in_dest && unsignedp)
+ if (! in_dest && unsignedp
+ && mode_for_extraction (EP_extzv, -1) != MAX_MACHINE_MODE)
{
- wanted_inner_reg_mode
- = insn_data[(int) CODE_FOR_extzv].operand[1].mode;
- if (wanted_inner_reg_mode == VOIDmode)
- wanted_inner_reg_mode = word_mode;
-
- pos_mode = insn_data[(int) CODE_FOR_extzv].operand[3].mode;
- if (pos_mode == VOIDmode)
- pos_mode = word_mode;
-
- extraction_mode = insn_data[(int) CODE_FOR_extzv].operand[0].mode;
- if (extraction_mode == VOIDmode)
- extraction_mode = word_mode;
+ wanted_inner_reg_mode = mode_for_extraction (EP_extzv, 1);
+ pos_mode = mode_for_extraction (EP_extzv, 3);
+ extraction_mode = mode_for_extraction (EP_extzv, 0);
}
-#endif
-#ifdef HAVE_extv
- if (! in_dest && ! unsignedp)
+ if (! in_dest && ! unsignedp
+ && mode_for_extraction (EP_extv, -1) != MAX_MACHINE_MODE)
{
- wanted_inner_reg_mode
- = insn_data[(int) CODE_FOR_extv].operand[1].mode;
- if (wanted_inner_reg_mode == VOIDmode)
- wanted_inner_reg_mode = word_mode;
-
- pos_mode = insn_data[(int) CODE_FOR_extv].operand[3].mode;
- if (pos_mode == VOIDmode)
- pos_mode = word_mode;
-
- extraction_mode = insn_data[(int) CODE_FOR_extv].operand[0].mode;
- if (extraction_mode == VOIDmode)
- extraction_mode = word_mode;
+ wanted_inner_reg_mode = mode_for_extraction (EP_extv, 1);
+ pos_mode = mode_for_extraction (EP_extv, 3);
+ extraction_mode = mode_for_extraction (EP_extv, 0);
}
-#endif
/* Never narrow an object, since that might not be safe. */
- GET_MODE_SIZE (wanted_inner_mode) - offset);
if (offset != 0 || inner_mode != wanted_inner_mode)
- {
- rtx newmem = gen_rtx_MEM (wanted_inner_mode,
- plus_constant (XEXP (inner, 0), offset));
-
- MEM_COPY_ATTRIBUTES (newmem, inner);
- inner = newmem;
- }
+ inner = adjust_address_nv (inner, wanted_inner_mode, offset);
}
/* If INNER is not memory, we can always get it into the proper mode. If we
rtx temp = gen_rtx_ZERO_EXTEND (pos_mode, pos_rtx);
/* If we know that no extraneous bits are set, and that the high
- bit is not set, convert extraction to cheaper one - eighter
+ bit is not set, convert extraction to cheaper one - either
SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
cases. */
if (flag_expensive_optimizations
Return the new rtx, usually just X.
- Also, for machines like the Vax that don't have logical shift insns,
+ Also, for machines like the VAX that don't have logical shift insns,
try to convert logical to arithmetic shift operations in cases where
they are equivalent. This undoes the canonicalizations to logical
shifts done elsewhere.
/* On machines without logical shifts, if the operand of the AND is
a logical shift and our mask turns off all the propagated sign
bits, we can replace the logical shift with an arithmetic shift. */
- else if (ashr_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing
- && (lshr_optab->handlers[(int) mode].insn_code
- == CODE_FOR_nothing)
- && GET_CODE (XEXP (x, 0)) == LSHIFTRT
+ else if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
+ && !have_insn_for (LSHIFTRT, mode)
+ && have_insn_for (ASHIFTRT, mode)
&& GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
&& INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
&& INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
case LSHIFTRT:
/* If the sign bit is known to be zero, replace this with an
arithmetic shift. */
- if (ashr_optab->handlers[(int) mode].insn_code == CODE_FOR_nothing
- && lshr_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing
+ if (have_insn_for (ASHIFTRT, mode)
+ && ! have_insn_for (LSHIFTRT, mode)
&& mode_width <= HOST_BITS_PER_WIDE_INT
&& (nonzero_bits (XEXP (x, 0), mode) & (1 << (mode_width - 1))) == 0)
{
NULL_RTX, 0);
/* If we have something other than a SUBREG, we might have
- done an expansion, so rerun outselves. */
+ done an expansion, so rerun ourselves. */
if (GET_CODE (newer) != SUBREG)
newer = make_compound_operation (newer, in_code);
that the operation is valid in MODE, in which case we do the operation
in MODE. */
op_mode = ((GET_MODE_CLASS (mode) == GET_MODE_CLASS (GET_MODE (x))
- && code_to_optab[(int) code] != 0
- && (code_to_optab[(int) code]->handlers[(int) mode].insn_code
- != CODE_FOR_nothing))
+ && have_insn_for (code, mode))
? mode : GET_MODE (x));
/* It is not valid to do a right-shift in a narrower mode
need it. */
if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT
- && (unsigned HOST_WIDE_INT) INTVAL (XEXP (x, 1)) == mask)
+ && ((INTVAL (XEXP (x, 1)) & GET_MODE_MASK (GET_MODE (x)))
+ == (HOST_WIDE_INT) mask))
x = XEXP (x, 0);
/* If it remains an AND, try making another AND with the bits
smask |= (HOST_WIDE_INT) -1 << width;
if (GET_CODE (XEXP (x, 1)) == CONST_INT
- && exact_log2 (- smask) >= 0)
- {
-#ifdef STACK_BIAS
- if (STACK_BIAS
- && (XEXP (x, 0) == stack_pointer_rtx
- || XEXP (x, 0) == frame_pointer_rtx))
- {
- int sp_alignment = STACK_BOUNDARY / BITS_PER_UNIT;
- unsigned HOST_WIDE_INT sp_mask = GET_MODE_MASK (mode);
-
- sp_mask &= ~(sp_alignment - 1);
- if ((sp_mask & ~smask) == 0
- && ((INTVAL (XEXP (x, 1)) - STACK_BIAS) & ~smask) != 0)
- return force_to_mode (plus_constant (XEXP (x, 0),
- ((INTVAL (XEXP (x, 1)) -
- STACK_BIAS) & smask)
- + STACK_BIAS),
- mode, smask, reg, next_select);
- }
-#endif
- if ((nonzero_bits (XEXP (x, 0), mode) & ~smask) == 0
- && (INTVAL (XEXP (x, 1)) & ~smask) != 0)
- return force_to_mode (plus_constant (XEXP (x, 0),
- (INTVAL (XEXP (x, 1))
- & smask)),
- mode, smask, reg, next_select);
- }
+ && exact_log2 (- smask) >= 0
+ && (nonzero_bits (XEXP (x, 0), mode) & ~smask) == 0
+ && (INTVAL (XEXP (x, 1)) & ~smask) != 0)
+ return force_to_mode (plus_constant (XEXP (x, 0),
+ (INTVAL (XEXP (x, 1)) & smask)),
+ mode, smask, reg, next_select);
}
/* ... fall through ... */
binop:
/* For most binary operations, just propagate into the operation and
- change the mode if we have an operation of that mode. */
+ change the mode if we have an operation of that mode. */
op0 = gen_lowpart_for_combine (op_mode,
force_to_mode (XEXP (x, 0), mode, mask,
{
int i = -1;
- /* If the considered data is wider then HOST_WIDE_INT, we can't
+ /* If the considered data is wider than HOST_WIDE_INT, we can't
represent a mask for all its bits in a single scalar.
But we only care about the lower bits, so calculate these. */
case NEG:
/* If we just want the low-order bit, the NEG isn't needed since it
- won't change the low-order bit. */
+ won't change the low-order bit. */
if (mask == 1)
return force_to_mode (XEXP (x, 0), mode, mask, reg, just_select);
}
}
- /* Similarly for MULT, AND and UMIN, execpt that for these the result
+ /* Similarly for MULT, AND and UMIN, except that for these the result
is always zero. */
if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
&& (code == MULT || code == AND || code == UMIN)
if (side_effects_p (x))
return x;
- if (cond == EQ && rtx_equal_p (x, reg) && !FLOAT_MODE_P (cond))
+ /* If either operand of the condition is a floating point value,
+ then we have to avoid collapsing an EQ comparison. */
+ if (cond == EQ
+ && rtx_equal_p (x, reg)
+ && ! FLOAT_MODE_P (GET_MODE (x))
+ && ! FLOAT_MODE_P (GET_MODE (val)))
return val;
+
if (cond == UNEQ && rtx_equal_p (x, reg))
return val;
/* Do not reverse the condition when it is NE or EQ.
This is because we cannot conclude anything about
the value of 'SMAX (x, y)' when x is not equal to y,
- but we can when x equals y. */
+ but we can when x equals y. */
if ((code == SMAX || code == UMAX)
&& ! (cond == EQ || cond == NE))
cond = reverse_condition (cond);
}
}
}
+ else if (code == SUBREG)
+ {
+ enum machine_mode inner_mode = GET_MODE (SUBREG_REG (x));
+ rtx new, r = known_cond (SUBREG_REG (x), cond, reg, val);
+
+ if (SUBREG_REG (x) != r)
+ {
+ /* We must simplify subreg here, before we lose track of the
+ original inner_mode. */
+ new = simplify_subreg (GET_MODE (x), r,
+ inner_mode, SUBREG_BYTE (x));
+ if (new)
+ return new;
+ else
+ SUBST (SUBREG_REG (x), r);
+ }
+
+ return x;
+ }
+ /* We don't have to handle SIGN_EXTEND here, because even in the
+ case of replacing something with a modeless CONST_INT, a
+ CONST_INT is already (supposed to be) a valid sign extension for
+ its narrower mode, which implies it's already properly
+ sign-extended for the wider mode. Now, for ZERO_EXTEND, the
+ story is different. */
+ else if (code == ZERO_EXTEND)
+ {
+ enum machine_mode inner_mode = GET_MODE (XEXP (x, 0));
+ rtx new, r = known_cond (XEXP (x, 0), cond, reg, val);
+
+ if (XEXP (x, 0) != r)
+ {
+ /* We must simplify the zero_extend here, before we lose
+ track of the original inner_mode. */
+ new = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
+ r, inner_mode);
+ if (new)
+ return new;
+ else
+ SUBST (XEXP (x, 0), r);
+ }
+
+ return x;
+ }
fmt = GET_RTX_FORMAT (code);
for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
MODE. */
nonzero = nonzero_bits (varop, mode) & GET_MODE_MASK (mode);
- nonzero = trunc_int_for_mode (nonzero, mode);
/* Turn off all bits in the constant that are known to already be zero.
Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
simplify_and_const_int (NULL_RTX, GET_MODE (varop),
XEXP (varop, 1), constop))));
+ /* If VAROP is PLUS, and the constant is a mask of low bite, distribute
+ the AND and see if one of the operands simplifies to zero. If so, we
+ may eliminate it. */
+
+ if (GET_CODE (varop) == PLUS
+ && exact_log2 (constop + 1) >= 0)
+ {
+ rtx o0, o1;
+
+ o0 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 0), constop);
+ o1 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 1), constop);
+ if (o0 == const0_rtx)
+ return o1;
+ if (o1 == const0_rtx)
+ return o0;
+ }
+
/* Get VAROP in MODE. Try to get a SUBREG if not. Don't make a new SUBREG
if we already had one (just check for the simplest cases). */
if (x && GET_CODE (XEXP (x, 0)) == SUBREG
/* If we are only masking insignificant bits, return VAROP. */
if (constop == nonzero)
x = varop;
-
- /* Otherwise, return an AND. See how much, if any, of X we can use. */
- else if (x == 0 || GET_CODE (x) != AND || GET_MODE (x) != mode)
- x = gen_binary (AND, mode, varop, GEN_INT (constop));
-
else
{
- if (GET_CODE (XEXP (x, 1)) != CONST_INT
- || (unsigned HOST_WIDE_INT) INTVAL (XEXP (x, 1)) != constop)
- SUBST (XEXP (x, 1), GEN_INT (constop));
+ /* Otherwise, return an AND. */
+ constop = trunc_int_for_mode (constop, mode);
+ /* See how much, if any, of X we can use. */
+ if (x == 0 || GET_CODE (x) != AND || GET_MODE (x) != mode)
+ x = gen_binary (AND, mode, varop, GEN_INT (constop));
+
+ else
+ {
+ if (GET_CODE (XEXP (x, 1)) != CONST_INT
+ || (unsigned HOST_WIDE_INT) INTVAL (XEXP (x, 1)) != constop)
+ SUBST (XEXP (x, 1), GEN_INT (constop));
- SUBST (XEXP (x, 0), varop);
+ SUBST (XEXP (x, 0), varop);
+ }
}
return x;
switch (code)
{
case REG:
-#ifdef POINTERS_EXTEND_UNSIGNED
+#if defined(POINTERS_EXTEND_UNSIGNED) && !defined(HAVE_ptr_extend)
/* If pointers extend unsigned and this is a pointer in Pmode, say that
all the bits above ptr_mode are known to be zero. */
if (POINTERS_EXTEND_UNSIGNED && GET_MODE (x) == Pmode
nonzero &= GET_MODE_MASK (ptr_mode);
#endif
-#ifdef STACK_BOUNDARY
- /* If this is the stack pointer, we may know something about its
- alignment. If PUSH_ROUNDING is defined, it is possible for the
- stack to be momentarily aligned only to that amount, so we pick
- the least alignment. */
-
- /* We can't check for arg_pointer_rtx here, because it is not
- guaranteed to have as much alignment as the stack pointer.
- In particular, in the Irix6 n64 ABI, the stack has 128 bit
- alignment but the argument pointer has only 64 bit alignment. */
-
- if ((x == frame_pointer_rtx
- || x == stack_pointer_rtx
- || x == hard_frame_pointer_rtx
- || (REGNO (x) >= FIRST_VIRTUAL_REGISTER
- && REGNO (x) <= LAST_VIRTUAL_REGISTER))
-#ifdef STACK_BIAS
- && !STACK_BIAS
-#endif
- )
+ /* Include declared information about alignment of pointers. */
+ /* ??? We don't properly preserve REG_POINTER changes across
+ pointer-to-integer casts, so we can't trust it except for
+ things that we know must be pointers. See execute/960116-1.c. */
+ if ((x == stack_pointer_rtx
+ || x == frame_pointer_rtx
+ || x == arg_pointer_rtx)
+ && REGNO_POINTER_ALIGN (REGNO (x)))
{
- int sp_alignment = STACK_BOUNDARY / BITS_PER_UNIT;
+ unsigned HOST_WIDE_INT alignment
+ = REGNO_POINTER_ALIGN (REGNO (x)) / BITS_PER_UNIT;
#ifdef PUSH_ROUNDING
- if (REGNO (x) == STACK_POINTER_REGNUM && PUSH_ARGS)
- sp_alignment = MIN (PUSH_ROUNDING (1), sp_alignment);
+ /* If PUSH_ROUNDING is defined, it is possible for the
+ stack to be momentarily aligned only to that amount,
+ so we pick the least alignment. */
+ if (x == stack_pointer_rtx && PUSH_ARGS)
+ alignment = MIN (PUSH_ROUNDING (1), alignment);
#endif
- /* We must return here, otherwise we may get a worse result from
- one of the choices below. There is nothing useful below as
- far as the stack pointer is concerned. */
- return nonzero &= ~(sp_alignment - 1);
+ nonzero &= ~(alignment - 1);
}
-#endif
/* If X is a register whose nonzero bits value is current, use it.
Otherwise, if X is a register whose value we can find, use that
&& ! REGNO_REG_SET_P (BASIC_BLOCK (0)->global_live_at_start,
REGNO (x))))
&& INSN_CUID (reg_last_set[REGNO (x)]) < subst_low_cuid)
- return reg_last_set_nonzero_bits[REGNO (x)];
+ return reg_last_set_nonzero_bits[REGNO (x)] & nonzero;
tem = get_last_value (x);
| ((HOST_WIDE_INT) (-1)
<< GET_MODE_BITSIZE (GET_MODE (x))));
#endif
- return nonzero_bits (tem, mode);
+ return nonzero_bits (tem, mode) & nonzero;
}
else if (nonzero_sign_valid && reg_nonzero_bits[REGNO (x)])
- return reg_nonzero_bits[REGNO (x)] & nonzero;
+ {
+ unsigned HOST_WIDE_INT mask = reg_nonzero_bits[REGNO (x)];
+
+ if (GET_MODE_BITSIZE (GET_MODE (x)) < mode_width)
+ /* We don't know anything about the upper bits. */
+ mask |= GET_MODE_MASK (mode) ^ GET_MODE_MASK (GET_MODE (x));
+ return nonzero & mask;
+ }
else
return nonzero;
switch (code)
{
case PLUS:
-#ifdef STACK_BIAS
- if (STACK_BIAS
- && (XEXP (x, 0) == stack_pointer_rtx
- || XEXP (x, 0) == frame_pointer_rtx)
- && GET_CODE (XEXP (x, 1)) == CONST_INT)
- {
- int sp_alignment = STACK_BOUNDARY / BITS_PER_UNIT;
-
- nz0 = (GET_MODE_MASK (mode) & ~(sp_alignment - 1));
- nz1 = INTVAL (XEXP (x, 1)) - STACK_BIAS;
- width0 = floor_log2 (nz0) + 1;
- width1 = floor_log2 (nz1) + 1;
- low0 = floor_log2 (nz0 & -nz0);
- low1 = floor_log2 (nz1 & -nz1);
- }
-#endif
result_width = MAX (width0, width1) + 1;
result_low = MIN (low0, low1);
break;
result_low = low0 + low1;
break;
case DIV:
+ if (width1 == 0)
+ break;
if (! op0_maybe_minusp && ! op1_maybe_minusp)
result_width = width0;
break;
case UDIV:
+ if (width1 == 0)
+ break;
result_width = width0;
break;
case MOD:
+ if (width1 == 0)
+ break;
if (! op0_maybe_minusp && ! op1_maybe_minusp)
result_width = MIN (width0, width1);
result_low = MIN (low0, low1);
break;
case UMOD:
+ if (width1 == 0)
+ break;
result_width = MIN (width0, width1);
result_low = MIN (low0, low1);
break;
/* If pointers extend unsigned and this is an addition or subtraction
to a pointer in Pmode, all the bits above ptr_mode are known to be
zero. */
- if (POINTERS_EXTEND_UNSIGNED && GET_MODE (x) == Pmode
+ if (POINTERS_EXTEND_UNSIGNED > 0 && GET_MODE (x) == Pmode
&& (code == PLUS || code == MINUS)
&& GET_CODE (XEXP (x, 0)) == REG && REG_POINTER (XEXP (x, 0)))
nonzero &= GET_MODE_MASK (ptr_mode);
been zero-extended, we know that at least the high-order bits
are zero, though others might be too. */
- if (SUBREG_PROMOTED_VAR_P (x) && SUBREG_PROMOTED_UNSIGNED_P (x))
+ if (SUBREG_PROMOTED_VAR_P (x) && SUBREG_PROMOTED_UNSIGNED_P (x) > 0)
nonzero = (GET_MODE_MASK (GET_MODE (x))
& nonzero_bits (SUBREG_REG (x), GET_MODE (x)));
{
case REG:
-#ifdef POINTERS_EXTEND_UNSIGNED
+#if defined(POINTERS_EXTEND_UNSIGNED) && !defined(HAVE_ptr_extend)
/* If pointers extend signed and this is a pointer in Pmode, say that
all the bits above ptr_mode are known to be sign bit copies. */
if (! POINTERS_EXTEND_UNSIGNED && GET_MODE (x) == Pmode && mode == Pmode
if (tem != 0)
return num_sign_bit_copies (tem, mode);
- if (nonzero_sign_valid && reg_sign_bit_copies[REGNO (x)] != 0)
+ if (nonzero_sign_valid && reg_sign_bit_copies[REGNO (x)] != 0
+ && GET_MODE_BITSIZE (GET_MODE (x)) == bitwidth)
return reg_sign_bit_copies[REGNO (x)];
break;
of sign bit copies, we can just subtract that amount from the
number. */
if (GET_CODE (XEXP (x, 1)) == CONST_INT
- && INTVAL (XEXP (x, 1)) >= 0 && INTVAL (XEXP (x, 1)) < bitwidth)
+ && INTVAL (XEXP (x, 1)) >= 0
+ && INTVAL (XEXP (x, 1)) < (int) bitwidth)
{
num0 = num_sign_bit_copies (XEXP (x, 0), mode);
return MAX (1, num0 - (code == ROTATE ? INTVAL (XEXP (x, 1))
if (! POINTERS_EXTEND_UNSIGNED && GET_MODE (x) == Pmode
&& (code == PLUS || code == MINUS)
&& GET_CODE (XEXP (x, 0)) == REG && REG_POINTER (XEXP (x, 0)))
- result = MAX ((GET_MODE_BITSIZE (Pmode)
- - GET_MODE_BITSIZE (ptr_mode) + 1),
+ result = MAX ((int) (GET_MODE_BITSIZE (Pmode)
+ - GET_MODE_BITSIZE (ptr_mode) + 1),
result);
#endif
return result;
return num_sign_bit_copies (XEXP (x, 0), mode);
case UMOD:
- /* The result must be <= the scond operand. */
+ /* The result must be <= the second operand. */
return num_sign_bit_copies (XEXP (x, 1), mode);
case DIV:
num0 = num_sign_bit_copies (XEXP (x, 0), mode);
if (GET_CODE (XEXP (x, 1)) == CONST_INT
&& INTVAL (XEXP (x, 1)) > 0)
- num0 = MIN (bitwidth, num0 + INTVAL (XEXP (x, 1)));
+ num0 = MIN ((int) bitwidth, num0 + INTVAL (XEXP (x, 1)));
return num0;
/* Left shifts destroy copies. */
if (GET_CODE (XEXP (x, 1)) != CONST_INT
|| INTVAL (XEXP (x, 1)) < 0
- || INTVAL (XEXP (x, 1)) >= bitwidth)
+ || INTVAL (XEXP (x, 1)) >= (int) bitwidth)
return 1;
num0 = num_sign_bit_copies (XEXP (x, 0), mode);
are ASHIFTRT and ROTATE, which are always done in their original mode, */
static rtx
-simplify_shift_const (x, code, result_mode, varop, input_count)
+simplify_shift_const (x, code, result_mode, varop, orig_count)
rtx x;
enum rtx_code code;
enum machine_mode result_mode;
rtx varop;
- int input_count;
+ int orig_count;
{
enum rtx_code orig_code = code;
- int orig_count = input_count;
unsigned int count;
int signed_count;
enum machine_mode mode = result_mode;
int complement_p = 0;
rtx new;
+ /* Make sure and truncate the "natural" shift on the way in. We don't
+ want to do this inside the loop as it makes it more difficult to
+ combine shifts. */
+#ifdef SHIFT_COUNT_TRUNCATED
+ if (SHIFT_COUNT_TRUNCATED)
+ orig_count &= GET_MODE_BITSIZE (mode) - 1;
+#endif
+
/* If we were given an invalid count, don't do anything except exactly
what was requested. */
- if (input_count < 0 || input_count > (int) GET_MODE_BITSIZE (mode))
+ if (orig_count < 0 || orig_count >= (int) GET_MODE_BITSIZE (mode))
{
if (x)
return x;
- return gen_rtx_fmt_ee (code, mode, varop, GEN_INT (input_count));
+ return gen_rtx_fmt_ee (code, mode, varop, GEN_INT (orig_count));
}
- count = input_count;
-
- /* Make sure and truncate the "natural" shift on the way in. We don't
- want to do this inside the loop as it makes it more difficult to
- combine shifts. */
-#ifdef SHIFT_COUNT_TRUNCATED
- if (SHIFT_COUNT_TRUNCATED)
- count %= GET_MODE_BITSIZE (mode);
-#endif
+ count = orig_count;
/* Unless one of the branches of the `if' in this loop does a `continue',
we will `break' the loop after the `if'. */
/* We simplify the tests below and elsewhere by converting
ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
`make_compound_operation' will convert it to a ASHIFTRT for
- those machines (such as Vax) that don't have a LSHIFTRT. */
+ those machines (such as VAX) that don't have a LSHIFTRT. */
if (GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
&& code == ASHIFTRT
&& ((nonzero_bits (varop, shift_mode)
&& (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
MODE_INT, 1)) != BLKmode)
{
- if (BYTES_BIG_ENDIAN)
- new = gen_rtx_MEM (tmode, XEXP (varop, 0));
- else
- new = gen_rtx_MEM (tmode,
- plus_constant (XEXP (varop, 0),
- count / BITS_PER_UNIT));
+ new = adjust_address_nv (varop, tmode,
+ BYTES_BIG_ENDIAN ? 0
+ : count / BITS_PER_UNIT);
- MEM_COPY_ATTRIBUTES (new, varop);
varop = gen_rtx_fmt_e (code == ASHIFTRT ? SIGN_EXTEND
: ZERO_EXTEND, mode, new);
count = 0;
if (new != 0)
x = new;
else
- {
- if (x == 0 || GET_CODE (x) != code || GET_MODE (x) != shift_mode)
- x = gen_rtx_fmt_ee (code, shift_mode, varop, const_rtx);
-
- SUBST (XEXP (x, 0), varop);
- SUBST (XEXP (x, 1), const_rtx);
- }
+ x = gen_rtx_fmt_ee (code, shift_mode, varop, const_rtx);
/* If we have an outer operation and we just made a shift, it is
possible that we could have simplified the shift were it not
rtx insn;
rtx *pnotes;
{
- register rtx pat = *pnewpat;
+ rtx pat = *pnewpat;
int insn_code_number;
int num_clobbers_to_add = 0;
int i;
rtx notes = 0;
- rtx old_notes;
+ rtx dummy_insn;
/* If PAT is a PARALLEL, check to see if it contains the CLOBBER
we use to indicate that something didn't match. If we find such a
&& XEXP (XVECEXP (pat, 0, i), 0) == const0_rtx)
return -1;
- /* Remove the old notes prior to trying to recognize the new pattern. */
- old_notes = REG_NOTES (insn);
- REG_NOTES (insn) = 0;
+ /* *pnewpat does not have to be actual PATTERN (insn), so make a dummy
+ instruction for pattern recognition. */
+ dummy_insn = shallow_copy_rtx (insn);
+ PATTERN (dummy_insn) = pat;
+ REG_NOTES (dummy_insn) = 0;
- /* Is the result of combination a valid instruction? */
- insn_code_number = recog (pat, insn, &num_clobbers_to_add);
+ insn_code_number = recog (pat, dummy_insn, &num_clobbers_to_add);
/* If it isn't, there is the possibility that we previously had an insn
that clobbered some register as a side effect, but the combined
if (pos == 1)
pat = XVECEXP (pat, 0, 0);
- insn_code_number = recog (pat, insn, &num_clobbers_to_add);
+ PATTERN (dummy_insn) = pat;
+ insn_code_number = recog (pat, dummy_insn, &num_clobbers_to_add);
}
- REG_NOTES (insn) = old_notes;
+ /* Recognize all noop sets, these will be killed by followup pass. */
+ if (insn_code_number < 0 && GET_CODE (pat) == SET && set_noop_p (pat))
+ insn_code_number = NOOP_MOVE_INSN_CODE, num_clobbers_to_add = 0;
/* If we had any clobbers to add, make a new pattern than contains
them. Then check to make sure that all of them are dead. */
static rtx
gen_lowpart_for_combine (mode, x)
enum machine_mode mode;
- register rtx x;
+ rtx x;
{
rtx result;
if (GET_CODE (x) == MEM)
{
- register int offset = 0;
- rtx new;
+ int offset = 0;
/* Refuse to work on a volatile memory ref or one with a mode-dependent
address. */
offset -= (MIN (UNITS_PER_WORD, GET_MODE_SIZE (mode))
- MIN (UNITS_PER_WORD, GET_MODE_SIZE (GET_MODE (x))));
}
- new = gen_rtx_MEM (mode, plus_constant (XEXP (x, 0), offset));
- MEM_COPY_ATTRIBUTES (new, x);
- return new;
+
+ return adjust_address_nv (x, mode, offset);
}
/* If X is a comparison operator, rewrite it in a new mode. This
{
if (BITS_BIG_ENDIAN)
{
-#ifdef HAVE_extzv
- mode = insn_data[(int) CODE_FOR_extzv].operand[1].mode;
- if (mode == VOIDmode)
- mode = word_mode;
- i = (GET_MODE_BITSIZE (mode) - 1 - i);
-#else
- i = BITS_PER_WORD - 1 - i;
-#endif
+ enum machine_mode new_mode
+ = mode_for_extraction (EP_extzv, 1);
+ if (new_mode == MAX_MACHINE_MODE)
+ i = BITS_PER_WORD - 1 - i;
+ else
+ {
+ mode = new_mode;
+ i = (GET_MODE_BITSIZE (mode) - 1 - i);
+ }
}
op0 = XEXP (op0, 2);
new_code = GET_CODE (op0);
else
new_code = combine_reversed_comparison_code (op0);
-
+
if (new_code != UNKNOWN)
{
code = new_code;
unsigned HOST_WIDE_INT temp = const_op & GET_MODE_MASK (mode);
temp >>= INTVAL (XEXP (op0, 1));
- op1 = GEN_INT (trunc_int_for_mode (temp, mode));
+ op1 = gen_int_mode (temp, mode);
op0 = XEXP (op0, 0);
continue;
}
|| (floor_log2 (const_op) + INTVAL (XEXP (op0, 1))
< mode_width)))
{
+ /* If the shift was logical, then we must make the condition
+ unsigned. */
+ if (GET_CODE (op0) == LSHIFTRT)
+ code = unsigned_condition (code);
+
const_op <<= INTVAL (XEXP (op0, 1));
op1 = GEN_INT (const_op);
op0 = XEXP (op0, 0);
if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
&& GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
+ && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op0))) == MODE_INT
&& (code == NE || code == EQ)
&& ((GET_MODE_SIZE (GET_MODE (op0))
> GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0))))))
else if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
&& GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
+ && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op0))) == MODE_INT
&& (code == NE || code == EQ)
&& (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
<= HOST_BITS_PER_WIDE_INT)
mode = GET_MODE (op0);
if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
&& GET_MODE_SIZE (mode) < UNITS_PER_WORD
- && cmp_optab->handlers[(int) mode].insn_code == CODE_FOR_nothing)
+ && ! have_insn_for (COMPARE, mode))
for (tmode = GET_MODE_WIDER_MODE (mode);
(tmode != VOIDmode
&& GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT);
tmode = GET_MODE_WIDER_MODE (tmode))
- if (cmp_optab->handlers[(int) tmode].insn_code != CODE_FOR_nothing)
+ if (have_insn_for (COMPARE, tmode))
{
/* If the only nonzero bits in OP0 and OP1 are those in the
narrower mode and this is an equality or unsigned comparison,
/* If OP0 is an AND and we don't have an AND in MODE either,
make a new AND in the proper mode. */
if (GET_CODE (op0) == AND
- && (add_optab->handlers[(int) mode].insn_code
- == CODE_FOR_nothing))
+ && !have_insn_for (AND, mode))
op0 = gen_binary (AND, tmode,
gen_lowpart_for_combine (tmode,
XEXP (op0, 0)),
combine_reversed_comparison_code (exp)
rtx exp;
{
- enum rtx_code code1 = reversed_comparison_code (exp, NULL);
- rtx x;
-
- if (code1 != UNKNOWN
- || GET_MODE_CLASS (GET_MODE (XEXP (exp, 0))) != MODE_CC)
- return code1;
- /* Otherwise try and find where the condition codes were last set and
- use that. */
- x = get_last_value (XEXP (exp, 0));
- if (!x || GET_CODE (x) != COMPARE)
- return UNKNOWN;
- return reversed_comparison_code_parts (GET_CODE (exp),
- XEXP (x, 0), XEXP (x, 1), NULL);
+ enum rtx_code code1 = reversed_comparison_code (exp, NULL);
+ rtx x;
+
+ if (code1 != UNKNOWN
+ || GET_MODE_CLASS (GET_MODE (XEXP (exp, 0))) != MODE_CC)
+ return code1;
+ /* Otherwise try and find where the condition codes were last set and
+ use that. */
+ x = get_last_value (XEXP (exp, 0));
+ if (!x || GET_CODE (x) != COMPARE)
+ return UNKNOWN;
+ return reversed_comparison_code_parts (GET_CODE (exp),
+ XEXP (x, 0), XEXP (x, 1), NULL);
}
/* Return comparison with reversed code of EXP and operands OP0 and OP1.
Return NULL_RTX in case we fail to do the reversal. */
update_table_tick (x)
rtx x;
{
- register enum rtx_code code = GET_CODE (x);
- register const char *fmt = GET_RTX_FORMAT (code);
- register int i;
+ enum rtx_code code = GET_CODE (x);
+ const char *fmt = GET_RTX_FORMAT (code);
+ int i;
if (code == REG)
{
record_dead_and_set_regs (insn)
rtx insn;
{
- register rtx link;
+ rtx link;
unsigned int i;
for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
if (GET_CODE (insn) == CALL_INSN)
{
for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
- if (call_used_regs[i])
+ if (TEST_HARD_REG_BIT (regs_invalidated_by_call, i))
{
reg_last_set_value[i] = 0;
reg_last_set_mode[i] = 0;
}
last_call_cuid = mem_last_set = INSN_CUID (insn);
+
+ /* Don't bother recording what this insn does. It might set the
+ return value register, but we can't combine into a call
+ pattern anyway, so there's no point trying (and it may cause
+ a crash, if e.g. we wind up asking for last_set_value of a
+ SUBREG of the return value register). */
+ return;
}
note_stores (PATTERN (insn), record_dead_and_set_regs_1, insn);
if (reg_last_set[regno] == insn)
{
- if (SUBREG_PROMOTED_UNSIGNED_P (subreg))
+ if (SUBREG_PROMOTED_UNSIGNED_P (subreg) > 0)
reg_last_set_nonzero_bits[regno] &= GET_MODE_MASK (mode);
}
it's either a hard register, set more than once, or it's a live
at the beginning of the function, return 0.
- Because if it's not live at the beginnning of the function then the reg
+ Because if it's not live at the beginning of the function then the reg
is always set before being used (is never used without being set).
And, if it's set only once, and it's always set before use, then all
uses must have the same last value, even if it's not from this basic
static int
use_crosses_set_p (x, from_cuid)
- register rtx x;
+ rtx x;
int from_cuid;
{
- register const char *fmt;
- register int i;
- register enum rtx_code code = GET_CODE (x);
+ const char *fmt;
+ int i;
+ enum rtx_code code = GET_CODE (x);
if (code == REG)
{
{
if (fmt[i] == 'E')
{
- register int j;
+ int j;
for (j = XVECLEN (x, i) - 1; j >= 0; j--)
if (use_crosses_set_p (XVECEXP (x, i, j), from_cuid))
return 1;
case CONST_INT:
case CONST:
case CONST_DOUBLE:
+ case CONST_VECTOR:
case PC:
case ADDR_VEC:
case ADDR_DIFF_VEC:
{
/* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
the address. */
- register rtx testreg = SET_DEST (x);
+ rtx testreg = SET_DEST (x);
while (GET_CODE (testreg) == SUBREG
|| GET_CODE (testreg) == ZERO_EXTRACT
/* Recursively scan the operands of this expression. */
{
- register const char *fmt = GET_RTX_FORMAT (code);
+ const char *fmt = GET_RTX_FORMAT (code);
for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
{
mark_used_regs_combine (XEXP (x, i));
else if (fmt[i] == 'E')
{
- register int j;
+ int j;
for (j = 0; j < XVECLEN (x, i); j++)
mark_used_regs_combine (XVECEXP (x, i, j));
unsigned int regno;
rtx insn;
{
- register rtx note = find_regno_note (insn, REG_DEAD, regno);
+ rtx note = find_regno_note (insn, REG_DEAD, regno);
if (note)
{
rtx to_insn;
rtx *pnotes;
{
- register const char *fmt;
- register int len, i;
- register enum rtx_code code = GET_CODE (x);
+ const char *fmt;
+ int len, i;
+ enum rtx_code code = GET_CODE (x);
if (code == REG)
{
unsigned int regno = REGNO (x);
- register rtx where_dead = reg_last_death[regno];
- register rtx before_dead, after_dead;
+ rtx where_dead = reg_last_death[regno];
+ rtx before_dead, after_dead;
/* Don't move the register if it gets killed in between from and to */
if (maybe_kill_insn && reg_set_p (x, maybe_kill_insn)
{
if (fmt[i] == 'E')
{
- register int j;
+ int j;
for (j = XVECLEN (x, i) - 1; j >= 0; j--)
move_deaths (XVECEXP (x, i, j), maybe_kill_insn, from_cuid,
to_insn, pnotes);
switch (REG_NOTE_KIND (note))
{
case REG_BR_PROB:
+ case REG_BR_PRED:
case REG_EXEC_COUNT:
/* Doesn't matter much where we put this, as long as it's somewhere.
It is preferable to keep these notes on branches, which is most
place = i3;
break;
+ case REG_VTABLE_REF:
+ /* ??? Should remain with *a particular* memory load. Given the
+ nature of vtable data, the last insn seems relatively safe. */
+ place = i3;
+ break;
+
case REG_NON_LOCAL_GOTO:
if (GET_CODE (i3) == JUMP_INSN)
place = i3;
else if (i2 && GET_CODE (i2) == JUMP_INSN)
place = i2;
else
- abort();
+ abort ();
break;
case REG_EH_REGION:
abort ();
break;
- case REG_EH_RETHROW:
case REG_NORETURN:
+ case REG_SETJMP:
/* These notes must remain with the call. It should not be
possible for both I2 and I3 to be a call. */
if (GET_CODE (i3) == CALL_INSN)
else
place = i2;
}
+
+ /* Don't attach REG_LABEL note to a JUMP_INSN which has
+ JUMP_LABEL already. Instead, decrement LABEL_NUSES. */
+ if (place && GET_CODE (place) == JUMP_INSN && JUMP_LABEL (place))
+ {
+ if (JUMP_LABEL (place) != XEXP (note, 0))
+ abort ();
+ if (GET_CODE (JUMP_LABEL (place)) == CODE_LABEL)
+ LABEL_NUSES (JUMP_LABEL (place))--;
+ place = 0;
+ }
+ if (place2 && GET_CODE (place2) == JUMP_INSN && JUMP_LABEL (place2))
+ {
+ if (JUMP_LABEL (place2) != XEXP (note, 0))
+ abort ();
+ if (GET_CODE (JUMP_LABEL (place2)) == CODE_LABEL)
+ LABEL_NUSES (JUMP_LABEL (place2))--;
+ place2 = 0;
+ }
break;
case REG_NONNEG:
{
unsigned int regno = REGNO (XEXP (note, 0));
+ /* Similarly, if the instruction on which we want to place
+ the note is a noop, we'll need do a global live update
+ after we remove them in delete_noop_moves. */
+ if (noop_move_p (place))
+ {
+ SET_BIT (refresh_blocks, this_basic_block);
+ need_refresh = 1;
+ }
+
if (dead_or_set_p (place, XEXP (note, 0))
|| reg_bitfield_target_p (XEXP (note, 0), PATTERN (place)))
{
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