Explain why we don't use RDPC for sparc PIC register setup.

[pf3gnuchains/gcc-fork.git] / gcc / ChangeLog

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+2012-02-20  David S. Miller  <davem@davemloft.net>
+
+       * config/sparc/sparc.md (load_pcrel_sym<P:mode>): Explain why we
+       don't use the "rd %pc" instruction on v9 for PIC register loads.
+
+2012-02-20  Aldy Hernandez  <aldyh@redhat.com>
+
+       PR middle-end/52141
+       * trans-mem.c (ipa_tm_scan_irr_block): Error out on GIMPLE_ASM's
+       in a transaction safe function.
+
+2012-02-20  Kai Tietz  <ktietz@redhat.com>
+
+       PR target/52238
+       * stor-layout.c (place_field): Handle desired_align for
+       ms-bitfields, too.
+
+2012-02-20  Richard Guenther  <rguenther@suse.de>
+
+       PR tree-optimization/52298
+       * tree-vect-stmts.c (vectorizable_store): Properly use
+       STMT_VINFO_DR_STEP instead of DR_STEP when vectorizing
+       outer loops.
+       (vectorizable_load): Likewise.
+       * tree-vect-data-refs.c (vect_analyze_data_ref_access):
+       Access DR_STEP after ensuring it is not NULL.
+
 2012-02-20  Jakub Jelinek  <jakub@redhat.com>
 
        PR tree-optimization/52286