+2007-07-25 Kaveh R. Ghazi <ghazi@caip.rutgers.edu>
+
+ * cfglayout.c (insn_scope, insn_line): Constify.
+ * emit-rtl.c (const_int_htab_hash, const_int_htab_eq,
+ const_double_htab_hash, const_double_htab_eq,
+ mem_attrs_htab_hash): Likewise.
+ * loop-iv.c (biv_eq): Likewise.
+ * print-rtl.c (print_rtx, print_decl_name, print_mem_expr,
+ print_inline_rtx, debug_rtx, debug_rtx_list, debug_rtx_range,
+ debug_rtx_find, print_rtl, print_rtl_single, print_simple_rtl):
+ Likewise.
+ * rtl-error.c (location_for_asm, diagnostic_for_asm,
+ error_for_asm, warning_for_asm, _fatal_insn,
+ _fatal_insn_not_found): Likewise.
+ * rtl.c (rtx_size, shared_const_p, shallow_copy_rtx_stat,
+ rtx_equal_p, rtl_check_failed_bounds, rtl_check_failed_type1,
+ rtl_check_failed_type2, rtl_check_failed_code1,
+ rtl_check_failed_code2, rtl_check_failed_code_mode,
+ rtvec_check_failed_bounds, rtl_check_failed_flag): Likewise.
+ * rtl.h (rtl_check_failed_bounds, rtl_check_failed_type1,
+ rtl_check_failed_type2, rtl_check_failed_code1,
+ rtl_check_failed_code2, rtl_check_failed_code_mode,
+ rtvec_check_failed_bounds, rtl_check_failed_flag, LABEL_KIND,
+ SET_LABEL_KIND, rhs_regno, subreg_lsb, subreg_regno, subreg_nregs,
+ shared_const_p, rtx_size, shallow_copy_rtx_stat, rtx_equal_p,
+ get_pool_mode, insn_line, insn_file, simplify_replace_rtx,
+ mode_signbit_p, rtx_addr_can_trap_p, nonzero_address_p,
+ rtx_unstable_p, get_integer_term, get_related_value,
+ offset_within_block_p, reg_mentioned_p, count_occurrences,
+ reg_referenced_p, reg_used_between_p, no_labels_between_p,
+ single_set_2, multiple_sets, set_noop_p, refers_to_regno_p,
+ reg_overlap_mentioned_p, dead_or_set_p, dead_or_set_regno_p,
+ find_reg_note, find_regno_note, find_reg_equal_equiv_note,
+ find_constant_src, find_reg_fusage, find_regno_fusage,
+ pure_call_p, remove_note, side_effects_p, volatile_refs_p,
+ volatile_insn_p, may_trap_p, may_trap_after_code_motion_p,
+ may_trap_or_fault_p, inequality_comparisons_p, tablejump_p,
+ computed_jump_p, auto_inc_p, in_expr_list_p,
+ remove_node_from_expr_list, loc_mentioned_in_p,
+ label_is_jump_target_p, reversed_comparison_code_parts,
+ debug_rtx, debug_rtx_list, debug_rtx_range, debug_rtx_find,
+ print_mem_expr, print_rtl, print_simple_rtl, print_rtl_single,
+ print_inline_rtx): Likewise.
+ * rtlanal.c (covers_regno_p, covers_regno_no_parallel_p,
+ computed_jump_p_1, nonzero_bits1, rtx_unstable_p,
+ rtx_addr_can_trap_p_1, rtx_addr_can_trap_p, nonzero_address_p,
+ get_integer_term, get_related_value, offset_within_block_p,
+ count_occurrences, reg_mentioned_p, no_labels_between_p,
+ reg_used_between_p, reg_referenced_p, single_set_2,
+ multiple_sets, set_noop_p, refers_to_regno_p,
+ reg_overlap_mentioned_p, dead_or_set_p,
+ covers_regno_no_parallel_p, covers_regno_p,
+ dead_or_set_regno_p, find_reg_note, find_regno_note,
+ find_reg_equal_equiv_note, find_constant_src, find_reg_fusage,
+ find_regno_fusage, pure_call_p, remove_note, in_expr_list_p,
+ remove_node_from_expr_list, volatile_insn_p, volatile_refs_p,
+ side_effects_p, may_trap_p_1, may_trap_p,
+ may_trap_after_code_motion_p, may_trap_or_fault_p,
+ inequality_comparisons_p, tablejump_p, computed_jump_p_1,
+ computed_jump_p, auto_inc_p, loc_mentioned_in_p, subreg_lsb,
+ subreg_regno, subreg_nregs, label_is_jump_target_p): Likewise.
+ * simplify-rtx.c (neg_const_int, plus_minus_operand_p,
+ mode_signbit_p, simplify_replace_rtx, plus_minus_operand_p):
+ Likewise.
+ * toplev.h (_fatal_insn_not_found, _fatal_insn, error_for_asm,
+ warning_for_asm): Likewise.
+ * tree.h (print_rtl): Likewise.
+ * varasm.c (get_pool_mode): Likewise.
+
+2007-07-25 Kaveh R. Ghazi <ghazi@caip.rutgers.edu>
+
+ * c-lex.c (c_lex_with_flags, lex_string): Constify.
+ * c-ppoutput.c (print_line, pp_dir_change): Likewise.
+ * c-typeck.c (free_all_tagged_tu_seen_up_to): Likewise.
+ * cfg.c (bb_copy_original_hash, bb_copy_original_eq): Likewise.
+ * cfgloop.c (loop_exit_hash, loop_exit_eq): Likewise.
+ * ddg.c (compare_sccs): Likewise.
+ * df-scan.c (df_ref_compare, df_mw_compare): Likewise.
+ * dfp.c (decimal_real_from_string, decimal_to_decnumber,
+ decimal_to_binary, decimal_do_compare, decimal_real_to_decimal,
+ decimal_do_fix_trunc, decimal_real_to_integer,
+ decimal_real_to_integer2, decimal_real_maxval): Likewise.
+ * dse.c (const_group_info_t): New.
+ (invariant_group_base_eq, invariant_group_base_hash): Constify.
+ * dwarf2out.c (const_dw_die_ref): New.
+ (decl_die_table_hash, decl_die_table_eq, file_info_cmp): Constify.
+ * tree-browser.c (TB_parent_eq): Likewise.
+ * unwind-dw2-fde.c (__register_frame_info_bases,
+ __deregister_frame_info_bases, fde_unencoded_compare, fde_split,
+ add_fdes, linear_search_fdes, binary_search_unencoded_fdes):
+ Likewise.
+ * unwind-dw2-fde.h (get_cie, next_fde): Likewise.
+ * unwind-dw2.c (uw_frame_state_for): Likewise.
+ * value-prof.c (histogram_hash, histogram_eq): Likewise.
+ * value-prof.h (const_histogram_value): New.
+
+2007-07-25 Richard Sandiford <richard@codesourcery.com>
+
+ * config/mips/mips.c (machine_function): Add
+ initialized_mips16_gp_pseudo_p.
+ (mips16_gp_pseudo_reg): Do not emit the initialization of
+ mips16_gp_pseudo_rtx when being called from the gimple cost-
+ calculation routines; emit it on the first use outside those
+ routines.
+
+2007-07-25 Kaveh R. Ghazi <ghazi@caip.rutgers.edu>
+
+ * coretypes.h (const_bitmap, const_rtx, const_rtvec, const_tree):
+ New.
+
+ * rtl.h (RTL_CHECK1, RTL_CHECK2, RTL_CHECKC1, RTL_CHECKC2,
+ RTVEC_ELT, XWINT, XCWINT, XCMWINT, XCNMPRV, BLOCK_SYMBOL_CHECK,
+ RTL_FLAG_CHECK1, RTL_FLAG_CHECK2, RTL_FLAG_CHECK3,
+ RTL_FLAG_CHECK4, RTL_FLAG_CHECK5, RTL_FLAG_CHECK6,
+ RTL_FLAG_CHECK7, RTL_FLAG_CHECK8, LABEL_KIND, SET_LABEL_KIND):
+ Preserve const-ness of parameters through use of __typeof(),
+ also constify and tidy.
+
+ * tree.h (TREE_CHECK, TREE_NOT_CHECK, TREE_CHECK2,
+ TREE_NOT_CHECK2, TREE_CHECK3, TREE_NOT_CHECK3, TREE_CHECK4,
+ NON_TREE_CHECK4, TREE_CHECK5, TREE_NOT_CHECK5,
+ CONTAINS_STRUCT_CHECK, TREE_CLASS_CHECK, TREE_RANGE_CHECK,
+ OMP_CLAUSE_SUBCODE_CHECK, OMP_CLAUSE_RANGE_CHECK, EXPR_CHECK,
+ GIMPLE_STMT_CHECK, NON_TYPE_CHECK, TREE_VEC_ELT_CHECK,
+ PHI_NODE_ELT_CHECK, OMP_CLAUSE_ELT_CHECK, TREE_OPERAND_CHECK,
+ TREE_OPERAND_CHECK_CODE, GIMPLE_STMT_OPERAND_CHECK,
+ TREE_RTL_OPERAND_CHECK, TREE_CHAIN, TREE_TYPE): Likewise.
+
+2007-07-25 Julian Brown <julian@codesourcery.com>
+ Mark Shinwell <shinwell@codesourcery.com>
+
+ * config/alpha/alpha.c (alpha_mangle_fundamental_type): Rename to...
+ (alpha_mangle_type): This.
+ (TARGET_MANGLE_FUNDAMENTAL_TYPE): Don't define.
+ (TARGET_MANGLE_TYPE): Define this instead.
+ * config/arm/arm-protos.h (arm_mangle_type): Add prototype.
+ * config/arm/arm.c (TARGET_MANGLE_TYPE): Define target hook.
+ (arm_init_neon_builtins): Fix comment.
+ (arm_mangle_map_entry): New.
+ (arm_mangle_map): New.
+ (arm_mangle_type): New.
+ * config/i386/i386.c (ix86_mangle_fundamental_type): Rename to...
+ (ix86_mangle_type): This. Use TYPE_MAIN_VARIANT and restrict
+ mangled types to VOID_TYPE, BOOLEAN_TYPE, INTEGER_TYPE, REAL_TYPE.
+ (TARGET_MANGLE_FUNDAMENTAL_TYPE): Don't define.
+ (TARGET_MANGLE_TYPE): Define this instead.
+ * config/ia64/ia64.c (ia64_mangle_fundamental_type): Rename to...
+ (ia64_mangle_type): This. Use TYPE_MAIN_VARIANT and restrict
+ mangled types to VOID_TYPE, BOOLEAN_TYPE, INTEGER_TYPE, REAL_TYPE.
+ (TARGET_MANGLE_FUNDAMENTAL_TYPE): Don't define.
+ (TARGET_MANGLE_TYPE): Define this instead.
+ * config/rs6000/rs6000.c (rs6000_mangle_fundamental_type): Rename
+ to...
+ (rs6000_mangle_type): This. Use TYPE_MAIN_VARIANT.
+ (TARGET_MANGLE_FUNDAMENTAL_TYPE): Don't define.
+ (TARGET_MANGLE_TYPE): Define this instead.
+ * config/s390/s390.c (s390_mangle_fundamental_type): Rename to...
+ (s390_mangle_type): This.
+ (TARGET_MANGLE_FUNDAMENTAL_TYPE): Don't define.
+ (TARGET_MANGLE_TYPE): Define this instead.
+ * config/sparc/sparc.c (sparc_mangle_fundamental_type): Rename to...
+ (sparc_mangle_type): This.
+ (TARGET_MANGLE_FUNDAMENTAL_TYPE): Don't define.
+ (TARGET_MANGLE_TYPE): Define this instead.
+ * cp/mangle.c (write_type): Call mangle_type target hook on all
+ types before mangling. Use original type, not main variant, as
+ argument.
+ * target-def.h (TARGET_MANGLE_FUNDAMENTAL_TYPE): Rename hook to...
+ (TARGET_MANGLE_TYPE): This.
+ * target.h (gcc_target): Rename mangle_fundamental_type to
+ mangle_type.
+ * doc/tm.texi (TARGET_MANGLE_FUNDAMENTAL_TYPE): Rename section to...
+ (TARGET_MANGLE_TYPE): This. Note slightly different semantics.
+
+2007-07-25 Julian Brown <julian@codesourcery.com>
+ Paul Brook <paul@codesourcery.com>
+ Joseph Myers <joseph@codesourcery.com>
+ Mark Shinwell <shinwell@codesourcery.com>
+
+ * Makefile.in (TEXI_GCC_FILES): Add arm-neon-intrinsics.texi.
+ * config.gcc (arm*-*-*): Add arm_neon.h to extra headers.
+ (with_fpu): Allow --with-fpu=neon.
+ * config/arm/aof.h (ADDITIONAL_REGISTER_NAMES): Add Q0-Q15.
+ * config/arm/aout.h (ADDITIONAL_REGISTER_NAMES): Add Q0-Q15.
+ * config/arm/arm-modes.def (EI, OI, CI, XI): New modes.
+ * config/arm/arm-protos.h (neon_immediate_valid_for_move)
+ (neon_immediate_valid_for_logic, neon_output_logic_immediate)
+ (neon_pairwise_reduce, neon_expand_vector_init, neon_reinterpret)
+ (neon_emit_pair_result_insn, neon_disambiguate_copy)
+ (neon_vector_mem_operand, neon_struct_mem_operand, output_move_quad)
+ (output_move_neon): Add prototypes.
+ * config/arm/arm.c (FL_NEON): New flag for NEON processor capability.
+ (all_fpus): Add FPUTYPE_NEON.
+ (fp_model_for_fpu): Add NEON field.
+ (arm_return_in_memory): Return vectors <= 16 bytes in ARM registers.
+ (arm_arg_partial_bytes): Allow NEON vectors to be passed partially
+ in registers.
+ (arm_legitimate_address_p): Don't support fancy addressing for NEON
+ structure moves.
+ (thumb2_legitimate_address_p): Likewise.
+ (neon_valid_immediate): Recognize and prepare constants suitable for
+ NEON instructions.
+ (neon_immediate_valid_for_move): New function. Recognize and prepare
+ immediates for NEON move instructions.
+ (neon_immediate_valid_for_logic): New function. Recognize and
+ prepare immediates for NEON logic instructions.
+ (neon_output_logic_immediate): New function. Create asm string
+ suitable for outputting immediate logic instructions.
+ (neon_pairwise_reduce): New function. Implement reduction using
+ pairwise operations.
+ (neon_expand_vector_init): New function. Expand a (possibly
+ non-constant) vector initialization.
+ (neon_vector_mem_operand): New function. Memory operands supported
+ for quad-word loads/stores to/from ARM or NEON registers. Don't
+ allow base+offset addressing for core regs.
+ (neon_struct_mem_operand): New function. Valid mems for NEON
+ structure moves.
+ (coproc_secondary_reload_class): Enable NEON registers to be loaded
+ from neon_vector_mem_operand addresses without a secondary register.
+ (add_minipool_forward_ref): Handle >8-byte minipool entries.
+ (add_minipool_backward_ref): Likewise.
+ (dump_minipool): Likewise.
+ (push_minipool_fix): Likewise.
+ (output_move_quad): New function. Output quad-word moves, loads and
+ stores using ARM registers.
+ (output_move_vfp): Add support for vectors in VFP (NEON) D
+ registers.
+ (output_move_neon): Output a NEON load/store to/from a quadword
+ register.
+ (arm_print_operand): Implement new codes:
+ - 'c' for unadorned integers (without a # sign).
+ - 'J', 'K' for reg+2/reg+3, reg+3/reg+2 in little/big-endian
+ mode.
+ - 'e', 'f' for the low and high D parts of a NEON Q register.
+ - 'q' outputs a NEON Q register.
+ - 'h' outputs ranges of D registers for VLDM/VSTM etc.
+ - 'T' prints NEON opcode features from a coded bitmask.
+ - 'F' is similar to T, but signed/unsigned codes both print as
+ 'i'.
+ - 't' is similar to T, but 'u' is printed instead of 'p'.
+ - 'O' prints 'r' if NEON instruction should perform rounding (as
+ specified by bitmask), else prints nothing.
+ - '#' is a punctuation character to stop operand numbers from
+ running together with following digits in the assembler
+ strings for instructions (when using mode attributes).
+ (arm_assemble_integer): Handle extra NEON vector modes. Permute
+ constant vectors in big-endian mode, where necessary.
+ (arm_hard_regno_mode_ok): Allow vectors in VFP/NEON registers.
+ Handle EI, OI, CI, XI modes.
+ (ashlv4hi3, ashlv2si3, lshrv4hi3, lshrv2si3, ashrv4hi3)
+ (ashrv2si3): Rename IWMMXT2_BUILTINs to...
+ (ashlv4hi3_iwmmxt, ashlv2si3_iwmmxt, lshrv4hi3_iwmmxt)
+ (lshrv2si3_iwmmxt, ashrv4hi3_iwmmxt, ashrv2si3_iwmmxt): New names.
+ (neon_builtin_type_bits): Add enumeration, one bit for each vector
+ type.
+ (v8qi_UP, v4hi_UP, v2si_UP, v2sf_UP, di_UP, v16qi_UP, v8hi_UP)
+ (v4si_UP, v4sf_UP, v2di_UP, ti_UP, ei_UP, oi_UP, UP): Define macros
+ to turn v8qi, etc. into bits defined above.
+ (neon_itype): New enumeration. Classifications of NEON builtins.
+ (neon_builtin_datum): Define struct. Contains information about
+ a single builtin (with multiple modes).
+ (CF): Define helper macro for...
+ (VAR1...VAR10): Define builtins with a type, name and 1-10 different
+ modes.
+ (neon_builtin_data): New array. Define information about builtins
+ for use during initialization/expansion.
+ (arm_init_neon_builtins): New function.
+ (arm_init_builtins): Call arm_init_neon_builtins if TARGET_NEON is
+ true.
+ (neon_builtin_compare): New function.
+ (locate_neon_builtin_icode): New function. Find an insn code for a
+ builtin given a function code for that builtin. Also return type of
+ builtin (NEON_BINOP, NEON_UNOP etc.).
+ (builtin_arg): New enumeration. Types of arguments for builtins.
+ (arm_expand_neon_args): New function. Expand a generic NEON builtin.
+ Takes a variable argument list of builtin_arg types, terminated by
+ NEON_ARG_STOP.
+ (arm_expand_neon_builtin): New function. Expand a NEON builtin.
+ (neon_reinterpret): New function. Expand NEON reinterpret intrinsic.
+ (neon_emit_pair_result_insn): New function. Support returning pairs
+ of vectors via a pointer.
+ (neon_disambiguate_copy): New function. Set up operands for a
+ multi-word copy such that registers do not get clobbered.
+ (arm_expand_builtin): Call arm_expand_neon_builtin if fcode >=
+ ARM_BUILTIN_NEON_BASE.
+ (arm_file_start): Set float-abi attribute for NEON.
+ (arm_vector_mode_supported_p): Enable NEON vector modes.
+ (arm_mangle_map_entry): New.
+ (arm_mangle_map): New.
+ (arm_mangle_vector_type): New.
+ * config/arm/arm.h (TARGET_CPU_CPP_BUILTINS): Define __ARM_NEON__
+ when appropriate.
+ (TARGET_NEON): New macro. Target supports NEON.
+ (fputype): Add FPUTYPE_NEON.
+ (UNITS_PER_SIMD_WORD): Define. Allow quad-word registers to be used
+ for vectorization based on command-line arg.
+ (NEON_REGNO_OK_FOR_NREGS): Define.
+ (VALID_NEON_DREG_MODE, VALID_NEON_QREG_MODE)
+ (VALID_NEON_STRUCT_MODE): Define.
+ (PRINT_OPERAND_PUNCT_VALID_P): '#' is valid punctuation.
+ (arm_builtins): Add ARM_BUILTIN_NEON_BASE.
+ * config/arm/arm.md (VUNSPEC_POOL_16): Insert constant for unspec.
+ (consttable_16): Add pattern for outputting 16-byte minipool
+ entries.
+ (movv2si, movv4hi, movv8qi): Remove blank expanders (redefined in
+ vec-common.md).
+ (vec-common.md, neon.md): Include md files.
+ * config/arm/arm.opt (mvectorize-with-neon-quad): Add option.
+ * config/arm/constraints.md (constraint "Dn", "Dl", "DL"): Define.
+ (memory_constraint "Ut", "Un", "Us"): Define.
+ * config/arm/iwmmxt.md (VMMX, VSHFT): New mode macros.
+ (MMX_char): New mode attribute.
+ (addv8qi3, addv4hi3, addv2si3): Remove. Replace with...
+ (*add<mode>3_iwmmxt): New insn pattern.
+ (subv8qi3, subv4hi3, subv2si3): Remove. Replace with...
+ (*sub<mode>3_iwmmxt): New insn pattern.
+ (mulv4hi3): Rename to...
+ (*mulv4hi3_iwmmxt): This.
+ (smaxv8qi3, smaxv4hi3, smaxv2si3, umaxv8qi3, umaxv4hi3)
+ (umaxv2si3, sminv8qi3, sminv4hi3, sminv2si3, uminv8qi3)
+ (uminv4hi3, uminv2si3): Remove. Replace with...
+ (*smax<mode>3_iwmmxt, *umax<mode>3_iwmmxt, *smin<mode>3_iwmmxt)
+ (*umin<mode>3_iwmmxt): These.
+ (ashrv4hi3, ashrv2si3, ashrdi3_iwmmxt): Replace with...
+ (ashr<mode>3_iwmmxt): This new pattern.
+ (lshrv4hi3, lshrv2si3, lshrdi3_iwmmxt): Replace with...
+ (lshr<mode>3_iwmmxt): This new pattern.
+ (ashlv4hi3, ashlv2si3, ashldi3_iwmmxt): Replace with...
+ (ashl<mode>3_iwmmxt): This new pattern.
+ * config/arm/neon-docgen.ml: New file. Generate documentation for
+ intrinsics.
+ * config/arm/neon-gen.ml: New file. Generate arm_neon.h header.
+ * config/arm/arm_neon.h: New (autogenerated).
+ * config/arm/neon-testgen.ml: New file. Generate NEON tests
+ automatically.
+ * config/arm/neon.md: New file. Define NEON instructions.
+ * config/arm/neon.ml: New file. Abstract description of NEON
+ instructions, used to generate arm_neon.h header, documentation and
+ tests.
+ * config/arm/t-arm (MD_INCLUDES): Add vec-common.md, neon.md.
+ * vec-common.md: New file. Shared parts for iWMMXt and NEON vector
+ support.
+ * doc/extend.texi (ARM Built-in Functions): Rename and remove
+ extraneous comma.
+ (ARM NEON Intrinsics): New subsection.
+ * doc/arm-neon-intrinsics.texi: New (autogenerated).
+
+2007-07-25 Danny Smith <dannysmith@users.sourceforge.net>
+
+ * config/i386/i386-protos.h (i386_pe_asm_file_end): Remove
+ prototype.
+
+2007-07-24 Jan Hubicka <jh@suse.cz>
+
+ * regclass.c (move_table): New type.
+ (move_cost, may_move_in_cost, may_move_out_cost): Use it.
+ (init_move_cost): Break out from ...
+ (init_reg_sets_1): ... here; simplify computation of
+ have_regs-of_mode and contains_reg_of_mode.
+ (record_reg_classes): Unswitch internal loops.
+ (copy_cost): Trigger lazy initialization of move cost
+ (record_address_regs): Likewise.
+
+2007-07-24 Daniel Berlin <dberlin@dberlin.org>
+
+ * config/darwin.c (darwin_override_options): Don't force on
+ flag_var_tracking_uninit when no debug info is requested.
+
+2007-07-25 Zdenek Dvorak <dvorakz@suse.cz>
+
+ * cfgloop.c (init_loops_structure): New function.
+ (flow_loops_find): Create root of the loop tree unconditionally.
+
+2007-07-24 Daniel Jacobowitz <dan@codesourcery.com>
+
+ * tree-ssa-ccp.c (fold_const_aggregate_ref): Use fold_convert.
+
+2007-07-24 Jan Hubicka <jh@suse.cz>
+
+ * caller-save.c: Include ggc.h, gt-caller-save.h
+ (reg_save_code, reg_restore_code): Rename to ...
+ (cached_reg_save_code, cached_reg_restore_code): ... those.
+ (savepat, restpat, test_reg, test_mem, saveinsn, restinsn): New.
+ (reg_save_code, reg_restore_code): New functions.
+ (init_caller_save): Do not intialize
+ reg_save_code/reg_restore_code tables.
+ * Makeifle.in: (gt-caller-save.h): New.
+
+2007-07-24 Andreas Krebbel <krebbel1@de.ibm.com>
+
+ * tree-ssa-ifcombine.c (ifcombine_ifandif): Use a ONE operand
+ with the mode of the original operand instead of
+ integer_one_node.
+
+2007-07-23 Jan Hubicka <jH@suse.cz>
+
+ * i386.c (ix86_secondary_memory_needed): Break out to...
+ (inline_secondary_memory_needed): ... here.
+ (ix86_memory_move_cost): Break out to ...
+ (inline_memory_move_cost): ... here; add support for IN value of 2 for
+ maximum of input and output; fix handling of Q_REGS on 64bit.
+ (ix86_secondary_memory_needed): Microoptimize.
+
+2007-07-23 Sebastian Pop <sebpop@gmail.com>
+
+ * tree-data-ref.c (find_vertex_for_stmt, create_rdg_edge_for_ddr,
+ create_rdg_edges_for_scalar, create_rdg_edges, create_rdg_vertices,
+ stmts_from_loop, known_dependences_p, build_rdg): New.
+ * tree-data-ref.h: Depends on graphds.h.
+ (rdg_vertex, RDGV_STMT, rdg_dep_type, rdg_edge, RDGE_TYPE): New.
+ (build_rdg): Declared.
+ * Makefile.in (TREE_DATA_REF_H): Depends on graphds.h.
+
+2007-07-23 Daniel Berlin <dberlin@dberlin.org>
+
+ * tree-ssa-propagate.c (valid_gimple_expression_p): Match up with
+ ccp_min_invariant.
+
+2007-07-23 Peter Bergner <bergner@vnet.ibm.com>
+ Jakub Jelinek <jakub@redhat.com>
+
+ PR middle-end/PR28690
+ * optabs.c (expand_binop): (emit_cmp_and_jump_insns): Allow EQ compares.
+ * rtlanal.c (commutative_operand_precedence): Prefer both REG_POINTER
+ and MEM_POINTER operands over REG and MEM operands.
+ (swap_commutative_operands_p): Change return value to bool.
+ * rtl.h: Update the corresponding prototype.
+ * tree-ssa-address.c (gen_addr_rtx): Use simplify_gen_binary
+ instead of gen_rtx_PLUS.
+ * simplify-rtx.c (simplify_plus_minus_op_data_cmp): Change return
+ value to bool. Change function arguments to rtx's and update code
+ to match.
+ (simplify_plus_minus): Update the simplify_plus_minus_op_data_cmp
+ calls to match the new declaration.
+ * simplify-rtx.c (simplify_associative_operation): Don't
+ reorder simplify_binary_operation arguments.
+
+2007-07-23 Richard Sandiford <richard@codesourcery.com>
+
+ * config/mips/mips.c (override_options): Use mips_costs to derive
+ the default branch cost.
+ * config/mips/mips.h (BRANCH_COST): Use mips_branch_cost rather
+ than mips_costs.
+ * config/mips/mips.opt (mbranch-cost=): New option.
+ * doc/invoke.texi (-mbranch-cost): Document new MIPS option.
+
+2007-07-23 Richard Sandiford <richard@codesourcery.com>
+
+ * config/mips/mips.h (GR_REG_CLASS_P, COP_REG_CLASS_P): Delete.
+ (SECONDARY_MEMORY_NEEDED): Delete commented-out definition.
+ * config/mips/mips.c (mips_register_move_cost): Use reg_class_subset_p
+ instead of GR_REG_CLASS_P and COP_REG_CLASS_P.
+
+2007-07-23 Richard Sandiford <richard@codesourcery.com>
+
+ * config/mips/constraints.md (ks): New constraint.
+ * config/mips/mips.md (*add<mode>3_sp1, *add<mode>3_sp2): Fold into...
+ (*add<mode>3_mips16): ...here.
+
+2007-07-21 Uros Bizjak <ubizjak@gmail.com>
+
+ * optabs.h (enum optab_index): Add new OTI_signbit.
+ (signbit_optab): Define corresponding macro.
+ (enum insn_code signbit_optab[]): Remove array.
+ * optabs.c (init_optabs): Initialize signbit_optab using init_optab.
+ (expand_copysign_absneg): If back end provides signbit insn, use it
+ instead of bit operations on floating point argument.
+ * builtins.c (enum insn_code signbit_optab[]): Remove array.
+ (expand_builtin_signbit): Check signbit_optab->handlers[].insn_code for
+ availability of signbit insn.
+
+ * config/i386/i386.md (signbit<mode>2): New insn pattern to implement
+ signbitf, signbit and signbitl built-ins as inline x87 intrinsics when
+ SSE mode is not active.
+ (isinf<mode>2): Disable for mfpmath=sse,387.
+
+2007-07-22 Ben Elliston <bje@au.ibm.com>
+
+ * regclass.c (invalid_mode_change_p): Attach ATTRIBUTE_UNUSED to
+ `class' parameter.
+ * struct-equiv.c (note_local_live): Likewise for `y_regno'.
+
+2007-07-20 Richard Guenther <rguenther@suse.de>
+
+ * tree-cfg.c (verify_expr): COND_EXPRs can have any
+ integral typed condition.
+ * tree-ssa.c (useless_type_conversion_p): Do not preserve
+ booleanness. Only preserve conversions from a non-base
+ type to a base type, not in general between types with
+ different TYPE_MIN_VALUE or TYPE_MAX_VALUE.
+ * tree.def (COND_EXPR): Document that the condition
+ can be of any integral type.
+
+2007-07-20 Nigel Stephens <nigel@mips.com>
+ Richard Sandiford <richard@codesourcery.com>
+
+ * config/mips/mips.h (mips_dwarf_regno): Declare.
+ (DBX_REGISTER_NUMBER): Remove redundant brackets.
+ (HI_REGNUM, LO_REGNUM): Define in an endian-dependent way.
+ (AC1HI_REGNUM, AC1LO_REGNUM, AC2HI_REGNUM, AC2LO_REGNUM)
+ (AC3HI_REGNUM, AC3LO_REGNUM, ACC_HI_REG_P): Delete.
+ (reg_class): Rename HI_REG to MD0_REG and LO_REG to MD1_REG.
+ (REG_CLASS_NAMES): Update accordingly.
+ * config/mips/mips.c (mips_dwarf_regno): New array.
+ (mips_regno_to_class): Rename HI_REG to MD0_REG and LO_REG to MD1_REG.
+ (mips_subword): Remove special handling for accumulator registers.
+ (override_options): Initiailize mips_dwarf_regno. Remove use
+ of ACC_HI_REG_P.
+ (mips_swap_registers): New function.
+ (mips_conditional_register_usage): Swap accumulator registers
+ around if TARGET_LITTLE_ENDIAN.
+ (mips_cannot_change_mode_class): Remove special treatment of ACC_REGS.
+ * config/mips/constraints.md (h, l): Use the endianness to choose
+ between MD0_REG and MD1_REG.
+ * config/mips/mips.md (*mfhilo_<mode>_macc): Use a fixed-string,
+ alternative-dependent template.
+
+2007-07-20 Richard Sandiford <richard@codesourcery.com>
+
+ * config/arm/arm.md (movsi): Use can_create_pseudo_p instead of
+ no_new_pseudos.
+
+2007-07-20 Zdenek Dvorak <dvorakz@suse.cz>
+
+ * function.c (thread_prologue_and_epilogue_insns): Fix exit
+ predecessor fallthru flags.
+
+2007-07-20 Zdenek Dvorak <dvorakz@suse.cz>
+
+ * tree-ssa-loop-niter.c (assert_loop_rolls_lt): Convert the operands
+ of compare to the same type.
+ * cfgloopmanip.c (add_loop): Update information about loop exits.
+ (loop_version): Remove the innermost loop requirement.
+ * tree-ssa-loop-manip.c (determine_exit_conditions): Convert bounds
+ to sizetype for pointers.
+
+2007-07-18 H.J. Lu <hongjiu.lu@intel.com>
+
+ * Makefile.in (D32PBIT_FUNCS): Add _sd_to_tf and _tf_to_sd.
+ (D64PBIT_FUNCS): Add _dd_to_tf and _tf_to_dd.
+ (D128PBIT_FUNCS): Add _td_to_tf and _tf_to_td.
+
+ * config/dfp-bit.c: Empty for TFmode conversions.
+
+2007-07-18 Caroline Tice <ctice@apple.com>
+
+ * var-tracking.c (find_src_status): Check for COND_EXEC insns
+ and handle them correctly; check that src is not NULL before
+ trying to use it.
+ (find_src_set_src): Likewise.
+
+2007-07-18 Bob Wilson <bob.wilson@acm.org>
+
+ * config/xtensa/xtensa.c (xtensa_expand_mask_and_shift): New.
+ (struct alignment_context, init_alignment_context): New.
+ (xtensa_expand_compare_and_swap, xtensa_expand_atomic): New.
+ * config/xtensa/xtensa.h (XCHAL_HAVE_RELEASE_SYNC): Add default.
+ (XCHAL_HAVE_S32C1I): Likewise.
+ (TARGET_RELEASE_SYNC, TARGET_S32C1I): New.
+ * config/xtensa/xtensa.md (UNSPECV_MEMW): New constant.
+ (UNSPECV_S32RI, UNSPECV_S32C1I): Likewise.
+ (ATOMIC, HQI): New macros.
+ (memory_barrier, *memory_barrier): New.
+ (sync_lock_releasesi): New.
+ (sync_compare_and_swapsi, sync_compare_and_swap<mode>): New.
+ (sync_lock_test_and_set<mode>): New.
+ (sync_<atomic><mode>): New.
+ (sync_old_<atomic><mode>, sync_new_<atomic><mode>): New.
+ * config/xtensa/xtensa-protos.h (xtensa_expand_compare_and_swap): New.
+ (xtensa_expand_atomic): New.
+
+2007-07-18 Kaveh R. Ghazi <ghazi@caip.rutgers.edu>
+
+ PR target/30652
+
+ * builtins.c (expand_builtin_interclass_mathfn): Provide a generic
+ transformation for builtin ISNORMAL.
+ (expand_builtin): Handle BUILT_IN_ISNORMAL.
+ * builtins.def (BUILT_IN_ISNORMAL): New.
+ * doc/extend.texi: Document isnormal.
+
+2007-07-18 Kaveh R. Ghazi <ghazi@caip.rutgers.edu>
+
+ PR target/30652
+
+ * builtins.c (expand_builtin_interclass_mathfn): Allow for missing
+ optabs infrastructure. Provide generic implementation for
+ FINITE/ISFINITE.
+ (expand_builtin): Handle FINITE/ISFINITE.
+ (fold_builtin_classify): Make ISFINITE canonical instead of FINITE.
+ (fold_builtin_1): Likewise.
+
+ * builtins.def (BUILT_IN_ISFINITE): New.
+
+ * doc/extend.texi: Document isfinite.
+
+2007-07-18 Kaveh R. Ghazi <ghazi@caip.rutgers.edu>
+
+ PR target/30652
+ PR middle-end/20558
+
+ * builtins.c (expand_builtin_interclass_mathfn): Provide a
+ generic fallback for isinf.
+ * c-cppbuiltin.c (builtin_define_float_constants): Move FP max
+ calculation code ...
+ * real.c (get_max_float): ... to here.
+ * real.h (get_max_float): New.
+
+2007-07-18 Kaveh R. Ghazi <ghazi@caip.rutgers.edu>
+
+ PR middle-end/32668
+
+ * builtin-attrs.def (ATTR_TYPEGENERIC,
+ ATTR_CONST_NOTHROW_TYPEGENERIC): New.
+
+ * builtins.def (BUILT_IN_ISINF, BUILT_IN_ISNAN,
+ BUILT_IN_ISGREATER, BUILT_IN_ISGREATEREQUAL, BUILT_IN_ISLESS,
+ BUILT_IN_ISLESSEQUAL, BUILT_IN_ISLESSGREATER,
+ BUILT_IN_ISUNORDERED): Use ATTR_CONST_NOTHROW_TYPEGENERIC.
+
+ * c-common.c (handle_type_generic_attribute): New.
+ (c_common_attribute_table): Add "type generic".
+
+ * c-typeck.c (convert_arguments): Handle "type generic" functions.
+
+2007-07-18 Daniel Berlin <dberlin@dberlin.org>
+
+ * tree-ssa-sccvn.c (try_to_simplify): Use valid_gimple_expression
+ * tree-ssa-propagate (valid_gimple_expression): Handle ADDR_EXPR
+ properly.
+
+2007-07-18 Rask Ingemann Lambertsen <rask@sygehus.dk>
+
+ PR target/32808
+ * config/cris/cris.c (cris_print_index): Don't use XEXP before
+ checking that the operand is an expression.
+
+2007-07-19 Christoph von Wittich <Christoph_vW@reactos.org>
+ Danny Smith <dannysmith@users.sourceforge.net>
+
+ PR/other 30335
+ * config/i386/host-mingw32.c (mingw32_gt_pch_use_address): Put
+ file mapping object in local namespace if Windows version later
+ than NT4
+
+2007-07-18 Richard Sandiford <richard@codesourcery.com>
+
+ * config/arm/arm-protos.h (arm_cannot_force_const_mem): Declare.
+ * config/arm/arm.c (TARGET_CANNOT_FORCE_CONST_MEM): Redefine to
+ arm_cannot_force_const_mem.
+ (arm_cannot_force_const_mem): New function.
+ * config/arm/arm.h (ARM_OFFSETS_MUST_BE_WITHIN_SECTIONS_P): New macro.
+ (LEGITIMATE_CONSTANT_P): Test arm_cannot_force_const_mem instead
+ of arm_tls_referenced_p.
+ * config/arm/arm.md (movsi): Split out-of-section constants when
+ ARM_OFFSETS_MUST_BE_WITHIN_SECTIONS_P.
+ * config/arm/vxworks.h (ARM_OFFSETS_MUST_BE_WITHIN_SECTIONS_P): Define.
+
+2007-07-18 Richard Sandiford <richard@codesourcery.com>
+
+ * config/mips/mips.md (clear_cache): Treat the size argument as Pmode.
+
+2007-07-18 Richard Sandiford <richard@codesourcery.com>
+
+ * config/mips/mips.md (*extendqihi2): Convert the destination
+ to SImode.
+
+2007-07-17 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
+
+ * config/pa/fptr.c: Update license header.
+ * config/pa/milli64.S: Likewise.
+
+2007-07-17 Nick Clifton <nickc@redhat.com>
+
+ * COPYING_v3: New file. Contains version 3 of the GNU General
+ Public License.
+ * COPYING.LIB_v3: New file. Contains version 3 of the GNU
+ Lesser General Public License.
+ * doc/include/gpl_v3.texi: New file. Contains version 3 of
+ the GNU General Public License.
+
+2007-07-17 Zdenek Dvorak <dvorakz@suse.cz>
+
+ PR rtl-optimization/32773
+ * cfglayout.c (force_one_exit_fallthru): New function.
+ (cfg_layout_finalize): Use it.
+
+2007-07-16 Richard Guenther <rguenther@suse.de>
+ Uros Bizjak <ubizjak@gmail.com>
+
+ * tree-if-conv.c (find_phi_replacement_condition): Unshare "*cond"
+ before forcing it to gimple operand.
+
+2007-07-16 Sandra Loosemore <sandra@codesourcery.com>
+ David Ung <davidu@mips.com>
+
+ * config/mips/mips.h (TUNE_24K): Define.
+ (TUNE_MACC_CHAINS): Add TUNE_24K.
+ * config/mips/mips.md: (*mul_acc_si, *mul_sub_si): Change type to
+ imadd.
+ * config/mips/74k.md (r74k_int_mult): Split madd/msub to ..
+ (r74k_int_madd): .. this new reservation.
+ (define_bypass): Fixed bypasses for r74k_int_madd to use
+ mips_linked_madd_p.
+ * config/mips/24k.md (define_bypass): Define new
+ r24k_int_mul3->r24k_int_madd bypass using mips_linked_madd_p.
+
+2007-07-16 Sandra Loosemore <sandra@codesourcery.com>
+ Nigel Stephens <nigel@mips.com>
+
+ * config/mips/mips.md: Include 20kc.md.
+ * config/mips/20kc.md: New file.
+ * config/mips/mips.c (mips_rtx_cost_data): Fill in 20Kc costs.
+ (mips_adjust_cost): Tweak for 20Kc.
+ (mips_issue_rate): Likewise.
+ * config/mips/mips.h (TUNE_20KC): Define.
+
+2007-07-16 David Edelsohn <edelsohn@gnu.og>
+
+ * config/rs6000/rs6000.c (struct processor_cost): Add
+ cache_line_size, l1_cache_lines, and simultaneous_prefetches
+ fields.
+ (*_cost): Add cache information.
+ (rs6000_override_options): Set cache parameters.
+
+2007-07-16 Rainer Orth <ro@TechFak.Uni-Bielefeld.DE>
+
+ PR bootstrap/3456
+ * config.gcc (mips-sgi-irix[56]*): Enable pthread support.
+ * doc/install.texi (mips-sgi-irix6): pthread support works now.
+
+2007-07-16 Paul Brook <paul@codesourcery.com>
+
+ PR target/32753
+ * config/arm/cirrus.md (cirrus_arm_movsi_insn): Remove dead insn.
+ (cirrus_thumb2_movsi_insn): Ditto.
+
+2007-07-15 Geoffrey Keating <geoffk@apple.com>
+
+ * config/rs6000/darwin-fallback.c (interpret_libc): Change
+ CR2_REGNO to R_CR2.
+
+2007-07-15 Andrew Haley <aph@redhat.com>
+
+ * unwind-sjlj.c (_Unwind_GetIPInfo): Check for context->fc != NULL
+ before looking in the context.
+
+2007-07-15 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
+
+ PR middle-end/32398
+ PR middle-end/32769
+ * pa-protos.h (pa_eh_return_handler_rtx): Declare.
+ * pa.c (pa_extra_live_on_entry, rp_saved): Declare.
+ (TARGET_EXTRA_LIVE_ON_ENTRY): Define.
+ (pa_output_function_prologue): Use rp_saved and current_function_is_leaf
+ to generate .CALLINFO statement.
+ (hppa_expand_prologue): Set rp_saved.
+ (hppa_expand_epilogue): Use rp_saved.
+ (pa_extra_live_on_entry, pa_eh_return_handler_rtx): New functions.
+ * pa.h (EH_RETURN_HANDLER_RTX): Use pa_eh_return_handler_rtx.
+
+2007-07-14 Dirk Mueller <dmueller@suse.de>
+
+ * omega.c (coalesce): Fix memory leak on early exit.
+ * matrix-reorg.c (check_allocation_function): Likewise.
+ * tree-vect-transform.c (vect_get_new_vect_var): free result
+ of concat().
+ * bb-reorder.c (find_rarely_executed_basic_blocks_and_crossing_edges):
+ pass pointer to edge vector
+ (partition_hot_cold_basic_blocks): Fix memory leak.
+ * collect2.c (prefix_from_string): Free temporary storage.
+ * reload1.c (fixup_abnormal_edges): Free sbitmap.
+
+2007-07-14 Kaz Kojima <kkojima@gcc.gnu.org>
+
+ * config/sh/sh.h (DO_GLOBAL_CTORS_BODY): Add void to prototype.
+ (DO_GLOBAL_DTORS_BODY): Likewise.
+
+2007-07-14 Sandra Loosemore <sandra@codesourcery.com>
+ Nigel Stephens <nigel@mips.com>
+
+ * config/mips/mips.c (mips_classify_symbol): Don't return
+ SYMBOL_SMALL_DATA for constant pool addresses if
+ TARGET_EMBEDDED_DATA is true.
+
+2007-07-14 Uros Bizjak <ubizjak@gmail.com>
+
+ * config/i386/i386.c (init_mmx_sse_builtins): Define all builtins
+ except __builtin_ia32_emms, __builtin_ia32_ldmxcsr,
+ __builtin_ia32_stmxcsr, __builtin_ia32_maskmovq, __builtin_ia32_loadups,
+ __builtin_ia32_storeups, __builtin_ia32_loadhps, __builtin_ia32_loadlps,
+ __builtin_ia32_storehps, __builtin_ia32_storelps,
+ __builtin_ia32_movntps, __builtin_ia32_movntq, __builtin_ia32_sfence,
+ __builtin_ia32_femms, __builtin_ia32_maskmovdqu, __builtin_ia32_loadupd,
+ __builtin_ia32_storeupd, __builtin_ia32_loadhpd, __builtin_ia32_loadlpd,
+ __builtin_ia32_movnti, __builtin_ia32_movntpd, __builtin_ia32_movntdq,
+ __builtin_ia32_clflush, __builtin_ia32_lfence, __builtin_ia32_mfence,
+ __builtin_ia32_loaddqu, __builtin_ia32_storedqu, __builtin_ia32_monitor,
+ __builtin_ia32_mwait, __builtin_ia32_lddqu, __builtin_ia32_movntdqa,
+ __builtin_ia32_movntsd and __builtin_ia32_movntss as const builtins
+ using def_builtin_const.
+
+2007-07-14 Eric Botcazou <ebotcazou@adacore.com>
+
+ PR tree-optimization/32705
+ * tree-ssa-sccvn.c (set_ssa_val_to): Accept VN_TOP as value number.
+ (simplify_binary_expression): Use SSA_VAL consistently.
+
+2007-07-13 David Edelsohn <edelsohn@gnu.org>
+
+ * config/rs6000/spe.md (SPE_ACC_REGNO): Delete definition.
+ (SPEFSCR_REGNO): Delete definition.
+ * config/rs6000/rs6000.c: LINK_REGISTER_REGNUM -> LR_REGNO.
+ COUNT_REGISTER_REGNUM -> CTR_REGNO.
+ * config/rs6000/rs6000.h: Do not define *_REGNO.
+ LINK_REGISTER_REGNUM -> LR_REGNO.
+ COUNT_REGISTER_REGNUM -> CTR_REGNO.
+ * config/rs6000/predicates.md: LINK_REGISTER_REGNUM -> LR_REGNO.
+ COUNT_REGISTER_REGNUM -> CTR_REGNO.
+ * config/rs6000/linux-unwind.h: Define R_LR, R_CR2, R_VR0,
+ R_VRSAVE, R_VSCR. Use them.
+ * config/rs6000/darwin-fallback.c: Define R_LR, R_CTR, R_CR2,
+ R_XER, R_VR0, R_VRSAVE, R_VSCR, R_SPEFSCR. Use them.
+ * config/rs6000/rs6000.md: Define REGNO constants. Use them.
+ * config/rs6000/aix.h: Define R_LR. Use it.
+
+2007-07-13 Caroline Tice <ctice@apple.com>
+
+ * toplev.c (process_options): Turn flag_var_tracking_uninit off when
+ flag_var_tracking is explicitly turned off (i.e. when variable
+ tracking is not feasible); otherwise, turn flag_var_tracking on when
+ flag_var_tracking_uninit is on.
+ * rtl.def (VAR_LOCATION): Add a new integer subfield to VAR_LOCATION
+ note definitions, to allow recording of initialization status in the
+ notes.
+ * dwarf2out.c (dwarf_stack_op_name): Add case for DW_OP_GNU_uninit.
+ (add_var_loc_to_decl): Add comparison of NOTE_VAR_LOCATION_STATUS to
+ determine if two note locations are equal.
+ (output_loc_list): Don't output list entries whose start & end labels
+ are the same.
+ (reg_loc_descriptor): Add parameter for initialization status; pass it
+ to other loc descriptor functions.
+ (one_reg_loc_descriptor): Add parameter for initialization status;
+ check its value and add DW_OP_GNU_uninit to returned loc descr if
+ appropriate.
+ (multiple_reg_loc_descriptor): Add parameter for initialization
+ status;
+ pass init status argument to other loc descriptor functions; check
+ value of intialization parameter and add DW_OP_GNU_uninit to returned
+ loc descr if appropriate.
+ (based_loc_descr): Add parameter for initialization status; add new
+ variable for return value; check value of initialization parameter and
+ add DW_OP_GNU_uninit to returned loc descr if appropriate.
+ (concatn_mem_loc_descriptor): Add parameter for initialization status;
+ pass init status argument to other loc descriptor functions; check
+ value of intialization parameter and add DW_OP_GNU_uninit to returned
+ loc descr if appropriate.
+ (mem_loc_descriptor): Likewise.
+ (concat_loc_descriptor): Likewise.
+ (concatn_loc_descriptor): Likewise.
+ (loc_descriptor): Add parameter for initialization status; pass it as
+ argument to other loc descriptor function calls.
+ (loc_descriptor_from_tree_1): Add appropriate initialization status
+ to loc descriptor function calls.
+ (add_location_or_const_value_attribute): Get initialization status
+ from VAR_LOCATION note; add initialization status to loc descriptor
+ function calls.
+ * dwarf2.h (enum dwarf_location_atom): New op, DW_OP_GNU_uninit.
+ * print-rtl.c (print_rtx): When printing a VAR_LOCATION note, if
+ status is uninitialized, add "[uninint]" to output.
+ * common.opt (fvar-tracking-uninit): New option, similar to
+ fvar-tracking, to turn on tracking of uninitialized variables; creates
+ a new global flag, flag_var_tracking_uninit.
+ * rtl.h (NOTE_VAR_LOCATION_STATUS): New macro for accessing new field.
+ (enum var_init_status): New type, for var initialization status field.
+ * var-tracking.c (struct location_chain_def): Two new fields, init,
+ for initialization status, and set_src for the assignment value expr.
+ (unshare_variable): New parameter for initialization status;
+ initialize new init and set_src fields.
+ (var_reg_set): New parameters for initialization status and value;
+ pass them to set_variable_part.
+ (var_mem_set): Likewise.
+ (get_init_value): New function.
+ (var_reg_delete_and_set): New initialization status & value
+ parameters; add call to get_init_value if status is unknown; pass new
+ parameters to clobber_variable_part and var_reg_set.
+ (var_mem_delete_and_set): Likewise.
+ (var_reg_delete): Pass null set_src value to clobber_variable_part.
+ (var_mem_delete): Likewise.
+ (variable_union): Pass status to unshare_variable; initialize new init
+ and set_src fields. If flag_var_tracking_uninit is not set, force
+ status to initialized.
+ (add_stores): Store insn, rather than NEXT_INSN(insn), so it can be
+ used later to get the set_src value.
+ (find_src_status): New function.
+ (find_src_set_src): New function.
+ (compute_bb_dataflow): Pass init status to calls to var_reg_set,
+ var_mem_set, var_reg_delete_and_set and var_mem_delete_and_set; for
+ MO_SET, get set_src value and pass it to var_reg_delete_and_set
+ and var_mem_delete_and_set.
+ (dump_variable): Print out "[uninit]" if appropriate.
+ (set_variable_part): Add new initialization and set_src parameters;
+ pass status to unshare_variable; set node->init and node- >set_src
+ fields and modify slot in hash table appropriately; save the init and
+ set_src values if appropriate and assign to the new node.
+ (clobber_variable_part): New set_src parameter; if two nodes have
+ same variable and same location but different set_src (assignment)
+ values, clobber old node.
+ (delete_variable_part): Pass init status to unshare_variable.
+ (emit_note_insn_var_location): Add initialized var; assign var's init
+ status to new 'initialized'; pass new init status field to calls to
+ gen_rtx_VAR_LOCATION. If flag_var_tracking_uninit is not set, force
+ status to initialized.
+ (emit_notes_in_bb): Pass initialization status to calls to
+ var_reg_set, var_mem_set, var_reg_delete_and_set and
+ var_mem_delete_and_set; for MO_SET, get set_src value and pass it to
+ var_reg_delete_and_set and var_mem_delete_and_set; call
+ emit_notes_for_changes on NEXT_INSN(insn) rather than on insn, to
+ make up for change in add_stores.
+ (vt_add_function_parameters): Add status to calls to
+ set_variable_part.
+ * config/darwin.c (darwin_override_options): Turn on uninitialized
+ tracking automatically, if var_tracking is on and the system is
+ 10.5 or higher.
+
+2007-07-13 Sa Liu <saliu@de.ibm.com>
+
+ * config.gcc: Add options for arch and tune on SPU.
+ * config/spu/predicates.md: Add constant operands 0 and 1.
+ * config/spu/spu-builtins.def: Add builtins for double precision
+ floating point comparison: si_dfceq, si_dfcmeq, si_dfcgt, si_dfcmgt,
+ si_dftsv, spu_cmpeq_13, spu_cmpabseq_1, spu_cmpgt_13, spu_cmpabsgt_1,
+ spu_testsv.
+ * config/spu/spu-c.c: Define __SPU_EDP__ when builtins invoked with
+ a CELLEDP target.
+ * config/spu/spu-protos.h: Add new function prototypes.
+ * config/spu/spu.c (spu_override_options): Check options -march and
+ -mtune.
+ (spu_comp_icode): Add comparison code for DFmode and vector mode.
+ (spu_emit_branch_or_set): Use the new code for DFmode and vector
+ mode comparison.
+ (spu_const_from_int): New. Create a vector constant from 4 ints.
+ (get_vec_cmp_insn): New. Get insn index of vector compare instruction.
+ (spu_emit_vector_compare): New. Emit vector compare.
+ (spu_emit_vector_cond_expr): New. Emit vector conditional expression.
+ * config/spu/spu.h: Add options -march and -mtune. Define processor
+ types PROCESSOR_CELL and PROCESSOR_CELLEDP. Define macro
+ CANONICALIZE_COMPARISON.
+ * config/spu/spu.md: Add new insns for double precision compare
+ and double precision vector compare. Add vcond and smax/smin patterns
+ to enable DFmode vector conditional expression.
+ * config/spu/spu.opt: Add options -march and -mtune.
+ * config/spu/spu_internals.h: Add builtins for CELLEDP target:
+ si_dfceq, si_dfcmeq, si_dfcgt, si_dfcmgt, si_dftsv. Add builtin for
+ both CELL and CELLEDP targets: spu_testsv.
+ * config/spu/spu_intrinsics.h: Add flag mnemonics for test special
+ values.
+
+2007-07-13 Richard Guenther <rguenther@suse.de>
+
+ PR tree-optimization/32721
+ * tree-ssa-ccp.c (maybe_fold_stmt_indirect): Preserve
+ TREE_THIS_VOLATILE on the folded reference.
+ * tree-ssa-operands.c (get_expr_operands): Set has_volatile_ops
+ if the array reference has TREE_THIS_VOLATILE set.
+
+2007-07-13 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR other/32188
+ * doc/libgcc.texi: Update DFP intrinsics for DPD and BID.
+
+2007-07-13 Andreas Schwab <schwab@suse.de>
+
+ * gengtype-lex.l: Allow declarations to be indented.
+
+2007-07-12 Geoffrey Keating <geoffk@apple.com>
+
+ * ginclude/tgmath.h: New.
+ * config.gcc: Use GCC's tgmath.h on non-glibc systems.
+ * doc/sourcebuild.texi (Headers): Document use_gcc_tgmath.
+ * configure.ac (STMP_FIXPROTO): Honor use_gcc_tgmath.
+ * configure: Regenerate.
+
+2007-07-13 Kaz Kojima <kkojima@gcc.gnu.org>
+
+ * config/sh/linux-unwind.h (sh_fallback_frame_state): Use
+ correct index when setting register save state for xd
+ registers.
+
+2007-07-13 Kaz Kojima <kkojima@gcc.gnu.org>
+
+ * config/sh/sh.c (mark_use): Remove.
+
+2007-07-12 Paul Brook <paul@codesourcery.com>
+
+ * config/arm/arm.c (thumb1_compute_save_reg_mask): Make sure scratch
+ reg does not overlap return value.
+
+2007-07-12 Daniel Berlin <dberlin@dberlin.org>
+
+ * tree-ssa-pre.c (get_expression_vuses): Move out side-effect.
+ (set_expression_vuses): Ditto.
+ (init_pre): Initialize expression_vuses.
+
+2007-07-12 Zdenek Dvorak <dvorakz@suse.cz>
+
+ * config/i386/sse.md (storentdf, storentsf): New.
+
2007-07-12 Geoffrey Keating <geoffk@apple.com>
* builtins.c (get_pointer_alignment): Honor DECL_ALIGN on a
FUNCTION_BOUNDARY.
2007-07-12 Dorit Nuzman <dorit@il.ibm.com>
+ Devang Patel <dpatel@apple.com>
+
+ PR tree-optimization/25413
+ * targhooks.c (default_builtin_vector_alignment_reachable): New.
+ * targhooks.h (default_builtin_vector_alignment_reachable): New.
+ * tree.h (contains_packed_reference): New.
+ * expr.c (contains_packed_reference): New.
+ * tree-vect-analyze.c (vector_alignment_reachable_p): New.
+ (vect_enhance_data_refs_alignment): Call
+ vector_alignment_reachable_p.
+ * target.h (vector_alignment_reachable): New builtin.
+ * target-def.h (TARGET_VECTOR_ALIGNMENT_REACHABLE): New.
+ * config/rs6000/rs6000.c (rs6000_vector_alignment_reachable): New.
+ (TARGET_VECTOR_ALIGNMENT_REACHABLE): Define.
+
+2007-07-12 Dorit Nuzman <dorit@il.ibm.com>
* target.h (builtin_vectorization_cost): Add new target builtin.
* target-def.h (TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST): New.
offsets->locals_base to avoid negative stack size.
(thumb1_expand_prologue): Assert on negative stack size.
-2007-04-19 Sebastian Pop <sebpop@gmail.com>
+2007-06-19 Sebastian Pop <sebpop@gmail.com>
PR tree-optimization/32367
* tree-chrec.h (build_polynomial_chrec): Verify that the left hand side
float constant.
(_m_to_float): Use C89 compatible assignment.
-2007-04-20 Martin Michlmayr <tbm@cyrius.com>
+2007-05-20 Martin Michlmayr <tbm@cyrius.com>
PR target/32007
* config/arm/lib1funcs.asm: Define __ARM_ARCH__ on v2/v3 machines.
size never inline functions increasing caller size.
(cgraph_early_inlining): Inline for size when optimizing for size.
-2007-04-18 Bernd Schmidt <bernd.schmidt@analog.com>
+2007-05-04 Bernd Schmidt <bernd.schmidt@analog.com>
* config/bfin/bfin.md (<optab>di3): Now a define_expand which expands
logical operations piecewise.
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