Backport from mainline

[pf3gnuchains/gcc-fork.git] / gcc / ChangeLog

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 8660db3..446ca4a 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,87 @@
+2014-02-04  Uros Bizjak  <ubizjak@gmail.com>
+
+       Backport from mainline
+       2014-02-02  Uros Bizjak  <ubizjak@gmail.com>
+
+       PR target/60017
+       * config/i386/i386.c (classify_argument): Fix handling of bit_offset
+       when calculating size of integer atomic types.
+
+2014-02-02  Uros Bizjak  <ubizjak@gmail.com>
+
+       Backport from mainline
+       2014-01-30  Jakub Jelinek  <jakub@redhat.com>
+
+       * config/i386/f16cintrin.h (_cvtsh_ss): Avoid -Wnarrowing warning.
+
+2014-01-31  Richard Henderson  <rth@redhat.com>
+
+       PR middle-end/60004
+       * tree-eh.c (lower_try_finally_switch): Delay lowering finally block
+       until after else_eh is processed.
+
+2014-01-29  Markus Trippelsdorf  <markus@trippelsdorf.de>
+
+       Backport from mainline
+       2012-12-13  Jakub Jelinek  <jakub@redhat.com>
+
+       PR gcov-profile/55650
+       * coverage.c (coverage_obj_init): Return false if no functions
+       are being emitted.
+
+2014-01-25  Walter Lee  <walt@tilera.com>
+
+       Backport from mainline
+       2014-01-25  Walter Lee  <walt@tilera.com>
+
+       * config/tilegx/sync.md (atomic_fetch_sub): Fix negation and
+       avoid clobbering a live register.
+
+2014-01-25  Walter Lee  <walt@tilera.com>
+
+       Backport from mainline
+       2014-01-25  Walter Lee  <walt@tilera.com>
+
+       * config/tilegx/tilegx-c.c (tilegx_cpu_cpp_builtins):
+       Define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_{1,2}.
+       * config/tilegx/tilepro-c.c (tilepro_cpu_cpp_builtins):
+       Define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_{1,2,4,8}.
+
+2014-01-25  Walter Lee  <walt@tilera.com>
+
+       Backport from mainline
+       2014-01-25  Walter Lee  <walt@tilera.com>
+
+       * config/tilegx/tilegx.c (tilegx_gen_bundles): Delete barrier
+       insns before bundling.
+       * config/tilegx/tilegx.md (tile_network_barrier): Update comment.
+
+2014-01-25  Walter Lee  <walt@tilera.com>
+
+       Backport from mainline
+       2014-01-25  Walter Lee  <walt@tilera.com>
+
+       * config/tilegx/tilegx.c (tilegx_expand_builtin): Set
+       PREFETCH_SCHEDULE_BARRIER_P to true for prefetches.
+       * config/tilepro/tilepro.c (tilepro_expand_builtin): Ditto.
+
+2014-01-25  Walter Lee  <walt@tilera.com>
+
+       Backport from mainline
+       2014-01-25  Walter Lee  <walt@tilera.com>
+
+       * config/tilepro/tilepro.md (ctzdi2): Use register_operand predicate.
+       (clzdi2): Ditto.
+       (ffsdi2): Ditto.
+
+2014-01-25  Walter Lee  <walt@tilera.com>
+
+       Backport from mainline
+       2014-01-25  Walter Lee  <walt@tilera.com>
+
+       * config/tilegx/tilegx.c (tilegx_expand_to_rtl_hook): New.
+       (TARGET_EXPAND_TO_RTL_HOOK): Define.
+
 2014-01-22  Uros Bizjak  <ubizjak@gmail.com>
            Jakub Jelinek  <jakub@redhat.com>