+2012-09-03 Jakub Jelinek <jakub@redhat.com>
+
+ Backported from mainline
+ 2012-09-01 Jakub Jelinek <jakub@redhat.com>
+
+ PR target/54436
+ * config/i386/i386.md (*mov<mode>_insv_1_rex64, *movsi_insv_1): If
+ operands[1] is CONST_INT_P, convert it to QImode before printing.
+
+ 2012-08-31 Jakub Jelinek <jakub@redhat.com>
+
+ PR c/54428
+ * c-convert.c (convert): Don't call fold_convert_loc if
+ TYPE_MAIN_VARIANT of a COMPLEX_TYPE is the same, unless e
+ is a COMPLEX_EXPR. Remove TYPE_MAIN_VARIANT check from
+ COMPLEX_TYPE -> COMPLEX_TYPE conversion.
+
+ 2012-08-24 Jakub Jelinek <jakub@redhat.com>
+
+ PR c/54363
+ * gimplify.c (optimize_compound_literals_in_ctor): Only recurse
+ if init is a CONSTRUCTOR.
+
+2012-09-02 Eric Botcazou <ebotcazou@adacore.com>
+
+ PR rtl-optimization/54369
+ * config/mips/mips.c (mips_reorg): Invoke cleanup_barriers before
+ calling dbr_schedule.
+ * config/sparc/sparc.c (sparc_reorg): Likewise.
+
+2012-08-31 Kirill Yukhin <kirill.yukhin@intel.com>
+
+ Backport from mainline
+ 2012-08-23 Yuri Rumyantsev <ysrumyan@gmail.com>
+
+ * config/i386/i386.c (ia32_multipass_dfa_lookahead) : Add
+ case for Atom processor.
+
+2012-08-28 Uros Bizjak <ubizjak@gmail.com>
+
+ Backport from mainline
+ 2012-08-27 Uros Bizjak <ubizjak@gmail.com>
+
+ PR target/46254
+ * config/i386/predicates.md (cmpxchg8b_pic_memory_operand): Return
+ true for TARGET_64BIT or !flag_pic.
+ * config/i386/sync.md (*atomic_compare_and_swap_doubledi_pic): Remove.
+ (atomic_compare_and_swap_double<mode>): Change operand 2 predicate
+ to cmpxchg8b_pic_memory_operand. Use DWIH mode iterator.
+ Add insn constraint. Conditionally emit xchg asm insns.
+ (atomic_compare_and_swap<mode>): Update calls. Check only
+ cmpxchg8b_pic_memory_operand in memory address fixup.
+ (DCASMODE): Remove.
+ (CASHMODE): Rename from DCASHMODE.
+ (doublemodesuffix): Update modes.
+ (regprefix): New mode attribute.
+
+ (unspecv) <UNSPECV_CMPXCHG_{1,2,3,4}>: Remove.
+ <UNSPECV_CMPXCHG>: New constant.
+ (atomic_compare_and_swap<mode>_1): Rename from
+ atomic_compare_and_swap_single<mode>. Update calls and
+ unspec_volatile constants.
+ (atomic_compare_and_swap<mode>_doubleword): Rename from
+ atomic_compare_and_swap_double<mode>. Update calls and
+ unspec_volatile constants.
+
2012-08-28 Walter Lee <walt@tilera.com>
+
Backport from mainline
2012-08-28 Walter Lee <walt@tilera.com>
-
+
* confg/tilegx/tilegx.md: Fix code style.
(*zero_extendsidi_truncdisi): Fix typo.
* config/tilegx/tilegx.c: Fix code style.
Backport from mainline
2012-08-27 Walter Lee <walt@tilera.com>
-
+
* doc/md.texi (TILE-Gx): Fix typo.
2012-08-27 Walter Lee <walt@tilera.com>
Backport from mainline
2012-08-27 Walter Lee <walt@tilera.com>
-
+
* config/tilegx/tilegx.c (tilegx_function_profiler): Fix typo.
- config/tilepro/tilepro.c (tilepro_function_profiler): Ditto.
-
+ * config/tilepro/tilepro.c (tilepro_function_profiler): Ditto.
+
2012-08-27 Walter Lee <walt@tilera.com>
Backport from mainline
2012-08-27 Walter Lee <walt@tilera.com>
-
+
* config/tilegx/tilegx.md (*bfins): Rename to insn_bfins.
(insn_bfins): Delete.
* config/tilegx/sync.md (atomic_compare_and_swap_bare<mode>,
atomic_exchange_bare<mode>,
atomic_fetch_<fetchop_name>_bare<mode>): Set type to X1_remote.
- * config/tilegx/tilegx-generic.md (X1_remote): New
- insn_reservation.
+ * config/tilegx/tilegx-generic.md (X1_remote): New insn_reservation.
* config/tilegx/tilegx.md (type): Add X1_remove.
(insn_cmpexch<four_if_si>, insn_exch<four_if_si>,
insn_fetchadd<four_if_si>, insn_fetchaddgez<four_if_si>,
(destroy_bb_vec_info): Free the SLP instances.
2012-08-17 Richard Guenther <rguenther@suse.de>
-
+
* params.def (integer-share-limit): Decrease from 256 to 251,
add rationale.
2012-08-21 Richard Guenther <rguenther@suse.de>
-
+
* tree-ssa-loop-im.c (tree_ssa_lim_finalize): Properly free
the affine expansion cache.
* config/tilegx/feedback.h: New file.
* config/tilepro/feedback.h: New file.
-2012-08-08
Pavel Chupin <pavel.v.chupin@intel.com>
+2012-08-08
Pavel Chupin <pavel.v.chupin@intel.com>
Backport from mainline r189840 and r187586:
2012-07-25 Sergey Melnikov <sergey.melnikov@intel.com>
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