--- /dev/null
+/*
+ * TOPPERS/JSP Kernel
+ * Toyohashi Open Platform for Embedded Real-Time Systems/
+ * Just Standard Profile Kernel
+ *
+ * Copyright (C) 2000-2003 by Embedded and Real-Time Systems Laboratory
+ * Toyohashi Univ. of Technology, JAPAN
+ *
+ * ¾åµÃøºî¸¢¼Ô¤Ï¡¤°Ê²¼¤Î (1)¡Á(4) ¤Î¾ò·ï¤«¡¤Free Software Foundation
+ * ¤Ë¤è¤Ã¤Æ¸øɽ¤µ¤ì¤Æ¤¤¤ë GNU General Public License ¤Î Version 2 ¤Ëµ
+ * ½Ò¤µ¤ì¤Æ¤¤¤ë¾ò·ï¤òËþ¤¿¤¹¾ì¹ç¤Ë¸Â¤ê¡¤ËÜ¥½¥Õ¥È¥¦¥§¥¢¡ÊËÜ¥½¥Õ¥È¥¦¥§¥¢
+ * ¤ò²þÊѤ·¤¿¤â¤Î¤ò´Þ¤à¡¥°Ê²¼Æ±¤¸¡Ë¤ò»ÈÍÑ¡¦Ê£À½¡¦²þÊÑ¡¦ºÆÇÛÉۡʰʲ¼¡¤
+ * ÍøÍѤȸƤ֡ˤ¹¤ë¤³¤È¤ò̵½þ¤ÇµöÂú¤¹¤ë¡¥
+ * (1) ËÜ¥½¥Õ¥È¥¦¥§¥¢¤ò¥½¡¼¥¹¥³¡¼¥É¤Î·Á¤ÇÍøÍѤ¹¤ë¾ì¹ç¤Ë¤Ï¡¤¾åµ¤ÎÃøºî
+ * ¸¢É½¼¨¡¤¤³¤ÎÍøÍѾò·ï¤ª¤è¤Ó²¼µ¤Î̵Êݾڵ¬Ä꤬¡¤¤½¤Î¤Þ¤Þ¤Î·Á¤Ç¥½¡¼
+ * ¥¹¥³¡¼¥ÉÃæ¤Ë´Þ¤Þ¤ì¤Æ¤¤¤ë¤³¤È¡¥
+ * (2) ËÜ¥½¥Õ¥È¥¦¥§¥¢¤ò¡¤¥é¥¤¥Ö¥é¥ê·Á¼°¤Ê¤É¡¤Â¾¤Î¥½¥Õ¥È¥¦¥§¥¢³«È¯¤Ë»È
+ * ÍѤǤ¤ë·Á¤ÇºÆÇÛÉÛ¤¹¤ë¾ì¹ç¤Ë¤Ï¡¤ºÆÇÛÉÛ¤Ëȼ¤¦¥É¥¥å¥á¥ó¥È¡ÊÍøÍÑ
+ * ¼Ô¥Þ¥Ë¥å¥¢¥ë¤Ê¤É¡Ë¤Ë¡¤¾åµ¤ÎÃøºî¸¢É½¼¨¡¤¤³¤ÎÍøÍѾò·ï¤ª¤è¤Ó²¼µ
+ * ¤Î̵Êݾڵ¬Äê¤ò·ÇºÜ¤¹¤ë¤³¤È¡¥
+ * (3) ËÜ¥½¥Õ¥È¥¦¥§¥¢¤ò¡¤µ¡´ï¤ËÁȤ߹þ¤à¤Ê¤É¡¤Â¾¤Î¥½¥Õ¥È¥¦¥§¥¢³«È¯¤Ë»È
+ * ÍѤǤ¤Ê¤¤·Á¤ÇºÆÇÛÉÛ¤¹¤ë¾ì¹ç¤Ë¤Ï¡¤¼¡¤Î¤¤¤º¤ì¤«¤Î¾ò·ï¤òËþ¤¿¤¹¤³
+ * ¤È¡¥
+ * (a) ºÆÇÛÉÛ¤Ëȼ¤¦¥É¥¥å¥á¥ó¥È¡ÊÍøÍѼԥޥ˥奢¥ë¤Ê¤É¡Ë¤Ë¡¤¾åµ¤ÎÃø
+ * ºî¸¢É½¼¨¡¤¤³¤ÎÍøÍѾò·ï¤ª¤è¤Ó²¼µ¤Î̵Êݾڵ¬Äê¤ò·ÇºÜ¤¹¤ë¤³¤È¡¥
+ * (b) ºÆÇÛÉۤηÁÂÖ¤ò¡¤Ê̤ËÄê¤á¤ëÊýË¡¤Ë¤è¤Ã¤Æ¡¤TOPPERS¥×¥í¥¸¥§¥¯¥È¤Ë
+ * Êó¹ð¤¹¤ë¤³¤È¡¥
+ * (4) ËÜ¥½¥Õ¥È¥¦¥§¥¢¤ÎÍøÍѤˤè¤êľÀÜŪ¤Þ¤¿¤Ï´ÖÀÜŪ¤ËÀ¸¤¸¤ë¤¤¤«¤Ê¤ë»
+ * ³²¤«¤é¤â¡¤¾åµÃøºî¸¢¼Ô¤ª¤è¤ÓTOPPERS¥×¥í¥¸¥§¥¯¥È¤òÌÈÀÕ¤¹¤ë¤³¤È¡¥
+ *
+ * ËÜ¥½¥Õ¥È¥¦¥§¥¢¤Ï¡¤ÌµÊݾڤÇÄ󶡤µ¤ì¤Æ¤¤¤ë¤â¤Î¤Ç¤¢¤ë¡¥¾åµÃøºî¸¢¼Ô¤ª
+ * ¤è¤ÓTOPPERS¥×¥í¥¸¥§¥¯¥È¤Ï¡¤ËÜ¥½¥Õ¥È¥¦¥§¥¢¤Ë´Ø¤·¤Æ¡¤¤½¤ÎŬÍѲÄǽÀ¤â
+ * ´Þ¤á¤Æ¡¤¤¤¤«¤Ê¤ëÊݾڤâ¹Ô¤ï¤Ê¤¤¡¥¤Þ¤¿¡¤ËÜ¥½¥Õ¥È¥¦¥§¥¢¤ÎÍøÍѤˤè¤êľ
+ * ÀÜŪ¤Þ¤¿¤Ï´ÖÀÜŪ¤ËÀ¸¤¸¤¿¤¤¤«¤Ê¤ë»³²¤Ë´Ø¤·¤Æ¤â¡¤¤½¤ÎÀÕǤ¤òÉé¤ï¤Ê¤¤¡¥
+ *
+ * @(#) $Id: upd72001.c,v 1.4 2003/12/13 06:21:49 hiro Exp $
+ */
+
+/*
+ * ¦ÌPD72001ÍÑ ´Ê°×SIO¥É¥é¥¤¥Ð
+ */
+
+#include <s_services.h>
+#include <upd72001.h>
+
+/*
+ * ¥Ç¥Ð¥¤¥¹¥ì¥¸¥¹¥¿¤Î¥¢¥¯¥»¥¹´Ö³Ö»þ´Ö¡Ênsecñ°Ì¡Ë
+ *
+ * 200¤È¤¤¤¦Ãͤˤ¢¤Þ¤êº¬µò¤Ï¤Ê¤¤¡¥
+ */
+#define UPD72001_DELAY 200
+
+/*
+ * ¦ÌPD72001¤Î¥ì¥¸¥¹¥¿¤ÎÈÖ¹æ
+ */
+#define UPD72001_CR0 0x00u /* ¥³¥ó¥È¥í¡¼¥ë¥ì¥¸¥¹¥¿ */
+#define UPD72001_CR1 0x01u
+#define UPD72001_CR2 0x02u
+#define UPD72001_CR3 0x03u
+#define UPD72001_CR4 0x04u
+#define UPD72001_CR5 0x05u
+#define UPD72001_CR10 0x0au
+#define UPD72001_CR12 0x0cu
+#define UPD72001_CR14 0x0eu
+#define UPD72001_CR15 0x0fu
+
+#define UPD72001_SR0 0x00u /* ¥¹¥Æ¡¼¥¿¥¹¥ì¥¸¥¹¥¿ */
+
+/*
+ * ¥³¥ó¥È¥í¡¼¥ë¥ì¥¸¥¹¥¿¤ÎÀßÄêÃÍ
+ */
+#define CR_RESET 0x18u /* ¥Ý¡¼¥È¥ê¥»¥Ã¥È¥³¥Þ¥ó¥É */
+
+#define CR0_EOI 0x38u /* EOI¡ÊEnd of Interrupt¡Ë*/
+
+#define CR1_DOWN 0x00u /* Á´³ä¹þ¤ß¤ò¶Ø»ß */
+#define CR1_RECV 0x10u /* ¼õ¿®³ä¹þ¤ßµö²Ä¥Ó¥Ã¥È */
+#define CR1_SEND 0x02u /* Á÷¿®³ä¹þ¤ßµö²Ä¥Ó¥Ã¥È */
+
+#define CR3_DEF 0xc1u /* ¥Ç¡¼¥¿ 8bit¡¤¼õ¿®¥¤¥Í¡¼¥Ö¥ë */
+#define CR4_DEF 0x44u /* ¥¹¥È¥Ã¥×¥Ó¥Ã¥È 1bit¡¤¥Ñ¥ê¥Æ¥£¤Ê¤· */
+#define CR5_DEF 0xeau /* ¥Ç¡¼¥¿ 8bit¡¤Á÷¿®¥¤¥Í¡¼¥Ö¥ë */
+
+#define CR10_DEF 0x00u /* NRZ */
+#define CR14_DEF 0x07u /* ¥Ü¡¼¥ì¡¼¥È¥¸¥§¥Í¥ì¡¼¥¿¥¤¥Í¡¼¥Ö¥ë */
+#define CR15_DEF 0x56u /* ¥Ü¡¼¥ì¡¼¥È¥¸¥§¥Í¥ì¡¼¥¿»ÈÍÑ */
+
+#define SR0_RECV 0x01u /* ¼õ¿®ÄÌÃÎ¥Ó¥Ã¥È */
+#define SR0_SEND 0x04u /* Á÷¿®²Äǽ¥Ó¥Ã¥È */
+
+/*
+ * ¥·¥ê¥¢¥ëI/O¥Ý¡¼¥È½é´ü²½¥Ö¥í¥Ã¥¯¤ÎÄêµÁ
+ */
+typedef struct sio_port_initialization_block {
+ VP data; /* ¥Ç¡¼¥¿¥ì¥¸¥¹¥¿¤ÎÈÖÃÏ */
+ VP ctrl; /* ¥³¥ó¥È¥í¡¼¥ë¥ì¥¸¥¹¥¿¤ÎÈÖÃÏ */
+
+ UB cr3_def; /* CR3¤ÎÀßÄêÃ͡ʼõ¿®¥Ó¥Ã¥È¿ô¡Ë*/
+ UB cr4_def; /* CR4¤ÎÀßÄêÃÍ¡Ê¥¹¥È¥Ã¥×¥Ó¥Ã¥È¡¤¥Ñ¥ê¥Æ¥£¡Ë*/
+ UB cr5_def; /* CR5¤ÎÀßÄêÃÍ¡ÊÁ÷¿®¥Ó¥Ã¥È¿ô¡Ë*/
+ UB brg1_def; /* ¥Ü¡¼¥ì¡¼¥È¾å°Ì¤ÎÀßÄêÃÍ */
+ UB brg2_def; /* ¥Ü¡¼¥ì¡¼¥È²¼°Ì¤ÎÀßÄêÃÍ */
+} SIOPINIB;
+
+/*
+ * ¥·¥ê¥¢¥ëI/O¥Ý¡¼¥È´ÉÍý¥Ö¥í¥Ã¥¯¤ÎÄêµÁ
+ */
+struct sio_port_control_block {
+ const SIOPINIB *siopinib; /* ¥·¥ê¥¢¥ëI/O¥Ý¡¼¥È½é´ü²½¥Ö¥í¥Ã¥¯ */
+ VP_INT exinf; /* ³ÈÄ¥¾ðÊó */
+ BOOL openflag; /* ¥ª¡¼¥×¥óºÑ¤ß¥Õ¥é¥° */
+ UB cr1; /* CR1¤ÎÀßÄêÃ͡ʳä¹þ¤ßµö²Ä¡Ë*/
+ BOOL getready; /* ʸ»ú¤ò¼õ¿®¤·¤¿¾õÂÖ */
+ BOOL putready; /* ʸ»ú¤òÁ÷¿®¤Ç¤¤ë¾õÂÖ */
+};
+
+/*
+ * ¥·¥ê¥¢¥ëI/O¥Ý¡¼¥È½é´ü²½¥Ö¥í¥Ã¥¯
+ *
+ * ID = 1 ¤ò¥Ý¡¼¥ÈB¡¤ID = 2 ¤ò¥Ý¡¼¥ÈA¤ËÂбþ¤µ¤»¤Æ¤¤¤ë¡¥
+ */
+const SIOPINIB siopinib_table[TNUM_SIOP] = {
+ { (VP) TADR_UPD72001_DATAB, (VP) TADR_UPD72001_CTRLB,
+ CR3_DEF, CR4_DEF, CR5_DEF, BRG1_DEF, BRG2_DEF },
+#if TNUM_SIOP >= 2
+ { (VP) TADR_UPD72001_DATAA, (VP) TADR_UPD72001_CTRLA,
+ CR3_DEF, CR4_DEF, CR5_DEF, BRG1_DEF, BRG2_DEF },
+#endif /* TNUM_SIOP >= 2 */
+};
+
+/*
+ * ¥·¥ê¥¢¥ëI/O¥Ý¡¼¥È´ÉÍý¥Ö¥í¥Ã¥¯¤Î¥¨¥ê¥¢
+ */
+SIOPCB siopcb_table[TNUM_SIOP];
+
+/*
+ * ¥·¥ê¥¢¥ëI/O¥Ý¡¼¥ÈID¤«¤é´ÉÍý¥Ö¥í¥Ã¥¯¤ò¼è¤ê½Ð¤¹¤¿¤á¤Î¥Þ¥¯¥í
+ */
+#define INDEX_SIOP(siopid) ((UINT)((siopid) - 1))
+#define get_siopcb(siopid) (&(siopcb_table[INDEX_SIOP(siopid)]))
+
+/*
+ * ¥Ç¥Ð¥¤¥¹¥ì¥¸¥¹¥¿¤Ø¤Î¥¢¥¯¥»¥¹´Ø¿ô
+ */
+Inline UB
+upd72001_read_reg(VP addr)
+{
+ UB val;
+
+ val = (UB) upd72001_reb_reg(addr);
+ sil_dly_nse(UPD72001_DELAY);
+ return(val);
+}
+
+Inline void
+upd72001_write_reg(VP addr, UB val)
+{
+ upd72001_wrb_reg(addr, (VB) val);
+ sil_dly_nse(UPD72001_DELAY);
+}
+
+Inline UB
+upd72001_read_ctrl(VP addr, UB reg)
+{
+ upd72001_write_reg(addr, reg);
+ return(upd72001_read_reg(addr));
+}
+
+Inline void
+upd72001_write_ctrl(VP addr, UB reg, UB val)
+{
+ upd72001_write_reg(addr, reg);
+ upd72001_write_reg(addr, val);
+}
+
+Inline void
+upd72001_write_brg(VP addr, UB reg, UB val, UB brg2, UB brg1)
+{
+ upd72001_write_reg(addr, reg);
+ upd72001_write_reg(addr, val);
+ upd72001_write_reg(addr, brg2);
+ upd72001_write_reg(addr, brg1);
+ (void) upd72001_read_reg(addr); /* ¥À¥ß¡¼¥ê¡¼¥É */
+}
+
+/*
+ * ¾õÂÖ¤ÎÆɽФ·¡ÊSR0¤ÎÆɽФ·¡Ë
+ *
+ * ¦ÌPD72001¤Ï¡¤¾õÂÖ¡ÊSR0¡Ë¤ò°ìÅÙÆɤà¤È¼õ¿®ÄÌÃΥӥåȤ¬Íî¤Á¤Æ¤·¤Þ¤¦¤¿
+ * ¤á¡¤¾õÂÖ¤òÆɤ߽Ф¹´Ø¿ô¤òÀߤ±¡¤¥·¥ê¥¢¥ëI/O¥Ý¡¼¥È´ÉÍý¥Ö¥í¥Ã¥¯Ãæ¤Î
+ * getready ¤Ë¼õ¿®ÄÌÃξõÂÖ¡¤putready ¤ËÁ÷¿®²Äǽ¾õÂÖ¤òÊݸ¤·¤Æ¤¤¤ë¡ÊÁ÷
+ * ¿®²Äǽ¾õÂÖ¤ÎÊݸ¤ÏÉÔÍפ«¤â¤·¤ì¤Ê¤¤¡Ë¡¥
+ * ¾õÂ֥쥸¥¹¥¿¤òÆɤó¤Ç¤â¼õ¿®ÄÌÃΥӥåȤ¬Íî¤Á¤Ê¤¤¥Ç¥Ð¥¤¥¹¡Ê¤³¤Á¤é¤¬Éá
+ * Ä̤Ȼפï¤ì¤ë¡Ë¤Ç¤Ï¡¤¤³¤Î´Ø¿ô¤ÏɬÍפʤ¤¡¥
+ */
+static void
+upd72001_get_stat(SIOPCB *siopcb)
+{
+ UB sr0;
+
+ sr0 = upd72001_read_ctrl(siopcb->siopinib->ctrl, UPD72001_SR0);
+ if ((sr0 & SR0_RECV) != 0) {
+ siopcb->getready = TRUE;
+ }
+ if ((sr0 & SR0_SEND) != 0) {
+ siopcb->putready = TRUE;
+ }
+}
+
+/*
+ * ʸ»ú¤ò¼õ¿®¤Ç¤¤ë¤«¡©
+ */
+Inline BOOL
+upd72001_getready(SIOPCB *siopcb)
+{
+ upd72001_get_stat(siopcb);
+ return(siopcb->getready);
+}
+
+/*
+ * ʸ»ú¤òÁ÷¿®¤Ç¤¤ë¤«¡©
+ */
+Inline BOOL
+upd72001_putready(SIOPCB *siopcb)
+{
+ upd72001_get_stat(siopcb);
+ return(siopcb->putready);
+}
+
+/*
+ * ¼õ¿®¤·¤¿Ê¸»ú¤Î¼è½Ð¤·
+ */
+Inline char
+upd72001_getchar(SIOPCB *siopcb)
+{
+ siopcb->getready = FALSE;
+ return((char) upd72001_read_reg(siopcb->siopinib->data));
+}
+
+/*
+ * Á÷¿®¤¹¤ëʸ»ú¤Î½ñ¹þ¤ß
+ */
+Inline void
+upd72001_putchar(SIOPCB *siopcb, char c)
+{
+ siopcb->putready = FALSE;
+ upd72001_write_reg(siopcb->siopinib->data, (UB) c);
+}
+
+/*
+ * EOI¡ÊEnd Of Interrupt¡Ëȯ¹Ô
+ */
+Inline void
+upd72001_eoi()
+{
+ upd72001_write_ctrl((VP) TADR_UPD72001_CTRLA, UPD72001_CR0, CR0_EOI);
+}
+
+/*
+ * SIO¥É¥é¥¤¥Ð¤Î½é´ü²½¥ë¡¼¥Á¥ó
+ */
+void
+upd72001_initialize()
+{
+ SIOPCB *siopcb;
+ UINT i;
+
+ /*
+ * ¥·¥ê¥¢¥ëI/O¥Ý¡¼¥È´ÉÍý¥Ö¥í¥Ã¥¯¤Î½é´ü²½
+ */
+ for (siopcb = siopcb_table, i = 0; i < TNUM_SIOP; siopcb++, i++) {
+ siopcb->siopinib = &(siopinib_table[i]);
+ siopcb->openflag = FALSE;
+ }
+}
+
+/*
+ * ¥ª¡¼¥×¥ó¤·¤Æ¤¤¤ë¥Ý¡¼¥È¤¬¤¢¤ë¤«¡©
+ */
+BOOL
+upd72001_openflag(void)
+{
+#if TNUM_SIOP < 2
+ return(siopcb_table[0].openflag);
+#else /* TNUM_SIOP < 2 */
+ return(siopcb_table[0].openflag || siopcb_table[1].openflag);
+#endif /* TNUM_SIOP < 2 */
+}
+
+/*
+ * ¥·¥ê¥¢¥ëI/O¥Ý¡¼¥È¤Î¥ª¡¼¥×¥ó
+ */
+SIOPCB *
+upd72001_opn_por(ID siopid, VP_INT exinf)
+{
+ SIOPCB *siopcb;
+ const SIOPINIB *siopinib;
+
+ siopcb = get_siopcb(siopid);
+ siopinib = siopcb->siopinib;
+
+ upd72001_write_reg(siopinib->ctrl, CR_RESET);
+ if (!upd72001_openflag()) {
+ upd72001_write_ctrl((VP) TADR_UPD72001_CTRLA,
+ UPD72001_CR2, 0x18);
+ upd72001_write_ctrl((VP) TADR_UPD72001_CTRLB,
+ UPD72001_CR2, 0x00);
+ }
+ siopcb->cr1 = CR1_DOWN;
+ upd72001_write_ctrl(siopinib->ctrl, UPD72001_CR1, siopcb->cr1);
+ upd72001_write_ctrl(siopinib->ctrl, UPD72001_CR4, siopinib->cr4_def);
+ upd72001_write_brg(siopinib->ctrl, UPD72001_CR12,
+ 0x01, siopinib->brg2_def, siopinib->brg1_def);
+ upd72001_write_brg(siopinib->ctrl, UPD72001_CR12,
+ 0x02, siopinib->brg2_def, siopinib->brg1_def);
+ upd72001_write_ctrl(siopinib->ctrl, UPD72001_CR15, CR15_DEF);
+ upd72001_write_ctrl(siopinib->ctrl, UPD72001_CR14, CR14_DEF);
+ upd72001_write_ctrl(siopinib->ctrl, UPD72001_CR10, CR10_DEF);
+ upd72001_write_ctrl(siopinib->ctrl, UPD72001_CR3, siopinib->cr3_def);
+ upd72001_write_ctrl(siopinib->ctrl, UPD72001_CR5, siopinib->cr5_def);
+ siopcb->exinf = exinf;
+ siopcb->getready = siopcb->putready = FALSE;
+ siopcb->openflag = TRUE;
+ return(siopcb);
+}
+
+/*
+ * ¥·¥ê¥¢¥ëI/O¥Ý¡¼¥È¤Î¥¯¥í¡¼¥º
+ */
+void
+upd72001_cls_por(SIOPCB *siopcb)
+{
+ upd72001_write_ctrl(siopcb->siopinib->ctrl, UPD72001_CR1, CR1_DOWN);
+ siopcb->openflag = FALSE;
+}
+
+/*
+ * ¥·¥ê¥¢¥ëI/O¥Ý¡¼¥È¤Ø¤Îʸ»úÁ÷¿®
+ */
+BOOL
+upd72001_snd_chr(SIOPCB *siopcb, char c)
+{
+ if (upd72001_putready(siopcb)) {
+ upd72001_putchar(siopcb, c);
+ return(TRUE);
+ }
+ return(FALSE);
+}
+
+/*
+ * ¥·¥ê¥¢¥ëI/O¥Ý¡¼¥È¤«¤é¤Îʸ»ú¼õ¿®
+ */
+INT
+upd72001_rcv_chr(SIOPCB *siopcb)
+{
+ if (upd72001_getready(siopcb)) {
+ return((INT)(UB) upd72001_getchar(siopcb));
+ }
+ return(-1);
+}
+
+/*
+ * ¥·¥ê¥¢¥ëI/O¥Ý¡¼¥È¤«¤é¤Î¥³¡¼¥ë¥Ð¥Ã¥¯¤Îµö²Ä
+ */
+void
+upd72001_ena_cbr(SIOPCB *siopcb, UINT cbrtn)
+{
+ UB cr1_bit = 0;
+
+ switch (cbrtn) {
+ case SIO_ERDY_SND:
+ cr1_bit = CR1_SEND;
+ break;
+ case SIO_ERDY_RCV:
+ cr1_bit = CR1_RECV;
+ break;
+ }
+ siopcb->cr1 |= cr1_bit;
+ upd72001_write_ctrl(siopcb->siopinib->ctrl, UPD72001_CR1, siopcb->cr1);
+}
+
+/*
+ * ¥·¥ê¥¢¥ëI/O¥Ý¡¼¥È¤«¤é¤Î¥³¡¼¥ë¥Ð¥Ã¥¯¤Î¶Ø»ß
+ */
+void
+upd72001_dis_cbr(SIOPCB *siopcb, UINT cbrtn)
+{
+ UB cr1_bit = 0;
+
+ switch (cbrtn) {
+ case SIO_ERDY_SND:
+ cr1_bit = CR1_SEND;
+ break;
+ case SIO_ERDY_RCV:
+ cr1_bit = CR1_RECV;
+ break;
+ }
+ siopcb->cr1 &= ~cr1_bit;
+ upd72001_write_ctrl(siopcb->siopinib->ctrl, UPD72001_CR1, siopcb->cr1);
+}
+
+/*
+ * ¥·¥ê¥¢¥ëI/O¥Ý¡¼¥È¤ËÂФ¹¤ë³ä¹þ¤ß½èÍý
+ */
+static void
+upd72001_isr_siop(SIOPCB *siopcb)
+{
+ if ((siopcb->cr1 & CR1_RECV) != 0 && upd72001_getready(siopcb)) {
+ /*
+ * ¼õ¿®ÄÌÃÎ¥³¡¼¥ë¥Ð¥Ã¥¯¥ë¡¼¥Á¥ó¤ò¸Æ¤Ó½Ð¤¹¡¥
+ */
+ upd72001_ierdy_rcv(siopcb->exinf);
+ }
+ if ((siopcb->cr1 & CR1_SEND) != 0 && upd72001_putready(siopcb)) {
+ /*
+ * Á÷¿®²Äǽ¥³¡¼¥ë¥Ð¥Ã¥¯¥ë¡¼¥Á¥ó¤ò¸Æ¤Ó½Ð¤¹¡¥
+ */
+ upd72001_ierdy_snd(siopcb->exinf);
+ }
+}
+
+/*
+ * SIO¤Î³ä¹þ¤ß¥µ¡¼¥Ó¥¹¥ë¡¼¥Á¥ó
+ */
+void
+upd72001_isr()
+{
+ if (siopcb_table[0].openflag) {
+ upd72001_isr_siop(&(siopcb_table[0]));
+ }
+#if TNUM_SIOP >= 2
+ if (siopcb_table[1].openflag) {
+ upd72001_isr_siop(&(siopcb_table[1]));
+ }
+#endif /* TNUM_SIOP >= 2 */
+ upd72001_eoi();
+}
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