+2010-04-20 Uros Bizjak <ubizjak@gmail.com>
+
+ * config/i386/i386.md (ffs<mode>2): Macroize expander from ffs_cmove
+ and ffsdi2 using SWI48 mode iterator. Expand SImode insn through
+ ffsi2_no_cmove for !TARGET_CMOVE.
+ (ffssi2_no_cmove): Rename from *ffs_no_cmove. Make public.
+ (ffssi2): Remove expander.
+ (*ffs<mode>_1): Macroize insn from *ffs{si,di} using SWI48
+ mode iterator.
+ (ctz<mode>2): Ditto from ctz{si,di}2.
+ (clz<mode>2): Macroize expander from ctz{hi,si,di}2 using SWI248
+ mode iterator.
+ (clz<mode>2_abm): Macroize insn from clz{hi,si,di}2_abm using SWI248
+ mode iterator.
+
2010-04-20 Jakub Jelinek <jakub@redhat.com>
* dwarf2out.c (AT_linkage_name): Define.
2010-04-20 Xinliang David Li <davidxl@gcc.gnu.org>
PR middle-end/41952
- * fold-const.c (fold_comparison): New folding rule.
+ * fold-const.c (fold_comparison): New folding rule.
2010-04-20 Anatoly Sokolov <aesok@post.ru>
* cgraph.c (cgraph_remove_node): Kill bodies in other partitoin.
(dump_cgraph_node): Dump new flags.
- * cgraph.h (struct cgraph_node): Add flags reachable_from_other_partition
- and in_other_partition.
- (cgraph_can_remove_if_no_direct_calls_p): Functions used by other partition
- can not be removed.
- * cgraphunit.c (cgraph_mark_functions_to_output): Functions used by the other
- partition must be output; silence sanity checking on leaking functions
- bodies from other paritition.
+ * cgraph.h (struct cgraph_node): Add flags
+ reachable_from_other_partition and in_other_partition.
+ (cgraph_can_remove_if_no_direct_calls_p): Functions used by
+ other partition can not be removed.
+ * cgraphunit.c (cgraph_mark_functions_to_output): Functions used by
+ the other partition must be output; silence sanity checking on
+ leaking functions bodies from other paritition.
* lto-cgraph.c (reachable_from_other_partition_p): New function.
(lto_output_node): Output new flags; do not sanity check that inline
clones are output; drop lto_forced_extern_inline_p code; do not mock
2010-04-20 Richard Guenther <rguenther@suse.de>
- * tree-ssa-structalias.c (do_structure_copy): Properly handle
- DEREF.
+ * tree-ssa-structalias.c (do_structure_copy): Properly handle DEREF.
(dump_sa_points_to_info): Remove asserts.
(init_base_vars): nothing_id isn't an escape point nor does it
have pointers.
2010-04-19 Jakub Jelinek <jakub@redhat.com>
- * dwarf2out.c (lower_bound_default): For DW_LANG_Python return
- 0 for -gdwarf-4.
+ * dwarf2out.c (lower_bound_default): For DW_LANG_Python return 0
+ for -gdwarf-4.
PR middle-end/43337
* tree-nested.c (convert_nonlocal_omp_clauses): OMP_CLAUSE_PRIVATE
2010-04-19 Ira Rosen <irar@il.ibm.com>
PR tree-optimization/37027
- * tree-vectorizer.h (struct _loop_vec_info): Add new field reductions
+ * tree-vectorizer.h (struct _loop_vec_info): Add new field reductions
and macro to access it.
(vectorizable_reduction): Add argument.
(vect_get_slp_defs): Likewise.
(vect_create_epilog_for_reduction): Handle SLP. Modify documentation,
add new argument.
(vectorizable_reduction): Likewise.
- * tree-vect-stmts.c (vect_get_vec_defs): Update call to
+ * tree-vect-stmts.c (vect_get_vec_defs): Update call to
vect_get_slp_defs.
(vectorizable_type_demotion, vectorizable_type_promotion,
vectorizable_store): Likewise.
(vect_build_slp_tree): Fix indentation. Check that there are no loads
from different interleaving chains in same node.
(vect_slp_rearrange_stmts): New function.
- (vect_supported_load_permutation_p): Allow load permutations for
+ (vect_supported_load_permutation_p): Allow load permutations for
reductions. Call vect_slp_rearrange_stmts() to rearrange statements
inside SLP nodes if necessary.
(vect_analyze_slp_instance): Handle reductions.
(vect_detect_hybrid_slp_stmts): Skip reduction statements.
(vect_get_constant_vectors): Create initial vectors for reductions
according to reduction code. Add new argument.
- (vect_get_slp_defs): Add new argument, pass it to
+ (vect_get_slp_defs): Add new argument, pass it to
vect_get_constant_vectors.
(vect_schedule_slp_instance): Remove SLP tree root statements.
* gcc.c (main): Search for liblto_plugin.so with mode R_OK.
-2010-04-18 Ira Rosen <irar@il.ibm.com>
+2010-04-18 Ira Rosen <irar@il.ibm.com>
PR tree-optimization/43771
* tree-vect-slp.c (vect_supported_load_permutation_p): Check that
* config/i386/i386.md (*jcc_bt<mode>): Fix build breakage by adding
missing left parenthesis.
-
+
2010-04-16 Uros Bizjak <ubizjak@gmail.com>
* config/i386/i386.md (*bt<mode>): Macroize insn from *btsi and
* config/h8300/h8300.h (OK_FOR_U): Support 'U' constraint for H8300SX.
- * config/h8300/h8300.md (movqi_h8sx, movhi_h8sx, movsi_h8sx,
+ * config/h8300/h8300.md (movqi_h8sx, movhi_h8sx, movsi_h8sx,
cmphi_h8300hs_znvc, cmpsi, addhi3_h8sx) : Emit instructions in
#xx:3 and #xx:4 mode.
2010-04-16 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>
- * configure.ac: Check for elf_getshdrstrndx or elf_getshstrndx
- flavor.
+ * configure.ac: Check for elf_getshdrstrndx or elf_getshstrndx flavor.
* configure: Regenerate.
* config.in: Regenerate.
* doc/install.texi (Prerequisites): Document that Solaris 2 libelf
2010-04-16 Diego Novillo <dnovillo@google.com>
- * doc/invoke.texi: Explain how are unrecognized -Wno- warnings
- handled.
+ * doc/invoke.texi: Explain how are unrecognized -Wno- warnings handled.
2010-04-16 Bernd Schmidt <bernds@codesourcery.com>
(dump_points_to_solution): Likewise.
* tree-dfa.c (dump_variable): Also dump DECL_PT_UID.
* tree-inline.c (remap_ssa_name): Copy IPA points-to solution.
- (remap_gimple_stmt): Reset call clobber/use information if
- necessary.
+ (remap_gimple_stmt): Reset call clobber/use information if necessary.
(copy_decl_to_var): Copy DECL_PT_UID.
(copy_result_decl_to_var): Likewise.
* tree.c (make_node_stat): Initialize DECL_PT_UID.
PR target/43742
* config/sh/sh.md (doloop_end_split): Remove "+r" constraint
- in an input-only operand.
+ in an input-only operand.
2010-04-15 Anatoly Sokolov <aesok@post.ru>
(double_int_negative_p): Convert to static inline function.
* double-int.c (double_int_lshift, double_int_lshift): Add new function.
(double_int_negative_p): Remove.
- * tree.h (lshift_double, rshift_double):
+ * tree.h (lshift_double, rshift_double):
* tree.c (build_low_bits_mask): Clean up, use double_int_* functions.
* fold-const.c (fold_convert_const_int_from_real,
fold_convert_const_int_from_fixed, div_if_zero_remainder): (Ditto.).
* expmed.c (mask_rtx, lshift_value): (Ditto.).
2010-04-14 Bernd Schmidt <bernds@codesourcery.com>
-
+
PR target/21803
* ifcvt.c (cond_exec_process_if_block): Look for identical sequences
at the start and end of the then/else blocks, and omit them from the
(use (match_dup 1))
(clobber (reg:CC FLAGS_REG))])]
{
- operands[5] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) - 1);
+ operands[5] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode)-1);
if (<MODE>mode != HImode
&& (optimize_function_for_size_p (cfun) || TARGET_USE_CLTD))
"leave"
[(set_attr "type" "leave")])
\f
-(define_expand "ffssi2"
- [(parallel
- [(set (match_operand:SI 0 "register_operand" "")
- (ffs:SI (match_operand:SI 1 "nonimmediate_operand" "")))
- (clobber (match_scratch:SI 2 ""))
- (clobber (reg:CC FLAGS_REG))])]
- ""
-{
- if (TARGET_CMOVE)
- {
- emit_insn (gen_ffs_cmove (operands[0], operands[1]));
- DONE;
- }
-})
+;; Bit manipulation instructions.
-(define_expand "ffs_cmove"
+(define_expand "ffs<mode>2"
[(set (match_dup 2) (const_int -1))
(parallel [(set (reg:CCZ FLAGS_REG)
- (compare:CCZ (match_operand:SI 1 "nonimmediate_operand" "")
- (const_int 0)))
- (set (match_operand:SI 0 "register_operand" "")
- (ctz:SI (match_dup 1)))])
- (set (match_dup 0) (if_then_else:SI
+ (compare:CCZ
+ (match_operand:SWI48 1 "nonimmediate_operand" "")
+ (const_int 0)))
+ (set (match_operand:SWI48 0 "register_operand" "")
+ (ctz:SWI48 (match_dup 1)))])
+ (set (match_dup 0) (if_then_else:SWI48
(eq (reg:CCZ FLAGS_REG) (const_int 0))
(match_dup 2)
(match_dup 0)))
- (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (const_int 1)))
+ (parallel [(set (match_dup 0) (plus:SWI48 (match_dup 0) (const_int 1)))
(clobber (reg:CC FLAGS_REG))])]
- "TARGET_CMOVE"
- "operands[2] = gen_reg_rtx (SImode);")
+ ""
+{
+ if (<MODE>mode == SImode && !TARGET_CMOVE)
+ {
+ emit_insn (gen_ffssi2_no_cmove (operands[0], operands [1]));
+ DONE;
+ }
+ operands[2] = gen_reg_rtx (<MODE>mode);
+})
-(define_insn_and_split "*ffs_no_cmove"
+(define_insn_and_split "ffssi2_no_cmove"
[(set (match_operand:SI 0 "register_operand" "=r")
(ffs:SI (match_operand:SI 1 "nonimmediate_operand" "rm")))
(clobber (match_scratch:SI 2 "=&q"))
ix86_expand_clear (operands[2]);
})
-(define_insn "*ffssi_1"
+(define_insn "*ffs<mode>_1"
[(set (reg:CCZ FLAGS_REG)
- (compare:CCZ (match_operand:SI 1 "nonimmediate_operand" "rm")
+ (compare:CCZ (match_operand:SWI48 1 "nonimmediate_operand" "rm")
(const_int 0)))
- (set (match_operand:SI 0 "register_operand" "=r")
- (ctz:SI (match_dup 1)))]
+ (set (match_operand:SWI48 0 "register_operand" "=r")
+ (ctz:SWI48 (match_dup 1)))]
""
- "bsf{l}\t{%1, %0|%0, %1}"
- [(set_attr "type" "alu1")
- (set_attr "prefix_0f" "1")
- (set_attr "mode" "SI")])
-
-(define_expand "ffsdi2"
- [(set (match_dup 2) (const_int -1))
- (parallel [(set (reg:CCZ FLAGS_REG)
- (compare:CCZ (match_operand:DI 1 "nonimmediate_operand" "")
- (const_int 0)))
- (set (match_operand:DI 0 "register_operand" "")
- (ctz:DI (match_dup 1)))])
- (set (match_dup 0) (if_then_else:DI
- (eq (reg:CCZ FLAGS_REG) (const_int 0))
- (match_dup 2)
- (match_dup 0)))
- (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (const_int 1)))
- (clobber (reg:CC FLAGS_REG))])]
- "TARGET_64BIT"
- "operands[2] = gen_reg_rtx (DImode);")
-
-(define_insn "*ffsdi_1"
- [(set (reg:CCZ FLAGS_REG)
- (compare:CCZ (match_operand:DI 1 "nonimmediate_operand" "rm")
- (const_int 0)))
- (set (match_operand:DI 0 "register_operand" "=r")
- (ctz:DI (match_dup 1)))]
- "TARGET_64BIT"
- "bsf{q}\t{%1, %0|%0, %1}"
+ "bsf{<imodesuffix>}\t{%1, %0|%0, %1}"
[(set_attr "type" "alu1")
(set_attr "prefix_0f" "1")
- (set_attr "mode" "DI")])
+ (set_attr "mode" "<MODE>")])
-(define_insn "ctzsi2"
- [(set (match_operand:SI 0 "register_operand" "=r")
- (ctz:SI (match_operand:SI 1 "nonimmediate_operand" "rm")))
+(define_insn "ctz<mode>2"
+ [(set (match_operand:SWI48 0 "register_operand" "=r")
+ (ctz:SWI48 (match_operand:SWI48 1 "nonimmediate_operand" "rm")))
(clobber (reg:CC FLAGS_REG))]
""
- "bsf{l}\t{%1, %0|%0, %1}"
+ "bsf{<imodesuffix>}\t{%1, %0|%0, %1}"
[(set_attr "type" "alu1")
(set_attr "prefix_0f" "1")
- (set_attr "mode" "SI")])
-
-(define_insn "ctzdi2"
- [(set (match_operand:DI 0 "register_operand" "=r")
- (ctz:DI (match_operand:DI 1 "nonimmediate_operand" "rm")))
- (clobber (reg:CC FLAGS_REG))]
- "TARGET_64BIT"
- "bsf{q}\t{%1, %0|%0, %1}"
- [(set_attr "type" "alu1")
- (set_attr "prefix_0f" "1")
- (set_attr "mode" "DI")])
+ (set_attr "mode" "<MODE>")])
-(define_expand "clzsi2"
+(define_expand "clz<mode>2"
[(parallel
- [(set (match_operand:SI 0 "register_operand" "")
- (minus:SI (const_int 31)
- (clz:SI (match_operand:SI 1 "nonimmediate_operand" ""))))
+ [(set (match_operand:SWI248 0 "register_operand" "")
+ (minus:SWI248
+ (match_dup 2)
+ (clz:SWI248 (match_operand:SWI248 1 "nonimmediate_operand" ""))))
(clobber (reg:CC FLAGS_REG))])
(parallel
- [(set (match_dup 0) (xor:SI (match_dup 0) (const_int 31)))
+ [(set (match_dup 0) (xor:SWI248 (match_dup 0) (match_dup 2)))
(clobber (reg:CC FLAGS_REG))])]
""
{
if (TARGET_ABM)
{
- emit_insn (gen_clzsi2_abm (operands[0], operands[1]));
+ emit_insn (gen_clz<mode>2_abm (operands[0], operands[1]));
DONE;
}
+ operands[2] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode)-1);
})
-(define_insn "clzsi2_abm"
- [(set (match_operand:SI 0 "register_operand" "=r")
- (clz:SI (match_operand:SI 1 "nonimmediate_operand" "rm")))
+(define_insn "clz<mode>2_abm"
+ [(set (match_operand:SWI248 0 "register_operand" "=r")
+ (clz:SWI248 (match_operand:SWI248 1 "nonimmediate_operand" "rm")))
(clobber (reg:CC FLAGS_REG))]
"TARGET_ABM"
- "lzcnt{l}\t{%1, %0|%0, %1}"
+ "lzcnt{<imodesuffix>}\t{%1, %0|%0, %1}"
[(set_attr "prefix_rep" "1")
(set_attr "type" "bitmanip")
- (set_attr "mode" "SI")])
+ (set_attr "mode" "<MODE>")])
+
+(define_insn "bsr_rex64"
+ [(set (match_operand:DI 0 "register_operand" "=r")
+ (minus:DI (const_int 63)
+ (clz:DI (match_operand:DI 1 "nonimmediate_operand" "rm"))))
+ (clobber (reg:CC FLAGS_REG))]
+ "TARGET_64BIT"
+ "bsr{q}\t{%1, %0|%0, %1}"
+ [(set_attr "type" "alu1")
+ (set_attr "prefix_0f" "1")
+ (set_attr "mode" "DI")])
(define_insn "bsr"
[(set (match_operand:SI 0 "register_operand" "=r")
(set_attr "prefix_0f" "1")
(set_attr "mode" "SI")])
+(define_insn "*bsrhi"
+ [(set (match_operand:HI 0 "register_operand" "=r")
+ (minus:HI (const_int 15)
+ (clz:HI (match_operand:HI 1 "nonimmediate_operand" "rm"))))
+ (clobber (reg:CC FLAGS_REG))]
+ ""
+ "bsr{w}\t{%1, %0|%0, %1}"
+ [(set_attr "type" "alu1")
+ (set_attr "prefix_0f" "1")
+ (set_attr "mode" "HI")])
+
(define_insn "popcount<mode>2"
[(set (match_operand:SWI248 0 "register_operand" "=r")
(popcount:SWI248
(set_attr "type" "bitmanip")
(set_attr "mode" "SI")])
+(define_expand "bswapdi2"
+ [(set (match_operand:DI 0 "register_operand" "")
+ (bswap:DI (match_operand:DI 1 "register_operand" "")))]
+ "TARGET_64BIT"
+ "")
+
(define_expand "bswapsi2"
[(set (match_operand:SI 0 "register_operand" "")
(bswap:SI (match_operand:SI 1 "register_operand" "")))]
}
})
+(define_insn "*bswapdi_movbe"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m")
+ (bswap:DI (match_operand:DI 1 "nonimmediate_operand" "0,m,r")))]
+ "TARGET_64BIT && TARGET_MOVBE
+ && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
+ "@
+ bswap\t%0
+ movbe\t{%1, %0|%0, %1}
+ movbe\t{%1, %0|%0, %1}"
+ [(set_attr "type" "*,imov,imov")
+ (set_attr "modrm" "*,1,1")
+ (set_attr "prefix_0f" "1")
+ (set_attr "prefix_extra" "*,1,1")
+ (set_attr "length" "3,*,*")
+ (set_attr "mode" "DI")])
+
(define_insn "*bswapsi_movbe"
[(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,m")
(bswap:SI (match_operand:SI 1 "nonimmediate_operand" "0,m,r")))]
(set_attr "length" "2,*,*")
(set_attr "mode" "SI")])
+(define_insn "*bswapdi_1"
+ [(set (match_operand:DI 0 "register_operand" "=r")
+ (bswap:DI (match_operand:DI 1 "register_operand" "0")))]
+ "TARGET_64BIT"
+ "bswap\t%0"
+ [(set_attr "prefix_0f" "1")
+ (set_attr "length" "3")])
+
(define_insn "*bswapsi_1"
[(set (match_operand:SI 0 "register_operand" "=r")
(bswap:SI (match_operand:SI 1 "register_operand" "0")))]
[(set_attr "length" "4")
(set_attr "mode" "HI")])
-(define_expand "bswapdi2"
- [(set (match_operand:DI 0 "register_operand" "")
- (bswap:DI (match_operand:DI 1 "register_operand" "")))]
- "TARGET_64BIT"
- "")
-
-(define_insn "*bswapdi_movbe"
- [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m")
- (bswap:DI (match_operand:DI 1 "nonimmediate_operand" "0,m,r")))]
- "TARGET_64BIT && TARGET_MOVBE
- && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
- "@
- bswap\t%0
- movbe\t{%1, %0|%0, %1}
- movbe\t{%1, %0|%0, %1}"
- [(set_attr "type" "*,imov,imov")
- (set_attr "modrm" "*,1,1")
- (set_attr "prefix_0f" "1")
- (set_attr "prefix_extra" "*,1,1")
- (set_attr "length" "3,*,*")
- (set_attr "mode" "DI")])
-
-(define_insn "*bswapdi_1"
- [(set (match_operand:DI 0 "register_operand" "=r")
- (bswap:DI (match_operand:DI 1 "register_operand" "0")))]
- "TARGET_64BIT"
- "bswap\t%0"
- [(set_attr "prefix_0f" "1")
- (set_attr "length" "3")])
-
-(define_expand "clzdi2"
- [(parallel
- [(set (match_operand:DI 0 "register_operand" "")
- (minus:DI (const_int 63)
- (clz:DI (match_operand:DI 1 "nonimmediate_operand" ""))))
- (clobber (reg:CC FLAGS_REG))])
- (parallel
- [(set (match_dup 0) (xor:DI (match_dup 0) (const_int 63)))
- (clobber (reg:CC FLAGS_REG))])]
- "TARGET_64BIT"
-{
- if (TARGET_ABM)
- {
- emit_insn (gen_clzdi2_abm (operands[0], operands[1]));
- DONE;
- }
-})
-
-(define_insn "clzdi2_abm"
- [(set (match_operand:DI 0 "register_operand" "=r")
- (clz:DI (match_operand:DI 1 "nonimmediate_operand" "rm")))
- (clobber (reg:CC FLAGS_REG))]
- "TARGET_64BIT && TARGET_ABM"
- "lzcnt{q}\t{%1, %0|%0, %1}"
- [(set_attr "prefix_rep" "1")
- (set_attr "type" "bitmanip")
- (set_attr "mode" "DI")])
-
-(define_insn "bsr_rex64"
- [(set (match_operand:DI 0 "register_operand" "=r")
- (minus:DI (const_int 63)
- (clz:DI (match_operand:DI 1 "nonimmediate_operand" "rm"))))
- (clobber (reg:CC FLAGS_REG))]
- "TARGET_64BIT"
- "bsr{q}\t{%1, %0|%0, %1}"
- [(set_attr "type" "alu1")
- (set_attr "prefix_0f" "1")
- (set_attr "mode" "DI")])
-
-(define_expand "clzhi2"
- [(parallel
- [(set (match_operand:HI 0 "register_operand" "")
- (minus:HI (const_int 15)
- (clz:HI (match_operand:HI 1 "nonimmediate_operand" ""))))
- (clobber (reg:CC FLAGS_REG))])
- (parallel
- [(set (match_dup 0) (xor:HI (match_dup 0) (const_int 15)))
- (clobber (reg:CC FLAGS_REG))])]
- ""
-{
- if (TARGET_ABM)
- {
- emit_insn (gen_clzhi2_abm (operands[0], operands[1]));
- DONE;
- }
-})
-
-(define_insn "clzhi2_abm"
- [(set (match_operand:HI 0 "register_operand" "=r")
- (clz:HI (match_operand:HI 1 "nonimmediate_operand" "rm")))
- (clobber (reg:CC FLAGS_REG))]
- "TARGET_ABM"
- "lzcnt{w}\t{%1, %0|%0, %1}"
- [(set_attr "prefix_rep" "1")
- (set_attr "type" "bitmanip")
- (set_attr "mode" "HI")])
-
-(define_insn "*bsrhi"
- [(set (match_operand:HI 0 "register_operand" "=r")
- (minus:HI (const_int 15)
- (clz:HI (match_operand:HI 1 "nonimmediate_operand" "rm"))))
- (clobber (reg:CC FLAGS_REG))]
- ""
- "bsr{w}\t{%1, %0|%0, %1}"
- [(set_attr "type" "alu1")
- (set_attr "prefix_0f" "1")
- (set_attr "mode" "HI")])
-
(define_expand "paritydi2"
[(set (match_operand:DI 0 "register_operand" "")
(parity:DI (match_operand:DI 1 "register_operand" "")))]
DONE;
})
+(define_expand "paritysi2"
+ [(set (match_operand:SI 0 "register_operand" "")
+ (parity:SI (match_operand:SI 1 "register_operand" "")))]
+ "! TARGET_POPCNT"
+{
+ rtx scratch = gen_reg_rtx (QImode);
+ rtx cond;
+
+ emit_insn (gen_paritysi2_cmp (NULL_RTX, NULL_RTX, operands[1]));
+
+ cond = gen_rtx_fmt_ee (ORDERED, QImode,
+ gen_rtx_REG (CCmode, FLAGS_REG),
+ const0_rtx);
+ emit_insn (gen_rtx_SET (VOIDmode, scratch, cond));
+
+ emit_insn (gen_zero_extendqisi2 (operands[0], scratch));
+ DONE;
+})
+
(define_insn_and_split "paritydi2_cmp"
[(set (reg:CC FLAGS_REG)
(parity:CC (match_operand:DI 3 "register_operand" "0")))
operands[1] = gen_highpart (SImode, operands[3]);
})
-(define_expand "paritysi2"
- [(set (match_operand:SI 0 "register_operand" "")
- (parity:SI (match_operand:SI 1 "register_operand" "")))]
- "! TARGET_POPCNT"
-{
- rtx scratch = gen_reg_rtx (QImode);
- rtx cond;
-
- emit_insn (gen_paritysi2_cmp (NULL_RTX, NULL_RTX, operands[1]));
-
- cond = gen_rtx_fmt_ee (ORDERED, QImode,
- gen_rtx_REG (CCmode, FLAGS_REG),
- const0_rtx);
- emit_insn (gen_rtx_SET (VOIDmode, scratch, cond));
-
- emit_insn (gen_zero_extendqisi2 (operands[0], scratch));
- DONE;
-})
-
(define_insn_and_split "paritysi2_cmp"
[(set (reg:CC FLAGS_REG)
(parity:CC (match_operand:SI 2 "register_operand" "0")))
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