/* Current frame information calculated by m68k_compute_frame_layout(). */
static struct m68k_frame current_frame;
+static bool m68k_handle_option (size_t, const char *, int);
static rtx find_addr_reg (rtx);
static const char *singlemove_string (rtx *);
static void m68k_output_function_prologue (FILE *, HOST_WIDE_INT);
\f
/* Specify the identification number of the library being built */
-const char *m68k_library_id_string;
+const char *m68k_library_id_string = "_current_shared_library_a5_offset_";
/* Nonzero if the last compare/test insn had FP operands. The
sCC expanders peek at this to determine what to do for the
#undef TARGET_ASM_FILE_START_APP_OFF
#define TARGET_ASM_FILE_START_APP_OFF true
+#undef TARGET_DEFAULT_TARGET_FLAGS
+#define TARGET_DEFAULT_TARGET_FLAGS (TARGET_DEFAULT | MASK_STRICT_ALIGNMENT)
+#undef TARGET_HANDLE_OPTION
+#define TARGET_HANDLE_OPTION m68k_handle_option
+
#undef TARGET_RTX_COSTS
#define TARGET_RTX_COSTS m68k_rtx_costs
struct gcc_target targetm = TARGET_INITIALIZER;
\f
+/* These bits are controlled by all CPU selection options. Many options
+ also control MASK_68881, but some (notably -m68020) leave it alone. */
+
+#define MASK_ALL_CPU_BITS \
+ (MASK_COLDFIRE | MASK_CF_HWDIV | MASK_68060 | MASK_68040 \
+ | MASK_68040_ONLY | MASK_68030 | MASK_68020 | MASK_BITFIELD)
+
+/* Implement TARGET_HANDLE_OPTION. */
+
+static bool
+m68k_handle_option (size_t code, const char *arg, int value)
+{
+ switch (code)
+ {
+ case OPT_m5200:
+ target_flags &= ~(MASK_ALL_CPU_BITS | MASK_68881);
+ target_flags |= MASK_5200;
+ return true;
+
+ case OPT_m5206e:
+ target_flags &= ~(MASK_ALL_CPU_BITS | MASK_68881);
+ target_flags |= MASK_5200 | MASK_CF_HWDIV;
+ return true;
+
+ case OPT_m528x:
+ target_flags &= ~(MASK_ALL_CPU_BITS | MASK_68881);
+ target_flags |= MASK_528x | MASK_CF_HWDIV;
+ return true;
+
+ case OPT_m5307:
+ target_flags &= ~(MASK_ALL_CPU_BITS | MASK_68881);
+ target_flags |= MASK_CFV3 | MASK_CF_HWDIV;
+ return true;
+
+ case OPT_m5407:
+ target_flags &= ~(MASK_ALL_CPU_BITS | MASK_68881);
+ target_flags |= MASK_CFV4 | MASK_CF_HWDIV;
+ return true;
+
+ case OPT_m68000:
+ case OPT_mc68000:
+ target_flags &= ~(MASK_ALL_CPU_BITS | MASK_68881);
+ return true;
+
+ case OPT_m68020:
+ case OPT_mc68020:
+ target_flags &= ~MASK_ALL_CPU_BITS;
+ target_flags |= MASK_68020 | MASK_BITFIELD;
+ return true;
+
+ case OPT_m68020_40:
+ target_flags &= ~MASK_ALL_CPU_BITS;
+ target_flags |= MASK_BITFIELD | MASK_68881 | MASK_68020 | MASK_68040;
+ return true;
+
+ case OPT_m68020_60:
+ target_flags &= ~MASK_ALL_CPU_BITS;
+ target_flags |= (MASK_BITFIELD | MASK_68881 | MASK_68020
+ | MASK_68040 | MASK_68060);
+ return true;
+
+ case OPT_m68030:
+ target_flags &= ~MASK_ALL_CPU_BITS;
+ target_flags |= MASK_68020 | MASK_68030 | MASK_BITFIELD;
+ return true;
+
+ case OPT_m68040:
+ target_flags &= ~MASK_ALL_CPU_BITS;
+ target_flags |= (MASK_68020 | MASK_68881 | MASK_BITFIELD
+ | MASK_68040_ONLY | MASK_68040);
+ return true;
+
+ case OPT_m68060:
+ target_flags &= ~MASK_ALL_CPU_BITS;
+ target_flags |= (MASK_68020 | MASK_68881 | MASK_BITFIELD
+ | MASK_68040_ONLY | MASK_68060);
+ return true;
+
+ case OPT_m68302:
+ target_flags &= ~(MASK_ALL_CPU_BITS | MASK_68881);
+ return true;
+
+ case OPT_m68332:
+ case OPT_mcpu32:
+ target_flags &= ~(MASK_ALL_CPU_BITS | MASK_68881);
+ target_flags |= MASK_68020;
+ return true;
+
+ case OPT_mshared_library_id_:
+ if (value > MAX_LIBRARY_ID)
+ error ("-mshared-library-id=%s is not between 0 and %d",
+ arg, MAX_LIBRARY_ID);
+ else
+ asprintf ((char **) &m68k_library_id_string, "%d", (value * -4) - 4);
+ return true;
+
+ default:
+ return true;
+ }
+}
+
/* Sometimes certain combinations of command options do not make
sense on a particular target machine. You can define a macro
`OVERRIDE_OPTIONS' to take account of this. This macro, if
void
override_options (void)
{
- /* Library identification */
- if (m68k_library_id_string)
- {
- int id;
-
- if (! TARGET_ID_SHARED_LIBRARY)
- error ("-mshared-library-id= specified without -mid-shared-library");
- id = atoi (m68k_library_id_string);
- if (id < 0 || id > MAX_LIBRARY_ID)
- error ("-mshared-library-id=%d is not between 0 and %d", id, MAX_LIBRARY_ID);
-
- /* From now on, m68k_library_id_string will contain the library offset. */
- asprintf ((char **)&m68k_library_id_string, "%d", (id * -4) - 4);
- }
- else
- /* If TARGET_ID_SHARED_LIBRARY is enabled, this will point to the
- current library. */
- m68k_library_id_string = "_current_shared_library_a5_offset_";
-
/* Sanity check to ensure that msep-data and mid-sahred-library are not
* both specified together. Doing so simply doesn't make sense.
*/
/* Set the default. */
#define INT_OP_GROUP INT_OP_DOT_WORD
-/* Run-time compilation parameters selecting different hardware subsets. */
-
-extern int target_flags;
-
-/* Macros used in the machine description to test the flags. */
-
-/* Compile for a 68020 (not a 68000 or 68010). */
-#define MASK_68020 (1<<0)
-#define TARGET_68020 (target_flags & MASK_68020)
-
-/* Compile for a 68030. This does not really make a difference in GCC,
- it just enables the __mc68030__ predefine. */
-#define MASK_68030 (1<<1)
-#define TARGET_68030 (target_flags & MASK_68030)
-
-/* Optimize for 68040, but still allow execution on 68020
- (-m68020-40 or -m68040).
- The 68040 will execute all 68030 and 68881/2 instructions, but some
- of them must be emulated in software by the OS. When TARGET_68040 is
- turned on, these instructions won't be used. This code will still
- run on a 68030 and 68881/2. */
-#define MASK_68040 (1<<2)
-#define TARGET_68040 (target_flags & MASK_68040)
-
-/* Use the 68040-only fp instructions (-m68040 or -m68060). */
-#define MASK_68040_ONLY (1<<3)
-#define TARGET_68040_ONLY (target_flags & MASK_68040_ONLY)
-
-/* Optimize for 68060, but still allow execution on 68020
- (-m68020-60 or -m68060).
- The 68060 will execute all 68030 and 68881/2 instructions, but some
- of them must be emulated in software by the OS. When TARGET_68060 is
- turned on, these instructions won't be used. This code will still
- run on a 68030 and 68881/2. */
-#define MASK_68060 (1<<4)
-#define TARGET_68060 (target_flags & MASK_68060)
-
-/* Compile for mcf5200 */
-#define MASK_5200 (1<<5)
-#define TARGET_5200 (target_flags & MASK_5200)
-
-/* Build for ColdFire v3 */
-#define MASK_CFV3 (1<<6)
-#define TARGET_CFV3 (target_flags & MASK_CFV3)
-
-/* Build for ColdFire v4 */
-#define MASK_CFV4 (1<<7)
-#define TARGET_CFV4 (target_flags & MASK_CFV4)
-
-/* Compile for ColdFire 528x */
-#define MASK_528x (1<<8)
-#define TARGET_528x (target_flags & MASK_528x)
-
-/* Divide support for ColdFire */
-#define MASK_CF_HWDIV (1<<9)
-#define TARGET_CF_HWDIV (target_flags & MASK_CF_HWDIV)
-
-/* Compile 68881 insns for floating point (not library calls). */
-#define MASK_68881 (1<<10)
-#define TARGET_68881 (target_flags & MASK_68881)
-
-/* Compile using 68020 bit-field insns. */
-#define MASK_BITFIELD (1<<11)
-#define TARGET_BITFIELD (target_flags & MASK_BITFIELD)
-
-/* Compile with 16-bit `int'. */
-#define MASK_SHORT (1<<12)
-#define TARGET_SHORT (target_flags & MASK_SHORT)
-
-/* Align ints to a word boundary. This breaks compatibility with the
- published ABI's for structures containing ints, but produces faster
- code on cpus with 32-bit busses (020, 030, 040, 060, CPU32+, ColdFire).
- It's required for ColdFire cpus without a misalignment module. */
-#define MASK_ALIGN_INT (1<<13)
-#define TARGET_ALIGN_INT (target_flags & MASK_ALIGN_INT)
-
-/* Use PC-relative addressing modes (without using a global offset table).
- The m68000 supports 16-bit PC-relative addressing.
- The m68020 supports 32-bit PC-relative addressing
- (using outer displacements).
-
- Under this model, all SYMBOL_REFs (and CONSTs) and LABEL_REFs are
- treated as all containing an implicit PC-relative component, and hence
- cannot be used directly as addresses for memory writes. See the comments
- in m68k.c for more information. */
-#define MASK_PCREL (1<<14)
-#define TARGET_PCREL (target_flags & MASK_PCREL)
-
-/* Relax strict alignment. */
-#define MASK_NO_STRICT_ALIGNMENT (1<<15)
-#define TARGET_STRICT_ALIGNMENT (~target_flags & MASK_NO_STRICT_ALIGNMENT)
-
-/* Compile using rtd insn calling sequence.
- This will not work unless you use prototypes at least
- for all functions that can take varying numbers of args. */
-#define MASK_RTD (1<<16)
-#define TARGET_RTD (target_flags & MASK_RTD)
-
-/* Support A5 relative data separate from text.
- * This option implies -fPIC, however it inhibits the generation of the
- * A5 save/restore in functions and the loading of a5 with a got pointer.
- */
-#define MASK_SEP_DATA (1<<17)
-#define TARGET_SEP_DATA (target_flags & MASK_SEP_DATA)
-
-/* Compile using library ID based shared libraries.
- * Set a specific ID using the -mshared-library-id=xxx option.
- */
-#define MASK_ID_SHARED_LIBRARY (1<<18)
-#define TARGET_ID_SHARED_LIBRARY (target_flags & MASK_ID_SHARED_LIBRARY)
-
/* Compile for a CPU32. A 68020 without bitfields is a good
heuristic for a CPU32. */
#define TARGET_CPU32 (TARGET_68020 && !TARGET_BITFIELD)
/* Is the target a ColdFire? */
-#define MASK_COLDFIRE (MASK_5200|MASK_528x|MASK_CFV3|MASK_CFV4)
-#define TARGET_COLDFIRE (target_flags & MASK_COLDFIRE)
-
-/* Which bits can be set by specifying a ColdFire */
-#define MASK_ALL_CF_BITS (MASK_COLDFIRE|MASK_CF_HWDIV)
-
-#define TARGET_SWITCHES \
- { { "68020", - (MASK_ALL_CF_BITS|MASK_68060|MASK_68040|MASK_68040_ONLY), \
- N_("Generate code for a 68020") }, \
- { "c68020", - (MASK_ALL_CF_BITS|MASK_68060|MASK_68040|MASK_68040_ONLY), \
- N_("Generate code for a 68020") }, \
- { "68020", (MASK_68020|MASK_BITFIELD), "" }, \
- { "c68020", (MASK_68020|MASK_BITFIELD), "" }, \
- { "68000", - (MASK_ALL_CF_BITS|MASK_68060|MASK_68040|MASK_68040_ONLY \
- |MASK_68020|MASK_BITFIELD|MASK_68881), \
- N_("Generate code for a 68000") }, \
- { "c68000", - (MASK_ALL_CF_BITS|MASK_68060|MASK_68040|MASK_68040_ONLY \
- |MASK_68020|MASK_BITFIELD|MASK_68881), \
- N_("Generate code for a 68000") }, \
- { "bitfield", MASK_BITFIELD, \
- N_("Use the bit-field instructions") }, \
- { "nobitfield", - MASK_BITFIELD, \
- N_("Do not use the bit-field instructions") }, \
- { "short", MASK_SHORT, \
- N_("Consider type 'int' to be 16 bits wide") }, \
- { "noshort", - MASK_SHORT, \
- N_("Consider type 'int' to be 32 bits wide") }, \
- { "68881", MASK_68881, "" }, \
- { "soft-float", - MASK_68881, \
- N_("Generate code with library calls for floating point") }, \
- { "68020-40", -(MASK_ALL_CF_BITS|MASK_68060|MASK_68040_ONLY), \
- N_("Generate code for a 68040, without any new instructions") }, \
- { "68020-40", (MASK_BITFIELD|MASK_68881|MASK_68020|MASK_68040), ""},\
- { "68020-60", -(MASK_ALL_CF_BITS|MASK_68040_ONLY), \
- N_("Generate code for a 68060, without any new instructions") }, \
- { "68020-60", (MASK_BITFIELD|MASK_68881|MASK_68020|MASK_68040 \
- |MASK_68060), "" }, \
- { "68030", - (MASK_ALL_CF_BITS|MASK_68060|MASK_68040|MASK_68040_ONLY), \
- N_("Generate code for a 68030") }, \
- { "68030", (MASK_68020|MASK_68030|MASK_BITFIELD), "" }, \
- { "68040", - (MASK_ALL_CF_BITS|MASK_68060), \
- N_("Generate code for a 68040") }, \
- { "68040", (MASK_68020|MASK_68881|MASK_BITFIELD \
- |MASK_68040_ONLY|MASK_68040), "" }, \
- { "68060", - (MASK_ALL_CF_BITS|MASK_68040), \
- N_("Generate code for a 68060") }, \
- { "68060", (MASK_68020|MASK_68881|MASK_BITFIELD \
- |MASK_68040_ONLY|MASK_68060), "" }, \
- { "5200", - (MASK_ALL_CF_BITS|MASK_68060|MASK_68040|MASK_68040_ONLY|MASK_68020 \
- |MASK_BITFIELD|MASK_68881), \
- N_("Generate code for a 520X") }, \
- { "5200", (MASK_5200), "" }, \
- { "5206e", - (MASK_ALL_CF_BITS|MASK_68060|MASK_68040|MASK_68040_ONLY|MASK_68020 \
- |MASK_BITFIELD|MASK_68881), \
- N_("Generate code for a 5206e") }, \
- { "5206e", (MASK_5200|MASK_CF_HWDIV), "" }, \
- { "528x", - (MASK_ALL_CF_BITS|MASK_68060|MASK_68040|MASK_68040_ONLY|MASK_68020 \
- |MASK_BITFIELD|MASK_68881), \
- N_("Generate code for a 528x") }, \
- { "528x", (MASK_528x|MASK_CF_HWDIV), "" }, \
- { "5307", - (MASK_ALL_CF_BITS|MASK_68060|MASK_68040|MASK_68040_ONLY|MASK_68020 \
- |MASK_BITFIELD|MASK_68881), \
- N_("Generate code for a 5307") }, \
- { "5307", (MASK_CFV3|MASK_CF_HWDIV), "" }, \
- { "5407", - (MASK_ALL_CF_BITS|MASK_68060|MASK_68040|MASK_68040_ONLY|MASK_68020 \
- |MASK_BITFIELD|MASK_68881), \
- N_("Generate code for a 5407") }, \
- { "5407", (MASK_CFV4|MASK_CF_HWDIV), "" }, \
- { "68851", 0, \
- N_("Generate code for a 68851") }, \
- { "no-68851", 0, \
- N_("Do no generate code for a 68851") }, \
- { "68302", - (MASK_ALL_CF_BITS|MASK_68060|MASK_68040|MASK_68040_ONLY \
- |MASK_68020|MASK_BITFIELD|MASK_68881), \
- N_("Generate code for a 68302") }, \
- { "68332", - (MASK_ALL_CF_BITS|MASK_68060|MASK_68040|MASK_68040_ONLY \
- |MASK_BITFIELD|MASK_68881), \
- N_("Generate code for a 68332") }, \
- { "68332", MASK_68020, "" }, \
- { "cpu32", - (MASK_ALL_CF_BITS|MASK_68060|MASK_68040|MASK_68040_ONLY \
- |MASK_BITFIELD|MASK_68881), \
- N_("Generate code for a cpu32") }, \
- { "cpu32", MASK_68020, "" }, \
- { "align-int", MASK_ALIGN_INT, \
- N_("Align variables on a 32-bit boundary") }, \
- { "no-align-int", -MASK_ALIGN_INT, \
- N_("Align variables on a 16-bit boundary") }, \
- { "sep-data", MASK_SEP_DATA, \
- N_("Enable separate data segment") }, \
- { "no-sep-data", -MASK_SEP_DATA, \
- N_("Disable separate data segment") }, \
- { "id-shared-library", MASK_ID_SHARED_LIBRARY, \
- N_("Enable ID based shared library") }, \
- { "no-id-shared-library", -MASK_ID_SHARED_LIBRARY, \
- N_("Disable ID based shared library") }, \
- { "pcrel", MASK_PCREL, \
- N_("Generate pc-relative code") }, \
- { "strict-align", -MASK_NO_STRICT_ALIGNMENT, \
- N_("Do not use unaligned memory references") }, \
- { "no-strict-align", MASK_NO_STRICT_ALIGNMENT, \
- N_("Use unaligned memory references") }, \
- { "rtd", MASK_RTD, \
- N_("Use different calling convention using 'rtd'") }, \
- { "nortd", - MASK_RTD, \
- N_("Use normal calling convention") }, \
- SUBTARGET_SWITCHES \
- { "", TARGET_DEFAULT, "" }}
-/* TARGET_DEFAULT is defined in m68k-none.h, netbsd.h, etc. */
-
-#define TARGET_OPTIONS \
-{ \
- { "shared-library-id=", &m68k_library_id_string, \
- N_("ID of shared library to build"), 0}, \
- SUBTARGET_OPTIONS \
-}
+#define MASK_COLDFIRE (MASK_5200 | MASK_528x | MASK_CFV3 | MASK_CFV4)
+#define TARGET_COLDFIRE ((target_flags & MASK_COLDFIRE) != 0)
#define OVERRIDE_OPTIONS override_options()
/* These are meant to be redefined in the host dependent files */
-#define SUBTARGET_SWITCHES
-#define SUBTARGET_OPTIONS
#define SUBTARGET_OVERRIDE_OPTIONS
\f
/* target machine storage layout */
--- /dev/null
+; Options for the Motorola 68000 port of the compiler.
+
+; Copyright (C) 2005 Free Software Foundation, Inc.
+;
+; This file is part of GCC.
+;
+; GCC is free software; you can redistribute it and/or modify it under
+; the terms of the GNU General Public License as published by the Free
+; Software Foundation; either version 2, or (at your option) any later
+; version.
+;
+; GCC is distributed in the hope that it will be useful, but WITHOUT ANY
+; WARRANTY; without even the implied warranty of MERCHANTABILITY or
+; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+; for more details.
+;
+; You should have received a copy of the GNU General Public License
+; along with GCC; see the file COPYING. If not, write to the Free
+; Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+; 02111-1307, USA.
+
+m5200
+Target RejectNegative Mask(5200)
+Generate code for a 520X
+
+m5206e
+Target RejectNegative Mask(CF_HWDIV)
+Generate code for a 5206e
+
+m528x
+Target RejectNegative Mask(528x)
+Generate code for a 528x
+
+m5307
+Target RejectNegative Mask(CFV3)
+Generate code for a 5307
+
+m5407
+Target RejectNegative Mask(CFV4)
+Generate code for a 5407
+
+m68000
+Target RejectNegative
+Generate code for a 68000
+
+m68020
+Target RejectNegative Mask(68020)
+Generate code for a 68020
+
+m68020-40
+Target RejectNegative Mask(68040)
+Generate code for a 68040, without any new instructions
+
+m68020-60
+Target RejectNegative Mask(68060)
+Generate code for a 68060, without any new instructions
+
+m68030
+Target RejectNegative Mask(68030)
+Generate code for a 68030
+
+m68040
+Target RejectNegative Mask(68040_ONLY)
+Generate code for a 68040
+
+m68060
+Target RejectNegative
+Generate code for a 68060
+
+m68302
+Target RejectNegative
+Generate code for a 68302
+
+m68332
+Target RejectNegative
+Generate code for a 68332
+
+; Has no effect on gcc
+m68851
+Target
+Generate code for a 68851
+
+m68881
+Target RejectNegative Mask(68881)
+Generate code that uses 68881 floating-point instructions
+
+malign-int
+Target Report Mask(ALIGN_INT)
+Align variables on a 32-bit boundary
+
+mbitfield
+Target Report RejectNegative Mask(BITFIELD)
+Use the bit-field instructions
+
+mc68000
+Target RejectNegative
+Generate code for a 68000
+
+mc68020
+Target RejectNegative
+Generate code for a 68020
+
+mcpu32
+Target RejectNegative
+Generate code for a cpu32
+
+mid-shared-library
+Target Report Mask(ID_SHARED_LIBRARY)
+Enable ID based shared library
+
+mnobitfield
+Target RejectNegative InverseMask(BITFIELD)
+Do not use the bit-field instructions
+
+mnortd
+Target RejectNegative InverseMask(RTD)
+Use normal calling convention
+
+mnoshort
+Target RejectNegative InverseMask(SHORT)
+Consider type 'int' to be 32 bits wide
+
+mpcrel
+Target Report Mask(PCREL)
+Generate pc-relative code
+
+mrtd
+Target Report RejectNegative Mask(RTD)
+Use different calling convention using 'rtd'
+
+msep-data
+Target Report Mask(SEP_DATA)
+Enable separate data segment
+
+mshared-library-id=
+Target RejectNegative Joined UInteger
+ID of shared library to build
+
+mshort
+Target Report RejectNegative Mask(SHORT)
+Consider type 'int' to be 16 bits wide
+
+msoft-float
+Target RejectNegative InverseMask(68881)
+Generate code with library calls for floating point
+
+mstrict-align
+Target Report Mask(STRICT_ALIGNMENT)
+Do not use unaligned memory references
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