* arm.md (*casesi_insn): Add a clobber of the condition-code register.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@30238 138bc75d-0d04-0410-961f-82ee72b054a4

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 55403b9..26a29ff 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,8 @@
+Thu Oct 28 11:05:13 1999  Richard Earnshaw <rearnsha@arm.com>
+
+       * arm.md (casesi_insn): Add a clobber of the condition code
+       register.
+
 Mon Oct 18 21:16:06 1999  Fred Fish  <fnf@be.com>
 
        * tm.texi (CC1PLUS_SPEC): Make it clear in the docs that CC1_SPEC is

diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md
index b59e535..88c0dbe 100644 (file)
--- a/gcc/config/arm/arm.md
+++ b/gcc/config/arm/arm.md
@@ -4686,6 +4686,7 @@
                (mem:SI (plus:SI (mult:SI (match_dup 0) (const_int 4))
                                 (label_ref (match_operand 2 "" ""))))
                (label_ref (match_operand 3 "" ""))))
+             (clobber (reg:CC 24))
              (use (label_ref (match_dup 2)))])]
   ""
   "*